xref: /dragonfly/sys/dev/drm/i915/i915_gem_object.h (revision 5ca0a96d)
1 /*
2  * Copyright © 2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  */
24 
25 #ifndef __I915_GEM_OBJECT_H__
26 #define __I915_GEM_OBJECT_H__
27 
28 #include <linux/reservation.h>
29 
30 #include <drm/drm_vma_manager.h>
31 #include <drm/drm_gem.h>
32 #include <drm/drmP.h>
33 
34 #include <drm/i915_drm.h>
35 
36 #include "i915_gem_request.h"
37 #include "i915_selftest.h"
38 
39 struct drm_i915_gem_object;
40 
41 /*
42  * struct i915_lut_handle tracks the fast lookups from handle to vma used
43  * for execbuf. Although we use a radixtree for that mapping, in order to
44  * remove them as the object or context is closed, we need a secondary list
45  * and a translation entry (i915_lut_handle).
46  */
47 struct i915_lut_handle {
48 	struct list_head obj_link;
49 	struct list_head ctx_link;
50 	struct i915_gem_context *ctx;
51 	u32 handle;
52 };
53 
54 struct drm_i915_gem_object_ops {
55 	unsigned int flags;
56 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
57 #define I915_GEM_OBJECT_IS_SHRINKABLE   BIT(1)
58 
59 	/* Interface between the GEM object and its backing storage.
60 	 * get_pages() is called once prior to the use of the associated set
61 	 * of pages before to binding them into the GTT, and put_pages() is
62 	 * called after we no longer need them. As we expect there to be
63 	 * associated cost with migrating pages between the backing storage
64 	 * and making them available for the GPU (e.g. clflush), we may hold
65 	 * onto the pages after they are no longer referenced by the GPU
66 	 * in case they may be used again shortly (for example migrating the
67 	 * pages to a different memory domain within the GTT). put_pages()
68 	 * will therefore most likely be called when the object itself is
69 	 * being released or under memory pressure (where we attempt to
70 	 * reap pages for the shrinker).
71 	 */
72 	int (*get_pages)(struct drm_i915_gem_object *);
73 	void (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);
74 
75 	int (*pwrite)(struct drm_i915_gem_object *,
76 		      const struct drm_i915_gem_pwrite *);
77 
78 	int (*dmabuf_export)(struct drm_i915_gem_object *);
79 	void (*release)(struct drm_i915_gem_object *);
80 };
81 
82 struct drm_i915_gem_object {
83 	struct drm_gem_object base;
84 
85 	const struct drm_i915_gem_object_ops *ops;
86 
87 	/**
88 	 * @vma_list: List of VMAs backed by this object
89 	 *
90 	 * The VMA on this list are ordered by type, all GGTT vma are placed
91 	 * at the head and all ppGTT vma are placed at the tail. The different
92 	 * types of GGTT vma are unordered between themselves, use the
93 	 * @vma_tree (which has a defined order between all VMA) to find an
94 	 * exact match.
95 	 */
96 	struct list_head vma_list;
97 	/**
98 	 * @vma_tree: Ordered tree of VMAs backed by this object
99 	 *
100 	 * All VMA created for this object are placed in the @vma_tree for
101 	 * fast retrieval via a binary search in i915_vma_instance().
102 	 * They are also added to @vma_list for easy iteration.
103 	 */
104 	struct rb_root vma_tree;
105 
106 	/**
107 	 * @lut_list: List of vma lookup entries in use for this object.
108 	 *
109 	 * If this object is closed, we need to remove all of its VMA from
110 	 * the fast lookup index in associated contexts; @lut_list provides
111 	 * this translation from object to context->handles_vma.
112 	 */
113 	struct list_head lut_list;
114 
115 	/** Stolen memory for this object, instead of being backed by shmem. */
116 	struct drm_mm_node *stolen;
117 	union {
118 		struct rcu_head rcu;
119 		struct llist_node freed;
120 	};
121 
122 	/**
123 	 * Whether the object is currently in the GGTT mmap.
124 	 */
125 	unsigned int userfault_count;
126 	struct list_head userfault_link;
127 
128 	struct list_head batch_pool_link;
129 	I915_SELFTEST_DECLARE(struct list_head st_link);
130 
131 	unsigned long flags;
132 
133 	/**
134 	 * Have we taken a reference for the object for incomplete GPU
135 	 * activity?
136 	 */
137 #define I915_BO_ACTIVE_REF 0
138 
139 	/*
140 	 * Is the object to be mapped as read-only to the GPU
141 	 * Only honoured if hardware has relevant pte bit
142 	 */
143 	unsigned long gt_ro:1;
144 	unsigned int cache_level:3;
145 	unsigned int cache_coherent:2;
146 #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
147 #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
148 	unsigned int cache_dirty:1;
149 
150 	atomic_t frontbuffer_bits;
151 	unsigned int frontbuffer_ggtt_origin; /* write once */
152 	struct i915_gem_active frontbuffer_write;
153 
154 	/** Current tiling stride for the object, if it's tiled. */
155 	unsigned int tiling_and_stride;
156 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
157 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
158 #define STRIDE_MASK (~TILING_MASK)
159 
160 	/** Count of VMA actually bound by this object */
161 	unsigned int bind_count;
162 	unsigned int active_count;
163 	/** Count of how many global VMA are currently pinned for use by HW */
164 	unsigned int pin_global;
165 
166 	struct {
167 		struct lock lock; /* protects the pages and their use */
168 		atomic_t pages_pin_count;
169 
170 		struct sg_table *pages;
171 		void *mapping;
172 
173 		/* TODO: whack some of this into the error state */
174 		struct i915_page_sizes {
175 			/**
176 			 * The sg mask of the pages sg_table. i.e the mask of
177 			 * of the lengths for each sg entry.
178 			 */
179 			unsigned int phys;
180 
181 			/**
182 			 * The gtt page sizes we are allowed to use given the
183 			 * sg mask and the supported page sizes. This will
184 			 * express the smallest unit we can use for the whole
185 			 * object, as well as the larger sizes we may be able
186 			 * to use opportunistically.
187 			 */
188 			unsigned int sg;
189 
190 			/**
191 			 * The actual gtt page size usage. Since we can have
192 			 * multiple vma associated with this object we need to
193 			 * prevent any trampling of state, hence a copy of this
194 			 * struct also lives in each vma, therefore the gtt
195 			 * value here should only be read/write through the vma.
196 			 */
197 			unsigned int gtt;
198 		} page_sizes;
199 
200 		I915_SELFTEST_DECLARE(unsigned int page_mask);
201 
202 		struct i915_gem_object_page_iter {
203 			struct scatterlist *sg_pos;
204 			unsigned int sg_idx; /* in pages, but 32bit eek! */
205 
206 			struct radix_tree_root radix;
207 			struct lock lock; /* protects this cache */
208 		} get_page;
209 
210 		/**
211 		 * Element within i915->mm.unbound_list or i915->mm.bound_list,
212 		 * locked by i915->mm.obj_lock.
213 		 */
214 		struct list_head link;
215 
216 		/**
217 		 * Advice: are the backing pages purgeable?
218 		 */
219 		unsigned int madv:2;
220 
221 		/**
222 		 * This is set if the object has been written to since the
223 		 * pages were last acquired.
224 		 */
225 		bool dirty:1;
226 
227 		/**
228 		 * This is set if the object has been pinned due to unknown
229 		 * swizzling.
230 		 */
231 		bool quirked:1;
232 	} mm;
233 
234 	/** Breadcrumb of last rendering to the buffer.
235 	 * There can only be one writer, but we allow for multiple readers.
236 	 * If there is a writer that necessarily implies that all other
237 	 * read requests are complete - but we may only be lazily clearing
238 	 * the read requests. A read request is naturally the most recent
239 	 * request on a ring, so we may have two different write and read
240 	 * requests on one ring where the write request is older than the
241 	 * read request. This allows for the CPU to read from an active
242 	 * buffer by only waiting for the write to complete.
243 	 */
244 	struct reservation_object *resv;
245 
246 	/** References from framebuffers, locks out tiling changes. */
247 	unsigned int framebuffer_references;
248 
249 	/** Record of address bit 17 of each page at last unbind. */
250 	unsigned long *bit_17;
251 
252 	union {
253 		struct i915_gem_userptr {
254 			uintptr_t ptr;
255 			unsigned read_only :1;
256 
257 			struct i915_mm_struct *mm;
258 			struct i915_mmu_object *mmu_object;
259 			struct work_struct *work;
260 		} userptr;
261 
262 		unsigned long scratch;
263 	};
264 
265 	/** for phys allocated objects */
266 	struct drm_dma_handle *phys_handle;
267 
268 	struct reservation_object __builtin_resv;
269 };
270 
271 static inline struct drm_i915_gem_object *
272 to_intel_bo(struct drm_gem_object *gem)
273 {
274 	/* Assert that to_intel_bo(NULL) == NULL */
275 	BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
276 
277 	return container_of(gem, struct drm_i915_gem_object, base);
278 }
279 
280 /**
281  * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
282  * @filp: DRM file private date
283  * @handle: userspace handle
284  *
285  * Returns:
286  *
287  * A pointer to the object named by the handle if such exists on @filp, NULL
288  * otherwise. This object is only valid whilst under the RCU read lock, and
289  * note carefully the object may be in the process of being destroyed.
290  */
291 static inline struct drm_i915_gem_object *
292 i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle)
293 {
294 #ifdef CONFIG_LOCKDEP
295 	WARN_ON(debug_locks && !lock_is_held(&rcu_lock_map));
296 #endif
297 	return idr_find(&file->object_idr, handle);
298 }
299 
300 static inline struct drm_i915_gem_object *
301 i915_gem_object_lookup(struct drm_file *file, u32 handle)
302 {
303 	struct drm_i915_gem_object *obj;
304 
305 	rcu_read_lock();
306 	obj = i915_gem_object_lookup_rcu(file, handle);
307 	if (obj && !kref_get_unless_zero(&obj->base.refcount))
308 		obj = NULL;
309 	rcu_read_unlock();
310 
311 	return obj;
312 }
313 
314 __attribute__((nonnull))
315 static inline struct drm_i915_gem_object *
316 i915_gem_object_get(struct drm_i915_gem_object *obj)
317 {
318 	drm_gem_object_reference(&obj->base);
319 	return obj;
320 }
321 
322 __attribute__((nonnull))
323 static inline void
324 i915_gem_object_put(struct drm_i915_gem_object *obj)
325 {
326 	__drm_gem_object_unreference(&obj->base);
327 }
328 
329 static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj)
330 {
331 	reservation_object_lock(obj->resv, NULL);
332 }
333 
334 static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj)
335 {
336 	reservation_object_unlock(obj->resv);
337 }
338 
339 static inline bool
340 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
341 {
342 	return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
343 }
344 
345 static inline bool
346 i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
347 {
348 	return obj->ops->flags & I915_GEM_OBJECT_IS_SHRINKABLE;
349 }
350 
351 static inline bool
352 i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
353 {
354 	return obj->active_count;
355 }
356 
357 static inline bool
358 i915_gem_object_has_active_reference(const struct drm_i915_gem_object *obj)
359 {
360 	return test_bit(I915_BO_ACTIVE_REF, &obj->flags);
361 }
362 
363 static inline void
364 i915_gem_object_set_active_reference(struct drm_i915_gem_object *obj)
365 {
366 	lockdep_assert_held(&obj->base.dev->struct_mutex);
367 	__set_bit(I915_BO_ACTIVE_REF, &obj->flags);
368 }
369 
370 static inline void
371 i915_gem_object_clear_active_reference(struct drm_i915_gem_object *obj)
372 {
373 	lockdep_assert_held(&obj->base.dev->struct_mutex);
374 	__clear_bit(I915_BO_ACTIVE_REF, &obj->flags);
375 }
376 
377 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj);
378 
379 static inline bool
380 i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
381 {
382 	return READ_ONCE(obj->framebuffer_references);
383 }
384 
385 static inline unsigned int
386 i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
387 {
388 	return obj->tiling_and_stride & TILING_MASK;
389 }
390 
391 static inline bool
392 i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
393 {
394 	return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
395 }
396 
397 static inline unsigned int
398 i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
399 {
400 	return obj->tiling_and_stride & STRIDE_MASK;
401 }
402 
403 static inline unsigned int
404 i915_gem_tile_height(unsigned int tiling)
405 {
406 	GEM_BUG_ON(!tiling);
407 	return tiling == I915_TILING_Y ? 32 : 8;
408 }
409 
410 static inline unsigned int
411 i915_gem_object_get_tile_height(struct drm_i915_gem_object *obj)
412 {
413 	return i915_gem_tile_height(i915_gem_object_get_tiling(obj));
414 }
415 
416 static inline unsigned int
417 i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj)
418 {
419 	return (i915_gem_object_get_stride(obj) *
420 		i915_gem_object_get_tile_height(obj));
421 }
422 
423 int i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
424 			       unsigned int tiling, unsigned int stride);
425 
426 static inline struct intel_engine_cs *
427 i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)
428 {
429 	struct intel_engine_cs *engine = NULL;
430 	struct dma_fence *fence;
431 
432 	rcu_read_lock();
433 	fence = reservation_object_get_excl_rcu(obj->resv);
434 	rcu_read_unlock();
435 
436 	if (fence && dma_fence_is_i915(fence) && !dma_fence_is_signaled(fence))
437 		engine = to_request(fence)->engine;
438 	dma_fence_put(fence);
439 
440 	return engine;
441 }
442 
443 void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
444 					 unsigned int cache_level);
445 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);
446 
447 #endif
448 
449