1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * $FreeBSD: src/sys/dev/drm2/i915/i915_gem_tiling.c,v 1.1 2012/05/22 11:07:44 kib Exp $ 27 */ 28 29 #include <sys/sfbuf.h> 30 31 #include <drm/drmP.h> 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 35 /** @file i915_gem_tiling.c 36 * 37 * Support for managing tiling state of buffer objects. 38 * 39 * The idea behind tiling is to increase cache hit rates by rearranging 40 * pixel data so that a group of pixel accesses are in the same cacheline. 41 * Performance improvement from doing this on the back/depth buffer are on 42 * the order of 30%. 43 * 44 * Intel architectures make this somewhat more complicated, though, by 45 * adjustments made to addressing of data when the memory is in interleaved 46 * mode (matched pairs of DIMMS) to improve memory bandwidth. 47 * For interleaved memory, the CPU sends every sequential 64 bytes 48 * to an alternate memory channel so it can get the bandwidth from both. 49 * 50 * The GPU also rearranges its accesses for increased bandwidth to interleaved 51 * memory, and it matches what the CPU does for non-tiled. However, when tiled 52 * it does it a little differently, since one walks addresses not just in the 53 * X direction but also Y. So, along with alternating channels when bit 54 * 6 of the address flips, it also alternates when other bits flip -- Bits 9 55 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) 56 * are common to both the 915 and 965-class hardware. 57 * 58 * The CPU also sometimes XORs in higher bits as well, to improve 59 * bandwidth doing strided access like we do so frequently in graphics. This 60 * is called "Channel XOR Randomization" in the MCH documentation. The result 61 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address 62 * decode. 63 * 64 * All of this bit 6 XORing has an effect on our memory management, 65 * as we need to make sure that the 3d driver can correctly address object 66 * contents. 67 * 68 * If we don't have interleaved memory, all tiling is safe and no swizzling is 69 * required. 70 * 71 * When bit 17 is XORed in, we simply refuse to tile at all. Bit 72 * 17 is not just a page offset, so as we page an objet out and back in, 73 * individual pages in it will have different bit 17 addresses, resulting in 74 * each 64 bytes being swapped with its neighbor! 75 * 76 * Otherwise, if interleaved, we have to tell the 3d driver what the address 77 * swizzling it needs to do is, since it's writing with the CPU to the pages 78 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the 79 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling 80 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order 81 * to match what the GPU expects. 82 */ 83 84 /** 85 * Detects bit 6 swizzling of address lookup between IGD access and CPU 86 * access through main memory. 87 */ 88 void 89 i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 90 { 91 drm_i915_private_t *dev_priv = dev->dev_private; 92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 94 95 if (IS_VALLEYVIEW(dev)) { 96 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 97 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 98 } else if (INTEL_INFO(dev)->gen >= 6) { 99 uint32_t dimm_c0, dimm_c1; 100 dimm_c0 = I915_READ(MAD_DIMM_C0); 101 dimm_c1 = I915_READ(MAD_DIMM_C1); 102 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; 103 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; 104 /* Enable swizzling when the channels are populated with 105 * identically sized dimms. We don't need to check the 3rd 106 * channel because no cpu with gpu attached ships in that 107 * configuration. Also, swizzling only makes sense for 2 108 * channels anyway. */ 109 if (dimm_c0 == dimm_c1) { 110 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 111 swizzle_y = I915_BIT_6_SWIZZLE_9; 112 } else { 113 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 114 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 115 } 116 } else if (IS_GEN5(dev)) { 117 /* On Ironlake whatever DRAM config, GPU always do 118 * same swizzling setup. 119 */ 120 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 121 swizzle_y = I915_BIT_6_SWIZZLE_9; 122 } else if (IS_GEN2(dev)) { 123 /* As far as we know, the 865 doesn't have these bit 6 124 * swizzling issues. 125 */ 126 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 127 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 128 } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) { 129 uint32_t dcc; 130 131 /* On 9xx chipsets, channel interleave by the CPU is 132 * determined by DCC. For single-channel, neither the CPU 133 * nor the GPU do swizzling. For dual channel interleaved, 134 * the GPU's interleave is bit 9 and 10 for X tiled, and bit 135 * 9 for Y tiled. The CPU's interleave is independent, and 136 * can be based on either bit 11 (haven't seen this yet) or 137 * bit 17 (common). 138 */ 139 dcc = I915_READ(DCC); 140 switch (dcc & DCC_ADDRESSING_MODE_MASK) { 141 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: 142 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: 143 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 144 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 145 break; 146 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: 147 if (dcc & DCC_CHANNEL_XOR_DISABLE) { 148 /* This is the base swizzling by the GPU for 149 * tiled buffers. 150 */ 151 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 152 swizzle_y = I915_BIT_6_SWIZZLE_9; 153 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { 154 /* Bit 11 swizzling by the CPU in addition. */ 155 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; 156 swizzle_y = I915_BIT_6_SWIZZLE_9_11; 157 } else { 158 /* Bit 17 swizzling by the CPU in addition. */ 159 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; 160 swizzle_y = I915_BIT_6_SWIZZLE_9_17; 161 } 162 break; 163 } 164 if (dcc == 0xffffffff) { 165 DRM_ERROR("Couldn't read from MCHBAR. " 166 "Disabling tiling.\n"); 167 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 168 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 169 } 170 } else { 171 /* The 965, G33, and newer, have a very flexible memory 172 * configuration. It will enable dual-channel mode 173 * (interleaving) on as much memory as it can, and the GPU 174 * will additionally sometimes enable different bit 6 175 * swizzling for tiled objects from the CPU. 176 * 177 * Here's what I found on the G965: 178 * slot fill memory size swizzling 179 * 0A 0B 1A 1B 1-ch 2-ch 180 * 512 0 0 0 512 0 O 181 * 512 0 512 0 16 1008 X 182 * 512 0 0 512 16 1008 X 183 * 0 512 0 512 16 1008 X 184 * 1024 1024 1024 0 2048 1024 O 185 * 186 * We could probably detect this based on either the DRB 187 * matching, which was the case for the swizzling required in 188 * the table above, or from the 1-ch value being less than 189 * the minimum size of a rank. 190 */ 191 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { 192 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 193 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 194 } else { 195 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 196 swizzle_y = I915_BIT_6_SWIZZLE_9; 197 } 198 } 199 200 dev_priv->mm.bit_6_swizzle_x = swizzle_x; 201 dev_priv->mm.bit_6_swizzle_y = swizzle_y; 202 } 203 204 /* Check pitch constriants for all chips & tiling formats */ 205 static bool 206 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) 207 { 208 int tile_width; 209 210 /* Linear is always fine */ 211 if (tiling_mode == I915_TILING_NONE) 212 return true; 213 214 if (IS_GEN2(dev) || 215 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) 216 tile_width = 128; 217 else 218 tile_width = 512; 219 220 /* check maximum stride & object size */ 221 if (INTEL_INFO(dev)->gen >= 4) { 222 /* i965 stores the end address of the gtt mapping in the fence 223 * reg, so dont bother to check the size */ 224 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) 225 return false; 226 } else { 227 if (stride > 8192) 228 return false; 229 230 if (IS_GEN3(dev)) { 231 if (size > I830_FENCE_MAX_SIZE_VAL << 20) 232 return false; 233 } else { 234 if (size > I830_FENCE_MAX_SIZE_VAL << 19) 235 return false; 236 } 237 } 238 239 /* 965+ just needs multiples of tile width */ 240 if (INTEL_INFO(dev)->gen >= 4) { 241 if (stride & (tile_width - 1)) 242 return false; 243 return true; 244 } 245 246 /* Pre-965 needs power of two tile widths */ 247 if (stride < tile_width) 248 return false; 249 250 if (stride & (stride - 1)) 251 return false; 252 253 return true; 254 } 255 256 /* Is the current GTT allocation valid for the change in tiling? */ 257 static bool 258 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) 259 { 260 u32 size; 261 262 if (tiling_mode == I915_TILING_NONE) 263 return true; 264 265 if (INTEL_INFO(obj->base.dev)->gen >= 4) 266 return true; 267 268 if (INTEL_INFO(obj->base.dev)->gen == 3) { 269 if (obj->gtt_offset & ~I915_FENCE_START_MASK) 270 return false; 271 } else { 272 if (obj->gtt_offset & ~I830_FENCE_START_MASK) 273 return false; 274 } 275 276 /* 277 * Previous chips need to be aligned to the size of the smallest 278 * fence register that can contain the object. 279 */ 280 if (INTEL_INFO(obj->base.dev)->gen == 3) 281 size = 1024*1024; 282 else 283 size = 512*1024; 284 285 while (size < obj->base.size) 286 size <<= 1; 287 288 if (obj->gtt_space->size != size) 289 return false; 290 291 if (obj->gtt_offset & (size - 1)) 292 return false; 293 294 return true; 295 } 296 297 /** 298 * Sets the tiling mode of an object, returning the required swizzling of 299 * bit 6 of addresses in the object. 300 */ 301 int 302 i915_gem_set_tiling(struct drm_device *dev, void *data, 303 struct drm_file *file) 304 { 305 struct drm_i915_gem_set_tiling *args = data; 306 drm_i915_private_t *dev_priv = dev->dev_private; 307 struct drm_i915_gem_object *obj; 308 int ret = 0; 309 310 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 311 if (&obj->base == NULL) 312 return -ENOENT; 313 314 if (!i915_tiling_ok(dev, 315 args->stride, obj->base.size, args->tiling_mode)) { 316 drm_gem_object_unreference_unlocked(&obj->base); 317 return -EINVAL; 318 } 319 320 if (obj->pin_count) { 321 drm_gem_object_unreference_unlocked(&obj->base); 322 return -EBUSY; 323 } 324 325 if (args->tiling_mode == I915_TILING_NONE) { 326 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 327 args->stride = 0; 328 } else { 329 if (args->tiling_mode == I915_TILING_X) 330 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; 331 else 332 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; 333 334 /* Hide bit 17 swizzling from the user. This prevents old Mesa 335 * from aborting the application on sw fallbacks to bit 17, 336 * and we use the pread/pwrite bit17 paths to swizzle for it. 337 * If there was a user that was relying on the swizzle 338 * information for drm_intel_bo_map()ed reads/writes this would 339 * break it, but we don't have any of those. 340 */ 341 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) 342 args->swizzle_mode = I915_BIT_6_SWIZZLE_9; 343 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) 344 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; 345 346 /* If we can't handle the swizzling, make it untiled. */ 347 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { 348 args->tiling_mode = I915_TILING_NONE; 349 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 350 args->stride = 0; 351 } 352 } 353 354 DRM_LOCK(dev); 355 if (args->tiling_mode != obj->tiling_mode || 356 args->stride != obj->stride) { 357 /* We need to rebind the object if its current allocation 358 * no longer meets the alignment restrictions for its new 359 * tiling mode. Otherwise we can just leave it alone, but 360 * need to ensure that any fence register is cleared. 361 * 362 * After updating the tiling parameters, we then flag whether 363 * we need to update an associated fence register. Note this 364 * has to also include the unfenced register the GPU uses 365 * whilst executing a fenced command for an untiled object. 366 */ 367 i915_gem_release_mmap(obj); 368 369 obj->map_and_fenceable = 370 obj->gtt_space == NULL || 371 (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && 372 i915_gem_object_fence_ok(obj, args->tiling_mode)); 373 374 /* Rebind if we need a change of alignment */ 375 if (!obj->map_and_fenceable) { 376 u32 unfenced_alignment = 377 i915_gem_get_unfenced_gtt_alignment(dev, 378 obj->base.size, 379 args->tiling_mode); 380 if (obj->gtt_offset & (unfenced_alignment - 1)) 381 ret = i915_gem_object_unbind(obj); 382 } 383 384 if (ret == 0) { 385 obj->fence_dirty = 386 obj->fenced_gpu_access || 387 obj->fence_reg != I915_FENCE_REG_NONE; 388 389 obj->tiling_mode = args->tiling_mode; 390 obj->stride = args->stride; 391 } 392 } 393 /* we have to maintain this existing ABI... */ 394 args->stride = obj->stride; 395 args->tiling_mode = obj->tiling_mode; 396 drm_gem_object_unreference(&obj->base); 397 DRM_UNLOCK(dev); 398 399 return ret; 400 } 401 402 /** 403 * Returns the current tiling mode and required bit 6 swizzling for the object. 404 */ 405 int 406 i915_gem_get_tiling(struct drm_device *dev, void *data, 407 struct drm_file *file) 408 { 409 struct drm_i915_gem_get_tiling *args = data; 410 drm_i915_private_t *dev_priv = dev->dev_private; 411 struct drm_i915_gem_object *obj; 412 413 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 414 if (&obj->base == NULL) 415 return -ENOENT; 416 417 DRM_LOCK(dev); 418 419 args->tiling_mode = obj->tiling_mode; 420 switch (obj->tiling_mode) { 421 case I915_TILING_X: 422 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; 423 break; 424 case I915_TILING_Y: 425 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; 426 break; 427 case I915_TILING_NONE: 428 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 429 break; 430 default: 431 DRM_ERROR("unknown tiling mode\n"); 432 } 433 434 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ 435 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) 436 args->swizzle_mode = I915_BIT_6_SWIZZLE_9; 437 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) 438 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; 439 440 drm_gem_object_unreference(&obj->base); 441 DRM_UNLOCK(dev); 442 443 return 0; 444 } 445 446 /** 447 * Swap every 64 bytes of this page around, to account for it having a new 448 * bit 17 of its physical address and therefore being interpreted differently 449 * by the GPU. 450 */ 451 static void 452 i915_gem_swizzle_page(vm_page_t m) 453 { 454 char temp[64]; 455 char *vaddr; 456 struct sf_buf *sf; 457 int i; 458 459 /* XXXKIB sleep */ 460 sf = sf_buf_alloc(m); 461 vaddr = (char *)sf_buf_kva(sf); 462 463 for (i = 0; i < PAGE_SIZE; i += 128) { 464 memcpy(temp, &vaddr[i], 64); 465 memcpy(&vaddr[i], &vaddr[i + 64], 64); 466 memcpy(&vaddr[i + 64], temp, 64); 467 } 468 469 sf_buf_free(sf); 470 } 471 472 void 473 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj) 474 { 475 int page_count = obj->base.size >> PAGE_SHIFT; 476 int i; 477 478 if (obj->bit_17 == NULL) 479 return; 480 481 for (i = 0; i < page_count; i++) { 482 char new_bit_17 = VM_PAGE_TO_PHYS(obj->pages[i]) >> 17; 483 if ((new_bit_17 & 0x1) != 484 (test_bit(i, obj->bit_17) != 0)) { 485 i915_gem_swizzle_page(obj->pages[i]); 486 vm_page_dirty(obj->pages[i]); 487 } 488 } 489 } 490 491 void 492 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj) 493 { 494 int page_count = obj->base.size >> PAGE_SHIFT; 495 int i; 496 497 if (obj->bit_17 == NULL) { 498 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * 499 sizeof(long), DRM_I915_GEM, M_WAITOK); 500 if (obj->bit_17 == NULL) { 501 DRM_ERROR("Failed to allocate memory for bit 17 " 502 "record\n"); 503 return; 504 } 505 } 506 507 /* XXXKIB: review locking, atomics might be not needed there */ 508 for (i = 0; i < page_count; i++) { 509 if (VM_PAGE_TO_PHYS(obj->pages[i]) & (1 << 17)) 510 set_bit(i, obj->bit_17); 511 else 512 clear_bit(i, obj->bit_17); 513 } 514 } 515