1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * $FreeBSD: src/sys/dev/drm2/i915/i915_gem_tiling.c,v 1.1 2012/05/22 11:07:44 kib Exp $ 27 */ 28 29 #include <sys/sfbuf.h> 30 31 #include <drm/drmP.h> 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 35 /** @file i915_gem_tiling.c 36 * 37 * Support for managing tiling state of buffer objects. 38 * 39 * The idea behind tiling is to increase cache hit rates by rearranging 40 * pixel data so that a group of pixel accesses are in the same cacheline. 41 * Performance improvement from doing this on the back/depth buffer are on 42 * the order of 30%. 43 * 44 * Intel architectures make this somewhat more complicated, though, by 45 * adjustments made to addressing of data when the memory is in interleaved 46 * mode (matched pairs of DIMMS) to improve memory bandwidth. 47 * For interleaved memory, the CPU sends every sequential 64 bytes 48 * to an alternate memory channel so it can get the bandwidth from both. 49 * 50 * The GPU also rearranges its accesses for increased bandwidth to interleaved 51 * memory, and it matches what the CPU does for non-tiled. However, when tiled 52 * it does it a little differently, since one walks addresses not just in the 53 * X direction but also Y. So, along with alternating channels when bit 54 * 6 of the address flips, it also alternates when other bits flip -- Bits 9 55 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) 56 * are common to both the 915 and 965-class hardware. 57 * 58 * The CPU also sometimes XORs in higher bits as well, to improve 59 * bandwidth doing strided access like we do so frequently in graphics. This 60 * is called "Channel XOR Randomization" in the MCH documentation. The result 61 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address 62 * decode. 63 * 64 * All of this bit 6 XORing has an effect on our memory management, 65 * as we need to make sure that the 3d driver can correctly address object 66 * contents. 67 * 68 * If we don't have interleaved memory, all tiling is safe and no swizzling is 69 * required. 70 * 71 * When bit 17 is XORed in, we simply refuse to tile at all. Bit 72 * 17 is not just a page offset, so as we page an objet out and back in, 73 * individual pages in it will have different bit 17 addresses, resulting in 74 * each 64 bytes being swapped with its neighbor! 75 * 76 * Otherwise, if interleaved, we have to tell the 3d driver what the address 77 * swizzling it needs to do is, since it's writing with the CPU to the pages 78 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the 79 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling 80 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order 81 * to match what the GPU expects. 82 */ 83 84 /** 85 * Detects bit 6 swizzling of address lookup between IGD access and CPU 86 * access through main memory. 87 */ 88 void 89 i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 90 { 91 drm_i915_private_t *dev_priv = dev->dev_private; 92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 94 95 if (INTEL_INFO(dev)->gen >= 6) { 96 uint32_t dimm_c0, dimm_c1; 97 dimm_c0 = I915_READ(MAD_DIMM_C0); 98 dimm_c1 = I915_READ(MAD_DIMM_C1); 99 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; 100 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK; 101 /* Enable swizzling when the channels are populated with 102 * identically sized dimms. We don't need to check the 3rd 103 * channel because no cpu with gpu attached ships in that 104 * configuration. Also, swizzling only makes sense for 2 105 * channels anyway. */ 106 if (dimm_c0 == dimm_c1) { 107 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 108 swizzle_y = I915_BIT_6_SWIZZLE_9; 109 } else { 110 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 111 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 112 } 113 } else if (IS_GEN5(dev)) { 114 /* On Ironlake whatever DRAM config, GPU always do 115 * same swizzling setup. 116 */ 117 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 118 swizzle_y = I915_BIT_6_SWIZZLE_9; 119 } else if (IS_GEN2(dev)) { 120 /* As far as we know, the 865 doesn't have these bit 6 121 * swizzling issues. 122 */ 123 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 124 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 125 } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) { 126 uint32_t dcc; 127 128 /* On 9xx chipsets, channel interleave by the CPU is 129 * determined by DCC. For single-channel, neither the CPU 130 * nor the GPU do swizzling. For dual channel interleaved, 131 * the GPU's interleave is bit 9 and 10 for X tiled, and bit 132 * 9 for Y tiled. The CPU's interleave is independent, and 133 * can be based on either bit 11 (haven't seen this yet) or 134 * bit 17 (common). 135 */ 136 dcc = I915_READ(DCC); 137 switch (dcc & DCC_ADDRESSING_MODE_MASK) { 138 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: 139 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: 140 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 141 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 142 break; 143 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: 144 if (dcc & DCC_CHANNEL_XOR_DISABLE) { 145 /* This is the base swizzling by the GPU for 146 * tiled buffers. 147 */ 148 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 149 swizzle_y = I915_BIT_6_SWIZZLE_9; 150 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { 151 /* Bit 11 swizzling by the CPU in addition. */ 152 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; 153 swizzle_y = I915_BIT_6_SWIZZLE_9_11; 154 } else { 155 /* Bit 17 swizzling by the CPU in addition. */ 156 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; 157 swizzle_y = I915_BIT_6_SWIZZLE_9_17; 158 } 159 break; 160 } 161 if (dcc == 0xffffffff) { 162 DRM_ERROR("Couldn't read from MCHBAR. " 163 "Disabling tiling.\n"); 164 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 165 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 166 } 167 } else { 168 /* The 965, G33, and newer, have a very flexible memory 169 * configuration. It will enable dual-channel mode 170 * (interleaving) on as much memory as it can, and the GPU 171 * will additionally sometimes enable different bit 6 172 * swizzling for tiled objects from the CPU. 173 * 174 * Here's what I found on the G965: 175 * slot fill memory size swizzling 176 * 0A 0B 1A 1B 1-ch 2-ch 177 * 512 0 0 0 512 0 O 178 * 512 0 512 0 16 1008 X 179 * 512 0 0 512 16 1008 X 180 * 0 512 0 512 16 1008 X 181 * 1024 1024 1024 0 2048 1024 O 182 * 183 * We could probably detect this based on either the DRB 184 * matching, which was the case for the swizzling required in 185 * the table above, or from the 1-ch value being less than 186 * the minimum size of a rank. 187 */ 188 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { 189 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 190 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 191 } else { 192 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 193 swizzle_y = I915_BIT_6_SWIZZLE_9; 194 } 195 } 196 197 dev_priv->mm.bit_6_swizzle_x = swizzle_x; 198 dev_priv->mm.bit_6_swizzle_y = swizzle_y; 199 } 200 201 /* Check pitch constriants for all chips & tiling formats */ 202 static bool 203 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) 204 { 205 int tile_width; 206 207 /* Linear is always fine */ 208 if (tiling_mode == I915_TILING_NONE) 209 return (true); 210 211 if (IS_GEN2(dev) || 212 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) 213 tile_width = 128; 214 else 215 tile_width = 512; 216 217 /* check maximum stride & object size */ 218 if (INTEL_INFO(dev)->gen >= 4) { 219 /* i965 stores the end address of the gtt mapping in the fence 220 * reg, so dont bother to check the size */ 221 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) 222 return (false); 223 } else { 224 if (stride > 8192) 225 return (false); 226 227 if (IS_GEN3(dev)) { 228 if (size > I830_FENCE_MAX_SIZE_VAL << 20) 229 return (false); 230 } else { 231 if (size > I830_FENCE_MAX_SIZE_VAL << 19) 232 return (false); 233 } 234 } 235 236 /* 965+ just needs multiples of tile width */ 237 if (INTEL_INFO(dev)->gen >= 4) { 238 if (stride & (tile_width - 1)) 239 return (false); 240 return (true); 241 } 242 243 /* Pre-965 needs power of two tile widths */ 244 if (stride < tile_width) 245 return (false); 246 247 if (stride & (stride - 1)) 248 return (false); 249 250 return (true); 251 } 252 253 /* Is the current GTT allocation valid for the change in tiling? */ 254 static bool 255 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) 256 { 257 u32 size; 258 259 if (tiling_mode == I915_TILING_NONE) 260 return (true); 261 262 if (INTEL_INFO(obj->base.dev)->gen >= 4) 263 return (true); 264 265 if (INTEL_INFO(obj->base.dev)->gen == 3) { 266 if (obj->gtt_offset & ~I915_FENCE_START_MASK) 267 return (false); 268 } else { 269 if (obj->gtt_offset & ~I830_FENCE_START_MASK) 270 return (false); 271 } 272 273 /* 274 * Previous chips need to be aligned to the size of the smallest 275 * fence register that can contain the object. 276 */ 277 if (INTEL_INFO(obj->base.dev)->gen == 3) 278 size = 1024*1024; 279 else 280 size = 512*1024; 281 282 while (size < obj->base.size) 283 size <<= 1; 284 285 if (obj->gtt_space->size != size) 286 return (false); 287 288 if (obj->gtt_offset & (size - 1)) 289 return (false); 290 291 return (true); 292 } 293 294 /** 295 * Sets the tiling mode of an object, returning the required swizzling of 296 * bit 6 of addresses in the object. 297 */ 298 int 299 i915_gem_set_tiling(struct drm_device *dev, void *data, 300 struct drm_file *file) 301 { 302 struct drm_i915_gem_set_tiling *args = data; 303 drm_i915_private_t *dev_priv = dev->dev_private; 304 struct drm_i915_gem_object *obj; 305 int ret; 306 307 ret = 0; 308 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 309 if (&obj->base == NULL) 310 return -ENOENT; 311 312 if (!i915_tiling_ok(dev, 313 args->stride, obj->base.size, args->tiling_mode)) { 314 drm_gem_object_unreference(&obj->base); 315 return -EINVAL; 316 } 317 318 if (obj->pin_count) { 319 drm_gem_object_unreference(&obj->base); 320 return -EBUSY; 321 } 322 323 if (args->tiling_mode == I915_TILING_NONE) { 324 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 325 args->stride = 0; 326 } else { 327 if (args->tiling_mode == I915_TILING_X) 328 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; 329 else 330 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; 331 332 /* Hide bit 17 swizzling from the user. This prevents old Mesa 333 * from aborting the application on sw fallbacks to bit 17, 334 * and we use the pread/pwrite bit17 paths to swizzle for it. 335 * If there was a user that was relying on the swizzle 336 * information for drm_intel_bo_map()ed reads/writes this would 337 * break it, but we don't have any of those. 338 */ 339 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) 340 args->swizzle_mode = I915_BIT_6_SWIZZLE_9; 341 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) 342 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; 343 344 /* If we can't handle the swizzling, make it untiled. */ 345 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { 346 args->tiling_mode = I915_TILING_NONE; 347 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 348 args->stride = 0; 349 } 350 } 351 352 if (args->tiling_mode != obj->tiling_mode || 353 args->stride != obj->stride) { 354 /* We need to rebind the object if its current allocation 355 * no longer meets the alignment restrictions for its new 356 * tiling mode. Otherwise we can just leave it alone, but 357 * need to ensure that any fence register is cleared. 358 */ 359 i915_gem_release_mmap(obj); 360 361 obj->map_and_fenceable = obj->gtt_space == NULL || 362 (obj->gtt_offset + obj->base.size <= 363 dev_priv->mm.gtt_mappable_end && 364 i915_gem_object_fence_ok(obj, args->tiling_mode)); 365 366 /* Rebind if we need a change of alignment */ 367 if (!obj->map_and_fenceable) { 368 uint32_t unfenced_alignment = 369 i915_gem_get_unfenced_gtt_alignment(dev, 370 obj->base.size, args->tiling_mode); 371 if (obj->gtt_offset & (unfenced_alignment - 1)) 372 ret = i915_gem_object_unbind(obj); 373 } 374 if (ret == 0) { 375 obj->tiling_changed = true; 376 obj->tiling_mode = args->tiling_mode; 377 obj->stride = args->stride; 378 } 379 } 380 /* we have to maintain this existing ABI... */ 381 args->stride = obj->stride; 382 args->tiling_mode = obj->tiling_mode; 383 drm_gem_object_unreference(&obj->base); 384 385 return (ret); 386 } 387 388 /** 389 * Returns the current tiling mode and required bit 6 swizzling for the object. 390 */ 391 int 392 i915_gem_get_tiling(struct drm_device *dev, void *data, 393 struct drm_file *file) 394 { 395 struct drm_i915_gem_get_tiling *args = data; 396 drm_i915_private_t *dev_priv = dev->dev_private; 397 struct drm_i915_gem_object *obj; 398 399 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 400 if (&obj->base == NULL) 401 return -ENOENT; 402 403 args->tiling_mode = obj->tiling_mode; 404 switch (obj->tiling_mode) { 405 case I915_TILING_X: 406 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; 407 break; 408 case I915_TILING_Y: 409 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; 410 break; 411 case I915_TILING_NONE: 412 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 413 break; 414 default: 415 DRM_ERROR("unknown tiling mode\n"); 416 } 417 418 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ 419 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) 420 args->swizzle_mode = I915_BIT_6_SWIZZLE_9; 421 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) 422 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; 423 424 drm_gem_object_unreference(&obj->base); 425 426 return 0; 427 } 428 429 /** 430 * Swap every 64 bytes of this page around, to account for it having a new 431 * bit 17 of its physical address and therefore being interpreted differently 432 * by the GPU. 433 */ 434 static void 435 i915_gem_swizzle_page(vm_page_t m) 436 { 437 char temp[64]; 438 char *vaddr; 439 struct sf_buf *sf; 440 int i; 441 442 /* XXXKIB sleep */ 443 sf = sf_buf_alloc(m); 444 vaddr = (char *)sf_buf_kva(sf); 445 446 for (i = 0; i < PAGE_SIZE; i += 128) { 447 memcpy(temp, &vaddr[i], 64); 448 memcpy(&vaddr[i], &vaddr[i + 64], 64); 449 memcpy(&vaddr[i + 64], temp, 64); 450 } 451 452 sf_buf_free(sf); 453 } 454 455 void 456 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj) 457 { 458 int page_count = obj->base.size >> PAGE_SHIFT; 459 int i; 460 461 if (obj->bit_17 == NULL) 462 return; 463 464 for (i = 0; i < page_count; i++) { 465 char new_bit_17 = VM_PAGE_TO_PHYS(obj->pages[i]) >> 17; 466 if ((new_bit_17 & 0x1) != 467 (test_bit(i, obj->bit_17) != 0)) { 468 i915_gem_swizzle_page(obj->pages[i]); 469 vm_page_dirty(obj->pages[i]); 470 } 471 } 472 } 473 474 void 475 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj) 476 { 477 int page_count = obj->base.size >> PAGE_SHIFT; 478 int i; 479 480 if (obj->bit_17 == NULL) { 481 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * 482 sizeof(long), DRM_I915_GEM, M_WAITOK); 483 } 484 485 /* XXXKIB: review locking, atomics might be not needed there */ 486 for (i = 0; i < page_count; i++) { 487 if (VM_PAGE_TO_PHYS(obj->pages[i]) & (1 << 17)) 488 set_bit(i, obj->bit_17); 489 else 490 clear_bit(i, obj->bit_17); 491 } 492 } 493