1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 #include <linux/bitops.h> 29 #include <drm/drmP.h> 30 #include <drm/i915_drm.h> 31 #include "i915_drv.h" 32 33 /** 34 * DOC: buffer object tiling 35 * 36 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to 37 * declare fence register requirements. 38 * 39 * In principle GEM doesn't care at all about the internal data layout of an 40 * object, and hence it also doesn't care about tiling or swizzling. There's two 41 * exceptions: 42 * 43 * - For X and Y tiling the hardware provides detilers for CPU access, so called 44 * fences. Since there's only a limited amount of them the kernel must manage 45 * these, and therefore userspace must tell the kernel the object tiling if it 46 * wants to use fences for detiling. 47 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which 48 * depends upon the physical page frame number. When swapping such objects the 49 * page frame number might change and the kernel must be able to fix this up 50 * and hence now the tiling. Note that on a subset of platforms with 51 * asymmetric memory channel population the swizzling pattern changes in an 52 * unknown way, and for those the kernel simply forbids swapping completely. 53 * 54 * Since neither of this applies for new tiling layouts on modern platforms like 55 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. 56 * Anything else can be handled in userspace entirely without the kernel's 57 * invovlement. 58 */ 59 60 /* Check pitch constriants for all chips & tiling formats */ 61 static bool 62 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) 63 { 64 int tile_width; 65 66 /* Linear is always fine */ 67 if (tiling_mode == I915_TILING_NONE) 68 return true; 69 70 if (IS_GEN2(dev) || 71 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) 72 tile_width = 128; 73 else 74 tile_width = 512; 75 76 /* check maximum stride & object size */ 77 /* i965+ stores the end address of the gtt mapping in the fence 78 * reg, so dont bother to check the size */ 79 if (INTEL_INFO(dev)->gen >= 7) { 80 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) 81 return false; 82 } else if (INTEL_INFO(dev)->gen >= 4) { 83 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) 84 return false; 85 } else { 86 if (stride > 8192) 87 return false; 88 89 if (IS_GEN3(dev)) { 90 if (size > I830_FENCE_MAX_SIZE_VAL << 20) 91 return false; 92 } else { 93 if (size > I830_FENCE_MAX_SIZE_VAL << 19) 94 return false; 95 } 96 } 97 98 if (stride < tile_width) 99 return false; 100 101 /* 965+ just needs multiples of tile width */ 102 if (INTEL_INFO(dev)->gen >= 4) { 103 if (stride & (tile_width - 1)) 104 return false; 105 return true; 106 } 107 108 /* Pre-965 needs power of two tile widths */ 109 if (stride & (stride - 1)) 110 return false; 111 112 return true; 113 } 114 115 /* Is the current GTT allocation valid for the change in tiling? */ 116 static bool 117 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) 118 { 119 u32 size; 120 121 if (tiling_mode == I915_TILING_NONE) 122 return true; 123 124 if (INTEL_INFO(obj->base.dev)->gen >= 4) 125 return true; 126 127 if (INTEL_INFO(obj->base.dev)->gen == 3) { 128 if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) 129 return false; 130 } else { 131 if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) 132 return false; 133 } 134 135 size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); 136 if (i915_gem_obj_ggtt_size(obj) != size) 137 return false; 138 139 if (i915_gem_obj_ggtt_offset(obj) & (size - 1)) 140 return false; 141 142 return true; 143 } 144 145 /** 146 * i915_gem_set_tiling - IOCTL handler to set tiling mode 147 * @dev: DRM device 148 * @data: data pointer for the ioctl 149 * @file: DRM file for the ioctl call 150 * 151 * Sets the tiling mode of an object, returning the required swizzling of 152 * bit 6 of addresses in the object. 153 * 154 * Called by the user via ioctl. 155 * 156 * Returns: 157 * Zero on success, negative errno on failure. 158 */ 159 int 160 i915_gem_set_tiling(struct drm_device *dev, void *data, 161 struct drm_file *file) 162 { 163 struct drm_i915_gem_set_tiling *args = data; 164 struct drm_i915_private *dev_priv = dev->dev_private; 165 struct drm_i915_gem_object *obj; 166 int ret = 0; 167 168 obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); 169 if (&obj->base == NULL) 170 return -ENOENT; 171 172 if (!i915_tiling_ok(dev, 173 args->stride, obj->base.size, args->tiling_mode)) { 174 drm_gem_object_unreference_unlocked(&obj->base); 175 return -EINVAL; 176 } 177 178 intel_runtime_pm_get(dev_priv); 179 180 mutex_lock(&dev->struct_mutex); 181 if (obj->pin_display || obj->framebuffer_references) { 182 ret = -EBUSY; 183 goto err; 184 } 185 186 if (args->tiling_mode == I915_TILING_NONE) { 187 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 188 args->stride = 0; 189 } else { 190 if (args->tiling_mode == I915_TILING_X) 191 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; 192 else 193 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; 194 195 /* Hide bit 17 swizzling from the user. This prevents old Mesa 196 * from aborting the application on sw fallbacks to bit 17, 197 * and we use the pread/pwrite bit17 paths to swizzle for it. 198 * If there was a user that was relying on the swizzle 199 * information for drm_intel_bo_map()ed reads/writes this would 200 * break it, but we don't have any of those. 201 */ 202 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) 203 args->swizzle_mode = I915_BIT_6_SWIZZLE_9; 204 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) 205 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; 206 207 /* If we can't handle the swizzling, make it untiled. */ 208 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { 209 args->tiling_mode = I915_TILING_NONE; 210 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 211 args->stride = 0; 212 } 213 } 214 215 if (args->tiling_mode != obj->tiling_mode || 216 args->stride != obj->stride) { 217 /* We need to rebind the object if its current allocation 218 * no longer meets the alignment restrictions for its new 219 * tiling mode. Otherwise we can just leave it alone, but 220 * need to ensure that any fence register is updated before 221 * the next fenced (either through the GTT or by the BLT unit 222 * on older GPUs) access. 223 * 224 * After updating the tiling parameters, we then flag whether 225 * we need to update an associated fence register. Note this 226 * has to also include the unfenced register the GPU uses 227 * whilst executing a fenced command for an untiled object. 228 */ 229 if (obj->map_and_fenceable && 230 !i915_gem_object_fence_ok(obj, args->tiling_mode)) 231 ret = i915_gem_object_ggtt_unbind(obj); 232 233 if (ret == 0) { 234 if (obj->pages && 235 obj->madv == I915_MADV_WILLNEED && 236 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { 237 if (args->tiling_mode == I915_TILING_NONE) 238 i915_gem_object_unpin_pages(obj); 239 if (obj->tiling_mode == I915_TILING_NONE) 240 i915_gem_object_pin_pages(obj); 241 } 242 243 obj->fence_dirty = 244 obj->last_fenced_req || 245 obj->fence_reg != I915_FENCE_REG_NONE; 246 247 obj->tiling_mode = args->tiling_mode; 248 obj->stride = args->stride; 249 250 /* Force the fence to be reacquired for GTT access */ 251 i915_gem_release_mmap(obj); 252 } 253 } 254 /* we have to maintain this existing ABI... */ 255 args->stride = obj->stride; 256 args->tiling_mode = obj->tiling_mode; 257 258 /* Try to preallocate memory required to save swizzling on put-pages */ 259 if (i915_gem_object_needs_bit17_swizzle(obj)) { 260 if (obj->bit_17 == NULL) { 261 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT), 262 sizeof(long), GFP_KERNEL); 263 } 264 } else { 265 kfree(obj->bit_17); 266 obj->bit_17 = NULL; 267 } 268 269 err: 270 drm_gem_object_unreference(&obj->base); 271 mutex_unlock(&dev->struct_mutex); 272 273 intel_runtime_pm_put(dev_priv); 274 275 return ret; 276 } 277 278 /** 279 * i915_gem_get_tiling - IOCTL handler to get tiling mode 280 * @dev: DRM device 281 * @data: data pointer for the ioctl 282 * @file: DRM file for the ioctl call 283 * 284 * Returns the current tiling mode and required bit 6 swizzling for the object. 285 * 286 * Called by the user via ioctl. 287 * 288 * Returns: 289 * Zero on success, negative errno on failure. 290 */ 291 int 292 i915_gem_get_tiling(struct drm_device *dev, void *data, 293 struct drm_file *file) 294 { 295 struct drm_i915_gem_get_tiling *args = data; 296 struct drm_i915_private *dev_priv = dev->dev_private; 297 struct drm_i915_gem_object *obj; 298 299 obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); 300 if (&obj->base == NULL) 301 return -ENOENT; 302 303 mutex_lock(&dev->struct_mutex); 304 305 args->tiling_mode = obj->tiling_mode; 306 switch (obj->tiling_mode) { 307 case I915_TILING_X: 308 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; 309 break; 310 case I915_TILING_Y: 311 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; 312 break; 313 case I915_TILING_NONE: 314 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 315 break; 316 default: 317 DRM_ERROR("unknown tiling mode\n"); 318 } 319 320 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ 321 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 322 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN; 323 else 324 args->phys_swizzle_mode = args->swizzle_mode; 325 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) 326 args->swizzle_mode = I915_BIT_6_SWIZZLE_9; 327 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) 328 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; 329 330 drm_gem_object_unreference(&obj->base); 331 mutex_unlock(&dev->struct_mutex); 332 333 return 0; 334 } 335