1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #ifndef _I915_GUC_REG_H_ 25 #define _I915_GUC_REG_H_ 26 27 /* Definitions of GuC H/W registers, bits, etc */ 28 29 #define GUC_STATUS _MMIO(0xc000) 30 #define GS_RESET_SHIFT 0 31 #define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT) 32 #define GS_BOOTROM_SHIFT 1 33 #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT) 34 #define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT) 35 #define GS_BOOTROM_JUMP_PASSED (0x76 << GS_BOOTROM_SHIFT) 36 #define GS_UKERNEL_SHIFT 8 37 #define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT) 38 #define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT) 39 #define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT) 40 #define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT) 41 #define GS_MIA_SHIFT 16 42 #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT) 43 #define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT) 44 #define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT) 45 #define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT) 46 #define GS_AUTH_STATUS_SHIFT 30 47 #define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT) 48 #define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT) 49 #define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT) 50 51 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) 52 #define SOFT_SCRATCH_COUNT 16 53 54 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) 55 #define UOS_RSA_SCRATCH_MAX_COUNT 64 56 #define DMA_ADDR_0_LOW _MMIO(0xc300) 57 #define DMA_ADDR_0_HIGH _MMIO(0xc304) 58 #define DMA_ADDR_1_LOW _MMIO(0xc308) 59 #define DMA_ADDR_1_HIGH _MMIO(0xc30c) 60 #define DMA_ADDRESS_SPACE_WOPCM (7 << 16) 61 #define DMA_ADDRESS_SPACE_GTT (8 << 16) 62 #define DMA_COPY_SIZE _MMIO(0xc310) 63 #define DMA_CTRL _MMIO(0xc314) 64 #define HUC_UKERNEL (1<<9) 65 #define UOS_MOVE (1<<4) 66 #define START_DMA (1<<0) 67 #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340) 68 #define HUC_LOADING_AGENT_VCR (0<<1) 69 #define HUC_LOADING_AGENT_GUC (1<<1) 70 #define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */ 71 #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4) 72 73 #define HUC_STATUS2 _MMIO(0xD3B0) 74 #define HUC_FW_VERIFIED (1<<7) 75 76 /* Defines WOPCM space available to GuC firmware */ 77 #define GUC_WOPCM_SIZE _MMIO(0xc050) 78 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */ 79 #define GUC_WOPCM_TOP (0x80 << 12) /* 512KB */ 80 #define BXT_GUC_WOPCM_RC6_RESERVED (0x10 << 12) /* 64KB */ 81 82 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ 83 #define GUC_GGTT_TOP 0xFEE00000 84 85 #define GEN8_GT_PM_CONFIG _MMIO(0x138140) 86 #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140) 87 #define GEN9_GT_PM_CONFIG _MMIO(0x13816c) 88 #define GT_DOORBELL_ENABLE (1<<0) 89 90 #define GEN8_GTCR _MMIO(0x4274) 91 #define GEN8_GTCR_INVALIDATE (1<<0) 92 93 #define GUC_ARAT_C6DIS _MMIO(0xA178) 94 95 #define GUC_SHIM_CONTROL _MMIO(0xc064) 96 #define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0) 97 #define GUC_ENABLE_READ_CACHE_LOGIC (1<<1) 98 #define GUC_ENABLE_MIA_CACHING (1<<2) 99 #define GUC_GEN10_MSGCH_ENABLE (1<<4) 100 #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9) 101 #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10) 102 #define GUC_ENABLE_MIA_CLOCK_GATING (1<<15) 103 #define GUC_GEN10_SHIM_WC_ENABLE (1<<21) 104 105 #define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES | \ 106 GUC_ENABLE_READ_CACHE_LOGIC | \ 107 GUC_ENABLE_MIA_CACHING | \ 108 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | \ 109 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | \ 110 GUC_ENABLE_MIA_CLOCK_GATING) 111 112 #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) 113 #define GUC_SEND_TRIGGER (1<<0) 114 115 #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8) 116 #define GEN8_DRB_VALID (1<<0) 117 #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4) 118 119 #define DE_GUCRMR _MMIO(0x44054) 120 121 #define GUC_BCS_RCS_IER _MMIO(0xC550) 122 #define GUC_VCS2_VCS1_IER _MMIO(0xC554) 123 #define GUC_WD_VECS_IER _MMIO(0xC558) 124 #define GUC_PM_P24C_IER _MMIO(0xC55C) 125 126 #endif 127