1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/circ_buf.h> 25 #include "i915_drv.h" 26 #include "intel_uc.h" 27 28 #include <trace/events/dma_fence.h> 29 30 /** 31 * DOC: GuC-based command submission 32 * 33 * GuC client: 34 * A i915_guc_client refers to a submission path through GuC. Currently, there 35 * is only one of these (the execbuf_client) and this one is charged with all 36 * submissions to the GuC. This struct is the owner of a doorbell, a process 37 * descriptor and a workqueue (all of them inside a single gem object that 38 * contains all required pages for these elements). 39 * 40 * GuC stage descriptor: 41 * During initialization, the driver allocates a static pool of 1024 such 42 * descriptors, and shares them with the GuC. 43 * Currently, there exists a 1:1 mapping between a i915_guc_client and a 44 * guc_stage_desc (via the client's stage_id), so effectively only one 45 * gets used. This stage descriptor lets the GuC know about the doorbell, 46 * workqueue and process descriptor. Theoretically, it also lets the GuC 47 * know about our HW contexts (context ID, etc...), but we actually 48 * employ a kind of submission where the GuC uses the LRCA sent via the work 49 * item instead (the single guc_stage_desc associated to execbuf client 50 * contains information about the default kernel context only, but this is 51 * essentially unused). This is called a "proxy" submission. 52 * 53 * The Scratch registers: 54 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes 55 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then 56 * triggers an interrupt on the GuC via another register write (0xC4C8). 57 * Firmware writes a success/fail code back to the action register after 58 * processes the request. The kernel driver polls waiting for this update and 59 * then proceeds. 60 * See intel_guc_send() 61 * 62 * Doorbells: 63 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) 64 * mapped into process space. 65 * 66 * Work Items: 67 * There are several types of work items that the host may place into a 68 * workqueue, each with its own requirements and limitations. Currently only 69 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which 70 * represents in-order queue. The kernel driver packs ring tail pointer and an 71 * ELSP context descriptor dword into Work Item. 72 * See guc_wq_item_append() 73 * 74 * ADS: 75 * The Additional Data Struct (ADS) has pointers for different buffers used by 76 * the GuC. One single gem object contains the ADS struct itself (guc_ads), the 77 * scheduling policies (guc_policies), a structure describing a collection of 78 * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save 79 * its internal state for sleep. 80 * 81 */ 82 83 static inline bool is_high_priority(struct i915_guc_client* client) 84 { 85 return client->priority <= GUC_CLIENT_PRIORITY_HIGH; 86 } 87 88 static int __reserve_doorbell(struct i915_guc_client *client) 89 { 90 unsigned long offset; 91 unsigned long end; 92 u16 id; 93 94 GEM_BUG_ON(client->doorbell_id != GUC_DOORBELL_INVALID); 95 96 /* 97 * The bitmap tracks which doorbell registers are currently in use. 98 * It is split into two halves; the first half is used for normal 99 * priority contexts, the second half for high-priority ones. 100 */ 101 offset = 0; 102 end = GUC_NUM_DOORBELLS/2; 103 if (is_high_priority(client)) { 104 offset = end; 105 end += offset; 106 } 107 108 id = find_next_zero_bit(client->guc->doorbell_bitmap, offset, end); 109 if (id == end) 110 return -ENOSPC; 111 112 __set_bit(id, client->guc->doorbell_bitmap); 113 client->doorbell_id = id; 114 DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n", 115 client->stage_id, yesno(is_high_priority(client)), 116 id); 117 return 0; 118 } 119 120 static void __unreserve_doorbell(struct i915_guc_client *client) 121 { 122 GEM_BUG_ON(client->doorbell_id == GUC_DOORBELL_INVALID); 123 124 __clear_bit(client->doorbell_id, client->guc->doorbell_bitmap); 125 client->doorbell_id = GUC_DOORBELL_INVALID; 126 } 127 128 /* 129 * Tell the GuC to allocate or deallocate a specific doorbell 130 */ 131 132 static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id) 133 { 134 u32 action[] = { 135 INTEL_GUC_ACTION_ALLOCATE_DOORBELL, 136 stage_id 137 }; 138 139 return intel_guc_send(guc, action, ARRAY_SIZE(action)); 140 } 141 142 static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id) 143 { 144 u32 action[] = { 145 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL, 146 stage_id 147 }; 148 149 return intel_guc_send(guc, action, ARRAY_SIZE(action)); 150 } 151 152 static struct guc_stage_desc *__get_stage_desc(struct i915_guc_client *client) 153 { 154 struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr; 155 156 return &base[client->stage_id]; 157 } 158 159 /* 160 * Initialise, update, or clear doorbell data shared with the GuC 161 * 162 * These functions modify shared data and so need access to the mapped 163 * client object which contains the page being used for the doorbell 164 */ 165 166 static void __update_doorbell_desc(struct i915_guc_client *client, u16 new_id) 167 { 168 struct guc_stage_desc *desc; 169 170 /* Update the GuC's idea of the doorbell ID */ 171 desc = __get_stage_desc(client); 172 desc->db_id = new_id; 173 } 174 175 static struct guc_doorbell_info *__get_doorbell(struct i915_guc_client *client) 176 { 177 return client->vaddr + client->doorbell_offset; 178 } 179 180 static bool has_doorbell(struct i915_guc_client *client) 181 { 182 if (client->doorbell_id == GUC_DOORBELL_INVALID) 183 return false; 184 185 return test_bit(client->doorbell_id, client->guc->doorbell_bitmap); 186 } 187 188 static int __create_doorbell(struct i915_guc_client *client) 189 { 190 struct guc_doorbell_info *doorbell; 191 int err; 192 193 doorbell = __get_doorbell(client); 194 doorbell->db_status = GUC_DOORBELL_ENABLED; 195 doorbell->cookie = client->doorbell_cookie; 196 197 err = __guc_allocate_doorbell(client->guc, client->stage_id); 198 if (err) { 199 doorbell->db_status = GUC_DOORBELL_DISABLED; 200 doorbell->cookie = 0; 201 } 202 return err; 203 } 204 205 static int __destroy_doorbell(struct i915_guc_client *client) 206 { 207 struct drm_i915_private *dev_priv = guc_to_i915(client->guc); 208 struct guc_doorbell_info *doorbell; 209 u16 db_id = client->doorbell_id; 210 211 GEM_BUG_ON(db_id >= GUC_DOORBELL_INVALID); 212 213 doorbell = __get_doorbell(client); 214 doorbell->db_status = GUC_DOORBELL_DISABLED; 215 doorbell->cookie = 0; 216 217 /* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit 218 * to go to zero after updating db_status before we call the GuC to 219 * release the doorbell */ 220 if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID), 10)) 221 WARN_ONCE(true, "Doorbell never became invalid after disable\n"); 222 223 return __guc_deallocate_doorbell(client->guc, client->stage_id); 224 } 225 226 static int create_doorbell(struct i915_guc_client *client) 227 { 228 int ret; 229 230 ret = __reserve_doorbell(client); 231 if (ret) 232 return ret; 233 234 __update_doorbell_desc(client, client->doorbell_id); 235 236 ret = __create_doorbell(client); 237 if (ret) 238 goto err; 239 240 return 0; 241 242 err: 243 __update_doorbell_desc(client, GUC_DOORBELL_INVALID); 244 __unreserve_doorbell(client); 245 return ret; 246 } 247 248 static int destroy_doorbell(struct i915_guc_client *client) 249 { 250 int err; 251 252 GEM_BUG_ON(!has_doorbell(client)); 253 254 /* XXX: wait for any interrupts */ 255 /* XXX: wait for workqueue to drain */ 256 257 err = __destroy_doorbell(client); 258 if (err) 259 return err; 260 261 __update_doorbell_desc(client, GUC_DOORBELL_INVALID); 262 263 __unreserve_doorbell(client); 264 265 return 0; 266 } 267 268 static unsigned long __select_cacheline(struct intel_guc* guc) 269 { 270 unsigned long offset; 271 272 /* Doorbell uses a single cache line within a page */ 273 offset = offset_in_page(guc->db_cacheline); 274 275 /* Moving to next cache line to reduce contention */ 276 guc->db_cacheline += cache_line_size(); 277 278 DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n", 279 offset, guc->db_cacheline, cache_line_size()); 280 return offset; 281 } 282 283 static inline struct guc_process_desc * 284 __get_process_desc(struct i915_guc_client *client) 285 { 286 return client->vaddr + client->proc_desc_offset; 287 } 288 289 /* 290 * Initialise the process descriptor shared with the GuC firmware. 291 */ 292 static void guc_proc_desc_init(struct intel_guc *guc, 293 struct i915_guc_client *client) 294 { 295 struct guc_process_desc *desc; 296 297 desc = memset(__get_process_desc(client), 0, sizeof(*desc)); 298 299 /* 300 * XXX: pDoorbell and WQVBaseAddress are pointers in process address 301 * space for ring3 clients (set them as in mmap_ioctl) or kernel 302 * space for kernel clients (map on demand instead? May make debug 303 * easier to have it mapped). 304 */ 305 desc->wq_base_addr = 0; 306 desc->db_base_addr = 0; 307 308 desc->stage_id = client->stage_id; 309 desc->wq_size_bytes = client->wq_size; 310 desc->wq_status = WQ_STATUS_ACTIVE; 311 desc->priority = client->priority; 312 } 313 314 /* 315 * Initialise/clear the stage descriptor shared with the GuC firmware. 316 * 317 * This descriptor tells the GuC where (in GGTT space) to find the important 318 * data structures relating to this client (doorbell, process descriptor, 319 * write queue, etc). 320 */ 321 static void guc_stage_desc_init(struct intel_guc *guc, 322 struct i915_guc_client *client) 323 { 324 struct drm_i915_private *dev_priv = guc_to_i915(guc); 325 struct intel_engine_cs *engine; 326 struct i915_gem_context *ctx = client->owner; 327 struct guc_stage_desc *desc; 328 unsigned int tmp; 329 u32 gfx_addr; 330 331 desc = __get_stage_desc(client); 332 memset(desc, 0, sizeof(*desc)); 333 334 desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | GUC_STAGE_DESC_ATTR_KERNEL; 335 desc->stage_id = client->stage_id; 336 desc->priority = client->priority; 337 desc->db_id = client->doorbell_id; 338 339 for_each_engine_masked(engine, dev_priv, client->engines, tmp) { 340 struct intel_context *ce = &ctx->engine[engine->id]; 341 uint32_t guc_engine_id = engine->guc_id; 342 struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id]; 343 344 /* TODO: We have a design issue to be solved here. Only when we 345 * receive the first batch, we know which engine is used by the 346 * user. But here GuC expects the lrc and ring to be pinned. It 347 * is not an issue for default context, which is the only one 348 * for now who owns a GuC client. But for future owner of GuC 349 * client, need to make sure lrc is pinned prior to enter here. 350 */ 351 if (!ce->state) 352 break; /* XXX: continue? */ 353 354 /* 355 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy 356 * submission or, in other words, not using a direct submission 357 * model) the KMD's LRCA is not used for any work submission. 358 * Instead, the GuC uses the LRCA of the user mode context (see 359 * guc_wq_item_append below). 360 */ 361 lrc->context_desc = lower_32_bits(ce->lrc_desc); 362 363 /* The state page is after PPHWSP */ 364 lrc->ring_lrca = 365 guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; 366 367 /* XXX: In direct submission, the GuC wants the HW context id 368 * here. In proxy submission, it wants the stage id */ 369 lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) | 370 (guc_engine_id << GUC_ELC_ENGINE_OFFSET); 371 372 lrc->ring_begin = guc_ggtt_offset(ce->ring->vma); 373 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; 374 lrc->ring_next_free_location = lrc->ring_begin; 375 lrc->ring_current_tail_pointer_value = 0; 376 377 desc->engines_used |= (1 << guc_engine_id); 378 } 379 380 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", 381 client->engines, desc->engines_used); 382 WARN_ON(desc->engines_used == 0); 383 384 /* 385 * The doorbell, process descriptor, and workqueue are all parts 386 * of the client object, which the GuC will reference via the GGTT 387 */ 388 gfx_addr = guc_ggtt_offset(client->vma); 389 desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + 390 client->doorbell_offset; 391 desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client); 392 desc->db_trigger_uk = gfx_addr + client->doorbell_offset; 393 desc->process_desc = gfx_addr + client->proc_desc_offset; 394 desc->wq_addr = gfx_addr + client->wq_offset; 395 desc->wq_size = client->wq_size; 396 397 desc->desc_private = (uintptr_t)client; 398 } 399 400 static void guc_stage_desc_fini(struct intel_guc *guc, 401 struct i915_guc_client *client) 402 { 403 struct guc_stage_desc *desc; 404 405 desc = __get_stage_desc(client); 406 memset(desc, 0, sizeof(*desc)); 407 } 408 409 /** 410 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue 411 * @request: request associated with the commands 412 * 413 * Return: 0 if space is available 414 * -EAGAIN if space is not currently available 415 * 416 * This function must be called (and must return 0) before a request 417 * is submitted to the GuC via i915_guc_submit() below. Once a result 418 * of 0 has been returned, it must be balanced by a corresponding 419 * call to submit(). 420 * 421 * Reservation allows the caller to determine in advance that space 422 * will be available for the next submission before committing resources 423 * to it, and helps avoid late failures with complicated recovery paths. 424 */ 425 int i915_guc_wq_reserve(struct drm_i915_gem_request *request) 426 { 427 const size_t wqi_size = sizeof(struct guc_wq_item); 428 struct i915_guc_client *client = request->i915->guc.execbuf_client; 429 struct guc_process_desc *desc = __get_process_desc(client); 430 u32 freespace; 431 int ret; 432 433 spin_lock_irq(&client->wq_lock); 434 freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size); 435 freespace -= client->wq_rsvd; 436 if (likely(freespace >= wqi_size)) { 437 client->wq_rsvd += wqi_size; 438 ret = 0; 439 } else { 440 client->no_wq_space++; 441 ret = -EAGAIN; 442 } 443 spin_unlock_irq(&client->wq_lock); 444 445 return ret; 446 } 447 448 static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size) 449 { 450 unsigned long flags; 451 452 spin_lock_irqsave(&client->wq_lock, flags); 453 client->wq_rsvd += size; 454 spin_unlock_irqrestore(&client->wq_lock, flags); 455 } 456 457 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request) 458 { 459 const int wqi_size = sizeof(struct guc_wq_item); 460 struct i915_guc_client *client = request->i915->guc.execbuf_client; 461 462 GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size); 463 guc_client_update_wq_rsvd(client, -wqi_size); 464 } 465 466 /* Construct a Work Item and append it to the GuC's Work Queue */ 467 static void guc_wq_item_append(struct i915_guc_client *client, 468 struct drm_i915_gem_request *rq) 469 { 470 /* wqi_len is in DWords, and does not include the one-word header */ 471 const size_t wqi_size = sizeof(struct guc_wq_item); 472 const u32 wqi_len = wqi_size/sizeof(u32) - 1; 473 struct intel_engine_cs *engine = rq->engine; 474 struct guc_process_desc *desc = __get_process_desc(client); 475 struct guc_wq_item *wqi; 476 u32 freespace, tail, wq_off; 477 478 /* Free space is guaranteed, see i915_guc_wq_reserve() above */ 479 freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size); 480 GEM_BUG_ON(freespace < wqi_size); 481 482 /* The GuC firmware wants the tail index in QWords, not bytes */ 483 tail = intel_ring_set_tail(rq->ring, rq->tail) >> 3; 484 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); 485 486 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we 487 * should not have the case where structure wqi is across page, neither 488 * wrapped to the beginning. This simplifies the implementation below. 489 * 490 * XXX: if not the case, we need save data to a temp wqi and copy it to 491 * workqueue buffer dw by dw. 492 */ 493 BUILD_BUG_ON(wqi_size != 16); 494 GEM_BUG_ON(client->wq_rsvd < wqi_size); 495 496 /* postincrement WQ tail for next time */ 497 wq_off = client->wq_tail; 498 GEM_BUG_ON(wq_off & (wqi_size - 1)); 499 client->wq_tail += wqi_size; 500 client->wq_tail &= client->wq_size - 1; 501 client->wq_rsvd -= wqi_size; 502 503 /* WQ starts from the page after doorbell / process_desc */ 504 wqi = client->vaddr + wq_off + GUC_DB_SIZE; 505 506 /* Now fill in the 4-word work queue item */ 507 wqi->header = WQ_TYPE_INORDER | 508 (wqi_len << WQ_LEN_SHIFT) | 509 (engine->guc_id << WQ_TARGET_SHIFT) | 510 WQ_NO_WCFLUSH_WAIT; 511 512 /* The GuC wants only the low-order word of the context descriptor */ 513 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine); 514 515 wqi->submit_element_info = tail << WQ_RING_TAIL_SHIFT; 516 wqi->fence_id = rq->global_seqno; 517 } 518 519 static void guc_reset_wq(struct i915_guc_client *client) 520 { 521 struct guc_process_desc *desc = __get_process_desc(client); 522 523 desc->head = 0; 524 desc->tail = 0; 525 526 client->wq_tail = 0; 527 } 528 529 static int guc_ring_doorbell(struct i915_guc_client *client) 530 { 531 struct guc_process_desc *desc = __get_process_desc(client); 532 union guc_doorbell_qw db_cmp, db_exc, db_ret; 533 union guc_doorbell_qw *db; 534 int attempt = 2, ret = -EAGAIN; 535 536 /* Update the tail so it is visible to GuC */ 537 desc->tail = client->wq_tail; 538 539 /* current cookie */ 540 db_cmp.db_status = GUC_DOORBELL_ENABLED; 541 db_cmp.cookie = client->doorbell_cookie; 542 543 /* cookie to be updated */ 544 db_exc.db_status = GUC_DOORBELL_ENABLED; 545 db_exc.cookie = client->doorbell_cookie + 1; 546 if (db_exc.cookie == 0) 547 db_exc.cookie = 1; 548 549 /* pointer of current doorbell cacheline */ 550 db = (union guc_doorbell_qw *)__get_doorbell(client); 551 552 while (attempt--) { 553 /* lets ring the doorbell */ 554 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, 555 db_cmp.value_qw, db_exc.value_qw); 556 557 /* if the exchange was successfully executed */ 558 if (db_ret.value_qw == db_cmp.value_qw) { 559 /* db was successfully rung */ 560 client->doorbell_cookie = db_exc.cookie; 561 ret = 0; 562 break; 563 } 564 565 /* XXX: doorbell was lost and need to acquire it again */ 566 if (db_ret.db_status == GUC_DOORBELL_DISABLED) 567 break; 568 569 DRM_WARN("Cookie mismatch. Expected %d, found %d\n", 570 db_cmp.cookie, db_ret.cookie); 571 572 /* update the cookie to newly read cookie from GuC */ 573 db_cmp.cookie = db_ret.cookie; 574 db_exc.cookie = db_ret.cookie + 1; 575 if (db_exc.cookie == 0) 576 db_exc.cookie = 1; 577 } 578 579 return ret; 580 } 581 582 /** 583 * __i915_guc_submit() - Submit commands through GuC 584 * @rq: request associated with the commands 585 * 586 * The caller must have already called i915_guc_wq_reserve() above with 587 * a result of 0 (success), guaranteeing that there is space in the work 588 * queue for the new request, so enqueuing the item cannot fail. 589 * 590 * Bad Things Will Happen if the caller violates this protocol e.g. calls 591 * submit() when _reserve() says there's no space, or calls _submit() 592 * a different number of times from (successful) calls to _reserve(). 593 * 594 * The only error here arises if the doorbell hardware isn't functioning 595 * as expected, which really shouln't happen. 596 */ 597 static void __i915_guc_submit(struct drm_i915_gem_request *rq) 598 { 599 struct drm_i915_private *dev_priv = rq->i915; 600 struct intel_engine_cs *engine = rq->engine; 601 unsigned int engine_id = engine->id; 602 struct intel_guc *guc = &rq->i915->guc; 603 struct i915_guc_client *client = guc->execbuf_client; 604 unsigned long flags; 605 int b_ret; 606 607 /* WA to flush out the pending GMADR writes to ring buffer. */ 608 if (i915_vma_is_map_and_fenceable(rq->ring->vma)) 609 POSTING_READ_FW(GUC_STATUS); 610 611 spin_lock_irqsave(&client->wq_lock, flags); 612 613 guc_wq_item_append(client, rq); 614 b_ret = guc_ring_doorbell(client); 615 616 client->submissions[engine_id] += 1; 617 client->retcode = b_ret; 618 if (b_ret) 619 client->b_fail += 1; 620 621 guc->submissions[engine_id] += 1; 622 guc->last_seqno[engine_id] = rq->global_seqno; 623 624 spin_unlock_irqrestore(&client->wq_lock, flags); 625 } 626 627 static void i915_guc_submit(struct drm_i915_gem_request *rq) 628 { 629 __i915_gem_request_submit(rq); 630 __i915_guc_submit(rq); 631 } 632 633 static void nested_enable_signaling(struct drm_i915_gem_request *rq) 634 { 635 /* If we use dma_fence_enable_sw_signaling() directly, lockdep 636 * detects an ordering issue between the fence lockclass and the 637 * global_timeline. This circular dependency can only occur via 2 638 * different fences (but same fence lockclass), so we use the nesting 639 * annotation here to prevent the warn, equivalent to the nesting 640 * inside i915_gem_request_submit() for when we also enable the 641 * signaler. 642 */ 643 644 if (test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 645 &rq->fence.flags)) 646 return; 647 648 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)); 649 trace_dma_fence_enable_signal(&rq->fence); 650 651 lockmgr(&rq->lock, LK_EXCLUSIVE); 652 intel_engine_enable_signaling(rq); 653 lockmgr(&rq->lock, LK_RELEASE); 654 } 655 656 static bool i915_guc_dequeue(struct intel_engine_cs *engine) 657 { 658 struct execlist_port *port = engine->execlist_port; 659 struct drm_i915_gem_request *last = port[0].request; 660 struct rb_node *rb; 661 bool submit = false; 662 663 spin_lock_irq(&engine->timeline->lock); 664 rb = engine->execlist_first; 665 while (rb) { 666 struct drm_i915_gem_request *rq = 667 rb_entry(rb, typeof(*rq), priotree.node); 668 669 if (last && rq->ctx != last->ctx) { 670 if (port != engine->execlist_port) 671 break; 672 673 i915_gem_request_assign(&port->request, last); 674 nested_enable_signaling(last); 675 port++; 676 } 677 678 rb = rb_next(rb); 679 rb_erase(&rq->priotree.node, &engine->execlist_queue); 680 RB_CLEAR_NODE(&rq->priotree.node); 681 rq->priotree.priority = INT_MAX; 682 683 i915_guc_submit(rq); 684 trace_i915_gem_request_in(rq, port - engine->execlist_port); 685 last = rq; 686 submit = true; 687 } 688 if (submit) { 689 i915_gem_request_assign(&port->request, last); 690 nested_enable_signaling(last); 691 engine->execlist_first = rb; 692 } 693 spin_unlock_irq(&engine->timeline->lock); 694 695 return submit; 696 } 697 698 static void i915_guc_irq_handler(unsigned long data) 699 { 700 struct intel_engine_cs *engine = (struct intel_engine_cs *)data; 701 struct execlist_port *port = engine->execlist_port; 702 struct drm_i915_gem_request *rq; 703 bool submit; 704 705 do { 706 rq = port[0].request; 707 while (rq && i915_gem_request_completed(rq)) { 708 trace_i915_gem_request_out(rq); 709 i915_gem_request_put(rq); 710 port[0].request = port[1].request; 711 port[1].request = NULL; 712 rq = port[0].request; 713 } 714 715 submit = false; 716 if (!port[1].request) 717 submit = i915_guc_dequeue(engine); 718 } while (submit); 719 } 720 721 /* 722 * Everything below here is concerned with setup & teardown, and is 723 * therefore not part of the somewhat time-critical batch-submission 724 * path of i915_guc_submit() above. 725 */ 726 727 /** 728 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage 729 * @guc: the guc 730 * @size: size of area to allocate (both virtual space and memory) 731 * 732 * This is a wrapper to create an object for use with the GuC. In order to 733 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate 734 * both some backing storage and a range inside the Global GTT. We must pin 735 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that 736 * range is reserved inside GuC. 737 * 738 * Return: A i915_vma if successful, otherwise an ERR_PTR. 739 */ 740 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) 741 { 742 struct drm_i915_private *dev_priv = guc_to_i915(guc); 743 struct drm_i915_gem_object *obj; 744 struct i915_vma *vma; 745 int ret; 746 747 obj = i915_gem_object_create(dev_priv, size); 748 if (IS_ERR(obj)) 749 return ERR_CAST(obj); 750 751 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); 752 if (IS_ERR(vma)) 753 goto err; 754 755 ret = i915_vma_pin(vma, 0, PAGE_SIZE, 756 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); 757 if (ret) { 758 vma = ERR_PTR(ret); 759 goto err; 760 } 761 762 return vma; 763 764 err: 765 i915_gem_object_put(obj); 766 return vma; 767 } 768 769 /* Check that a doorbell register is in the expected state */ 770 static bool doorbell_ok(struct intel_guc *guc, u16 db_id) 771 { 772 struct drm_i915_private *dev_priv = guc_to_i915(guc); 773 u32 drbregl; 774 bool valid; 775 776 GEM_BUG_ON(db_id >= GUC_DOORBELL_INVALID); 777 778 drbregl = I915_READ(GEN8_DRBREGL(db_id)); 779 valid = drbregl & GEN8_DRB_VALID; 780 781 if (test_bit(db_id, guc->doorbell_bitmap) == valid) 782 return true; 783 784 DRM_DEBUG_DRIVER("Doorbell %d has unexpected state (0x%x): valid=%s\n", 785 db_id, drbregl, yesno(valid)); 786 787 return false; 788 } 789 790 /* 791 * If the GuC thinks that the doorbell is unassigned (e.g. because we reset and 792 * reloaded the GuC FW) we can use this function to tell the GuC to reassign the 793 * doorbell to the rightful owner. 794 */ 795 static int __reset_doorbell(struct i915_guc_client* client, u16 db_id) 796 { 797 int err; 798 799 __update_doorbell_desc(client, db_id); 800 err = __create_doorbell(client); 801 if (!err) 802 err = __destroy_doorbell(client); 803 804 return err; 805 } 806 807 /* 808 * Set up & tear down each unused doorbell in turn, to ensure that all doorbell 809 * HW is (re)initialised. For that end, we might have to borrow the first 810 * client. Also, tell GuC about all the doorbells in use by all clients. 811 * We do this because the KMD, the GuC and the doorbell HW can easily go out of 812 * sync (e.g. we can reset the GuC, but not the doorbel HW). 813 */ 814 static int guc_init_doorbell_hw(struct intel_guc *guc) 815 { 816 struct i915_guc_client *client = guc->execbuf_client; 817 bool recreate_first_client = false; 818 u16 db_id; 819 int ret; 820 821 /* For unused doorbells, make sure they are disabled */ 822 for_each_clear_bit(db_id, guc->doorbell_bitmap, GUC_NUM_DOORBELLS) { 823 if (doorbell_ok(guc, db_id)) 824 continue; 825 826 if (has_doorbell(client)) { 827 /* Borrow execbuf_client (we will recreate it later) */ 828 destroy_doorbell(client); 829 recreate_first_client = true; 830 } 831 832 ret = __reset_doorbell(client, db_id); 833 WARN(ret, "Doorbell %u reset failed, err %d\n", db_id, ret); 834 } 835 836 if (recreate_first_client) { 837 ret = __reserve_doorbell(client); 838 if (unlikely(ret)) { 839 DRM_ERROR("Couldn't re-reserve first client db: %d\n", ret); 840 return ret; 841 } 842 843 __update_doorbell_desc(client, client->doorbell_id); 844 } 845 846 /* Now for every client (and not only execbuf_client) make sure their 847 * doorbells are known by the GuC */ 848 //for (client = client_list; client != NULL; client = client->next) 849 { 850 ret = __create_doorbell(client); 851 if (ret) { 852 DRM_ERROR("Couldn't recreate client %u doorbell: %d\n", 853 client->stage_id, ret); 854 return ret; 855 } 856 } 857 858 /* Read back & verify all (used & unused) doorbell registers */ 859 for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id) 860 WARN_ON(!doorbell_ok(guc, db_id)); 861 862 return 0; 863 } 864 865 /** 866 * guc_client_alloc() - Allocate an i915_guc_client 867 * @dev_priv: driver private data structure 868 * @engines: The set of engines to enable for this client 869 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW 870 * The kernel client to replace ExecList submission is created with 871 * NORMAL priority. Priority of a client for scheduler can be HIGH, 872 * while a preemption context can use CRITICAL. 873 * @ctx: the context that owns the client (we use the default render 874 * context) 875 * 876 * Return: An i915_guc_client object if success, else NULL. 877 */ 878 static struct i915_guc_client * 879 guc_client_alloc(struct drm_i915_private *dev_priv, 880 uint32_t engines, 881 uint32_t priority, 882 struct i915_gem_context *ctx) 883 { 884 struct i915_guc_client *client; 885 struct intel_guc *guc = &dev_priv->guc; 886 struct i915_vma *vma; 887 void *vaddr; 888 int ret; 889 890 client = kzalloc(sizeof(*client), GFP_KERNEL); 891 if (!client) 892 return ERR_PTR(-ENOMEM); 893 894 client->guc = guc; 895 client->owner = ctx; 896 client->engines = engines; 897 client->priority = priority; 898 client->doorbell_id = GUC_DOORBELL_INVALID; 899 client->wq_offset = GUC_DB_SIZE; 900 client->wq_size = GUC_WQ_SIZE; 901 lockinit(&client->wq_lock, "i9gcwql", 0, 0); 902 903 ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS, 904 GFP_KERNEL); 905 if (ret < 0) 906 goto err_client; 907 908 client->stage_id = ret; 909 910 /* The first page is doorbell/proc_desc. Two followed pages are wq. */ 911 vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE); 912 if (IS_ERR(vma)) { 913 ret = PTR_ERR(vma); 914 goto err_id; 915 } 916 917 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ 918 client->vma = vma; 919 920 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 921 if (IS_ERR(vaddr)) { 922 ret = PTR_ERR(vaddr); 923 goto err_vma; 924 } 925 client->vaddr = vaddr; 926 927 client->doorbell_offset = __select_cacheline(guc); 928 929 /* 930 * Since the doorbell only requires a single cacheline, we can save 931 * space by putting the application process descriptor in the same 932 * page. Use the half of the page that doesn't include the doorbell. 933 */ 934 if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) 935 client->proc_desc_offset = 0; 936 else 937 client->proc_desc_offset = (GUC_DB_SIZE / 2); 938 939 guc_proc_desc_init(guc, client); 940 guc_stage_desc_init(guc, client); 941 942 ret = create_doorbell(client); 943 if (ret) 944 goto err_vaddr; 945 946 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n", 947 priority, client, client->engines, client->stage_id); 948 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n", 949 client->doorbell_id, client->doorbell_offset); 950 951 return client; 952 953 err_vaddr: 954 i915_gem_object_unpin_map(client->vma->obj); 955 err_vma: 956 i915_vma_unpin_and_release(&client->vma); 957 err_id: 958 ida_simple_remove(&guc->stage_ids, client->stage_id); 959 err_client: 960 kfree(client); 961 return ERR_PTR(ret); 962 } 963 964 static void guc_client_free(struct i915_guc_client *client) 965 { 966 /* 967 * XXX: wait for any outstanding submissions before freeing memory. 968 * Be sure to drop any locks 969 */ 970 971 /* FIXME: in many cases, by the time we get here the GuC has been 972 * reset, so we cannot destroy the doorbell properly. Ignore the 973 * error message for now */ 974 destroy_doorbell(client); 975 guc_stage_desc_fini(client->guc, client); 976 i915_gem_object_unpin_map(client->vma->obj); 977 i915_vma_unpin_and_release(&client->vma); 978 ida_simple_remove(&client->guc->stage_ids, client->stage_id); 979 kfree(client); 980 } 981 982 static void guc_policies_init(struct guc_policies *policies) 983 { 984 struct guc_policy *policy; 985 u32 p, i; 986 987 policies->dpc_promote_time = 500000; 988 policies->max_num_work_items = POLICY_MAX_NUM_WI; 989 990 for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) { 991 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { 992 policy = &policies->policy[p][i]; 993 994 policy->execution_quantum = 1000000; 995 policy->preemption_time = 500000; 996 policy->fault_time = 250000; 997 policy->policy_flags = 0; 998 } 999 } 1000 1001 policies->is_valid = 1; 1002 } 1003 1004 static int guc_ads_create(struct intel_guc *guc) 1005 { 1006 struct drm_i915_private *dev_priv = guc_to_i915(guc); 1007 struct i915_vma *vma; 1008 struct page *page; 1009 /* The ads obj includes the struct itself and buffers passed to GuC */ 1010 struct { 1011 struct guc_ads ads; 1012 struct guc_policies policies; 1013 struct guc_mmio_reg_state reg_state; 1014 u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE]; 1015 } __packed *blob; 1016 struct intel_engine_cs *engine; 1017 enum intel_engine_id id; 1018 u32 base; 1019 1020 GEM_BUG_ON(guc->ads_vma); 1021 1022 vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob))); 1023 if (IS_ERR(vma)) 1024 return PTR_ERR(vma); 1025 1026 guc->ads_vma = vma; 1027 1028 page = i915_vma_first_page(vma); 1029 blob = kmap(page); 1030 1031 /* GuC scheduling policies */ 1032 guc_policies_init(&blob->policies); 1033 1034 /* MMIO reg state */ 1035 for_each_engine(engine, dev_priv, id) { 1036 blob->reg_state.white_list[engine->guc_id].mmio_start = 1037 engine->mmio_base + GUC_MMIO_WHITE_LIST_START; 1038 1039 /* Nothing to be saved or restored for now. */ 1040 blob->reg_state.white_list[engine->guc_id].count = 0; 1041 } 1042 1043 /* 1044 * The GuC requires a "Golden Context" when it reinitialises 1045 * engines after a reset. Here we use the Render ring default 1046 * context, which must already exist and be pinned in the GGTT, 1047 * so its address won't change after we've told the GuC where 1048 * to find it. 1049 */ 1050 blob->ads.golden_context_lrca = 1051 dev_priv->engine[RCS]->status_page.ggtt_offset; 1052 1053 for_each_engine(engine, dev_priv, id) 1054 blob->ads.eng_state_size[engine->guc_id] = 1055 intel_lr_context_size(engine); 1056 1057 base = guc_ggtt_offset(vma); 1058 blob->ads.scheduler_policies = base + ptr_offset(blob, policies); 1059 blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer); 1060 blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state); 1061 1062 kunmap(page); 1063 1064 return 0; 1065 } 1066 1067 static void guc_ads_destroy(struct intel_guc *guc) 1068 { 1069 i915_vma_unpin_and_release(&guc->ads_vma); 1070 } 1071 1072 /* 1073 * Set up the memory resources to be shared with the GuC (via the GGTT) 1074 * at firmware loading time. 1075 */ 1076 int i915_guc_submission_init(struct drm_i915_private *dev_priv) 1077 { 1078 struct intel_guc *guc = &dev_priv->guc; 1079 struct i915_vma *vma; 1080 void *vaddr; 1081 int ret; 1082 1083 if (guc->stage_desc_pool) 1084 return 0; 1085 1086 vma = intel_guc_allocate_vma(guc, 1087 PAGE_ALIGN(sizeof(struct guc_stage_desc) * 1088 GUC_MAX_STAGE_DESCRIPTORS)); 1089 if (IS_ERR(vma)) 1090 return PTR_ERR(vma); 1091 1092 guc->stage_desc_pool = vma; 1093 1094 vaddr = i915_gem_object_pin_map(guc->stage_desc_pool->obj, I915_MAP_WB); 1095 if (IS_ERR(vaddr)) { 1096 ret = PTR_ERR(vaddr); 1097 goto err_vma; 1098 } 1099 1100 guc->stage_desc_pool_vaddr = vaddr; 1101 1102 ret = intel_guc_log_create(guc); 1103 if (ret < 0) 1104 goto err_vaddr; 1105 1106 ret = guc_ads_create(guc); 1107 if (ret < 0) 1108 goto err_log; 1109 1110 ida_init(&guc->stage_ids); 1111 1112 return 0; 1113 1114 err_log: 1115 intel_guc_log_destroy(guc); 1116 err_vaddr: 1117 i915_gem_object_unpin_map(guc->stage_desc_pool->obj); 1118 err_vma: 1119 i915_vma_unpin_and_release(&guc->stage_desc_pool); 1120 return ret; 1121 } 1122 1123 void i915_guc_submission_fini(struct drm_i915_private *dev_priv) 1124 { 1125 struct intel_guc *guc = &dev_priv->guc; 1126 1127 ida_destroy(&guc->stage_ids); 1128 guc_ads_destroy(guc); 1129 intel_guc_log_destroy(guc); 1130 i915_gem_object_unpin_map(guc->stage_desc_pool->obj); 1131 i915_vma_unpin_and_release(&guc->stage_desc_pool); 1132 } 1133 1134 static void guc_interrupts_capture(struct drm_i915_private *dev_priv) 1135 { 1136 struct intel_engine_cs *engine; 1137 enum intel_engine_id id; 1138 int irqs; 1139 1140 /* tell all command streamers to forward interrupts (but not vblank) to GuC */ 1141 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); 1142 for_each_engine(engine, dev_priv, id) 1143 I915_WRITE(RING_MODE_GEN7(engine), irqs); 1144 1145 /* route USER_INTERRUPT to Host, all others are sent to GuC. */ 1146 irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | 1147 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1148 /* These three registers have the same bit definitions */ 1149 I915_WRITE(GUC_BCS_RCS_IER, ~irqs); 1150 I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); 1151 I915_WRITE(GUC_WD_VECS_IER, ~irqs); 1152 1153 /* 1154 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all 1155 * (unmasked) PM interrupts to the GuC. All other bits of this 1156 * register *disable* generation of a specific interrupt. 1157 * 1158 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when 1159 * writing to the PM interrupt mask register, i.e. interrupts 1160 * that must not be disabled. 1161 * 1162 * If the GuC is handling these interrupts, then we must not let 1163 * the PM code disable ANY interrupt that the GuC is expecting. 1164 * So for each ENABLED (0) bit in this register, we must SET the 1165 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC. 1166 * GuC needs ARAT expired interrupt unmasked hence it is set in 1167 * pm_intrmsk_mbz. 1168 * 1169 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will 1170 * result in the register bit being left SET! 1171 */ 1172 dev_priv->rps.pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; 1173 dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; 1174 } 1175 1176 static void guc_interrupts_release(struct drm_i915_private *dev_priv) 1177 { 1178 struct intel_engine_cs *engine; 1179 enum intel_engine_id id; 1180 int irqs; 1181 1182 /* 1183 * tell all command streamers NOT to forward interrupts or vblank 1184 * to GuC. 1185 */ 1186 irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); 1187 irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); 1188 for_each_engine(engine, dev_priv, id) 1189 I915_WRITE(RING_MODE_GEN7(engine), irqs); 1190 1191 /* route all GT interrupts to the host */ 1192 I915_WRITE(GUC_BCS_RCS_IER, 0); 1193 I915_WRITE(GUC_VCS2_VCS1_IER, 0); 1194 I915_WRITE(GUC_WD_VECS_IER, 0); 1195 1196 dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; 1197 dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; 1198 } 1199 1200 int i915_guc_submission_enable(struct drm_i915_private *dev_priv) 1201 { 1202 struct intel_guc *guc = &dev_priv->guc; 1203 struct i915_guc_client *client = guc->execbuf_client; 1204 struct intel_engine_cs *engine; 1205 enum intel_engine_id id; 1206 int err; 1207 1208 if (!client) { 1209 client = guc_client_alloc(dev_priv, 1210 INTEL_INFO(dev_priv)->ring_mask, 1211 GUC_CLIENT_PRIORITY_KMD_NORMAL, 1212 dev_priv->kernel_context); 1213 if (IS_ERR(client)) { 1214 DRM_ERROR("Failed to create GuC client for execbuf!\n"); 1215 return PTR_ERR(client); 1216 } 1217 1218 guc->execbuf_client = client; 1219 } 1220 1221 err = intel_guc_sample_forcewake(guc); 1222 if (err) 1223 goto err_execbuf_client; 1224 1225 guc_reset_wq(client); 1226 1227 err = guc_init_doorbell_hw(guc); 1228 if (err) 1229 goto err_execbuf_client; 1230 1231 /* Take over from manual control of ELSP (execlists) */ 1232 guc_interrupts_capture(dev_priv); 1233 1234 for_each_engine(engine, dev_priv, id) { 1235 const int wqi_size = sizeof(struct guc_wq_item); 1236 struct drm_i915_gem_request *rq; 1237 1238 /* The tasklet was initialised by execlists, and may be in 1239 * a state of flux (across a reset) and so we just want to 1240 * take over the callback without changing any other state 1241 * in the tasklet. 1242 */ 1243 engine->irq_tasklet.func = i915_guc_irq_handler; 1244 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); 1245 1246 /* Replay the current set of previously submitted requests */ 1247 spin_lock_irq(&engine->timeline->lock); 1248 list_for_each_entry(rq, &engine->timeline->requests, link) { 1249 guc_client_update_wq_rsvd(client, wqi_size); 1250 __i915_guc_submit(rq); 1251 } 1252 spin_unlock_irq(&engine->timeline->lock); 1253 } 1254 1255 return 0; 1256 1257 err_execbuf_client: 1258 guc_client_free(guc->execbuf_client); 1259 guc->execbuf_client = NULL; 1260 return err; 1261 } 1262 1263 void i915_guc_submission_disable(struct drm_i915_private *dev_priv) 1264 { 1265 struct intel_guc *guc = &dev_priv->guc; 1266 1267 guc_interrupts_release(dev_priv); 1268 1269 /* Revert back to manual ELSP submission */ 1270 intel_engines_reset_default_submission(dev_priv); 1271 1272 guc_client_free(guc->execbuf_client); 1273 guc->execbuf_client = NULL; 1274 } 1275 1276 /** 1277 * intel_guc_suspend() - notify GuC entering suspend state 1278 * @dev_priv: i915 device private 1279 */ 1280 int intel_guc_suspend(struct drm_i915_private *dev_priv) 1281 { 1282 struct intel_guc *guc = &dev_priv->guc; 1283 struct i915_gem_context *ctx; 1284 u32 data[3]; 1285 1286 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) 1287 return 0; 1288 1289 gen9_disable_guc_interrupts(dev_priv); 1290 1291 ctx = dev_priv->kernel_context; 1292 1293 data[0] = INTEL_GUC_ACTION_ENTER_S_STATE; 1294 /* any value greater than GUC_POWER_D0 */ 1295 data[1] = GUC_POWER_D1; 1296 /* first page is shared data with GuC */ 1297 data[2] = guc_ggtt_offset(ctx->engine[RCS].state); 1298 1299 return intel_guc_send(guc, data, ARRAY_SIZE(data)); 1300 } 1301 1302 /** 1303 * intel_guc_resume() - notify GuC resuming from suspend state 1304 * @dev_priv: i915 device private 1305 */ 1306 int intel_guc_resume(struct drm_i915_private *dev_priv) 1307 { 1308 struct intel_guc *guc = &dev_priv->guc; 1309 struct i915_gem_context *ctx; 1310 u32 data[3]; 1311 1312 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) 1313 return 0; 1314 1315 if (i915.guc_log_level >= 0) 1316 gen9_enable_guc_interrupts(dev_priv); 1317 1318 ctx = dev_priv->kernel_context; 1319 1320 data[0] = INTEL_GUC_ACTION_EXIT_S_STATE; 1321 data[1] = GUC_POWER_D0; 1322 /* first page is shared data with GuC */ 1323 data[2] = guc_ggtt_offset(ctx->engine[RCS].state); 1324 1325 return intel_guc_send(guc, data, ARRAY_SIZE(data)); 1326 } 1327