1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/firmware.h> 25 #include <linux/circ_buf.h> 26 #include <linux/debugfs.h> 27 #include <linux/relay.h> 28 #include "i915_drv.h" 29 #include "intel_guc.h" 30 31 /** 32 * DOC: GuC-based command submission 33 * 34 * i915_guc_client: 35 * We use the term client to avoid confusion with contexts. A i915_guc_client is 36 * equivalent to GuC object guc_context_desc. This context descriptor is 37 * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell 38 * and workqueue for it. Also the process descriptor (guc_process_desc), which 39 * is mapped to client space. So the client can write Work Item then ring the 40 * doorbell. 41 * 42 * To simplify the implementation, we allocate one gem object that contains all 43 * pages for doorbell, process descriptor and workqueue. 44 * 45 * The Scratch registers: 46 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes 47 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then 48 * triggers an interrupt on the GuC via another register write (0xC4C8). 49 * Firmware writes a success/fail code back to the action register after 50 * processes the request. The kernel driver polls waiting for this update and 51 * then proceeds. 52 * See host2guc_action() 53 * 54 * Doorbells: 55 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) 56 * mapped into process space. 57 * 58 * Work Items: 59 * There are several types of work items that the host may place into a 60 * workqueue, each with its own requirements and limitations. Currently only 61 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which 62 * represents in-order queue. The kernel driver packs ring tail pointer and an 63 * ELSP context descriptor dword into Work Item. 64 * See guc_wq_item_append() 65 * 66 */ 67 68 /* 69 * Read GuC command/status register (SOFT_SCRATCH_0) 70 * Return true if it contains a response rather than a command 71 */ 72 static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, 73 u32 *status) 74 { 75 u32 val = I915_READ(SOFT_SCRATCH(0)); 76 *status = val; 77 return GUC2HOST_IS_RESPONSE(val); 78 } 79 80 static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) 81 { 82 struct drm_i915_private *dev_priv = guc_to_i915(guc); 83 u32 status; 84 int i; 85 int ret; 86 87 if (WARN_ON(len < 1 || len > 15)) 88 return -EINVAL; 89 90 mutex_lock(&guc->action_lock); 91 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 92 93 dev_priv->guc.action_count += 1; 94 dev_priv->guc.action_cmd = data[0]; 95 96 for (i = 0; i < len; i++) 97 I915_WRITE(SOFT_SCRATCH(i), data[i]); 98 99 POSTING_READ(SOFT_SCRATCH(i - 1)); 100 101 I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); 102 103 /* 104 * Fast commands should complete in less than 10us, so sample quickly 105 * up to that length of time, then switch to a slower sleep-wait loop. 106 * No HOST2GUC command should ever take longer than 10ms. 107 */ 108 ret = wait_for_us(host2guc_action_response(dev_priv, &status), 10); 109 if (ret) 110 ret = wait_for(host2guc_action_response(dev_priv, &status), 10); 111 if (status != GUC2HOST_STATUS_SUCCESS) { 112 /* 113 * Either the GuC explicitly returned an error (which 114 * we convert to -EIO here) or no response at all was 115 * received within the timeout limit (-ETIMEDOUT) 116 */ 117 if (ret != -ETIMEDOUT) 118 ret = -EIO; 119 120 DRM_WARN("Action 0x%X failed; ret=%d status=0x%08X response=0x%08X\n", 121 data[0], ret, status, I915_READ(SOFT_SCRATCH(15))); 122 123 dev_priv->guc.action_fail += 1; 124 dev_priv->guc.action_err = ret; 125 } 126 dev_priv->guc.action_status = status; 127 128 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 129 mutex_unlock(&guc->action_lock); 130 131 return ret; 132 } 133 134 /* 135 * Tell the GuC to allocate or deallocate a specific doorbell 136 */ 137 138 static int host2guc_allocate_doorbell(struct intel_guc *guc, 139 struct i915_guc_client *client) 140 { 141 u32 data[2]; 142 143 data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; 144 data[1] = client->ctx_index; 145 146 return host2guc_action(guc, data, 2); 147 } 148 149 static int host2guc_release_doorbell(struct intel_guc *guc, 150 struct i915_guc_client *client) 151 { 152 u32 data[2]; 153 154 data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; 155 data[1] = client->ctx_index; 156 157 return host2guc_action(guc, data, 2); 158 } 159 160 static int host2guc_sample_forcewake(struct intel_guc *guc, 161 struct i915_guc_client *client) 162 { 163 struct drm_i915_private *dev_priv = guc_to_i915(guc); 164 u32 data[2]; 165 166 data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; 167 /* WaRsDisableCoarsePowerGating:skl,bxt */ 168 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) 169 data[1] = 0; 170 else 171 /* bit 0 and 1 are for Render and Media domain separately */ 172 data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; 173 174 return host2guc_action(guc, data, ARRAY_SIZE(data)); 175 } 176 177 #if 0 178 static int host2guc_logbuffer_flush_complete(struct intel_guc *guc) 179 { 180 u32 data[1]; 181 182 data[0] = HOST2GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE; 183 184 return host2guc_action(guc, data, 1); 185 } 186 #endif 187 188 static int host2guc_force_logbuffer_flush(struct intel_guc *guc) 189 { 190 u32 data[2]; 191 192 data[0] = HOST2GUC_ACTION_FORCE_LOG_BUFFER_FLUSH; 193 data[1] = 0; 194 195 return host2guc_action(guc, data, 2); 196 } 197 198 static int host2guc_logging_control(struct intel_guc *guc, u32 control_val) 199 { 200 u32 data[2]; 201 202 data[0] = HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING; 203 data[1] = control_val; 204 205 return host2guc_action(guc, data, 2); 206 } 207 208 /* 209 * Initialise, update, or clear doorbell data shared with the GuC 210 * 211 * These functions modify shared data and so need access to the mapped 212 * client object which contains the page being used for the doorbell 213 */ 214 215 static int guc_update_doorbell_id(struct intel_guc *guc, 216 struct i915_guc_client *client, 217 u16 new_id) 218 { 219 struct sg_table *sg = guc->ctx_pool_vma->pages; 220 void *doorbell_bitmap = guc->doorbell_bitmap; 221 struct guc_doorbell_info *doorbell; 222 struct guc_context_desc desc; 223 size_t len; 224 225 doorbell = client->vaddr + client->doorbell_offset; 226 227 if (client->doorbell_id != GUC_INVALID_DOORBELL_ID && 228 test_bit(client->doorbell_id, doorbell_bitmap)) { 229 /* Deactivate the old doorbell */ 230 doorbell->db_status = GUC_DOORBELL_DISABLED; 231 (void)host2guc_release_doorbell(guc, client); 232 __clear_bit(client->doorbell_id, doorbell_bitmap); 233 } 234 235 /* Update the GuC's idea of the doorbell ID */ 236 len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), 237 sizeof(desc) * client->ctx_index); 238 if (len != sizeof(desc)) 239 return -EFAULT; 240 desc.db_id = new_id; 241 len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), 242 sizeof(desc) * client->ctx_index); 243 if (len != sizeof(desc)) 244 return -EFAULT; 245 246 client->doorbell_id = new_id; 247 if (new_id == GUC_INVALID_DOORBELL_ID) 248 return 0; 249 250 /* Activate the new doorbell */ 251 __set_bit(new_id, doorbell_bitmap); 252 doorbell->cookie = 0; 253 doorbell->db_status = GUC_DOORBELL_ENABLED; 254 return host2guc_allocate_doorbell(guc, client); 255 } 256 257 static int guc_init_doorbell(struct intel_guc *guc, 258 struct i915_guc_client *client, 259 uint16_t db_id) 260 { 261 return guc_update_doorbell_id(guc, client, db_id); 262 } 263 264 static void guc_disable_doorbell(struct intel_guc *guc, 265 struct i915_guc_client *client) 266 { 267 (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID); 268 269 /* XXX: wait for any interrupts */ 270 /* XXX: wait for workqueue to drain */ 271 } 272 273 static uint16_t 274 select_doorbell_register(struct intel_guc *guc, uint32_t priority) 275 { 276 /* 277 * The bitmap tracks which doorbell registers are currently in use. 278 * It is split into two halves; the first half is used for normal 279 * priority contexts, the second half for high-priority ones. 280 * Note that logically higher priorities are numerically less than 281 * normal ones, so the test below means "is it high-priority?" 282 */ 283 const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); 284 const uint16_t half = GUC_MAX_DOORBELLS / 2; 285 const uint16_t start = hi_pri ? half : 0; 286 const uint16_t end = start + half; 287 uint16_t id; 288 289 id = find_next_zero_bit(guc->doorbell_bitmap, end, start); 290 if (id == end) 291 id = GUC_INVALID_DOORBELL_ID; 292 293 DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", 294 hi_pri ? "high" : "normal", id); 295 296 return id; 297 } 298 299 /* 300 * Select, assign and relase doorbell cachelines 301 * 302 * These functions track which doorbell cachelines are in use. 303 * The data they manipulate is protected by the host2guc lock. 304 */ 305 306 static uint32_t select_doorbell_cacheline(struct intel_guc *guc) 307 { 308 const uint32_t cacheline_size = cache_line_size(); 309 uint32_t offset; 310 311 /* Doorbell uses a single cache line within a page */ 312 offset = offset_in_page(guc->db_cacheline); 313 314 /* Moving to next cache line to reduce contention */ 315 guc->db_cacheline += cacheline_size; 316 317 DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", 318 offset, guc->db_cacheline, cacheline_size); 319 320 return offset; 321 } 322 323 /* 324 * Initialise the process descriptor shared with the GuC firmware. 325 */ 326 static void guc_proc_desc_init(struct intel_guc *guc, 327 struct i915_guc_client *client) 328 { 329 struct guc_process_desc *desc; 330 331 desc = client->vaddr + client->proc_desc_offset; 332 333 memset(desc, 0, sizeof(*desc)); 334 335 /* 336 * XXX: pDoorbell and WQVBaseAddress are pointers in process address 337 * space for ring3 clients (set them as in mmap_ioctl) or kernel 338 * space for kernel clients (map on demand instead? May make debug 339 * easier to have it mapped). 340 */ 341 desc->wq_base_addr = 0; 342 desc->db_base_addr = 0; 343 344 desc->context_id = client->ctx_index; 345 desc->wq_size_bytes = client->wq_size; 346 desc->wq_status = WQ_STATUS_ACTIVE; 347 desc->priority = client->priority; 348 } 349 350 /* 351 * Initialise/clear the context descriptor shared with the GuC firmware. 352 * 353 * This descriptor tells the GuC where (in GGTT space) to find the important 354 * data structures relating to this client (doorbell, process descriptor, 355 * write queue, etc). 356 */ 357 358 static void guc_ctx_desc_init(struct intel_guc *guc, 359 struct i915_guc_client *client) 360 { 361 struct drm_i915_private *dev_priv = guc_to_i915(guc); 362 struct intel_engine_cs *engine; 363 struct i915_gem_context *ctx = client->owner; 364 struct guc_context_desc desc; 365 struct sg_table *sg; 366 unsigned int tmp; 367 u32 gfx_addr; 368 369 memset(&desc, 0, sizeof(desc)); 370 371 desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; 372 desc.context_id = client->ctx_index; 373 desc.priority = client->priority; 374 desc.db_id = client->doorbell_id; 375 376 for_each_engine_masked(engine, dev_priv, client->engines, tmp) { 377 struct intel_context *ce = &ctx->engine[engine->id]; 378 uint32_t guc_engine_id = engine->guc_id; 379 struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id]; 380 381 /* TODO: We have a design issue to be solved here. Only when we 382 * receive the first batch, we know which engine is used by the 383 * user. But here GuC expects the lrc and ring to be pinned. It 384 * is not an issue for default context, which is the only one 385 * for now who owns a GuC client. But for future owner of GuC 386 * client, need to make sure lrc is pinned prior to enter here. 387 */ 388 if (!ce->state) 389 break; /* XXX: continue? */ 390 391 lrc->context_desc = lower_32_bits(ce->lrc_desc); 392 393 /* The state page is after PPHWSP */ 394 lrc->ring_lcra = 395 i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; 396 lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | 397 (guc_engine_id << GUC_ELC_ENGINE_OFFSET); 398 399 lrc->ring_begin = i915_ggtt_offset(ce->ring->vma); 400 lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; 401 lrc->ring_next_free_location = lrc->ring_begin; 402 lrc->ring_current_tail_pointer_value = 0; 403 404 desc.engines_used |= (1 << guc_engine_id); 405 } 406 407 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", 408 client->engines, desc.engines_used); 409 WARN_ON(desc.engines_used == 0); 410 411 /* 412 * The doorbell, process descriptor, and workqueue are all parts 413 * of the client object, which the GuC will reference via the GGTT 414 */ 415 gfx_addr = i915_ggtt_offset(client->vma); 416 desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + 417 client->doorbell_offset; 418 desc.db_trigger_cpu = 419 (uintptr_t)client->vaddr + client->doorbell_offset; 420 desc.db_trigger_uk = gfx_addr + client->doorbell_offset; 421 desc.process_desc = gfx_addr + client->proc_desc_offset; 422 desc.wq_addr = gfx_addr + client->wq_offset; 423 desc.wq_size = client->wq_size; 424 425 /* 426 * XXX: Take LRCs from an existing context if this is not an 427 * IsKMDCreatedContext client 428 */ 429 desc.desc_private = (uintptr_t)client; 430 431 /* Pool context is pinned already */ 432 sg = guc->ctx_pool_vma->pages; 433 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), 434 sizeof(desc) * client->ctx_index); 435 } 436 437 static void guc_ctx_desc_fini(struct intel_guc *guc, 438 struct i915_guc_client *client) 439 { 440 struct guc_context_desc desc; 441 struct sg_table *sg; 442 443 memset(&desc, 0, sizeof(desc)); 444 445 sg = guc->ctx_pool_vma->pages; 446 sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), 447 sizeof(desc) * client->ctx_index); 448 } 449 450 /** 451 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue 452 * @request: request associated with the commands 453 * 454 * Return: 0 if space is available 455 * -EAGAIN if space is not currently available 456 * 457 * This function must be called (and must return 0) before a request 458 * is submitted to the GuC via i915_guc_submit() below. Once a result 459 * of 0 has been returned, it must be balanced by a corresponding 460 * call to submit(). 461 * 462 * Reservation allows the caller to determine in advance that space 463 * will be available for the next submission before committing resources 464 * to it, and helps avoid late failures with complicated recovery paths. 465 */ 466 int i915_guc_wq_reserve(struct drm_i915_gem_request *request) 467 { 468 const size_t wqi_size = sizeof(struct guc_wq_item); 469 struct i915_guc_client *gc = request->i915->guc.execbuf_client; 470 struct guc_process_desc *desc = gc->vaddr + gc->proc_desc_offset; 471 u32 freespace; 472 int ret; 473 474 lockmgr(&gc->wq_lock, LK_EXCLUSIVE); 475 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); 476 freespace -= gc->wq_rsvd; 477 if (likely(freespace >= wqi_size)) { 478 gc->wq_rsvd += wqi_size; 479 ret = 0; 480 } else { 481 gc->no_wq_space++; 482 ret = -EAGAIN; 483 } 484 lockmgr(&gc->wq_lock, LK_RELEASE); 485 486 return ret; 487 } 488 489 void i915_guc_wq_unreserve(struct drm_i915_gem_request *request) 490 { 491 const size_t wqi_size = sizeof(struct guc_wq_item); 492 struct i915_guc_client *gc = request->i915->guc.execbuf_client; 493 494 GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size); 495 496 lockmgr(&gc->wq_lock, LK_EXCLUSIVE); 497 gc->wq_rsvd -= wqi_size; 498 lockmgr(&gc->wq_lock, LK_RELEASE); 499 } 500 501 /* Construct a Work Item and append it to the GuC's Work Queue */ 502 static void guc_wq_item_append(struct i915_guc_client *gc, 503 struct drm_i915_gem_request *rq) 504 { 505 /* wqi_len is in DWords, and does not include the one-word header */ 506 const size_t wqi_size = sizeof(struct guc_wq_item); 507 const u32 wqi_len = wqi_size/sizeof(u32) - 1; 508 struct intel_engine_cs *engine = rq->engine; 509 struct guc_process_desc *desc; 510 struct guc_wq_item *wqi; 511 u32 freespace, tail, wq_off; 512 513 desc = gc->vaddr + gc->proc_desc_offset; 514 515 /* Free space is guaranteed, see i915_guc_wq_reserve() above */ 516 freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); 517 GEM_BUG_ON(freespace < wqi_size); 518 519 /* The GuC firmware wants the tail index in QWords, not bytes */ 520 tail = rq->tail; 521 GEM_BUG_ON(tail & 7); 522 tail >>= 3; 523 GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); 524 525 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we 526 * should not have the case where structure wqi is across page, neither 527 * wrapped to the beginning. This simplifies the implementation below. 528 * 529 * XXX: if not the case, we need save data to a temp wqi and copy it to 530 * workqueue buffer dw by dw. 531 */ 532 BUILD_BUG_ON(wqi_size != 16); 533 GEM_BUG_ON(gc->wq_rsvd < wqi_size); 534 535 /* postincrement WQ tail for next time */ 536 wq_off = gc->wq_tail; 537 GEM_BUG_ON(wq_off & (wqi_size - 1)); 538 gc->wq_tail += wqi_size; 539 gc->wq_tail &= gc->wq_size - 1; 540 gc->wq_rsvd -= wqi_size; 541 542 /* WQ starts from the page after doorbell / process_desc */ 543 wqi = gc->vaddr + wq_off + GUC_DB_SIZE; 544 545 /* Now fill in the 4-word work queue item */ 546 wqi->header = WQ_TYPE_INORDER | 547 (wqi_len << WQ_LEN_SHIFT) | 548 (engine->guc_id << WQ_TARGET_SHIFT) | 549 WQ_NO_WCFLUSH_WAIT; 550 551 /* The GuC wants only the low-order word of the context descriptor */ 552 wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine); 553 554 wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; 555 wqi->fence_id = rq->global_seqno; 556 } 557 558 static int guc_ring_doorbell(struct i915_guc_client *gc) 559 { 560 struct guc_process_desc *desc; 561 union guc_doorbell_qw db_cmp, db_exc, db_ret; 562 union guc_doorbell_qw *db; 563 int attempt = 2, ret = -EAGAIN; 564 565 desc = gc->vaddr + gc->proc_desc_offset; 566 567 /* Update the tail so it is visible to GuC */ 568 desc->tail = gc->wq_tail; 569 570 /* current cookie */ 571 db_cmp.db_status = GUC_DOORBELL_ENABLED; 572 db_cmp.cookie = gc->cookie; 573 574 /* cookie to be updated */ 575 db_exc.db_status = GUC_DOORBELL_ENABLED; 576 db_exc.cookie = gc->cookie + 1; 577 if (db_exc.cookie == 0) 578 db_exc.cookie = 1; 579 580 /* pointer of current doorbell cacheline */ 581 db = gc->vaddr + gc->doorbell_offset; 582 583 while (attempt--) { 584 /* lets ring the doorbell */ 585 db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, 586 db_cmp.value_qw, db_exc.value_qw); 587 588 /* if the exchange was successfully executed */ 589 if (db_ret.value_qw == db_cmp.value_qw) { 590 /* db was successfully rung */ 591 gc->cookie = db_exc.cookie; 592 ret = 0; 593 break; 594 } 595 596 /* XXX: doorbell was lost and need to acquire it again */ 597 if (db_ret.db_status == GUC_DOORBELL_DISABLED) 598 break; 599 600 DRM_WARN("Cookie mismatch. Expected %d, found %d\n", 601 db_cmp.cookie, db_ret.cookie); 602 603 /* update the cookie to newly read cookie from GuC */ 604 db_cmp.cookie = db_ret.cookie; 605 db_exc.cookie = db_ret.cookie + 1; 606 if (db_exc.cookie == 0) 607 db_exc.cookie = 1; 608 } 609 610 return ret; 611 } 612 613 /** 614 * i915_guc_submit() - Submit commands through GuC 615 * @rq: request associated with the commands 616 * 617 * Return: 0 on success, otherwise an errno. 618 * (Note: nonzero really shouldn't happen!) 619 * 620 * The caller must have already called i915_guc_wq_reserve() above with 621 * a result of 0 (success), guaranteeing that there is space in the work 622 * queue for the new request, so enqueuing the item cannot fail. 623 * 624 * Bad Things Will Happen if the caller violates this protocol e.g. calls 625 * submit() when _reserve() says there's no space, or calls _submit() 626 * a different number of times from (successful) calls to _reserve(). 627 * 628 * The only error here arises if the doorbell hardware isn't functioning 629 * as expected, which really shouln't happen. 630 */ 631 static void i915_guc_submit(struct drm_i915_gem_request *rq) 632 { 633 struct drm_i915_private *dev_priv = rq->i915; 634 struct intel_engine_cs *engine = rq->engine; 635 unsigned int engine_id = engine->id; 636 struct intel_guc *guc = &rq->i915->guc; 637 struct i915_guc_client *client = guc->execbuf_client; 638 int b_ret; 639 640 /* We keep the previous context alive until we retire the following 641 * request. This ensures that any the context object is still pinned 642 * for any residual writes the HW makes into it on the context switch 643 * into the next object following the breadcrumb. Otherwise, we may 644 * retire the context too early. 645 */ 646 rq->previous_context = engine->last_context; 647 engine->last_context = rq->ctx; 648 649 i915_gem_request_submit(rq); 650 651 lockmgr(&client->wq_lock, LK_EXCLUSIVE); 652 guc_wq_item_append(client, rq); 653 654 /* WA to flush out the pending GMADR writes to ring buffer. */ 655 if (i915_vma_is_map_and_fenceable(rq->ring->vma)) 656 POSTING_READ_FW(GUC_STATUS); 657 658 b_ret = guc_ring_doorbell(client); 659 660 client->submissions[engine_id] += 1; 661 client->retcode = b_ret; 662 if (b_ret) 663 client->b_fail += 1; 664 665 guc->submissions[engine_id] += 1; 666 guc->last_seqno[engine_id] = rq->global_seqno; 667 lockmgr(&client->wq_lock, LK_RELEASE); 668 } 669 670 /* 671 * Everything below here is concerned with setup & teardown, and is 672 * therefore not part of the somewhat time-critical batch-submission 673 * path of i915_guc_submit() above. 674 */ 675 676 /** 677 * guc_allocate_vma() - Allocate a GGTT VMA for GuC usage 678 * @guc: the guc 679 * @size: size of area to allocate (both virtual space and memory) 680 * 681 * This is a wrapper to create an object for use with the GuC. In order to 682 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate 683 * both some backing storage and a range inside the Global GTT. We must pin 684 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that 685 * range is reserved inside GuC. 686 * 687 * Return: A i915_vma if successful, otherwise an ERR_PTR. 688 */ 689 static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size) 690 { 691 struct drm_i915_private *dev_priv = guc_to_i915(guc); 692 struct drm_i915_gem_object *obj; 693 struct i915_vma *vma; 694 int ret; 695 696 obj = i915_gem_object_create(&dev_priv->drm, size); 697 if (IS_ERR(obj)) 698 return ERR_CAST(obj); 699 700 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); 701 if (IS_ERR(vma)) 702 goto err; 703 704 ret = i915_vma_pin(vma, 0, PAGE_SIZE, 705 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); 706 if (ret) { 707 vma = ERR_PTR(ret); 708 goto err; 709 } 710 711 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ 712 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); 713 714 return vma; 715 716 err: 717 i915_gem_object_put(obj); 718 return vma; 719 } 720 721 static void 722 guc_client_free(struct drm_i915_private *dev_priv, 723 struct i915_guc_client *client) 724 { 725 struct intel_guc *guc = &dev_priv->guc; 726 727 if (!client) 728 return; 729 730 /* 731 * XXX: wait for any outstanding submissions before freeing memory. 732 * Be sure to drop any locks 733 */ 734 735 if (client->vaddr) { 736 /* 737 * If we got as far as setting up a doorbell, make sure we 738 * shut it down before unmapping & deallocating the memory. 739 */ 740 guc_disable_doorbell(guc, client); 741 742 i915_gem_object_unpin_map(client->vma->obj); 743 } 744 745 i915_vma_unpin_and_release(&client->vma); 746 747 if (client->ctx_index != GUC_INVALID_CTX_ID) { 748 guc_ctx_desc_fini(guc, client); 749 ida_simple_remove(&guc->ctx_ids, client->ctx_index); 750 } 751 752 kfree(client); 753 } 754 755 /* Check that a doorbell register is in the expected state */ 756 static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id) 757 { 758 struct drm_i915_private *dev_priv = guc_to_i915(guc); 759 i915_reg_t drbreg = GEN8_DRBREGL(db_id); 760 uint32_t value = I915_READ(drbreg); 761 bool enabled = (value & GUC_DOORBELL_ENABLED) != 0; 762 bool expected = test_bit(db_id, guc->doorbell_bitmap); 763 764 if (enabled == expected) 765 return true; 766 767 DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n", 768 db_id, drbreg.reg, value, 769 expected ? "active" : "inactive"); 770 771 return false; 772 } 773 774 /* 775 * Borrow the first client to set up & tear down each unused doorbell 776 * in turn, to ensure that all doorbell h/w is (re)initialised. 777 */ 778 static void guc_init_doorbell_hw(struct intel_guc *guc) 779 { 780 struct i915_guc_client *client = guc->execbuf_client; 781 uint16_t db_id; 782 int i, err; 783 784 /* Save client's original doorbell selection */ 785 db_id = client->doorbell_id; 786 787 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) { 788 /* Skip if doorbell is OK */ 789 if (guc_doorbell_check(guc, i)) 790 continue; 791 792 err = guc_update_doorbell_id(guc, client, i); 793 if (err) 794 DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n", 795 i, err); 796 } 797 798 /* Restore to original value */ 799 err = guc_update_doorbell_id(guc, client, db_id); 800 if (err) 801 DRM_WARN("Failed to restore doorbell to %d, err %d\n", 802 db_id, err); 803 804 /* Read back & verify all doorbell registers */ 805 for (i = 0; i < GUC_MAX_DOORBELLS; ++i) 806 (void)guc_doorbell_check(guc, i); 807 } 808 809 /** 810 * guc_client_alloc() - Allocate an i915_guc_client 811 * @dev_priv: driver private data structure 812 * @engines: The set of engines to enable for this client 813 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW 814 * The kernel client to replace ExecList submission is created with 815 * NORMAL priority. Priority of a client for scheduler can be HIGH, 816 * while a preemption context can use CRITICAL. 817 * @ctx: the context that owns the client (we use the default render 818 * context) 819 * 820 * Return: An i915_guc_client object if success, else NULL. 821 */ 822 static struct i915_guc_client * 823 guc_client_alloc(struct drm_i915_private *dev_priv, 824 uint32_t engines, 825 uint32_t priority, 826 struct i915_gem_context *ctx) 827 { 828 struct i915_guc_client *client; 829 struct intel_guc *guc = &dev_priv->guc; 830 struct i915_vma *vma; 831 void *vaddr; 832 uint16_t db_id; 833 834 client = kzalloc(sizeof(*client), GFP_KERNEL); 835 if (!client) 836 return NULL; 837 838 client->owner = ctx; 839 client->guc = guc; 840 client->engines = engines; 841 client->priority = priority; 842 client->doorbell_id = GUC_INVALID_DOORBELL_ID; 843 844 client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, 845 GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); 846 if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { 847 client->ctx_index = GUC_INVALID_CTX_ID; 848 goto err; 849 } 850 851 /* The first page is doorbell/proc_desc. Two followed pages are wq. */ 852 vma = guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE); 853 if (IS_ERR(vma)) 854 goto err; 855 856 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ 857 client->vma = vma; 858 859 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 860 if (IS_ERR(vaddr)) 861 goto err; 862 863 client->vaddr = vaddr; 864 865 lockinit(&client->wq_lock, "i9gcwql", 0, 0); 866 client->wq_offset = GUC_DB_SIZE; 867 client->wq_size = GUC_WQ_SIZE; 868 869 db_id = select_doorbell_register(guc, client->priority); 870 if (db_id == GUC_INVALID_DOORBELL_ID) 871 /* XXX: evict a doorbell instead? */ 872 goto err; 873 874 client->doorbell_offset = select_doorbell_cacheline(guc); 875 876 /* 877 * Since the doorbell only requires a single cacheline, we can save 878 * space by putting the application process descriptor in the same 879 * page. Use the half of the page that doesn't include the doorbell. 880 */ 881 if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) 882 client->proc_desc_offset = 0; 883 else 884 client->proc_desc_offset = (GUC_DB_SIZE / 2); 885 886 guc_proc_desc_init(guc, client); 887 guc_ctx_desc_init(guc, client); 888 if (guc_init_doorbell(guc, client, db_id)) 889 goto err; 890 891 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n", 892 priority, client, client->engines, client->ctx_index); 893 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n", 894 client->doorbell_id, client->doorbell_offset); 895 896 return client; 897 898 err: 899 guc_client_free(dev_priv, client); 900 return NULL; 901 } 902 903 #if 0 904 /* 905 * Sub buffer switch callback. Called whenever relay has to switch to a new 906 * sub buffer, relay stays on the same sub buffer if 0 is returned. 907 */ 908 static int subbuf_start_callback(struct rchan_buf *buf, 909 void *subbuf, 910 void *prev_subbuf, 911 size_t prev_padding) 912 { 913 /* Use no-overwrite mode by default, where relay will stop accepting 914 * new data if there are no empty sub buffers left. 915 * There is no strict synchronization enforced by relay between Consumer 916 * and Producer. In overwrite mode, there is a possibility of getting 917 * inconsistent/garbled data, the producer could be writing on to the 918 * same sub buffer from which Consumer is reading. This can't be avoided 919 * unless Consumer is fast enough and can always run in tandem with 920 * Producer. 921 */ 922 if (relay_buf_full(buf)) 923 return 0; 924 925 return 1; 926 } 927 928 /* 929 * file_create() callback. Creates relay file in debugfs. 930 */ 931 static struct dentry *create_buf_file_callback(const char *filename, 932 struct dentry *parent, 933 umode_t mode, 934 struct rchan_buf *buf, 935 int *is_global) 936 { 937 struct dentry *buf_file; 938 939 /* This to enable the use of a single buffer for the relay channel and 940 * correspondingly have a single file exposed to User, through which 941 * it can collect the logs in order without any post-processing. 942 * Need to set 'is_global' even if parent is NULL for early logging. 943 */ 944 *is_global = 1; 945 946 if (!parent) 947 return NULL; 948 949 /* Not using the channel filename passed as an argument, since for each 950 * channel relay appends the corresponding CPU number to the filename 951 * passed in relay_open(). This should be fine as relay just needs a 952 * dentry of the file associated with the channel buffer and that file's 953 * name need not be same as the filename passed as an argument. 954 */ 955 buf_file = debugfs_create_file("guc_log", mode, 956 parent, buf, &relay_file_operations); 957 return buf_file; 958 } 959 960 /* 961 * file_remove() default callback. Removes relay file in debugfs. 962 */ 963 static int remove_buf_file_callback(struct dentry *dentry) 964 { 965 debugfs_remove(dentry); 966 return 0; 967 } 968 969 /* relay channel callbacks */ 970 static struct rchan_callbacks relay_callbacks = { 971 .subbuf_start = subbuf_start_callback, 972 .create_buf_file = create_buf_file_callback, 973 .remove_buf_file = remove_buf_file_callback, 974 }; 975 976 static void guc_log_remove_relay_file(struct intel_guc *guc) 977 { 978 relay_close(guc->log.relay_chan); 979 } 980 981 static int guc_log_create_relay_channel(struct intel_guc *guc) 982 { 983 struct drm_i915_private *dev_priv = guc_to_i915(guc); 984 struct rchan *guc_log_relay_chan; 985 size_t n_subbufs, subbuf_size; 986 987 /* Keep the size of sub buffers same as shared log buffer */ 988 subbuf_size = guc->log.vma->obj->base.size; 989 990 /* Store up to 8 snapshots, which is large enough to buffer sufficient 991 * boot time logs and provides enough leeway to User, in terms of 992 * latency, for consuming the logs from relay. Also doesn't take 993 * up too much memory. 994 */ 995 n_subbufs = 8; 996 997 guc_log_relay_chan = relay_open(NULL, NULL, subbuf_size, 998 n_subbufs, &relay_callbacks, dev_priv); 999 if (!guc_log_relay_chan) { 1000 DRM_ERROR("Couldn't create relay chan for GuC logging\n"); 1001 return -ENOMEM; 1002 } 1003 1004 GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size); 1005 guc->log.relay_chan = guc_log_relay_chan; 1006 return 0; 1007 } 1008 1009 static int guc_log_create_relay_file(struct intel_guc *guc) 1010 { 1011 struct drm_i915_private *dev_priv = guc_to_i915(guc); 1012 struct dentry *log_dir; 1013 int ret; 1014 1015 /* For now create the log file in /sys/kernel/debug/dri/0 dir */ 1016 log_dir = dev_priv->drm.primary->debugfs_root; 1017 1018 /* If /sys/kernel/debug/dri/0 location do not exist, then debugfs is 1019 * not mounted and so can't create the relay file. 1020 * The relay API seems to fit well with debugfs only, for availing relay 1021 * there are 3 requirements which can be met for debugfs file only in a 1022 * straightforward/clean manner :- 1023 * i) Need the associated dentry pointer of the file, while opening the 1024 * relay channel. 1025 * ii) Should be able to use 'relay_file_operations' fops for the file. 1026 * iii) Set the 'i_private' field of file's inode to the pointer of 1027 * relay channel buffer. 1028 */ 1029 if (!log_dir) { 1030 DRM_ERROR("Debugfs dir not available yet for GuC log file\n"); 1031 return -ENODEV; 1032 } 1033 1034 ret = relay_late_setup_files(guc->log.relay_chan, "guc_log", log_dir); 1035 if (ret) { 1036 DRM_ERROR("Couldn't associate relay chan with file %d\n", ret); 1037 return ret; 1038 } 1039 1040 return 0; 1041 } 1042 1043 static void guc_move_to_next_buf(struct intel_guc *guc) 1044 { 1045 /* Make sure the updates made in the sub buffer are visible when 1046 * Consumer sees the following update to offset inside the sub buffer. 1047 */ 1048 smp_wmb(); 1049 1050 /* All data has been written, so now move the offset of sub buffer. */ 1051 relay_reserve(guc->log.relay_chan, guc->log.vma->obj->base.size); 1052 1053 /* Switch to the next sub buffer */ 1054 relay_flush(guc->log.relay_chan); 1055 } 1056 1057 static void *guc_get_write_buffer(struct intel_guc *guc) 1058 { 1059 if (!guc->log.relay_chan) 1060 return NULL; 1061 1062 /* Just get the base address of a new sub buffer and copy data into it 1063 * ourselves. NULL will be returned in no-overwrite mode, if all sub 1064 * buffers are full. Could have used the relay_write() to indirectly 1065 * copy the data, but that would have been bit convoluted, as we need to 1066 * write to only certain locations inside a sub buffer which cannot be 1067 * done without using relay_reserve() along with relay_write(). So its 1068 * better to use relay_reserve() alone. 1069 */ 1070 return relay_reserve(guc->log.relay_chan, 0); 1071 } 1072 1073 static bool 1074 guc_check_log_buf_overflow(struct intel_guc *guc, 1075 enum guc_log_buffer_type type, unsigned int full_cnt) 1076 { 1077 unsigned int prev_full_cnt = guc->log.prev_overflow_count[type]; 1078 bool overflow = false; 1079 1080 if (full_cnt != prev_full_cnt) { 1081 overflow = true; 1082 1083 guc->log.prev_overflow_count[type] = full_cnt; 1084 guc->log.total_overflow_count[type] += full_cnt - prev_full_cnt; 1085 1086 if (full_cnt < prev_full_cnt) { 1087 /* buffer_full_cnt is a 4 bit counter */ 1088 guc->log.total_overflow_count[type] += 16; 1089 } 1090 DRM_ERROR_RATELIMITED("GuC log buffer overflow\n"); 1091 } 1092 1093 return overflow; 1094 } 1095 1096 static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type) 1097 { 1098 switch (type) { 1099 case GUC_ISR_LOG_BUFFER: 1100 return (GUC_LOG_ISR_PAGES + 1) * PAGE_SIZE; 1101 case GUC_DPC_LOG_BUFFER: 1102 return (GUC_LOG_DPC_PAGES + 1) * PAGE_SIZE; 1103 case GUC_CRASH_DUMP_LOG_BUFFER: 1104 return (GUC_LOG_CRASH_PAGES + 1) * PAGE_SIZE; 1105 default: 1106 MISSING_CASE(type); 1107 } 1108 1109 return 0; 1110 } 1111 1112 static void guc_read_update_log_buffer(struct intel_guc *guc) 1113 { 1114 unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt; 1115 struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state; 1116 struct guc_log_buffer_state log_buf_state_local; 1117 enum guc_log_buffer_type type; 1118 void *src_data, *dst_data; 1119 bool new_overflow; 1120 1121 if (WARN_ON(!guc->log.buf_addr)) 1122 return; 1123 1124 /* Get the pointer to shared GuC log buffer */ 1125 log_buf_state = src_data = guc->log.buf_addr; 1126 1127 /* Get the pointer to local buffer to store the logs */ 1128 log_buf_snapshot_state = dst_data = guc_get_write_buffer(guc); 1129 1130 /* Actual logs are present from the 2nd page */ 1131 src_data += PAGE_SIZE; 1132 dst_data += PAGE_SIZE; 1133 1134 for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) { 1135 /* Make a copy of the state structure, inside GuC log buffer 1136 * (which is uncached mapped), on the stack to avoid reading 1137 * from it multiple times. 1138 */ 1139 memcpy(&log_buf_state_local, log_buf_state, 1140 sizeof(struct guc_log_buffer_state)); 1141 buffer_size = guc_get_log_buffer_size(type); 1142 read_offset = log_buf_state_local.read_ptr; 1143 write_offset = log_buf_state_local.sampled_write_ptr; 1144 full_cnt = log_buf_state_local.buffer_full_cnt; 1145 1146 /* Bookkeeping stuff */ 1147 guc->log.flush_count[type] += log_buf_state_local.flush_to_file; 1148 new_overflow = guc_check_log_buf_overflow(guc, type, full_cnt); 1149 1150 /* Update the state of shared log buffer */ 1151 log_buf_state->read_ptr = write_offset; 1152 log_buf_state->flush_to_file = 0; 1153 log_buf_state++; 1154 1155 if (unlikely(!log_buf_snapshot_state)) 1156 continue; 1157 1158 /* First copy the state structure in snapshot buffer */ 1159 memcpy(log_buf_snapshot_state, &log_buf_state_local, 1160 sizeof(struct guc_log_buffer_state)); 1161 1162 /* The write pointer could have been updated by GuC firmware, 1163 * after sending the flush interrupt to Host, for consistency 1164 * set write pointer value to same value of sampled_write_ptr 1165 * in the snapshot buffer. 1166 */ 1167 log_buf_snapshot_state->write_ptr = write_offset; 1168 log_buf_snapshot_state++; 1169 1170 /* Now copy the actual logs. */ 1171 if (unlikely(new_overflow)) { 1172 /* copy the whole buffer in case of overflow */ 1173 read_offset = 0; 1174 write_offset = buffer_size; 1175 } else if (unlikely((read_offset > buffer_size) || 1176 (write_offset > buffer_size))) { 1177 DRM_ERROR("invalid log buffer state\n"); 1178 /* copy whole buffer as offsets are unreliable */ 1179 read_offset = 0; 1180 write_offset = buffer_size; 1181 } 1182 1183 /* Just copy the newly written data */ 1184 if (read_offset > write_offset) { 1185 i915_memcpy_from_wc(dst_data, src_data, write_offset); 1186 bytes_to_copy = buffer_size - read_offset; 1187 } else { 1188 bytes_to_copy = write_offset - read_offset; 1189 } 1190 i915_memcpy_from_wc(dst_data + read_offset, 1191 src_data + read_offset, bytes_to_copy); 1192 1193 src_data += buffer_size; 1194 dst_data += buffer_size; 1195 } 1196 1197 if (log_buf_snapshot_state) 1198 guc_move_to_next_buf(guc); 1199 else { 1200 /* Used rate limited to avoid deluge of messages, logs might be 1201 * getting consumed by User at a slow rate. 1202 */ 1203 DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n"); 1204 guc->log.capture_miss_count++; 1205 } 1206 } 1207 1208 static void guc_capture_logs_work(struct work_struct *work) 1209 { 1210 struct drm_i915_private *dev_priv = 1211 container_of(work, struct drm_i915_private, guc.log.flush_work); 1212 1213 i915_guc_capture_logs(dev_priv); 1214 } 1215 1216 static void guc_log_cleanup(struct intel_guc *guc) 1217 { 1218 struct drm_i915_private *dev_priv = guc_to_i915(guc); 1219 1220 lockdep_assert_held(&dev_priv->drm.struct_mutex); 1221 1222 /* First disable the flush interrupt */ 1223 gen9_disable_guc_interrupts(dev_priv); 1224 1225 if (guc->log.flush_wq) 1226 destroy_workqueue(guc->log.flush_wq); 1227 1228 guc->log.flush_wq = NULL; 1229 1230 if (guc->log.relay_chan) 1231 guc_log_remove_relay_file(guc); 1232 1233 guc->log.relay_chan = NULL; 1234 1235 if (guc->log.buf_addr) 1236 i915_gem_object_unpin_map(guc->log.vma->obj); 1237 1238 guc->log.buf_addr = NULL; 1239 } 1240 1241 static int guc_log_create_extras(struct intel_guc *guc) 1242 { 1243 struct drm_i915_private *dev_priv = guc_to_i915(guc); 1244 void *vaddr; 1245 int ret; 1246 1247 lockdep_assert_held(&dev_priv->drm.struct_mutex); 1248 1249 /* Nothing to do */ 1250 if (i915.guc_log_level < 0) 1251 return 0; 1252 1253 if (!guc->log.buf_addr) { 1254 /* Create a WC (Uncached for read) vmalloc mapping of log 1255 * buffer pages, so that we can directly get the data 1256 * (up-to-date) from memory. 1257 */ 1258 vaddr = i915_gem_object_pin_map(guc->log.vma->obj, I915_MAP_WC); 1259 if (IS_ERR(vaddr)) { 1260 ret = PTR_ERR(vaddr); 1261 DRM_ERROR("Couldn't map log buffer pages %d\n", ret); 1262 return ret; 1263 } 1264 1265 guc->log.buf_addr = vaddr; 1266 } 1267 1268 if (!guc->log.relay_chan) { 1269 /* Create a relay channel, so that we have buffers for storing 1270 * the GuC firmware logs, the channel will be linked with a file 1271 * later on when debugfs is registered. 1272 */ 1273 ret = guc_log_create_relay_channel(guc); 1274 if (ret) 1275 return ret; 1276 } 1277 1278 if (!guc->log.flush_wq) { 1279 INIT_WORK(&guc->log.flush_work, guc_capture_logs_work); 1280 1281 /* 1282 * GuC log buffer flush work item has to do register access to 1283 * send the ack to GuC and this work item, if not synced before 1284 * suspend, can potentially get executed after the GFX device is 1285 * suspended. 1286 * By marking the WQ as freezable, we don't have to bother about 1287 * flushing of this work item from the suspend hooks, the pending 1288 * work item if any will be either executed before the suspend 1289 * or scheduled later on resume. This way the handling of work 1290 * item can be kept same between system suspend & rpm suspend. 1291 */ 1292 guc->log.flush_wq = alloc_ordered_workqueue("i915-guc_log", 1293 WQ_HIGHPRI | WQ_FREEZABLE); 1294 if (guc->log.flush_wq == NULL) { 1295 DRM_ERROR("Couldn't allocate the wq for GuC logging\n"); 1296 return -ENOMEM; 1297 } 1298 } 1299 1300 return 0; 1301 } 1302 #endif 1303 1304 static void guc_log_create(struct intel_guc *guc) 1305 { 1306 struct i915_vma *vma; 1307 unsigned long offset; 1308 uint32_t size, flags; 1309 1310 if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) 1311 i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; 1312 1313 /* The first page is to save log buffer state. Allocate one 1314 * extra page for others in case for overlap */ 1315 size = (1 + GUC_LOG_DPC_PAGES + 1 + 1316 GUC_LOG_ISR_PAGES + 1 + 1317 GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; 1318 1319 vma = guc->log.vma; 1320 if (!vma) { 1321 /* We require SSE 4.1 for fast reads from the GuC log buffer and 1322 * it should be present on the chipsets supporting GuC based 1323 * submisssions. 1324 */ 1325 if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) { 1326 /* logging will not be enabled */ 1327 i915.guc_log_level = -1; 1328 return; 1329 } 1330 1331 vma = guc_allocate_vma(guc, size); 1332 if (IS_ERR(vma)) { 1333 /* logging will be off */ 1334 i915.guc_log_level = -1; 1335 return; 1336 } 1337 1338 guc->log.vma = vma; 1339 1340 #if 0 1341 if (guc_log_create_extras(guc)) { 1342 guc_log_cleanup(guc); 1343 i915_vma_unpin_and_release(&guc->log.vma); 1344 i915.guc_log_level = -1; 1345 return; 1346 } 1347 #endif 1348 } 1349 1350 /* each allocated unit is a page */ 1351 flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | 1352 (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | 1353 (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | 1354 (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); 1355 1356 offset = i915_ggtt_offset(vma) >> PAGE_SHIFT; /* in pages */ 1357 guc->log.flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; 1358 } 1359 1360 #if 0 1361 static int guc_log_late_setup(struct intel_guc *guc) 1362 { 1363 struct drm_i915_private *dev_priv = guc_to_i915(guc); 1364 int ret; 1365 1366 lockdep_assert_held(&dev_priv->drm.struct_mutex); 1367 1368 if (i915.guc_log_level < 0) 1369 return -EINVAL; 1370 1371 /* If log_level was set as -1 at boot time, then setup needed to 1372 * handle log buffer flush interrupts would not have been done yet, 1373 * so do that now. 1374 */ 1375 ret = guc_log_create_extras(guc); 1376 if (ret) 1377 goto err; 1378 1379 ret = guc_log_create_relay_file(guc); 1380 if (ret) 1381 goto err; 1382 1383 return 0; 1384 err: 1385 guc_log_cleanup(guc); 1386 /* logging will remain off */ 1387 i915.guc_log_level = -1; 1388 return ret; 1389 } 1390 #endif 1391 1392 static void guc_policies_init(struct guc_policies *policies) 1393 { 1394 struct guc_policy *policy; 1395 u32 p, i; 1396 1397 policies->dpc_promote_time = 500000; 1398 policies->max_num_work_items = POLICY_MAX_NUM_WI; 1399 1400 for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { 1401 for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { 1402 policy = &policies->policy[p][i]; 1403 1404 policy->execution_quantum = 1000000; 1405 policy->preemption_time = 500000; 1406 policy->fault_time = 250000; 1407 policy->policy_flags = 0; 1408 } 1409 } 1410 1411 policies->is_valid = 1; 1412 } 1413 1414 static void guc_addon_create(struct intel_guc *guc) 1415 { 1416 struct drm_i915_private *dev_priv = guc_to_i915(guc); 1417 struct i915_vma *vma; 1418 struct guc_ads *ads; 1419 struct guc_policies *policies; 1420 struct guc_mmio_reg_state *reg_state; 1421 struct intel_engine_cs *engine; 1422 enum intel_engine_id id; 1423 struct page *page; 1424 u32 size; 1425 1426 /* The ads obj includes the struct itself and buffers passed to GuC */ 1427 size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + 1428 sizeof(struct guc_mmio_reg_state) + 1429 GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; 1430 1431 vma = guc->ads_vma; 1432 if (!vma) { 1433 vma = guc_allocate_vma(guc, PAGE_ALIGN(size)); 1434 if (IS_ERR(vma)) 1435 return; 1436 1437 guc->ads_vma = vma; 1438 } 1439 1440 page = i915_vma_first_page(vma); 1441 ads = kmap(page); 1442 1443 /* 1444 * The GuC requires a "Golden Context" when it reinitialises 1445 * engines after a reset. Here we use the Render ring default 1446 * context, which must already exist and be pinned in the GGTT, 1447 * so its address won't change after we've told the GuC where 1448 * to find it. 1449 */ 1450 engine = dev_priv->engine[RCS]; 1451 ads->golden_context_lrca = engine->status_page.ggtt_offset; 1452 1453 for_each_engine(engine, dev_priv, id) 1454 ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); 1455 1456 /* GuC scheduling policies */ 1457 policies = (void *)ads + sizeof(struct guc_ads); 1458 guc_policies_init(policies); 1459 1460 ads->scheduler_policies = 1461 i915_ggtt_offset(vma) + sizeof(struct guc_ads); 1462 1463 /* MMIO reg state */ 1464 reg_state = (void *)policies + sizeof(struct guc_policies); 1465 1466 for_each_engine(engine, dev_priv, id) { 1467 reg_state->mmio_white_list[engine->guc_id].mmio_start = 1468 engine->mmio_base + GUC_MMIO_WHITE_LIST_START; 1469 1470 /* Nothing to be saved or restored for now. */ 1471 reg_state->mmio_white_list[engine->guc_id].count = 0; 1472 } 1473 1474 ads->reg_state_addr = ads->scheduler_policies + 1475 sizeof(struct guc_policies); 1476 1477 ads->reg_state_buffer = ads->reg_state_addr + 1478 sizeof(struct guc_mmio_reg_state); 1479 1480 kunmap(page); 1481 } 1482 1483 /* 1484 * Set up the memory resources to be shared with the GuC. At this point, 1485 * we require just one object that can be mapped through the GGTT. 1486 */ 1487 int i915_guc_submission_init(struct drm_i915_private *dev_priv) 1488 { 1489 const size_t ctxsize = sizeof(struct guc_context_desc); 1490 const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; 1491 const size_t gemsize = round_up(poolsize, PAGE_SIZE); 1492 struct intel_guc *guc = &dev_priv->guc; 1493 struct i915_vma *vma; 1494 1495 /* Wipe bitmap & delete client in case of reinitialisation */ 1496 bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS); 1497 i915_guc_submission_disable(dev_priv); 1498 1499 if (!i915.enable_guc_submission) 1500 return 0; /* not enabled */ 1501 1502 if (guc->ctx_pool_vma) 1503 return 0; /* already allocated */ 1504 1505 vma = guc_allocate_vma(guc, gemsize); 1506 if (IS_ERR(vma)) 1507 return PTR_ERR(vma); 1508 1509 guc->ctx_pool_vma = vma; 1510 ida_init(&guc->ctx_ids); 1511 lockinit(&guc->action_lock, "i9gac", 0, LK_CANRECURSE); 1512 guc_log_create(guc); 1513 guc_addon_create(guc); 1514 1515 return 0; 1516 } 1517 1518 int i915_guc_submission_enable(struct drm_i915_private *dev_priv) 1519 { 1520 struct intel_guc *guc = &dev_priv->guc; 1521 struct drm_i915_gem_request *request; 1522 struct i915_guc_client *client; 1523 struct intel_engine_cs *engine; 1524 enum intel_engine_id id; 1525 1526 /* client for execbuf submission */ 1527 client = guc_client_alloc(dev_priv, 1528 INTEL_INFO(dev_priv)->ring_mask, 1529 GUC_CTX_PRIORITY_KMD_NORMAL, 1530 dev_priv->kernel_context); 1531 if (!client) { 1532 DRM_ERROR("Failed to create normal GuC client!\n"); 1533 return -ENOMEM; 1534 } 1535 1536 guc->execbuf_client = client; 1537 host2guc_sample_forcewake(guc, client); 1538 guc_init_doorbell_hw(guc); 1539 1540 /* Take over from manual control of ELSP (execlists) */ 1541 for_each_engine(engine, dev_priv, id) { 1542 engine->submit_request = i915_guc_submit; 1543 engine->schedule = NULL; 1544 1545 /* Replay the current set of previously submitted requests */ 1546 list_for_each_entry(request, 1547 &engine->timeline->requests, link) { 1548 client->wq_rsvd += sizeof(struct guc_wq_item); 1549 if (i915_sw_fence_done(&request->submit)) 1550 i915_guc_submit(request); 1551 } 1552 } 1553 1554 return 0; 1555 } 1556 1557 void i915_guc_submission_disable(struct drm_i915_private *dev_priv) 1558 { 1559 struct intel_guc *guc = &dev_priv->guc; 1560 1561 if (!guc->execbuf_client) 1562 return; 1563 1564 /* Revert back to manual ELSP submission */ 1565 intel_execlists_enable_submission(dev_priv); 1566 1567 guc_client_free(dev_priv, guc->execbuf_client); 1568 guc->execbuf_client = NULL; 1569 } 1570 1571 void i915_guc_submission_fini(struct drm_i915_private *dev_priv) 1572 { 1573 struct intel_guc *guc = &dev_priv->guc; 1574 1575 i915_vma_unpin_and_release(&guc->ads_vma); 1576 i915_vma_unpin_and_release(&guc->log.vma); 1577 1578 if (guc->ctx_pool_vma) 1579 ida_destroy(&guc->ctx_ids); 1580 i915_vma_unpin_and_release(&guc->ctx_pool_vma); 1581 } 1582 1583 /** 1584 * intel_guc_suspend() - notify GuC entering suspend state 1585 * @dev: drm device 1586 */ 1587 int intel_guc_suspend(struct drm_device *dev) 1588 { 1589 struct drm_i915_private *dev_priv = to_i915(dev); 1590 struct intel_guc *guc = &dev_priv->guc; 1591 struct i915_gem_context *ctx; 1592 u32 data[3]; 1593 1594 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) 1595 return 0; 1596 1597 gen9_disable_guc_interrupts(dev_priv); 1598 1599 ctx = dev_priv->kernel_context; 1600 1601 data[0] = HOST2GUC_ACTION_ENTER_S_STATE; 1602 /* any value greater than GUC_POWER_D0 */ 1603 data[1] = GUC_POWER_D1; 1604 /* first page is shared data with GuC */ 1605 data[2] = i915_ggtt_offset(ctx->engine[RCS].state); 1606 1607 return host2guc_action(guc, data, ARRAY_SIZE(data)); 1608 } 1609 1610 1611 /** 1612 * intel_guc_resume() - notify GuC resuming from suspend state 1613 * @dev: drm device 1614 */ 1615 int intel_guc_resume(struct drm_device *dev) 1616 { 1617 struct drm_i915_private *dev_priv = to_i915(dev); 1618 struct intel_guc *guc = &dev_priv->guc; 1619 struct i915_gem_context *ctx; 1620 u32 data[3]; 1621 1622 if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) 1623 return 0; 1624 1625 if (i915.guc_log_level >= 0) 1626 gen9_enable_guc_interrupts(dev_priv); 1627 1628 ctx = dev_priv->kernel_context; 1629 1630 data[0] = HOST2GUC_ACTION_EXIT_S_STATE; 1631 data[1] = GUC_POWER_D0; 1632 /* first page is shared data with GuC */ 1633 data[2] = i915_ggtt_offset(ctx->engine[RCS].state); 1634 1635 return host2guc_action(guc, data, ARRAY_SIZE(data)); 1636 } 1637 1638 void i915_guc_capture_logs(struct drm_i915_private *dev_priv) 1639 { 1640 #if 0 1641 guc_read_update_log_buffer(&dev_priv->guc); 1642 1643 /* Generally device is expected to be active only at this 1644 * time, so get/put should be really quick. 1645 */ 1646 intel_runtime_pm_get(dev_priv); 1647 host2guc_logbuffer_flush_complete(&dev_priv->guc); 1648 intel_runtime_pm_put(dev_priv); 1649 #endif 1650 } 1651 1652 void i915_guc_flush_logs(struct drm_i915_private *dev_priv) 1653 { 1654 if (!i915.enable_guc_submission || (i915.guc_log_level < 0)) 1655 return; 1656 1657 /* First disable the interrupts, will be renabled afterwards */ 1658 gen9_disable_guc_interrupts(dev_priv); 1659 1660 /* Before initiating the forceful flush, wait for any pending/ongoing 1661 * flush to complete otherwise forceful flush may not actually happen. 1662 */ 1663 flush_work(&dev_priv->guc.log.flush_work); 1664 1665 /* Ask GuC to update the log buffer state */ 1666 host2guc_force_logbuffer_flush(&dev_priv->guc); 1667 1668 /* GuC would have updated log buffer by now, so capture it */ 1669 i915_guc_capture_logs(dev_priv); 1670 } 1671 1672 void i915_guc_unregister(struct drm_i915_private *dev_priv) 1673 { 1674 if (!i915.enable_guc_submission) 1675 return; 1676 1677 mutex_lock(&dev_priv->drm.struct_mutex); 1678 #if 0 1679 guc_log_cleanup(&dev_priv->guc); 1680 #endif 1681 mutex_unlock(&dev_priv->drm.struct_mutex); 1682 } 1683 1684 void i915_guc_register(struct drm_i915_private *dev_priv) 1685 { 1686 if (!i915.enable_guc_submission) 1687 return; 1688 1689 mutex_lock(&dev_priv->drm.struct_mutex); 1690 #if 0 1691 guc_log_late_setup(&dev_priv->guc); 1692 #endif 1693 mutex_unlock(&dev_priv->drm.struct_mutex); 1694 } 1695 1696 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val) 1697 { 1698 union guc_log_control log_param; 1699 int ret; 1700 1701 log_param.value = control_val; 1702 1703 if (log_param.verbosity < GUC_LOG_VERBOSITY_MIN || 1704 log_param.verbosity > GUC_LOG_VERBOSITY_MAX) 1705 return -EINVAL; 1706 1707 /* This combination doesn't make sense & won't have any effect */ 1708 if (!log_param.logging_enabled && (i915.guc_log_level < 0)) 1709 return 0; 1710 1711 ret = host2guc_logging_control(&dev_priv->guc, log_param.value); 1712 if (ret < 0) { 1713 DRM_DEBUG_DRIVER("host2guc action failed %d\n", ret); 1714 return ret; 1715 } 1716 1717 i915.guc_log_level = log_param.verbosity; 1718 1719 /* If log_level was set as -1 at boot time, then the relay channel file 1720 * wouldn't have been created by now and interrupts also would not have 1721 * been enabled. 1722 */ 1723 if (!dev_priv->guc.log.relay_chan) { 1724 #if 0 1725 ret = guc_log_late_setup(&dev_priv->guc); 1726 if (!ret) 1727 gen9_enable_guc_interrupts(dev_priv); 1728 #endif 1729 } else if (!log_param.logging_enabled) { 1730 /* Once logging is disabled, GuC won't generate logs & send an 1731 * interrupt. But there could be some data in the log buffer 1732 * which is yet to be captured. So request GuC to update the log 1733 * buffer state and then collect the left over logs. 1734 */ 1735 i915_guc_flush_logs(dev_priv); 1736 1737 /* As logging is disabled, update log level to reflect that */ 1738 i915.guc_log_level = -1; 1739 } else { 1740 /* In case interrupts were disabled, enable them now */ 1741 gen9_enable_guc_interrupts(dev_priv); 1742 } 1743 1744 return ret; 1745 } 1746