1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/i915_drm.h> 31 #include "i915_drv.h" 32 #include "intel_drv.h" 33 34 /* For display hotplug interrupt */ 35 static void 36 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 37 { 38 if ((dev_priv->irq_mask & mask) != 0) { 39 dev_priv->irq_mask &= ~mask; 40 I915_WRITE(DEIMR, dev_priv->irq_mask); 41 POSTING_READ(DEIMR); 42 } 43 } 44 45 static inline void 46 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 47 { 48 if ((dev_priv->irq_mask & mask) != mask) { 49 dev_priv->irq_mask |= mask; 50 I915_WRITE(DEIMR, dev_priv->irq_mask); 51 POSTING_READ(DEIMR); 52 } 53 } 54 55 void 56 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 57 { 58 if ((dev_priv->pipestat[pipe] & mask) != mask) { 59 u32 reg = PIPESTAT(pipe); 60 61 dev_priv->pipestat[pipe] |= mask; 62 /* Enable the interrupt, clear any pending status */ 63 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 64 POSTING_READ(reg); 65 } 66 } 67 68 void 69 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 70 { 71 if ((dev_priv->pipestat[pipe] & mask) != 0) { 72 u32 reg = PIPESTAT(pipe); 73 74 dev_priv->pipestat[pipe] &= ~mask; 75 I915_WRITE(reg, dev_priv->pipestat[pipe]); 76 POSTING_READ(reg); 77 } 78 } 79 80 /** 81 * intel_enable_asle - enable ASLE interrupt for OpRegion 82 */ 83 void intel_enable_asle(struct drm_device *dev) 84 { 85 drm_i915_private_t *dev_priv = dev->dev_private; 86 87 /* FIXME: opregion/asle for VLV */ 88 if (IS_VALLEYVIEW(dev)) 89 return; 90 91 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 92 93 if (HAS_PCH_SPLIT(dev)) 94 ironlake_enable_display_irq(dev_priv, DE_GSE); 95 else { 96 i915_enable_pipestat(dev_priv, 1, 97 PIPE_LEGACY_BLC_EVENT_ENABLE); 98 if (INTEL_INFO(dev)->gen >= 4) 99 i915_enable_pipestat(dev_priv, 0, 100 PIPE_LEGACY_BLC_EVENT_ENABLE); 101 } 102 103 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 104 } 105 106 /** 107 * i915_pipe_enabled - check if a pipe is enabled 108 * @dev: DRM device 109 * @pipe: pipe to check 110 * 111 * Reading certain registers when the pipe is disabled can hang the chip. 112 * Use this routine to make sure the PLL is running and the pipe is active 113 * before reading such registers if unsure. 114 */ 115 static int 116 i915_pipe_enabled(struct drm_device *dev, int pipe) 117 { 118 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 120 pipe); 121 122 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE; 123 } 124 125 /* Called from drm generic code, passed a 'crtc', which 126 * we use as a pipe index 127 */ 128 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 129 { 130 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 131 unsigned long high_frame; 132 unsigned long low_frame; 133 u32 high1, high2, low; 134 135 if (!i915_pipe_enabled(dev, pipe)) { 136 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 137 "pipe %c\n", pipe_name(pipe)); 138 return 0; 139 } 140 141 high_frame = PIPEFRAME(pipe); 142 low_frame = PIPEFRAMEPIXEL(pipe); 143 144 /* 145 * High & low register fields aren't synchronized, so make sure 146 * we get a low value that's stable across two reads of the high 147 * register. 148 */ 149 do { 150 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 151 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; 152 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 153 } while (high1 != high2); 154 155 high1 >>= PIPE_FRAME_HIGH_SHIFT; 156 low >>= PIPE_FRAME_LOW_SHIFT; 157 return (high1 << 8) | low; 158 } 159 160 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 161 { 162 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 163 int reg = PIPE_FRMCOUNT_GM45(pipe); 164 165 if (!i915_pipe_enabled(dev, pipe)) { 166 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 167 "pipe %c\n", pipe_name(pipe)); 168 return 0; 169 } 170 171 return I915_READ(reg); 172 } 173 174 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 175 int *vpos, int *hpos) 176 { 177 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 178 u32 vbl = 0, position = 0; 179 int vbl_start, vbl_end, htotal, vtotal; 180 bool in_vbl = true; 181 int ret = 0; 182 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 183 pipe); 184 185 if (!i915_pipe_enabled(dev, pipe)) { 186 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 187 "pipe %c\n", pipe_name(pipe)); 188 return 0; 189 } 190 191 /* Get vtotal. */ 192 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); 193 194 if (INTEL_INFO(dev)->gen >= 4) { 195 /* No obvious pixelcount register. Only query vertical 196 * scanout position from Display scan line register. 197 */ 198 position = I915_READ(PIPEDSL(pipe)); 199 200 /* Decode into vertical scanout position. Don't have 201 * horizontal scanout position. 202 */ 203 *vpos = position & 0x1fff; 204 *hpos = 0; 205 } else { 206 /* Have access to pixelcount since start of frame. 207 * We can split this into vertical and horizontal 208 * scanout position. 209 */ 210 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 211 212 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff); 213 *vpos = position / htotal; 214 *hpos = position - (*vpos * htotal); 215 } 216 217 /* Query vblank area. */ 218 vbl = I915_READ(VBLANK(cpu_transcoder)); 219 220 /* Test position against vblank region. */ 221 vbl_start = vbl & 0x1fff; 222 vbl_end = (vbl >> 16) & 0x1fff; 223 224 if ((*vpos < vbl_start) || (*vpos > vbl_end)) 225 in_vbl = false; 226 227 /* Inside "upper part" of vblank area? Apply corrective offset: */ 228 if (in_vbl && (*vpos >= vbl_start)) 229 *vpos = *vpos - vtotal; 230 231 /* Readouts valid? */ 232 if (vbl > 0) 233 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 234 235 /* In vblank? */ 236 if (in_vbl) 237 ret |= DRM_SCANOUTPOS_INVBL; 238 239 return ret; 240 } 241 242 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 243 int *max_error, 244 struct timeval *vblank_time, 245 unsigned flags) 246 { 247 struct drm_i915_private *dev_priv = dev->dev_private; 248 struct drm_crtc *crtc; 249 250 if (pipe < 0 || pipe >= dev_priv->num_pipe) { 251 DRM_ERROR("Invalid crtc %d\n", pipe); 252 return -EINVAL; 253 } 254 255 /* Get drm_crtc to timestamp: */ 256 crtc = intel_get_crtc_for_pipe(dev, pipe); 257 if (crtc == NULL) { 258 DRM_ERROR("Invalid crtc %d\n", pipe); 259 return -EINVAL; 260 } 261 262 if (!crtc->enabled) { 263 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 264 return -EBUSY; 265 } 266 267 /* Helper routine in DRM core does all the work: */ 268 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 269 vblank_time, flags, 270 crtc); 271 } 272 273 /* 274 * Handle hotplug events outside the interrupt handler proper. 275 */ 276 static void i915_hotplug_work_func(struct work_struct *work) 277 { 278 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 279 hotplug_work); 280 struct drm_device *dev = dev_priv->dev; 281 struct drm_mode_config *mode_config = &dev->mode_config; 282 struct intel_encoder *encoder; 283 284 lockmgr(&mode_config->mutex, LK_EXCLUSIVE); 285 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 286 287 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 288 if (encoder->hot_plug) 289 encoder->hot_plug(encoder); 290 291 lockmgr(&mode_config->mutex, LK_RELEASE); 292 293 /* Just fire off a uevent and let userspace tell us what to do */ 294 drm_helper_hpd_irq_event(dev); 295 } 296 297 static void ironlake_handle_rps_change(struct drm_device *dev) 298 { 299 drm_i915_private_t *dev_priv = dev->dev_private; 300 u32 busy_up, busy_down, max_avg, min_avg; 301 u8 new_delay; 302 303 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 304 305 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 306 307 new_delay = dev_priv->ips.cur_delay; 308 309 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 310 busy_up = I915_READ(RCPREVBSYTUPAVG); 311 busy_down = I915_READ(RCPREVBSYTDNAVG); 312 max_avg = I915_READ(RCBMAXAVG); 313 min_avg = I915_READ(RCBMINAVG); 314 315 /* Handle RCS change request from hw */ 316 if (busy_up > max_avg) { 317 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) 318 new_delay = dev_priv->ips.cur_delay - 1; 319 if (new_delay < dev_priv->ips.max_delay) 320 new_delay = dev_priv->ips.max_delay; 321 } else if (busy_down < min_avg) { 322 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) 323 new_delay = dev_priv->ips.cur_delay + 1; 324 if (new_delay > dev_priv->ips.min_delay) 325 new_delay = dev_priv->ips.min_delay; 326 } 327 328 if (ironlake_set_drps(dev, new_delay)) 329 dev_priv->ips.cur_delay = new_delay; 330 331 lockmgr(&mchdev_lock, LK_RELEASE); 332 333 return; 334 } 335 336 static void notify_ring(struct drm_device *dev, 337 struct intel_ring_buffer *ring) 338 { 339 struct drm_i915_private *dev_priv = dev->dev_private; 340 341 if (ring->obj == NULL) 342 return; 343 344 lockmgr(&ring->irq_lock, LK_EXCLUSIVE); 345 wakeup(ring); 346 lockmgr(&ring->irq_lock, LK_RELEASE); 347 348 if (i915_enable_hangcheck) { 349 dev_priv->hangcheck_count = 0; 350 mod_timer(&dev_priv->hangcheck_timer, 351 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 352 } 353 } 354 355 static void gen6_pm_rps_work(struct work_struct *work) 356 { 357 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 358 rps.work); 359 u32 pm_iir, pm_imr; 360 u8 new_delay; 361 362 spin_lock(&dev_priv->rps.lock); 363 pm_iir = dev_priv->rps.pm_iir; 364 dev_priv->rps.pm_iir = 0; 365 pm_imr = I915_READ(GEN6_PMIMR); 366 I915_WRITE(GEN6_PMIMR, 0); 367 spin_unlock(&dev_priv->rps.lock); 368 369 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0) 370 return; 371 372 lockmgr(&dev_priv->rps.hw_lock, LK_EXCLUSIVE); 373 374 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) 375 new_delay = dev_priv->rps.cur_delay + 1; 376 else 377 new_delay = dev_priv->rps.cur_delay - 1; 378 379 /* sysfs frequency interfaces may have snuck in while servicing the 380 * interrupt 381 */ 382 if (!(new_delay > dev_priv->rps.max_delay || 383 new_delay < dev_priv->rps.min_delay)) { 384 gen6_set_rps(dev_priv->dev, new_delay); 385 } 386 387 lockmgr(&dev_priv->rps.hw_lock, LK_RELEASE); 388 } 389 390 391 /** 392 * ivybridge_parity_work - Workqueue called when a parity error interrupt 393 * occurred. 394 * @work: workqueue struct 395 * 396 * Doesn't actually do anything except notify userspace. As a consequence of 397 * this event, userspace should try to remap the bad rows since statistically 398 * it is likely the same row is more likely to go bad again. 399 */ 400 static void ivybridge_parity_work(struct work_struct *work) 401 { 402 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 403 l3_parity.error_work); 404 u32 error_status, row, bank, subbank; 405 uint32_t misccpctl; 406 407 /* We must turn off DOP level clock gating to access the L3 registers. 408 * In order to prevent a get/put style interface, acquire struct mutex 409 * any time we access those registers. 410 */ 411 DRM_LOCK(dev_priv->dev); 412 413 misccpctl = I915_READ(GEN7_MISCCPCTL); 414 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 415 POSTING_READ(GEN7_MISCCPCTL); 416 417 error_status = I915_READ(GEN7_L3CDERRST1); 418 row = GEN7_PARITY_ERROR_ROW(error_status); 419 bank = GEN7_PARITY_ERROR_BANK(error_status); 420 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 421 422 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | 423 GEN7_L3CDERRST1_ENABLE); 424 POSTING_READ(GEN7_L3CDERRST1); 425 426 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 427 428 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 429 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 430 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 431 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 432 433 DRM_UNLOCK(dev_priv->dev); 434 435 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n", 436 row, bank, subbank); 437 } 438 439 static void ivybridge_handle_parity_error(struct drm_device *dev) 440 { 441 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 442 443 if (!HAS_L3_GPU_CACHE(dev)) 444 return; 445 446 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 447 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 448 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 449 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 450 451 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); 452 } 453 454 static void snb_gt_irq_handler(struct drm_device *dev, 455 struct drm_i915_private *dev_priv, 456 u32 gt_iir) 457 { 458 459 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | 460 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) 461 notify_ring(dev, &dev_priv->ring[RCS]); 462 if (gt_iir & GEN6_BSD_USER_INTERRUPT) 463 notify_ring(dev, &dev_priv->ring[VCS]); 464 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) 465 notify_ring(dev, &dev_priv->ring[BCS]); 466 467 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | 468 GT_GEN6_BSD_CS_ERROR_INTERRUPT | 469 GT_RENDER_CS_ERROR_INTERRUPT)) { 470 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); 471 i915_handle_error(dev, false); 472 } 473 474 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT) 475 ivybridge_handle_parity_error(dev); 476 } 477 478 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, 479 u32 pm_iir) 480 { 481 482 /* 483 * IIR bits should never already be set because IMR should 484 * prevent an interrupt from being shown in IIR. The warning 485 * displays a case where we've unsafely cleared 486 * dev_priv->rps.pm_iir. Although missing an interrupt of the same 487 * type is not a problem, it displays a problem in the logic. 488 * 489 * The mask bit in IMR is cleared by dev_priv->rps.work. 490 */ 491 492 spin_lock(&dev_priv->rps.lock); 493 dev_priv->rps.pm_iir |= pm_iir; 494 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); 495 POSTING_READ(GEN6_PMIMR); 496 spin_unlock(&dev_priv->rps.lock); 497 498 queue_work(dev_priv->wq, &dev_priv->rps.work); 499 } 500 501 static irqreturn_t valleyview_irq_handler(void *arg) 502 { 503 struct drm_device *dev = (struct drm_device *) arg; 504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 505 u32 iir, gt_iir, pm_iir; 506 int pipe; 507 u32 pipe_stats[I915_MAX_PIPES]; 508 bool blc_event; 509 510 atomic_inc(&dev_priv->irq_received); 511 512 while (true) { 513 iir = I915_READ(VLV_IIR); 514 gt_iir = I915_READ(GTIIR); 515 pm_iir = I915_READ(GEN6_PMIIR); 516 517 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 518 goto out; 519 520 snb_gt_irq_handler(dev, dev_priv, gt_iir); 521 522 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 523 for_each_pipe(pipe) { 524 int reg = PIPESTAT(pipe); 525 pipe_stats[pipe] = I915_READ(reg); 526 527 /* 528 * Clear the PIPE*STAT regs before the IIR 529 */ 530 if (pipe_stats[pipe] & 0x8000ffff) { 531 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 532 DRM_DEBUG_DRIVER("pipe %c underrun\n", 533 pipe_name(pipe)); 534 I915_WRITE(reg, pipe_stats[pipe]); 535 } 536 } 537 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 538 539 for_each_pipe(pipe) { 540 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 541 drm_handle_vblank(dev, pipe); 542 543 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { 544 intel_prepare_page_flip(dev, pipe); 545 intel_finish_page_flip(dev, pipe); 546 } 547 } 548 549 /* Consume port. Then clear IIR or we'll miss events */ 550 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 551 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 552 553 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 554 hotplug_status); 555 if (hotplug_status & dev_priv->hotplug_supported_mask) 556 queue_work(dev_priv->wq, 557 &dev_priv->hotplug_work); 558 559 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 560 I915_READ(PORT_HOTPLUG_STAT); 561 } 562 563 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 564 blc_event = true; 565 566 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) 567 gen6_queue_rps_work(dev_priv, pm_iir); 568 569 I915_WRITE(GTIIR, gt_iir); 570 I915_WRITE(GEN6_PMIIR, pm_iir); 571 I915_WRITE(VLV_IIR, iir); 572 } 573 574 out: 575 return; 576 } 577 578 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 579 { 580 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 581 int pipe; 582 583 if (pch_iir & SDE_HOTPLUG_MASK) 584 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 585 586 if (pch_iir & SDE_AUDIO_POWER_MASK) 587 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 588 (pch_iir & SDE_AUDIO_POWER_MASK) >> 589 SDE_AUDIO_POWER_SHIFT); 590 591 if (pch_iir & SDE_GMBUS) 592 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 593 594 if (pch_iir & SDE_AUDIO_HDCP_MASK) 595 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 596 597 if (pch_iir & SDE_AUDIO_TRANS_MASK) 598 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 599 600 if (pch_iir & SDE_POISON) 601 DRM_ERROR("PCH poison interrupt\n"); 602 603 if (pch_iir & SDE_FDI_MASK) 604 for_each_pipe(pipe) 605 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 606 pipe_name(pipe), 607 I915_READ(FDI_RX_IIR(pipe))); 608 609 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 610 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 611 612 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 613 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 614 615 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 616 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); 617 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 618 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 619 } 620 621 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 622 { 623 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 624 int pipe; 625 626 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 627 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 628 629 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) 630 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 631 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 632 SDE_AUDIO_POWER_SHIFT_CPT); 633 634 if (pch_iir & SDE_AUX_MASK_CPT) 635 DRM_DEBUG_DRIVER("AUX channel interrupt\n"); 636 637 if (pch_iir & SDE_GMBUS_CPT) 638 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 639 640 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 641 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 642 643 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 644 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 645 646 if (pch_iir & SDE_FDI_MASK_CPT) 647 for_each_pipe(pipe) 648 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 649 pipe_name(pipe), 650 I915_READ(FDI_RX_IIR(pipe))); 651 } 652 653 static irqreturn_t ivybridge_irq_handler(void *arg) 654 { 655 struct drm_device *dev = (struct drm_device *) arg; 656 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 657 u32 de_iir, gt_iir, de_ier, pm_iir; 658 int i; 659 660 atomic_inc(&dev_priv->irq_received); 661 662 /* disable master interrupt before clearing iir */ 663 de_ier = I915_READ(DEIER); 664 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 665 666 gt_iir = I915_READ(GTIIR); 667 if (gt_iir) { 668 snb_gt_irq_handler(dev, dev_priv, gt_iir); 669 I915_WRITE(GTIIR, gt_iir); 670 } 671 672 de_iir = I915_READ(DEIIR); 673 if (de_iir) { 674 if (de_iir & DE_GSE_IVB) 675 intel_opregion_gse_intr(dev); 676 677 for (i = 0; i < 3; i++) { 678 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) 679 drm_handle_vblank(dev, i); 680 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { 681 intel_prepare_page_flip(dev, i); 682 intel_finish_page_flip_plane(dev, i); 683 } 684 } 685 686 /* check event from PCH */ 687 if (de_iir & DE_PCH_EVENT_IVB) { 688 u32 pch_iir = I915_READ(SDEIIR); 689 690 cpt_irq_handler(dev, pch_iir); 691 692 /* clear PCH hotplug event before clear CPU irq */ 693 I915_WRITE(SDEIIR, pch_iir); 694 } 695 696 I915_WRITE(DEIIR, de_iir); 697 } 698 699 pm_iir = I915_READ(GEN6_PMIIR); 700 if (pm_iir) { 701 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) 702 gen6_queue_rps_work(dev_priv, pm_iir); 703 I915_WRITE(GEN6_PMIIR, pm_iir); 704 } 705 706 I915_WRITE(DEIER, de_ier); 707 POSTING_READ(DEIER); 708 } 709 710 static void ilk_gt_irq_handler(struct drm_device *dev, 711 struct drm_i915_private *dev_priv, 712 u32 gt_iir) 713 { 714 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 715 notify_ring(dev, &dev_priv->ring[RCS]); 716 if (gt_iir & GT_BSD_USER_INTERRUPT) 717 notify_ring(dev, &dev_priv->ring[VCS]); 718 } 719 720 static irqreturn_t ironlake_irq_handler(void *arg) 721 { 722 struct drm_device *dev = (struct drm_device *) arg; 723 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 724 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 725 726 atomic_inc(&dev_priv->irq_received); 727 728 /* disable master interrupt before clearing iir */ 729 de_ier = I915_READ(DEIER); 730 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 731 POSTING_READ(DEIER); 732 733 de_iir = I915_READ(DEIIR); 734 gt_iir = I915_READ(GTIIR); 735 pch_iir = I915_READ(SDEIIR); 736 pm_iir = I915_READ(GEN6_PMIIR); 737 738 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && 739 (!IS_GEN6(dev) || pm_iir == 0)) 740 goto done; 741 742 if (IS_GEN5(dev)) 743 ilk_gt_irq_handler(dev, dev_priv, gt_iir); 744 else 745 snb_gt_irq_handler(dev, dev_priv, gt_iir); 746 747 if (de_iir & DE_GSE) 748 intel_opregion_gse_intr(dev); 749 750 if (de_iir & DE_PIPEA_VBLANK) 751 drm_handle_vblank(dev, 0); 752 753 if (de_iir & DE_PIPEB_VBLANK) 754 drm_handle_vblank(dev, 1); 755 756 if (de_iir & DE_PLANEA_FLIP_DONE) { 757 intel_prepare_page_flip(dev, 0); 758 intel_finish_page_flip_plane(dev, 0); 759 } 760 761 if (de_iir & DE_PLANEB_FLIP_DONE) { 762 intel_prepare_page_flip(dev, 1); 763 intel_finish_page_flip_plane(dev, 1); 764 } 765 766 /* check event from PCH */ 767 if (de_iir & DE_PCH_EVENT) { 768 if (HAS_PCH_CPT(dev)) 769 cpt_irq_handler(dev, pch_iir); 770 else 771 ibx_irq_handler(dev, pch_iir); 772 } 773 774 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 775 ironlake_handle_rps_change(dev); 776 777 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) 778 gen6_queue_rps_work(dev_priv, pm_iir); 779 780 /* should clear PCH hotplug event before clear CPU irq */ 781 I915_WRITE(SDEIIR, pch_iir); 782 I915_WRITE(GTIIR, gt_iir); 783 I915_WRITE(DEIIR, de_iir); 784 I915_WRITE(GEN6_PMIIR, pm_iir); 785 786 done: 787 I915_WRITE(DEIER, de_ier); 788 POSTING_READ(DEIER); 789 } 790 791 /** 792 * i915_error_work_func - do process context error handling work 793 * @work: work struct 794 * 795 * Fire an error uevent so userspace can see that a hang or error 796 * was detected. 797 */ 798 static void i915_error_work_func(struct work_struct *work) 799 { 800 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 801 error_work); 802 struct drm_device *dev = dev_priv->dev; 803 804 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */ 805 806 if (atomic_read(&dev_priv->mm.wedged)) { 807 DRM_DEBUG_DRIVER("resetting chip\n"); 808 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */ 809 if (!i915_reset(dev)) { 810 atomic_set(&dev_priv->mm.wedged, 0); 811 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); */ 812 } 813 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE); 814 dev_priv->error_completion++; 815 wakeup(&dev_priv->error_completion); 816 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE); 817 } 818 } 819 820 /* NB: please notice the memset */ 821 static void i915_get_extra_instdone(struct drm_device *dev, 822 uint32_t *instdone) 823 { 824 struct drm_i915_private *dev_priv = dev->dev_private; 825 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 826 827 switch(INTEL_INFO(dev)->gen) { 828 case 2: 829 case 3: 830 instdone[0] = I915_READ(INSTDONE); 831 break; 832 case 4: 833 case 5: 834 case 6: 835 instdone[0] = I915_READ(INSTDONE_I965); 836 instdone[1] = I915_READ(INSTDONE1); 837 break; 838 default: 839 #if 0 840 WARN_ONCE(1, "Unsupported platform\n"); 841 #endif 842 case 7: 843 instdone[0] = I915_READ(GEN7_INSTDONE_1); 844 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 845 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 846 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 847 break; 848 } 849 } 850 851 #if 0 /* CONFIG_DEBUG_FS */ 852 static struct drm_i915_error_object * 853 i915_error_object_create(struct drm_i915_private *dev_priv, 854 struct drm_i915_gem_object *src) 855 { 856 struct drm_i915_error_object *dst; 857 int i, count; 858 u32 reloc_offset; 859 860 if (src == NULL || src->pages == NULL) 861 return NULL; 862 863 count = src->base.size / PAGE_SIZE; 864 865 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC); 866 if (dst == NULL) 867 return NULL; 868 869 reloc_offset = src->gtt_offset; 870 for (i = 0; i < count; i++) { 871 unsigned long flags; 872 void *d; 873 874 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 875 if (d == NULL) 876 goto unwind; 877 878 local_irq_save(flags); 879 if (reloc_offset < dev_priv->mm.gtt_mappable_end && 880 src->has_global_gtt_mapping) { 881 void __iomem *s; 882 883 /* Simply ignore tiling or any overlapping fence. 884 * It's part of the error state, and this hopefully 885 * captures what the GPU read. 886 */ 887 888 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 889 reloc_offset); 890 memcpy_fromio(d, s, PAGE_SIZE); 891 io_mapping_unmap_atomic(s); 892 } else { 893 struct page *page; 894 void *s; 895 896 page = i915_gem_object_get_page(src, i); 897 898 drm_clflush_pages(&page, 1); 899 900 s = kmap_atomic(page); 901 memcpy(d, s, PAGE_SIZE); 902 kunmap_atomic(s); 903 904 drm_clflush_pages(&page, 1); 905 } 906 local_irq_restore(flags); 907 908 dst->pages[i] = d; 909 910 reloc_offset += PAGE_SIZE; 911 } 912 dst->page_count = count; 913 dst->gtt_offset = src->gtt_offset; 914 915 return dst; 916 917 unwind: 918 while (i--) 919 kfree(dst->pages[i]); 920 kfree(dst); 921 return NULL; 922 } 923 924 static void 925 i915_error_object_free(struct drm_i915_error_object *obj) 926 { 927 int page; 928 929 if (obj == NULL) 930 return; 931 932 for (page = 0; page < obj->page_count; page++) 933 kfree(obj->pages[page]); 934 935 kfree(obj); 936 } 937 938 void 939 i915_error_state_free(struct drm_device *dev, 940 struct drm_i915_error_state *error) 941 { 942 struct drm_i915_error_state *error = container_of(error_ref, 943 typeof(*error), ref); 944 int i; 945 946 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 947 i915_error_object_free(error->ring[i].batchbuffer); 948 i915_error_object_free(error->ring[i].ringbuffer); 949 kfree(error->ring[i].requests); 950 } 951 952 kfree(error->active_bo); 953 kfree(error->overlay); 954 kfree(error); 955 } 956 static void capture_bo(struct drm_i915_error_buffer *err, 957 struct drm_i915_gem_object *obj) 958 { 959 err->size = obj->base.size; 960 err->name = obj->base.name; 961 err->rseqno = obj->last_read_seqno; 962 err->wseqno = obj->last_write_seqno; 963 err->gtt_offset = obj->gtt_offset; 964 err->read_domains = obj->base.read_domains; 965 err->write_domain = obj->base.write_domain; 966 err->fence_reg = obj->fence_reg; 967 err->pinned = 0; 968 if (obj->pin_count > 0) 969 err->pinned = 1; 970 if (obj->user_pin_count > 0) 971 err->pinned = -1; 972 err->tiling = obj->tiling_mode; 973 err->dirty = obj->dirty; 974 err->purgeable = obj->madv != I915_MADV_WILLNEED; 975 err->ring = obj->ring ? obj->ring->id : -1; 976 err->cache_level = obj->cache_level; 977 } 978 979 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 980 int count, struct list_head *head) 981 { 982 struct drm_i915_gem_object *obj; 983 int i = 0; 984 985 list_for_each_entry(obj, head, mm_list) { 986 capture_bo(err++, obj); 987 if (++i == count) 988 break; 989 } 990 991 return i; 992 } 993 994 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 995 int count, struct list_head *head) 996 { 997 struct drm_i915_gem_object *obj; 998 int i = 0; 999 1000 list_for_each_entry(obj, head, gtt_list) { 1001 if (obj->pin_count == 0) 1002 continue; 1003 1004 capture_bo(err++, obj); 1005 if (++i == count) 1006 break; 1007 } 1008 1009 return i; 1010 } 1011 1012 static void i915_gem_record_fences(struct drm_device *dev, 1013 struct drm_i915_error_state *error) 1014 { 1015 struct drm_i915_private *dev_priv = dev->dev_private; 1016 int i; 1017 1018 /* Fences */ 1019 switch (INTEL_INFO(dev)->gen) { 1020 case 7: 1021 case 6: 1022 for (i = 0; i < 16; i++) 1023 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 1024 break; 1025 case 5: 1026 case 4: 1027 for (i = 0; i < 16; i++) 1028 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 1029 break; 1030 case 3: 1031 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 1032 for (i = 0; i < 8; i++) 1033 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 1034 case 2: 1035 for (i = 0; i < 8; i++) 1036 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 1037 break; 1038 1039 } 1040 } 1041 1042 static struct drm_i915_error_object * 1043 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 1044 struct intel_ring_buffer *ring) 1045 { 1046 struct drm_i915_gem_object *obj; 1047 u32 seqno; 1048 1049 if (!ring->get_seqno) 1050 return NULL; 1051 1052 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { 1053 u32 acthd = I915_READ(ACTHD); 1054 1055 if (WARN_ON(ring->id != RCS)) 1056 return NULL; 1057 1058 obj = ring->private; 1059 if (acthd >= obj->gtt_offset && 1060 acthd < obj->gtt_offset + obj->base.size) 1061 return i915_error_object_create(dev_priv, obj); 1062 } 1063 1064 seqno = ring->get_seqno(ring, false); 1065 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 1066 if (obj->ring != ring) 1067 continue; 1068 1069 if (i915_seqno_passed(seqno, obj->last_read_seqno)) 1070 continue; 1071 1072 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 1073 continue; 1074 1075 /* We need to copy these to an anonymous buffer as the simplest 1076 * method to avoid being overwritten by userspace. 1077 */ 1078 return i915_error_object_create(dev_priv, obj); 1079 } 1080 1081 return NULL; 1082 } 1083 1084 static void i915_record_ring_state(struct drm_device *dev, 1085 struct drm_i915_error_state *error, 1086 struct intel_ring_buffer *ring) 1087 { 1088 struct drm_i915_private *dev_priv = dev->dev_private; 1089 1090 if (INTEL_INFO(dev)->gen >= 6) { 1091 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); 1092 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); 1093 error->semaphore_mboxes[ring->id][0] 1094 = I915_READ(RING_SYNC_0(ring->mmio_base)); 1095 error->semaphore_mboxes[ring->id][1] 1096 = I915_READ(RING_SYNC_1(ring->mmio_base)); 1097 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0]; 1098 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1]; 1099 } 1100 1101 if (INTEL_INFO(dev)->gen >= 4) { 1102 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 1103 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 1104 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 1105 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 1106 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 1107 if (ring->id == RCS) 1108 error->bbaddr = I915_READ64(BB_ADDR); 1109 } else { 1110 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); 1111 error->ipeir[ring->id] = I915_READ(IPEIR); 1112 error->ipehr[ring->id] = I915_READ(IPEHR); 1113 error->instdone[ring->id] = I915_READ(INSTDONE); 1114 } 1115 1116 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); 1117 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); 1118 error->seqno[ring->id] = ring->get_seqno(ring, false); 1119 error->acthd[ring->id] = intel_ring_get_active_head(ring); 1120 error->head[ring->id] = I915_READ_HEAD(ring); 1121 error->tail[ring->id] = I915_READ_TAIL(ring); 1122 error->ctl[ring->id] = I915_READ_CTL(ring); 1123 1124 error->cpu_ring_head[ring->id] = ring->head; 1125 error->cpu_ring_tail[ring->id] = ring->tail; 1126 } 1127 1128 static void i915_gem_record_rings(struct drm_device *dev, 1129 struct drm_i915_error_state *error) 1130 { 1131 struct drm_i915_private *dev_priv = dev->dev_private; 1132 struct intel_ring_buffer *ring; 1133 struct drm_i915_gem_request *request; 1134 int i, count; 1135 1136 for_each_ring(ring, dev_priv, i) { 1137 i915_record_ring_state(dev, error, ring); 1138 1139 error->ring[i].batchbuffer = 1140 i915_error_first_batchbuffer(dev_priv, ring); 1141 1142 error->ring[i].ringbuffer = 1143 i915_error_object_create(dev_priv, ring->obj); 1144 1145 count = 0; 1146 list_for_each_entry(request, &ring->request_list, list) 1147 count++; 1148 1149 error->ring[i].num_requests = count; 1150 error->ring[i].requests = 1151 kmalloc(count*sizeof(struct drm_i915_error_request), 1152 GFP_ATOMIC); 1153 if (error->ring[i].requests == NULL) { 1154 error->ring[i].num_requests = 0; 1155 continue; 1156 } 1157 1158 count = 0; 1159 list_for_each_entry(request, &ring->request_list, list) { 1160 struct drm_i915_error_request *erq; 1161 1162 erq = &error->ring[i].requests[count++]; 1163 erq->seqno = request->seqno; 1164 erq->jiffies = request->emitted_jiffies; 1165 erq->tail = request->tail; 1166 } 1167 } 1168 } 1169 1170 /** 1171 * i915_capture_error_state - capture an error record for later analysis 1172 * @dev: drm device 1173 * 1174 * Should be called when an error is detected (either a hang or an error 1175 * interrupt) to capture error state from the time of the error. Fills 1176 * out a structure which becomes available in debugfs for user level tools 1177 * to pick up. 1178 */ 1179 static void i915_capture_error_state(struct drm_device *dev) 1180 { 1181 struct drm_i915_private *dev_priv = dev->dev_private; 1182 struct drm_i915_gem_object *obj; 1183 struct drm_i915_error_state *error; 1184 unsigned long flags; 1185 int i, pipe; 1186 1187 spin_lock_irqsave(&dev_priv->error_lock, flags); 1188 error = dev_priv->first_error; 1189 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1190 if (error) 1191 return; 1192 1193 /* Account for pipe specific data like PIPE*STAT */ 1194 error = kmalloc(sizeof(*error), DRM_I915_GEM, M_NOWAIT | M_ZERO); 1195 if (!error) { 1196 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1197 return; 1198 } 1199 1200 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", 1201 dev->primary->index); 1202 1203 kref_init(&error->ref); 1204 error->eir = I915_READ(EIR); 1205 error->pgtbl_er = I915_READ(PGTBL_ER); 1206 error->ccid = I915_READ(CCID); 1207 1208 if (HAS_PCH_SPLIT(dev)) 1209 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 1210 else if (IS_VALLEYVIEW(dev)) 1211 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 1212 else if (IS_GEN2(dev)) 1213 error->ier = I915_READ16(IER); 1214 else 1215 error->ier = I915_READ(IER); 1216 1217 if (INTEL_INFO(dev)->gen >= 6) 1218 error->derrmr = I915_READ(DERRMR); 1219 1220 if (IS_VALLEYVIEW(dev)) 1221 error->forcewake = I915_READ(FORCEWAKE_VLV); 1222 else if (INTEL_INFO(dev)->gen >= 7) 1223 error->forcewake = I915_READ(FORCEWAKE_MT); 1224 else if (INTEL_INFO(dev)->gen == 6) 1225 error->forcewake = I915_READ(FORCEWAKE); 1226 1227 for_each_pipe(pipe) 1228 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 1229 1230 if (INTEL_INFO(dev)->gen >= 6) { 1231 error->error = I915_READ(ERROR_GEN6); 1232 error->done_reg = I915_READ(DONE_REG); 1233 } 1234 1235 if (INTEL_INFO(dev)->gen == 7) 1236 error->err_int = I915_READ(GEN7_ERR_INT); 1237 1238 i915_get_extra_instdone(dev, error->extra_instdone); 1239 1240 i915_gem_record_fences(dev, error); 1241 i915_gem_record_rings(dev, error); 1242 1243 /* Record buffers on the active and pinned lists. */ 1244 error->active_bo = NULL; 1245 error->pinned_bo = NULL; 1246 1247 i = 0; 1248 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 1249 i++; 1250 error->active_bo_count = i; 1251 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) 1252 if (obj->pin_count) 1253 i++; 1254 error->pinned_bo_count = i - error->active_bo_count; 1255 1256 error->active_bo = NULL; 1257 error->pinned_bo = NULL; 1258 if (i) { 1259 error->active_bo = kmalloc(sizeof(*error->active_bo)*i, 1260 GFP_ATOMIC); 1261 if (error->active_bo) 1262 error->pinned_bo = 1263 error->active_bo + error->active_bo_count; 1264 } 1265 1266 if (error->active_bo) 1267 error->active_bo_count = 1268 capture_active_bo(error->active_bo, 1269 error->active_bo_count, 1270 &dev_priv->mm.active_list); 1271 1272 if (error->pinned_bo) 1273 error->pinned_bo_count = 1274 capture_pinned_bo(error->pinned_bo, 1275 error->pinned_bo_count, 1276 &dev_priv->mm.bound_list); 1277 1278 do_gettimeofday(&error->time); 1279 1280 error->overlay = intel_overlay_capture_error_state(dev); 1281 error->display = intel_display_capture_error_state(dev); 1282 1283 spin_lock_irqsave(&dev_priv->error_lock, flags); 1284 if (dev_priv->first_error == NULL) { 1285 dev_priv->first_error = error; 1286 error = NULL; 1287 } 1288 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1289 1290 if (error) 1291 i915_error_state_free(&error->ref); 1292 } 1293 1294 void i915_destroy_error_state(struct drm_device *dev) 1295 { 1296 struct drm_i915_private *dev_priv = dev->dev_private; 1297 struct drm_i915_error_state *error; 1298 1299 lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE); 1300 error = dev_priv->first_error; 1301 dev_priv->first_error = NULL; 1302 lockmgr(&dev_priv->error_lock, LK_RELEASE); 1303 1304 if (error) 1305 i915_error_state_free(dev, error); 1306 } 1307 #else 1308 #define i915_capture_error_state(x) 1309 #endif 1310 1311 static void i915_report_and_clear_eir(struct drm_device *dev) 1312 { 1313 struct drm_i915_private *dev_priv = dev->dev_private; 1314 uint32_t instdone[I915_NUM_INSTDONE_REG]; 1315 u32 eir = I915_READ(EIR); 1316 int pipe, i; 1317 1318 if (!eir) 1319 return; 1320 1321 pr_err("render error detected, EIR: 0x%08x\n", eir); 1322 1323 i915_get_extra_instdone(dev, instdone); 1324 1325 if (IS_G4X(dev)) { 1326 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 1327 u32 ipeir = I915_READ(IPEIR_I965); 1328 1329 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 1330 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 1331 for (i = 0; i < ARRAY_SIZE(instdone); i++) 1332 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 1333 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 1334 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 1335 I915_WRITE(IPEIR_I965, ipeir); 1336 POSTING_READ(IPEIR_I965); 1337 } 1338 if (eir & GM45_ERROR_PAGE_TABLE) { 1339 u32 pgtbl_err = I915_READ(PGTBL_ER); 1340 pr_err("page table error\n"); 1341 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 1342 I915_WRITE(PGTBL_ER, pgtbl_err); 1343 POSTING_READ(PGTBL_ER); 1344 } 1345 } 1346 1347 if (!IS_GEN2(dev)) { 1348 if (eir & I915_ERROR_PAGE_TABLE) { 1349 u32 pgtbl_err = I915_READ(PGTBL_ER); 1350 pr_err("page table error\n"); 1351 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 1352 I915_WRITE(PGTBL_ER, pgtbl_err); 1353 POSTING_READ(PGTBL_ER); 1354 } 1355 } 1356 1357 if (eir & I915_ERROR_MEMORY_REFRESH) { 1358 pr_err("memory refresh error:\n"); 1359 for_each_pipe(pipe) 1360 pr_err("pipe %c stat: 0x%08x\n", 1361 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 1362 /* pipestat has already been acked */ 1363 } 1364 if (eir & I915_ERROR_INSTRUCTION) { 1365 pr_err("instruction error\n"); 1366 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); 1367 for (i = 0; i < ARRAY_SIZE(instdone); i++) 1368 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 1369 if (INTEL_INFO(dev)->gen < 4) { 1370 u32 ipeir = I915_READ(IPEIR); 1371 1372 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); 1373 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); 1374 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); 1375 I915_WRITE(IPEIR, ipeir); 1376 POSTING_READ(IPEIR); 1377 } else { 1378 u32 ipeir = I915_READ(IPEIR_I965); 1379 1380 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 1381 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 1382 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 1383 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 1384 I915_WRITE(IPEIR_I965, ipeir); 1385 POSTING_READ(IPEIR_I965); 1386 } 1387 } 1388 1389 I915_WRITE(EIR, eir); 1390 POSTING_READ(EIR); 1391 eir = I915_READ(EIR); 1392 if (eir) { 1393 /* 1394 * some errors might have become stuck, 1395 * mask them. 1396 */ 1397 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 1398 I915_WRITE(EMR, I915_READ(EMR) | eir); 1399 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 1400 } 1401 } 1402 1403 /** 1404 * i915_handle_error - handle an error interrupt 1405 * @dev: drm device 1406 * 1407 * Do some basic checking of regsiter state at error interrupt time and 1408 * dump it to the syslog. Also call i915_capture_error_state() to make 1409 * sure we get a record and make it available in debugfs. Fire a uevent 1410 * so userspace knows something bad happened (should trigger collection 1411 * of a ring dump etc.). 1412 */ 1413 void i915_handle_error(struct drm_device *dev, bool wedged) 1414 { 1415 struct drm_i915_private *dev_priv = dev->dev_private; 1416 struct intel_ring_buffer *ring; 1417 int i; 1418 1419 i915_capture_error_state(dev); 1420 i915_report_and_clear_eir(dev); 1421 1422 if (wedged) { 1423 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE); 1424 dev_priv->error_completion = 0; 1425 atomic_set(&dev_priv->mm.wedged, 1); 1426 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE); 1427 1428 /* 1429 * Wakeup waiting processes so they don't hang 1430 */ 1431 for_each_ring(ring, dev_priv, i) 1432 wake_up_all(&ring->irq_queue); 1433 } 1434 1435 queue_work(dev_priv->wq, &dev_priv->error_work); 1436 } 1437 1438 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 1439 { 1440 drm_i915_private_t *dev_priv = dev->dev_private; 1441 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1443 struct drm_i915_gem_object *obj; 1444 struct intel_unpin_work *work; 1445 bool stall_detected; 1446 1447 /* Ignore early vblank irqs */ 1448 if (intel_crtc == NULL) 1449 return; 1450 1451 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 1452 work = intel_crtc->unpin_work; 1453 1454 if (work == NULL || 1455 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || 1456 !work->enable_stall_check) { 1457 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 1458 lockmgr(&dev->event_lock, LK_RELEASE); 1459 return; 1460 } 1461 1462 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1463 obj = work->pending_flip_obj; 1464 if (INTEL_INFO(dev)->gen >= 4) { 1465 int dspsurf = DSPSURF(intel_crtc->plane); 1466 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == 1467 obj->gtt_offset; 1468 } else { 1469 int dspaddr = DSPADDR(intel_crtc->plane); 1470 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1471 crtc->y * crtc->fb->pitches[0] + 1472 crtc->x * crtc->fb->bits_per_pixel/8); 1473 } 1474 1475 lockmgr(&dev->event_lock, LK_RELEASE); 1476 1477 if (stall_detected) { 1478 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 1479 intel_prepare_page_flip(dev, intel_crtc->plane); 1480 } 1481 } 1482 1483 /* Called from drm generic code, passed 'crtc' which 1484 * we use as a pipe index 1485 */ 1486 static int i915_enable_vblank(struct drm_device *dev, int pipe) 1487 { 1488 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1489 1490 if (!i915_pipe_enabled(dev, pipe)) 1491 return -EINVAL; 1492 1493 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1494 if (INTEL_INFO(dev)->gen >= 4) 1495 i915_enable_pipestat(dev_priv, pipe, 1496 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1497 else 1498 i915_enable_pipestat(dev_priv, pipe, 1499 PIPE_VBLANK_INTERRUPT_ENABLE); 1500 1501 /* maintain vblank delivery even in deep C-states */ 1502 if (dev_priv->info->gen == 3) 1503 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); 1504 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1505 1506 return 0; 1507 } 1508 1509 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1510 { 1511 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1512 1513 if (!i915_pipe_enabled(dev, pipe)) 1514 return -EINVAL; 1515 1516 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1517 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1518 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1519 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1520 1521 return 0; 1522 } 1523 1524 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1525 { 1526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1527 1528 if (!i915_pipe_enabled(dev, pipe)) 1529 return -EINVAL; 1530 1531 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1532 ironlake_enable_display_irq(dev_priv, 1533 DE_PIPEA_VBLANK_IVB << (5 * pipe)); 1534 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1535 1536 return 0; 1537 } 1538 1539 static int valleyview_enable_vblank(struct drm_device *dev, int pipe) 1540 { 1541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1542 u32 imr; 1543 1544 if (!i915_pipe_enabled(dev, pipe)) 1545 return -EINVAL; 1546 1547 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1548 imr = I915_READ(VLV_IMR); 1549 if (pipe == 0) 1550 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 1551 else 1552 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1553 I915_WRITE(VLV_IMR, imr); 1554 i915_enable_pipestat(dev_priv, pipe, 1555 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1556 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1557 1558 return 0; 1559 } 1560 1561 /* Called from drm generic code, passed 'crtc' which 1562 * we use as a pipe index 1563 */ 1564 static void i915_disable_vblank(struct drm_device *dev, int pipe) 1565 { 1566 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1567 1568 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1569 if (dev_priv->info->gen == 3) 1570 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); 1571 1572 i915_disable_pipestat(dev_priv, pipe, 1573 PIPE_VBLANK_INTERRUPT_ENABLE | 1574 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1575 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1576 } 1577 1578 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1579 { 1580 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1581 1582 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1583 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1584 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1585 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1586 } 1587 1588 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1589 { 1590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1591 1592 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1593 ironlake_disable_display_irq(dev_priv, 1594 DE_PIPEA_VBLANK_IVB << (pipe * 5)); 1595 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1596 } 1597 1598 static void valleyview_disable_vblank(struct drm_device *dev, int pipe) 1599 { 1600 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1601 u32 imr; 1602 1603 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1604 i915_disable_pipestat(dev_priv, pipe, 1605 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1606 imr = I915_READ(VLV_IMR); 1607 if (pipe == 0) 1608 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 1609 else 1610 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1611 I915_WRITE(VLV_IMR, imr); 1612 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1613 } 1614 1615 static u32 1616 ring_last_seqno(struct intel_ring_buffer *ring) 1617 { 1618 return list_entry(ring->request_list.prev, 1619 struct drm_i915_gem_request, list)->seqno; 1620 } 1621 1622 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) 1623 { 1624 if (list_empty(&ring->request_list) || 1625 i915_seqno_passed(ring->get_seqno(ring, false), 1626 ring_last_seqno(ring))) { 1627 /* Issue a wake-up to catch stuck h/w. */ 1628 #if 0 /* XXX From OpenBSD */ 1629 if (waitqueue_active(&ring->irq_queue)) { 1630 DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 1631 ring->name); 1632 wake_up_all(&ring->irq_queue); 1633 *err = true; 1634 } 1635 #else 1636 wake_up_all(&ring->irq_queue); 1637 #endif 1638 return true; 1639 } 1640 return false; 1641 } 1642 1643 static bool kick_ring(struct intel_ring_buffer *ring) 1644 { 1645 struct drm_device *dev = ring->dev; 1646 struct drm_i915_private *dev_priv = dev->dev_private; 1647 u32 tmp = I915_READ_CTL(ring); 1648 if (tmp & RING_WAIT) { 1649 DRM_ERROR("Kicking stuck wait on %s\n", 1650 ring->name); 1651 I915_WRITE_CTL(ring, tmp); 1652 return true; 1653 } 1654 return false; 1655 } 1656 1657 static bool i915_hangcheck_hung(struct drm_device *dev) 1658 { 1659 drm_i915_private_t *dev_priv = dev->dev_private; 1660 1661 if (dev_priv->hangcheck_count++ > 1) { 1662 bool hung = true; 1663 1664 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 1665 i915_handle_error(dev, true); 1666 1667 if (!IS_GEN2(dev)) { 1668 struct intel_ring_buffer *ring; 1669 int i; 1670 1671 /* Is the chip hanging on a WAIT_FOR_EVENT? 1672 * If so we can simply poke the RB_WAIT bit 1673 * and break the hang. This should work on 1674 * all but the second generation chipsets. 1675 */ 1676 for_each_ring(ring, dev_priv, i) 1677 hung &= !kick_ring(ring); 1678 } 1679 1680 return hung; 1681 } 1682 1683 return false; 1684 } 1685 1686 /** 1687 * This is called when the chip hasn't reported back with completed 1688 * batchbuffers in a long time. The first time this is called we simply record 1689 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1690 * again, we assume the chip is wedged and try to fix it. 1691 */ 1692 void i915_hangcheck_elapsed(unsigned long data) 1693 { 1694 struct drm_device *dev = (struct drm_device *)data; 1695 drm_i915_private_t *dev_priv = dev->dev_private; 1696 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG]; 1697 struct intel_ring_buffer *ring; 1698 bool err = false, idle; 1699 int i; 1700 1701 if (!i915_enable_hangcheck) 1702 return; 1703 1704 memset(acthd, 0, sizeof(acthd)); 1705 idle = true; 1706 for_each_ring(ring, dev_priv, i) { 1707 idle &= i915_hangcheck_ring_idle(ring, &err); 1708 acthd[i] = intel_ring_get_active_head(ring); 1709 } 1710 1711 /* If all work is done then ACTHD clearly hasn't advanced. */ 1712 if (idle) { 1713 if (err) { 1714 if (i915_hangcheck_hung(dev)) 1715 return; 1716 1717 goto repeat; 1718 } 1719 1720 dev_priv->hangcheck_count = 0; 1721 return; 1722 } 1723 1724 i915_get_extra_instdone(dev, instdone); 1725 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 && 1726 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) { 1727 if (i915_hangcheck_hung(dev)) 1728 return; 1729 } else { 1730 dev_priv->hangcheck_count = 0; 1731 1732 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd)); 1733 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone)); 1734 } 1735 1736 repeat: 1737 /* Reset timer case chip hangs without another request being added */ 1738 mod_timer(&dev_priv->hangcheck_timer, 1739 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 1740 } 1741 1742 /* drm_dma.h hooks 1743 */ 1744 static void ironlake_irq_preinstall(struct drm_device *dev) 1745 { 1746 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1747 1748 atomic_set(&dev_priv->irq_received, 0); 1749 1750 I915_WRITE(HWSTAM, 0xeffe); 1751 1752 /* XXX hotplug from PCH */ 1753 1754 I915_WRITE(DEIMR, 0xffffffff); 1755 I915_WRITE(DEIER, 0x0); 1756 POSTING_READ(DEIER); 1757 1758 /* and GT */ 1759 I915_WRITE(GTIMR, 0xffffffff); 1760 I915_WRITE(GTIER, 0x0); 1761 POSTING_READ(GTIER); 1762 1763 /* south display irq */ 1764 I915_WRITE(SDEIMR, 0xffffffff); 1765 I915_WRITE(SDEIER, 0x0); 1766 POSTING_READ(SDEIER); 1767 } 1768 1769 static void valleyview_irq_preinstall(struct drm_device *dev) 1770 { 1771 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1772 int pipe; 1773 1774 atomic_set(&dev_priv->irq_received, 0); 1775 1776 /* VLV magic */ 1777 I915_WRITE(VLV_IMR, 0); 1778 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); 1779 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); 1780 I915_WRITE(RING_IMR(BLT_RING_BASE), 0); 1781 1782 /* and GT */ 1783 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1784 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1785 I915_WRITE(GTIMR, 0xffffffff); 1786 I915_WRITE(GTIER, 0x0); 1787 POSTING_READ(GTIER); 1788 1789 I915_WRITE(DPINVGTT, 0xff); 1790 1791 I915_WRITE(PORT_HOTPLUG_EN, 0); 1792 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1793 for_each_pipe(pipe) 1794 I915_WRITE(PIPESTAT(pipe), 0xffff); 1795 I915_WRITE(VLV_IIR, 0xffffffff); 1796 I915_WRITE(VLV_IMR, 0xffffffff); 1797 I915_WRITE(VLV_IER, 0x0); 1798 POSTING_READ(VLV_IER); 1799 } 1800 1801 /* 1802 * Enable digital hotplug on the PCH, and configure the DP short pulse 1803 * duration to 2ms (which is the minimum in the Display Port spec) 1804 * 1805 * This register is the same on all known PCH chips. 1806 */ 1807 1808 static void ironlake_enable_pch_hotplug(struct drm_device *dev) 1809 { 1810 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1811 u32 hotplug; 1812 1813 hotplug = I915_READ(PCH_PORT_HOTPLUG); 1814 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 1815 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 1816 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 1817 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 1818 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 1819 } 1820 1821 static int ironlake_irq_postinstall(struct drm_device *dev) 1822 { 1823 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1824 /* enable kind of interrupts always enabled */ 1825 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1826 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1827 u32 render_irqs; 1828 u32 hotplug_mask; 1829 1830 dev_priv->irq_mask = ~display_mask; 1831 1832 /* should always can generate irq */ 1833 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1834 I915_WRITE(DEIMR, dev_priv->irq_mask); 1835 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); 1836 POSTING_READ(DEIER); 1837 1838 dev_priv->gt_irq_mask = ~0; 1839 1840 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1841 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1842 1843 if (IS_GEN6(dev)) 1844 render_irqs = 1845 GT_USER_INTERRUPT | 1846 GEN6_BSD_USER_INTERRUPT | 1847 GEN6_BLITTER_USER_INTERRUPT; 1848 else 1849 render_irqs = 1850 GT_USER_INTERRUPT | 1851 GT_PIPE_NOTIFY | 1852 GT_BSD_USER_INTERRUPT; 1853 I915_WRITE(GTIER, render_irqs); 1854 POSTING_READ(GTIER); 1855 1856 if (HAS_PCH_CPT(dev)) { 1857 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1858 SDE_PORTB_HOTPLUG_CPT | 1859 SDE_PORTC_HOTPLUG_CPT | 1860 SDE_PORTD_HOTPLUG_CPT); 1861 } else { 1862 hotplug_mask = (SDE_CRT_HOTPLUG | 1863 SDE_PORTB_HOTPLUG | 1864 SDE_PORTC_HOTPLUG | 1865 SDE_PORTD_HOTPLUG | 1866 SDE_AUX_MASK); 1867 } 1868 1869 dev_priv->pch_irq_mask = ~hotplug_mask; 1870 1871 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1872 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1873 I915_WRITE(SDEIER, hotplug_mask); 1874 POSTING_READ(SDEIER); 1875 1876 ironlake_enable_pch_hotplug(dev); 1877 1878 if (IS_IRONLAKE_M(dev)) { 1879 /* Clear & enable PCU event interrupts */ 1880 I915_WRITE(DEIIR, DE_PCU_EVENT); 1881 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); 1882 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 1883 } 1884 1885 return 0; 1886 } 1887 1888 static int ivybridge_irq_postinstall(struct drm_device *dev) 1889 { 1890 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1891 /* enable kind of interrupts always enabled */ 1892 u32 display_mask = 1893 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | 1894 DE_PLANEC_FLIP_DONE_IVB | 1895 DE_PLANEB_FLIP_DONE_IVB | 1896 DE_PLANEA_FLIP_DONE_IVB; 1897 u32 render_irqs; 1898 u32 hotplug_mask; 1899 1900 dev_priv->irq_mask = ~display_mask; 1901 1902 /* should always can generate irq */ 1903 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1904 I915_WRITE(DEIMR, dev_priv->irq_mask); 1905 I915_WRITE(DEIER, 1906 display_mask | 1907 DE_PIPEC_VBLANK_IVB | 1908 DE_PIPEB_VBLANK_IVB | 1909 DE_PIPEA_VBLANK_IVB); 1910 POSTING_READ(DEIER); 1911 1912 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 1913 1914 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1915 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1916 1917 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | 1918 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 1919 I915_WRITE(GTIER, render_irqs); 1920 POSTING_READ(GTIER); 1921 1922 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1923 SDE_PORTB_HOTPLUG_CPT | 1924 SDE_PORTC_HOTPLUG_CPT | 1925 SDE_PORTD_HOTPLUG_CPT); 1926 dev_priv->pch_irq_mask = ~hotplug_mask; 1927 1928 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1929 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1930 I915_WRITE(SDEIER, hotplug_mask); 1931 POSTING_READ(SDEIER); 1932 1933 ironlake_enable_pch_hotplug(dev); 1934 1935 return 0; 1936 } 1937 1938 static int valleyview_irq_postinstall(struct drm_device *dev) 1939 { 1940 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1941 u32 enable_mask; 1942 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1943 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; 1944 u32 render_irqs; 1945 u16 msid; 1946 1947 enable_mask = I915_DISPLAY_PORT_INTERRUPT; 1948 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1949 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 1950 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1951 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1952 1953 /* 1954 *Leave vblank interrupts masked initially. enable/disable will 1955 * toggle them based on usage. 1956 */ 1957 dev_priv->irq_mask = (~enable_mask) | 1958 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 1959 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1960 1961 dev_priv->pipestat[0] = 0; 1962 dev_priv->pipestat[1] = 0; 1963 1964 /* Hack for broken MSIs on VLV */ 1965 pci_write_config(dev_priv->dev->dev, 0x94, 0xfee00000, 4); 1966 msid = pci_read_config(dev->dev, 0x98, 2); 1967 msid &= 0xff; /* mask out delivery bits */ 1968 msid |= (1<<14); 1969 pci_write_config(dev_priv->dev->dev, 0x98, msid, 4); 1970 1971 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 1972 I915_WRITE(VLV_IER, enable_mask); 1973 I915_WRITE(VLV_IIR, 0xffffffff); 1974 I915_WRITE(PIPESTAT(0), 0xffff); 1975 I915_WRITE(PIPESTAT(1), 0xffff); 1976 POSTING_READ(VLV_IER); 1977 1978 i915_enable_pipestat(dev_priv, 0, pipestat_enable); 1979 i915_enable_pipestat(dev_priv, 1, pipestat_enable); 1980 1981 I915_WRITE(VLV_IIR, 0xffffffff); 1982 I915_WRITE(VLV_IIR, 0xffffffff); 1983 1984 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1985 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1986 1987 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | 1988 GEN6_BLITTER_USER_INTERRUPT; 1989 I915_WRITE(GTIER, render_irqs); 1990 POSTING_READ(GTIER); 1991 1992 /* ack & enable invalid PTE error interrupts */ 1993 #if 0 /* FIXME: add support to irq handler for checking these bits */ 1994 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); 1995 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); 1996 #endif 1997 1998 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 1999 /* Note HDMI and DP share bits */ 2000 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2001 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2002 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2003 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2004 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2005 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2006 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) 2007 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2008 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) 2009 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2010 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2011 hotplug_en |= CRT_HOTPLUG_INT_EN; 2012 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2013 } 2014 2015 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2016 2017 return 0; 2018 } 2019 2020 static void valleyview_irq_uninstall(struct drm_device *dev) 2021 { 2022 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2023 int pipe; 2024 2025 if (!dev_priv) 2026 return; 2027 2028 for_each_pipe(pipe) 2029 I915_WRITE(PIPESTAT(pipe), 0xffff); 2030 2031 I915_WRITE(HWSTAM, 0xffffffff); 2032 I915_WRITE(PORT_HOTPLUG_EN, 0); 2033 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2034 for_each_pipe(pipe) 2035 I915_WRITE(PIPESTAT(pipe), 0xffff); 2036 I915_WRITE(VLV_IIR, 0xffffffff); 2037 I915_WRITE(VLV_IMR, 0xffffffff); 2038 I915_WRITE(VLV_IER, 0x0); 2039 POSTING_READ(VLV_IER); 2040 } 2041 2042 static void ironlake_irq_uninstall(struct drm_device *dev) 2043 { 2044 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2045 2046 if (!dev_priv) 2047 return; 2048 2049 I915_WRITE(HWSTAM, 0xffffffff); 2050 2051 I915_WRITE(DEIMR, 0xffffffff); 2052 I915_WRITE(DEIER, 0x0); 2053 I915_WRITE(DEIIR, I915_READ(DEIIR)); 2054 2055 I915_WRITE(GTIMR, 0xffffffff); 2056 I915_WRITE(GTIER, 0x0); 2057 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2058 2059 I915_WRITE(SDEIMR, 0xffffffff); 2060 I915_WRITE(SDEIER, 0x0); 2061 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2062 } 2063 2064 static void i8xx_irq_preinstall(struct drm_device * dev) 2065 { 2066 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2067 int pipe; 2068 2069 atomic_set(&dev_priv->irq_received, 0); 2070 2071 for_each_pipe(pipe) 2072 I915_WRITE(PIPESTAT(pipe), 0); 2073 I915_WRITE16(IMR, 0xffff); 2074 I915_WRITE16(IER, 0x0); 2075 POSTING_READ16(IER); 2076 } 2077 2078 static int i8xx_irq_postinstall(struct drm_device *dev) 2079 { 2080 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2081 2082 dev_priv->pipestat[0] = 0; 2083 dev_priv->pipestat[1] = 0; 2084 2085 I915_WRITE16(EMR, 2086 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2087 2088 /* Unmask the interrupts that we always want on. */ 2089 dev_priv->irq_mask = 2090 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2091 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2092 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2093 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2094 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2095 I915_WRITE16(IMR, dev_priv->irq_mask); 2096 2097 I915_WRITE16(IER, 2098 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2099 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2100 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 2101 I915_USER_INTERRUPT); 2102 POSTING_READ16(IER); 2103 2104 return 0; 2105 } 2106 2107 static irqreturn_t i8xx_irq_handler(void *arg) 2108 { 2109 struct drm_device *dev = (struct drm_device *) arg; 2110 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2111 u16 iir, new_iir; 2112 u32 pipe_stats[2]; 2113 int irq_received; 2114 int pipe; 2115 u16 flip_mask = 2116 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2117 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2118 2119 atomic_inc(&dev_priv->irq_received); 2120 2121 iir = I915_READ16(IIR); 2122 if (iir == 0) 2123 return; 2124 2125 while (iir & ~flip_mask) { 2126 /* Can't rely on pipestat interrupt bit in iir as it might 2127 * have been cleared after the pipestat interrupt was received. 2128 * It doesn't set the bit in iir again, but it still produces 2129 * interrupts (for non-MSI). 2130 */ 2131 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2132 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2133 i915_handle_error(dev, false); 2134 2135 for_each_pipe(pipe) { 2136 int reg = PIPESTAT(pipe); 2137 pipe_stats[pipe] = I915_READ(reg); 2138 2139 /* 2140 * Clear the PIPE*STAT regs before the IIR 2141 */ 2142 if (pipe_stats[pipe] & 0x8000ffff) { 2143 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2144 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2145 pipe_name(pipe)); 2146 I915_WRITE(reg, pipe_stats[pipe]); 2147 irq_received = 1; 2148 } 2149 } 2150 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2151 2152 I915_WRITE16(IIR, iir & ~flip_mask); 2153 new_iir = I915_READ16(IIR); /* Flush posted writes */ 2154 2155 i915_update_dri1_breadcrumb(dev); 2156 2157 if (iir & I915_USER_INTERRUPT) 2158 notify_ring(dev, &dev_priv->ring[RCS]); 2159 2160 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && 2161 drm_handle_vblank(dev, 0)) { 2162 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 2163 intel_prepare_page_flip(dev, 0); 2164 intel_finish_page_flip(dev, 0); 2165 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; 2166 } 2167 } 2168 2169 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && 2170 drm_handle_vblank(dev, 1)) { 2171 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 2172 intel_prepare_page_flip(dev, 1); 2173 intel_finish_page_flip(dev, 1); 2174 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2175 } 2176 } 2177 2178 iir = new_iir; 2179 } 2180 2181 return; 2182 } 2183 2184 static void i8xx_irq_uninstall(struct drm_device * dev) 2185 { 2186 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2187 int pipe; 2188 2189 for_each_pipe(pipe) { 2190 /* Clear enable bits; then clear status bits */ 2191 I915_WRITE(PIPESTAT(pipe), 0); 2192 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 2193 } 2194 I915_WRITE16(IMR, 0xffff); 2195 I915_WRITE16(IER, 0x0); 2196 I915_WRITE16(IIR, I915_READ16(IIR)); 2197 } 2198 2199 static void i915_irq_preinstall(struct drm_device * dev) 2200 { 2201 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2202 int pipe; 2203 2204 atomic_set(&dev_priv->irq_received, 0); 2205 2206 if (I915_HAS_HOTPLUG(dev)) { 2207 I915_WRITE(PORT_HOTPLUG_EN, 0); 2208 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2209 } 2210 2211 I915_WRITE16(HWSTAM, 0xeffe); 2212 for_each_pipe(pipe) 2213 I915_WRITE(PIPESTAT(pipe), 0); 2214 I915_WRITE(IMR, 0xffffffff); 2215 I915_WRITE(IER, 0x0); 2216 POSTING_READ(IER); 2217 } 2218 2219 static int i915_irq_postinstall(struct drm_device *dev) 2220 { 2221 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2222 u32 enable_mask; 2223 2224 dev_priv->pipestat[0] = 0; 2225 dev_priv->pipestat[1] = 0; 2226 2227 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2228 2229 /* Unmask the interrupts that we always want on. */ 2230 dev_priv->irq_mask = 2231 ~(I915_ASLE_INTERRUPT | 2232 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2233 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2234 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2235 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2236 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2237 2238 enable_mask = 2239 I915_ASLE_INTERRUPT | 2240 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2241 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2242 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 2243 I915_USER_INTERRUPT; 2244 2245 if (I915_HAS_HOTPLUG(dev)) { 2246 /* Enable in IER... */ 2247 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 2248 /* and unmask in IMR */ 2249 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 2250 } 2251 2252 I915_WRITE(IMR, dev_priv->irq_mask); 2253 I915_WRITE(IER, enable_mask); 2254 POSTING_READ(IER); 2255 2256 if (I915_HAS_HOTPLUG(dev)) { 2257 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 2258 2259 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2260 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2261 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2262 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2263 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2264 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2265 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) 2266 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2267 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) 2268 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2269 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2270 hotplug_en |= CRT_HOTPLUG_INT_EN; 2271 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2272 } 2273 2274 /* Ignore TV since it's buggy */ 2275 2276 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2277 } 2278 2279 intel_opregion_enable_asle(dev); 2280 2281 return 0; 2282 } 2283 2284 static irqreturn_t i915_irq_handler(void *arg) 2285 { 2286 struct drm_device *dev = (struct drm_device *) arg; 2287 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2288 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 2289 u32 flip_mask = 2290 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2291 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2292 u32 flip[2] = { 2293 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT, 2294 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT 2295 }; 2296 int pipe; 2297 2298 atomic_inc(&dev_priv->irq_received); 2299 2300 iir = I915_READ(IIR); 2301 do { 2302 bool irq_received = (iir & ~flip_mask) != 0; 2303 bool blc_event = false; 2304 2305 /* Can't rely on pipestat interrupt bit in iir as it might 2306 * have been cleared after the pipestat interrupt was received. 2307 * It doesn't set the bit in iir again, but it still produces 2308 * interrupts (for non-MSI). 2309 */ 2310 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2311 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2312 i915_handle_error(dev, false); 2313 2314 for_each_pipe(pipe) { 2315 int reg = PIPESTAT(pipe); 2316 pipe_stats[pipe] = I915_READ(reg); 2317 2318 /* Clear the PIPE*STAT regs before the IIR */ 2319 if (pipe_stats[pipe] & 0x8000ffff) { 2320 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2321 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2322 pipe_name(pipe)); 2323 I915_WRITE(reg, pipe_stats[pipe]); 2324 irq_received = true; 2325 } 2326 } 2327 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2328 2329 if (!irq_received) 2330 break; 2331 2332 /* Consume port. Then clear IIR or we'll miss events */ 2333 if ((I915_HAS_HOTPLUG(dev)) && 2334 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 2335 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 2336 2337 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2338 hotplug_status); 2339 if (hotplug_status & dev_priv->hotplug_supported_mask) 2340 queue_work(dev_priv->wq, 2341 &dev_priv->hotplug_work); 2342 2343 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 2344 POSTING_READ(PORT_HOTPLUG_STAT); 2345 } 2346 2347 I915_WRITE(IIR, iir & ~flip_mask); 2348 new_iir = I915_READ(IIR); /* Flush posted writes */ 2349 2350 if (iir & I915_USER_INTERRUPT) 2351 notify_ring(dev, &dev_priv->ring[RCS]); 2352 2353 for_each_pipe(pipe) { 2354 int plane = pipe; 2355 if (IS_MOBILE(dev)) 2356 plane = !plane; 2357 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 2358 drm_handle_vblank(dev, pipe)) { 2359 if (iir & flip[plane]) { 2360 intel_prepare_page_flip(dev, plane); 2361 intel_finish_page_flip(dev, pipe); 2362 flip_mask &= ~flip[plane]; 2363 } 2364 } 2365 2366 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 2367 blc_event = true; 2368 } 2369 2370 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 2371 intel_opregion_asle_intr(dev); 2372 2373 /* With MSI, interrupts are only generated when iir 2374 * transitions from zero to nonzero. If another bit got 2375 * set while we were handling the existing iir bits, then 2376 * we would never get another interrupt. 2377 * 2378 * This is fine on non-MSI as well, as if we hit this path 2379 * we avoid exiting the interrupt handler only to generate 2380 * another one. 2381 * 2382 * Note that for MSI this could cause a stray interrupt report 2383 * if an interrupt landed in the time between writing IIR and 2384 * the posting read. This should be rare enough to never 2385 * trigger the 99% of 100,000 interrupts test for disabling 2386 * stray interrupts. 2387 */ 2388 iir = new_iir; 2389 } while (iir & ~flip_mask); 2390 2391 i915_update_dri1_breadcrumb(dev); 2392 } 2393 2394 static void i915_irq_uninstall(struct drm_device * dev) 2395 { 2396 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2397 int pipe; 2398 2399 if (I915_HAS_HOTPLUG(dev)) { 2400 I915_WRITE(PORT_HOTPLUG_EN, 0); 2401 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2402 } 2403 2404 I915_WRITE16(HWSTAM, 0xffff); 2405 for_each_pipe(pipe) { 2406 /* Clear enable bits; then clear status bits */ 2407 I915_WRITE(PIPESTAT(pipe), 0); 2408 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 2409 } 2410 I915_WRITE(IMR, 0xffffffff); 2411 I915_WRITE(IER, 0x0); 2412 2413 I915_WRITE(IIR, I915_READ(IIR)); 2414 } 2415 2416 static void i965_irq_preinstall(struct drm_device * dev) 2417 { 2418 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2419 int pipe; 2420 2421 atomic_set(&dev_priv->irq_received, 0); 2422 2423 I915_WRITE(PORT_HOTPLUG_EN, 0); 2424 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2425 2426 I915_WRITE(HWSTAM, 0xeffe); 2427 for_each_pipe(pipe) 2428 I915_WRITE(PIPESTAT(pipe), 0); 2429 I915_WRITE(IMR, 0xffffffff); 2430 I915_WRITE(IER, 0x0); 2431 POSTING_READ(IER); 2432 } 2433 2434 static int i965_irq_postinstall(struct drm_device *dev) 2435 { 2436 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2437 u32 hotplug_en; 2438 u32 enable_mask; 2439 u32 error_mask; 2440 2441 /* Unmask the interrupts that we always want on. */ 2442 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | 2443 I915_DISPLAY_PORT_INTERRUPT | 2444 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2445 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2446 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2447 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2448 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2449 2450 enable_mask = ~dev_priv->irq_mask; 2451 enable_mask |= I915_USER_INTERRUPT; 2452 2453 if (IS_G4X(dev)) 2454 enable_mask |= I915_BSD_USER_INTERRUPT; 2455 2456 dev_priv->pipestat[0] = 0; 2457 dev_priv->pipestat[1] = 0; 2458 2459 /* 2460 * Enable some error detection, note the instruction error mask 2461 * bit is reserved, so we leave it masked. 2462 */ 2463 if (IS_G4X(dev)) { 2464 error_mask = ~(GM45_ERROR_PAGE_TABLE | 2465 GM45_ERROR_MEM_PRIV | 2466 GM45_ERROR_CP_PRIV | 2467 I915_ERROR_MEMORY_REFRESH); 2468 } else { 2469 error_mask = ~(I915_ERROR_PAGE_TABLE | 2470 I915_ERROR_MEMORY_REFRESH); 2471 } 2472 I915_WRITE(EMR, error_mask); 2473 2474 I915_WRITE(IMR, dev_priv->irq_mask); 2475 I915_WRITE(IER, enable_mask); 2476 POSTING_READ(IER); 2477 2478 /* Note HDMI and DP share hotplug bits */ 2479 hotplug_en = 0; 2480 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2481 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2482 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2483 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2484 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2485 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2486 if (IS_G4X(dev)) { 2487 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) 2488 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2489 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X) 2490 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2491 } else { 2492 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965) 2493 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2494 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965) 2495 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2496 } 2497 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2498 hotplug_en |= CRT_HOTPLUG_INT_EN; 2499 2500 /* Programming the CRT detection parameters tends 2501 to generate a spurious hotplug event about three 2502 seconds later. So just do it once. 2503 */ 2504 if (IS_G4X(dev)) 2505 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 2506 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2507 } 2508 2509 /* Ignore TV since it's buggy */ 2510 2511 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2512 2513 intel_opregion_enable_asle(dev); 2514 2515 return 0; 2516 } 2517 2518 static irqreturn_t i965_irq_handler(void *arg) 2519 { 2520 struct drm_device *dev = (struct drm_device *) arg; 2521 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2522 u32 iir, new_iir; 2523 u32 pipe_stats[I915_MAX_PIPES]; 2524 int irq_received; 2525 int pipe; 2526 2527 atomic_inc(&dev_priv->irq_received); 2528 2529 iir = I915_READ(IIR); 2530 2531 for (;;) { 2532 bool blc_event = false; 2533 2534 irq_received = iir != 0; 2535 2536 /* Can't rely on pipestat interrupt bit in iir as it might 2537 * have been cleared after the pipestat interrupt was received. 2538 * It doesn't set the bit in iir again, but it still produces 2539 * interrupts (for non-MSI). 2540 */ 2541 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2542 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2543 i915_handle_error(dev, false); 2544 2545 for_each_pipe(pipe) { 2546 int reg = PIPESTAT(pipe); 2547 pipe_stats[pipe] = I915_READ(reg); 2548 2549 /* 2550 * Clear the PIPE*STAT regs before the IIR 2551 */ 2552 if (pipe_stats[pipe] & 0x8000ffff) { 2553 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2554 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2555 pipe_name(pipe)); 2556 I915_WRITE(reg, pipe_stats[pipe]); 2557 irq_received = 1; 2558 } 2559 } 2560 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2561 2562 if (!irq_received) 2563 break; 2564 2565 /* Consume port. Then clear IIR or we'll miss events */ 2566 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 2567 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 2568 2569 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2570 hotplug_status); 2571 if (hotplug_status & dev_priv->hotplug_supported_mask) 2572 queue_work(dev_priv->wq, 2573 &dev_priv->hotplug_work); 2574 2575 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 2576 I915_READ(PORT_HOTPLUG_STAT); 2577 } 2578 2579 I915_WRITE(IIR, iir); 2580 new_iir = I915_READ(IIR); /* Flush posted writes */ 2581 2582 if (iir & I915_USER_INTERRUPT) 2583 notify_ring(dev, &dev_priv->ring[RCS]); 2584 if (iir & I915_BSD_USER_INTERRUPT) 2585 notify_ring(dev, &dev_priv->ring[VCS]); 2586 2587 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) 2588 intel_prepare_page_flip(dev, 0); 2589 2590 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) 2591 intel_prepare_page_flip(dev, 1); 2592 2593 for_each_pipe(pipe) { 2594 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 2595 drm_handle_vblank(dev, pipe)) { 2596 i915_pageflip_stall_check(dev, pipe); 2597 intel_finish_page_flip(dev, pipe); 2598 } 2599 2600 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 2601 blc_event = true; 2602 } 2603 2604 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 2605 intel_opregion_asle_intr(dev); 2606 2607 /* With MSI, interrupts are only generated when iir 2608 * transitions from zero to nonzero. If another bit got 2609 * set while we were handling the existing iir bits, then 2610 * we would never get another interrupt. 2611 * 2612 * This is fine on non-MSI as well, as if we hit this path 2613 * we avoid exiting the interrupt handler only to generate 2614 * another one. 2615 * 2616 * Note that for MSI this could cause a stray interrupt report 2617 * if an interrupt landed in the time between writing IIR and 2618 * the posting read. This should be rare enough to never 2619 * trigger the 99% of 100,000 interrupts test for disabling 2620 * stray interrupts. 2621 */ 2622 iir = new_iir; 2623 } 2624 2625 i915_update_dri1_breadcrumb(dev); 2626 } 2627 2628 static void i965_irq_uninstall(struct drm_device * dev) 2629 { 2630 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2631 int pipe; 2632 2633 if (!dev_priv) 2634 return; 2635 2636 I915_WRITE(PORT_HOTPLUG_EN, 0); 2637 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2638 2639 I915_WRITE(HWSTAM, 0xffffffff); 2640 for_each_pipe(pipe) 2641 I915_WRITE(PIPESTAT(pipe), 0); 2642 I915_WRITE(IMR, 0xffffffff); 2643 I915_WRITE(IER, 0x0); 2644 2645 for_each_pipe(pipe) 2646 I915_WRITE(PIPESTAT(pipe), 2647 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2648 I915_WRITE(IIR, I915_READ(IIR)); 2649 } 2650 2651 void intel_irq_init(struct drm_device *dev) 2652 { 2653 struct drm_i915_private *dev_priv = dev->dev_private; 2654 2655 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 2656 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 2657 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); 2658 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 2659 2660 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2661 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2662 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 2663 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2664 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2665 } 2666 2667 if (drm_core_check_feature(dev, DRIVER_MODESET)) 2668 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 2669 else 2670 dev->driver->get_vblank_timestamp = NULL; 2671 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 2672 2673 if (IS_VALLEYVIEW(dev)) { 2674 dev->driver->irq_handler = valleyview_irq_handler; 2675 dev->driver->irq_preinstall = valleyview_irq_preinstall; 2676 dev->driver->irq_postinstall = valleyview_irq_postinstall; 2677 dev->driver->irq_uninstall = valleyview_irq_uninstall; 2678 dev->driver->enable_vblank = valleyview_enable_vblank; 2679 dev->driver->disable_vblank = valleyview_disable_vblank; 2680 } else if (IS_IVYBRIDGE(dev)) { 2681 /* Share pre & uninstall handlers with ILK/SNB */ 2682 dev->driver->irq_handler = ivybridge_irq_handler; 2683 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2684 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2685 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2686 dev->driver->enable_vblank = ivybridge_enable_vblank; 2687 dev->driver->disable_vblank = ivybridge_disable_vblank; 2688 } else if (IS_HASWELL(dev)) { 2689 /* Share interrupts handling with IVB */ 2690 dev->driver->irq_handler = ivybridge_irq_handler; 2691 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2692 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2693 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2694 dev->driver->enable_vblank = ivybridge_enable_vblank; 2695 dev->driver->disable_vblank = ivybridge_disable_vblank; 2696 } else if (HAS_PCH_SPLIT(dev)) { 2697 dev->driver->irq_handler = ironlake_irq_handler; 2698 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2699 dev->driver->irq_postinstall = ironlake_irq_postinstall; 2700 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2701 dev->driver->enable_vblank = ironlake_enable_vblank; 2702 dev->driver->disable_vblank = ironlake_disable_vblank; 2703 } else { 2704 if (INTEL_INFO(dev)->gen == 2) { 2705 dev->driver->irq_preinstall = i8xx_irq_preinstall; 2706 dev->driver->irq_postinstall = i8xx_irq_postinstall; 2707 dev->driver->irq_handler = i8xx_irq_handler; 2708 dev->driver->irq_uninstall = i8xx_irq_uninstall; 2709 } else if (INTEL_INFO(dev)->gen == 3) { 2710 dev->driver->irq_preinstall = i915_irq_preinstall; 2711 dev->driver->irq_postinstall = i915_irq_postinstall; 2712 dev->driver->irq_uninstall = i915_irq_uninstall; 2713 dev->driver->irq_handler = i915_irq_handler; 2714 } else { 2715 dev->driver->irq_preinstall = i965_irq_preinstall; 2716 dev->driver->irq_postinstall = i965_irq_postinstall; 2717 dev->driver->irq_uninstall = i965_irq_uninstall; 2718 dev->driver->irq_handler = i965_irq_handler; 2719 } 2720 dev->driver->enable_vblank = i915_enable_vblank; 2721 dev->driver->disable_vblank = i915_disable_vblank; 2722 } 2723 } 2724