1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/i915_drm.h> 31 #include "i915_drv.h" 32 #include "intel_drv.h" 33 34 /* For display hotplug interrupt */ 35 static void 36 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 37 { 38 if ((dev_priv->irq_mask & mask) != 0) { 39 dev_priv->irq_mask &= ~mask; 40 I915_WRITE(DEIMR, dev_priv->irq_mask); 41 POSTING_READ(DEIMR); 42 } 43 } 44 45 static inline void 46 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 47 { 48 if ((dev_priv->irq_mask & mask) != mask) { 49 dev_priv->irq_mask |= mask; 50 I915_WRITE(DEIMR, dev_priv->irq_mask); 51 POSTING_READ(DEIMR); 52 } 53 } 54 55 void 56 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 57 { 58 if ((dev_priv->pipestat[pipe] & mask) != mask) { 59 u32 reg = PIPESTAT(pipe); 60 61 dev_priv->pipestat[pipe] |= mask; 62 /* Enable the interrupt, clear any pending status */ 63 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 64 POSTING_READ(reg); 65 } 66 } 67 68 void 69 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 70 { 71 if ((dev_priv->pipestat[pipe] & mask) != 0) { 72 u32 reg = PIPESTAT(pipe); 73 74 dev_priv->pipestat[pipe] &= ~mask; 75 I915_WRITE(reg, dev_priv->pipestat[pipe]); 76 POSTING_READ(reg); 77 } 78 } 79 80 /** 81 * intel_enable_asle - enable ASLE interrupt for OpRegion 82 */ 83 void intel_enable_asle(struct drm_device *dev) 84 { 85 drm_i915_private_t *dev_priv = dev->dev_private; 86 87 /* FIXME: opregion/asle for VLV */ 88 if (IS_VALLEYVIEW(dev)) 89 return; 90 91 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 92 93 if (HAS_PCH_SPLIT(dev)) 94 ironlake_enable_display_irq(dev_priv, DE_GSE); 95 else { 96 i915_enable_pipestat(dev_priv, 1, 97 PIPE_LEGACY_BLC_EVENT_ENABLE); 98 if (INTEL_INFO(dev)->gen >= 4) 99 i915_enable_pipestat(dev_priv, 0, 100 PIPE_LEGACY_BLC_EVENT_ENABLE); 101 } 102 103 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 104 } 105 106 /** 107 * i915_pipe_enabled - check if a pipe is enabled 108 * @dev: DRM device 109 * @pipe: pipe to check 110 * 111 * Reading certain registers when the pipe is disabled can hang the chip. 112 * Use this routine to make sure the PLL is running and the pipe is active 113 * before reading such registers if unsure. 114 */ 115 static int 116 i915_pipe_enabled(struct drm_device *dev, int pipe) 117 { 118 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 120 pipe); 121 122 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE; 123 } 124 125 /* Called from drm generic code, passed a 'crtc', which 126 * we use as a pipe index 127 */ 128 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 129 { 130 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 131 unsigned long high_frame; 132 unsigned long low_frame; 133 u32 high1, high2, low; 134 135 if (!i915_pipe_enabled(dev, pipe)) { 136 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 137 "pipe %c\n", pipe_name(pipe)); 138 return 0; 139 } 140 141 high_frame = PIPEFRAME(pipe); 142 low_frame = PIPEFRAMEPIXEL(pipe); 143 144 /* 145 * High & low register fields aren't synchronized, so make sure 146 * we get a low value that's stable across two reads of the high 147 * register. 148 */ 149 do { 150 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 151 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; 152 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 153 } while (high1 != high2); 154 155 high1 >>= PIPE_FRAME_HIGH_SHIFT; 156 low >>= PIPE_FRAME_LOW_SHIFT; 157 return (high1 << 8) | low; 158 } 159 160 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 161 { 162 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 163 int reg = PIPE_FRMCOUNT_GM45(pipe); 164 165 if (!i915_pipe_enabled(dev, pipe)) { 166 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 167 "pipe %c\n", pipe_name(pipe)); 168 return 0; 169 } 170 171 return I915_READ(reg); 172 } 173 174 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 175 int *vpos, int *hpos) 176 { 177 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 178 u32 vbl = 0, position = 0; 179 int vbl_start, vbl_end, htotal, vtotal; 180 bool in_vbl = true; 181 int ret = 0; 182 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 183 pipe); 184 185 if (!i915_pipe_enabled(dev, pipe)) { 186 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 187 "pipe %c\n", pipe_name(pipe)); 188 return 0; 189 } 190 191 /* Get vtotal. */ 192 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); 193 194 if (INTEL_INFO(dev)->gen >= 4) { 195 /* No obvious pixelcount register. Only query vertical 196 * scanout position from Display scan line register. 197 */ 198 position = I915_READ(PIPEDSL(pipe)); 199 200 /* Decode into vertical scanout position. Don't have 201 * horizontal scanout position. 202 */ 203 *vpos = position & 0x1fff; 204 *hpos = 0; 205 } else { 206 /* Have access to pixelcount since start of frame. 207 * We can split this into vertical and horizontal 208 * scanout position. 209 */ 210 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 211 212 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff); 213 *vpos = position / htotal; 214 *hpos = position - (*vpos * htotal); 215 } 216 217 /* Query vblank area. */ 218 vbl = I915_READ(VBLANK(cpu_transcoder)); 219 220 /* Test position against vblank region. */ 221 vbl_start = vbl & 0x1fff; 222 vbl_end = (vbl >> 16) & 0x1fff; 223 224 if ((*vpos < vbl_start) || (*vpos > vbl_end)) 225 in_vbl = false; 226 227 /* Inside "upper part" of vblank area? Apply corrective offset: */ 228 if (in_vbl && (*vpos >= vbl_start)) 229 *vpos = *vpos - vtotal; 230 231 /* Readouts valid? */ 232 if (vbl > 0) 233 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 234 235 /* In vblank? */ 236 if (in_vbl) 237 ret |= DRM_SCANOUTPOS_INVBL; 238 239 return ret; 240 } 241 242 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 243 int *max_error, 244 struct timeval *vblank_time, 245 unsigned flags) 246 { 247 struct drm_i915_private *dev_priv = dev->dev_private; 248 struct drm_crtc *crtc; 249 250 if (pipe < 0 || pipe >= dev_priv->num_pipe) { 251 DRM_ERROR("Invalid crtc %d\n", pipe); 252 return -EINVAL; 253 } 254 255 /* Get drm_crtc to timestamp: */ 256 crtc = intel_get_crtc_for_pipe(dev, pipe); 257 if (crtc == NULL) { 258 DRM_ERROR("Invalid crtc %d\n", pipe); 259 return -EINVAL; 260 } 261 262 if (!crtc->enabled) { 263 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 264 return -EBUSY; 265 } 266 267 /* Helper routine in DRM core does all the work: */ 268 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 269 vblank_time, flags, 270 crtc); 271 } 272 273 /* 274 * Handle hotplug events outside the interrupt handler proper. 275 */ 276 static void i915_hotplug_work_func(struct work_struct *work) 277 { 278 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 279 hotplug_work); 280 struct drm_device *dev = dev_priv->dev; 281 struct drm_mode_config *mode_config = &dev->mode_config; 282 struct intel_encoder *encoder; 283 284 lockmgr(&mode_config->mutex, LK_EXCLUSIVE); 285 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 286 287 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 288 if (encoder->hot_plug) 289 encoder->hot_plug(encoder); 290 291 lockmgr(&mode_config->mutex, LK_RELEASE); 292 293 /* Just fire off a uevent and let userspace tell us what to do */ 294 drm_helper_hpd_irq_event(dev); 295 } 296 297 static void ironlake_handle_rps_change(struct drm_device *dev) 298 { 299 drm_i915_private_t *dev_priv = dev->dev_private; 300 u32 busy_up, busy_down, max_avg, min_avg; 301 u8 new_delay; 302 303 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 304 305 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 306 307 new_delay = dev_priv->ips.cur_delay; 308 309 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 310 busy_up = I915_READ(RCPREVBSYTUPAVG); 311 busy_down = I915_READ(RCPREVBSYTDNAVG); 312 max_avg = I915_READ(RCBMAXAVG); 313 min_avg = I915_READ(RCBMINAVG); 314 315 /* Handle RCS change request from hw */ 316 if (busy_up > max_avg) { 317 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) 318 new_delay = dev_priv->ips.cur_delay - 1; 319 if (new_delay < dev_priv->ips.max_delay) 320 new_delay = dev_priv->ips.max_delay; 321 } else if (busy_down < min_avg) { 322 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) 323 new_delay = dev_priv->ips.cur_delay + 1; 324 if (new_delay > dev_priv->ips.min_delay) 325 new_delay = dev_priv->ips.min_delay; 326 } 327 328 if (ironlake_set_drps(dev, new_delay)) 329 dev_priv->ips.cur_delay = new_delay; 330 331 lockmgr(&mchdev_lock, LK_RELEASE); 332 333 return; 334 } 335 336 static void notify_ring(struct drm_device *dev, 337 struct intel_ring_buffer *ring) 338 { 339 struct drm_i915_private *dev_priv = dev->dev_private; 340 341 if (ring->obj == NULL) 342 return; 343 344 wake_up_all(&ring->irq_queue); 345 if (i915_enable_hangcheck) { 346 dev_priv->hangcheck_count = 0; 347 mod_timer(&dev_priv->hangcheck_timer, 348 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 349 } 350 } 351 352 static void gen6_pm_rps_work(struct work_struct *work) 353 { 354 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 355 rps.work); 356 u32 pm_iir, pm_imr; 357 u8 new_delay; 358 359 spin_lock(&dev_priv->rps.lock); 360 pm_iir = dev_priv->rps.pm_iir; 361 dev_priv->rps.pm_iir = 0; 362 pm_imr = I915_READ(GEN6_PMIMR); 363 I915_WRITE(GEN6_PMIMR, 0); 364 spin_unlock(&dev_priv->rps.lock); 365 366 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0) 367 return; 368 369 lockmgr(&dev_priv->rps.hw_lock, LK_EXCLUSIVE); 370 371 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) 372 new_delay = dev_priv->rps.cur_delay + 1; 373 else 374 new_delay = dev_priv->rps.cur_delay - 1; 375 376 /* sysfs frequency interfaces may have snuck in while servicing the 377 * interrupt 378 */ 379 if (!(new_delay > dev_priv->rps.max_delay || 380 new_delay < dev_priv->rps.min_delay)) { 381 gen6_set_rps(dev_priv->dev, new_delay); 382 } 383 384 lockmgr(&dev_priv->rps.hw_lock, LK_RELEASE); 385 } 386 387 388 /** 389 * ivybridge_parity_work - Workqueue called when a parity error interrupt 390 * occurred. 391 * @work: workqueue struct 392 * 393 * Doesn't actually do anything except notify userspace. As a consequence of 394 * this event, userspace should try to remap the bad rows since statistically 395 * it is likely the same row is more likely to go bad again. 396 */ 397 static void ivybridge_parity_work(struct work_struct *work) 398 { 399 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 400 l3_parity.error_work); 401 u32 error_status, row, bank, subbank; 402 uint32_t misccpctl; 403 404 /* We must turn off DOP level clock gating to access the L3 registers. 405 * In order to prevent a get/put style interface, acquire struct mutex 406 * any time we access those registers. 407 */ 408 DRM_LOCK(dev_priv->dev); 409 410 misccpctl = I915_READ(GEN7_MISCCPCTL); 411 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 412 POSTING_READ(GEN7_MISCCPCTL); 413 414 error_status = I915_READ(GEN7_L3CDERRST1); 415 row = GEN7_PARITY_ERROR_ROW(error_status); 416 bank = GEN7_PARITY_ERROR_BANK(error_status); 417 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 418 419 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | 420 GEN7_L3CDERRST1_ENABLE); 421 POSTING_READ(GEN7_L3CDERRST1); 422 423 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 424 425 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 426 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 427 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 428 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 429 430 DRM_UNLOCK(dev_priv->dev); 431 432 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n", 433 row, bank, subbank); 434 } 435 436 static void ivybridge_handle_parity_error(struct drm_device *dev) 437 { 438 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 439 440 if (!HAS_L3_GPU_CACHE(dev)) 441 return; 442 443 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 444 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 445 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 446 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 447 448 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); 449 } 450 451 static void snb_gt_irq_handler(struct drm_device *dev, 452 struct drm_i915_private *dev_priv, 453 u32 gt_iir) 454 { 455 456 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | 457 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) 458 notify_ring(dev, &dev_priv->ring[RCS]); 459 if (gt_iir & GEN6_BSD_USER_INTERRUPT) 460 notify_ring(dev, &dev_priv->ring[VCS]); 461 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) 462 notify_ring(dev, &dev_priv->ring[BCS]); 463 464 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | 465 GT_GEN6_BSD_CS_ERROR_INTERRUPT | 466 GT_RENDER_CS_ERROR_INTERRUPT)) { 467 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); 468 i915_handle_error(dev, false); 469 } 470 471 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT) 472 ivybridge_handle_parity_error(dev); 473 } 474 475 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, 476 u32 pm_iir) 477 { 478 479 /* 480 * IIR bits should never already be set because IMR should 481 * prevent an interrupt from being shown in IIR. The warning 482 * displays a case where we've unsafely cleared 483 * dev_priv->rps.pm_iir. Although missing an interrupt of the same 484 * type is not a problem, it displays a problem in the logic. 485 * 486 * The mask bit in IMR is cleared by dev_priv->rps.work. 487 */ 488 489 spin_lock(&dev_priv->rps.lock); 490 dev_priv->rps.pm_iir |= pm_iir; 491 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); 492 POSTING_READ(GEN6_PMIMR); 493 spin_unlock(&dev_priv->rps.lock); 494 495 queue_work(dev_priv->wq, &dev_priv->rps.work); 496 } 497 498 static irqreturn_t valleyview_irq_handler(void *arg) 499 { 500 struct drm_device *dev = (struct drm_device *) arg; 501 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 502 u32 iir, gt_iir, pm_iir; 503 int pipe; 504 u32 pipe_stats[I915_MAX_PIPES]; 505 bool blc_event; 506 507 atomic_inc(&dev_priv->irq_received); 508 509 while (true) { 510 iir = I915_READ(VLV_IIR); 511 gt_iir = I915_READ(GTIIR); 512 pm_iir = I915_READ(GEN6_PMIIR); 513 514 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 515 goto out; 516 517 snb_gt_irq_handler(dev, dev_priv, gt_iir); 518 519 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 520 for_each_pipe(pipe) { 521 int reg = PIPESTAT(pipe); 522 pipe_stats[pipe] = I915_READ(reg); 523 524 /* 525 * Clear the PIPE*STAT regs before the IIR 526 */ 527 if (pipe_stats[pipe] & 0x8000ffff) { 528 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 529 DRM_DEBUG_DRIVER("pipe %c underrun\n", 530 pipe_name(pipe)); 531 I915_WRITE(reg, pipe_stats[pipe]); 532 } 533 } 534 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 535 536 for_each_pipe(pipe) { 537 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 538 drm_handle_vblank(dev, pipe); 539 540 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { 541 intel_prepare_page_flip(dev, pipe); 542 intel_finish_page_flip(dev, pipe); 543 } 544 } 545 546 /* Consume port. Then clear IIR or we'll miss events */ 547 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 548 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 549 550 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 551 hotplug_status); 552 if (hotplug_status & dev_priv->hotplug_supported_mask) 553 queue_work(dev_priv->wq, 554 &dev_priv->hotplug_work); 555 556 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 557 I915_READ(PORT_HOTPLUG_STAT); 558 } 559 560 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 561 blc_event = true; 562 563 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) 564 gen6_queue_rps_work(dev_priv, pm_iir); 565 566 I915_WRITE(GTIIR, gt_iir); 567 I915_WRITE(GEN6_PMIIR, pm_iir); 568 I915_WRITE(VLV_IIR, iir); 569 } 570 571 out: 572 return; 573 } 574 575 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 576 { 577 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 578 int pipe; 579 580 if (pch_iir & SDE_HOTPLUG_MASK) 581 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 582 583 if (pch_iir & SDE_AUDIO_POWER_MASK) 584 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 585 (pch_iir & SDE_AUDIO_POWER_MASK) >> 586 SDE_AUDIO_POWER_SHIFT); 587 588 if (pch_iir & SDE_GMBUS) 589 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 590 591 if (pch_iir & SDE_AUDIO_HDCP_MASK) 592 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 593 594 if (pch_iir & SDE_AUDIO_TRANS_MASK) 595 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 596 597 if (pch_iir & SDE_POISON) 598 DRM_ERROR("PCH poison interrupt\n"); 599 600 if (pch_iir & SDE_FDI_MASK) 601 for_each_pipe(pipe) 602 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 603 pipe_name(pipe), 604 I915_READ(FDI_RX_IIR(pipe))); 605 606 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 607 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 608 609 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 610 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 611 612 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 613 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); 614 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 615 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 616 } 617 618 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 619 { 620 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 621 int pipe; 622 623 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 624 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 625 626 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) 627 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 628 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 629 SDE_AUDIO_POWER_SHIFT_CPT); 630 631 if (pch_iir & SDE_AUX_MASK_CPT) 632 DRM_DEBUG_DRIVER("AUX channel interrupt\n"); 633 634 if (pch_iir & SDE_GMBUS_CPT) 635 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 636 637 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 638 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 639 640 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 641 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 642 643 if (pch_iir & SDE_FDI_MASK_CPT) 644 for_each_pipe(pipe) 645 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 646 pipe_name(pipe), 647 I915_READ(FDI_RX_IIR(pipe))); 648 } 649 650 static irqreturn_t ivybridge_irq_handler(void *arg) 651 { 652 struct drm_device *dev = (struct drm_device *) arg; 653 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 654 u32 de_iir, gt_iir, de_ier, pm_iir; 655 int i; 656 657 atomic_inc(&dev_priv->irq_received); 658 659 /* disable master interrupt before clearing iir */ 660 de_ier = I915_READ(DEIER); 661 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 662 663 gt_iir = I915_READ(GTIIR); 664 if (gt_iir) { 665 snb_gt_irq_handler(dev, dev_priv, gt_iir); 666 I915_WRITE(GTIIR, gt_iir); 667 } 668 669 de_iir = I915_READ(DEIIR); 670 if (de_iir) { 671 if (de_iir & DE_GSE_IVB) 672 intel_opregion_gse_intr(dev); 673 674 for (i = 0; i < 3; i++) { 675 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) 676 drm_handle_vblank(dev, i); 677 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { 678 intel_prepare_page_flip(dev, i); 679 intel_finish_page_flip_plane(dev, i); 680 } 681 } 682 683 /* check event from PCH */ 684 if (de_iir & DE_PCH_EVENT_IVB) { 685 u32 pch_iir = I915_READ(SDEIIR); 686 687 cpt_irq_handler(dev, pch_iir); 688 689 /* clear PCH hotplug event before clear CPU irq */ 690 I915_WRITE(SDEIIR, pch_iir); 691 } 692 693 I915_WRITE(DEIIR, de_iir); 694 } 695 696 pm_iir = I915_READ(GEN6_PMIIR); 697 if (pm_iir) { 698 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) 699 gen6_queue_rps_work(dev_priv, pm_iir); 700 I915_WRITE(GEN6_PMIIR, pm_iir); 701 } 702 703 I915_WRITE(DEIER, de_ier); 704 POSTING_READ(DEIER); 705 } 706 707 static void ilk_gt_irq_handler(struct drm_device *dev, 708 struct drm_i915_private *dev_priv, 709 u32 gt_iir) 710 { 711 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 712 notify_ring(dev, &dev_priv->ring[RCS]); 713 if (gt_iir & GT_BSD_USER_INTERRUPT) 714 notify_ring(dev, &dev_priv->ring[VCS]); 715 } 716 717 static irqreturn_t ironlake_irq_handler(void *arg) 718 { 719 struct drm_device *dev = (struct drm_device *) arg; 720 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 721 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 722 723 atomic_inc(&dev_priv->irq_received); 724 725 /* disable master interrupt before clearing iir */ 726 de_ier = I915_READ(DEIER); 727 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 728 POSTING_READ(DEIER); 729 730 de_iir = I915_READ(DEIIR); 731 gt_iir = I915_READ(GTIIR); 732 pch_iir = I915_READ(SDEIIR); 733 pm_iir = I915_READ(GEN6_PMIIR); 734 735 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && 736 (!IS_GEN6(dev) || pm_iir == 0)) 737 goto done; 738 739 if (IS_GEN5(dev)) 740 ilk_gt_irq_handler(dev, dev_priv, gt_iir); 741 else 742 snb_gt_irq_handler(dev, dev_priv, gt_iir); 743 744 if (de_iir & DE_GSE) 745 intel_opregion_gse_intr(dev); 746 747 if (de_iir & DE_PIPEA_VBLANK) 748 drm_handle_vblank(dev, 0); 749 750 if (de_iir & DE_PIPEB_VBLANK) 751 drm_handle_vblank(dev, 1); 752 753 if (de_iir & DE_PLANEA_FLIP_DONE) { 754 intel_prepare_page_flip(dev, 0); 755 intel_finish_page_flip_plane(dev, 0); 756 } 757 758 if (de_iir & DE_PLANEB_FLIP_DONE) { 759 intel_prepare_page_flip(dev, 1); 760 intel_finish_page_flip_plane(dev, 1); 761 } 762 763 /* check event from PCH */ 764 if (de_iir & DE_PCH_EVENT) { 765 if (HAS_PCH_CPT(dev)) 766 cpt_irq_handler(dev, pch_iir); 767 else 768 ibx_irq_handler(dev, pch_iir); 769 } 770 771 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 772 ironlake_handle_rps_change(dev); 773 774 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) 775 gen6_queue_rps_work(dev_priv, pm_iir); 776 777 /* should clear PCH hotplug event before clear CPU irq */ 778 I915_WRITE(SDEIIR, pch_iir); 779 I915_WRITE(GTIIR, gt_iir); 780 I915_WRITE(DEIIR, de_iir); 781 I915_WRITE(GEN6_PMIIR, pm_iir); 782 783 done: 784 I915_WRITE(DEIER, de_ier); 785 POSTING_READ(DEIER); 786 } 787 788 /** 789 * i915_error_work_func - do process context error handling work 790 * @work: work struct 791 * 792 * Fire an error uevent so userspace can see that a hang or error 793 * was detected. 794 */ 795 static void i915_error_work_func(struct work_struct *work) 796 { 797 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 798 error_work); 799 struct drm_device *dev = dev_priv->dev; 800 801 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */ 802 803 if (atomic_read(&dev_priv->mm.wedged)) { 804 DRM_DEBUG_DRIVER("resetting chip\n"); 805 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */ 806 if (!i915_reset(dev)) { 807 atomic_set(&dev_priv->mm.wedged, 0); 808 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); */ 809 } 810 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE); 811 dev_priv->error_completion++; 812 wakeup(&dev_priv->error_completion); 813 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE); 814 } 815 } 816 817 /* NB: please notice the memset */ 818 static void i915_get_extra_instdone(struct drm_device *dev, 819 uint32_t *instdone) 820 { 821 struct drm_i915_private *dev_priv = dev->dev_private; 822 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 823 824 switch(INTEL_INFO(dev)->gen) { 825 case 2: 826 case 3: 827 instdone[0] = I915_READ(INSTDONE); 828 break; 829 case 4: 830 case 5: 831 case 6: 832 instdone[0] = I915_READ(INSTDONE_I965); 833 instdone[1] = I915_READ(INSTDONE1); 834 break; 835 default: 836 #if 0 837 WARN_ONCE(1, "Unsupported platform\n"); 838 #endif 839 case 7: 840 instdone[0] = I915_READ(GEN7_INSTDONE_1); 841 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 842 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 843 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 844 break; 845 } 846 } 847 848 #if 0 /* CONFIG_DEBUG_FS */ 849 static struct drm_i915_error_object * 850 i915_error_object_create(struct drm_i915_private *dev_priv, 851 struct drm_i915_gem_object *src) 852 { 853 struct drm_i915_error_object *dst; 854 int i, count; 855 u32 reloc_offset; 856 857 if (src == NULL || src->pages == NULL) 858 return NULL; 859 860 count = src->base.size / PAGE_SIZE; 861 862 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC); 863 if (dst == NULL) 864 return NULL; 865 866 reloc_offset = src->gtt_offset; 867 for (i = 0; i < count; i++) { 868 unsigned long flags; 869 void *d; 870 871 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 872 if (d == NULL) 873 goto unwind; 874 875 local_irq_save(flags); 876 if (reloc_offset < dev_priv->mm.gtt_mappable_end && 877 src->has_global_gtt_mapping) { 878 void __iomem *s; 879 880 /* Simply ignore tiling or any overlapping fence. 881 * It's part of the error state, and this hopefully 882 * captures what the GPU read. 883 */ 884 885 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 886 reloc_offset); 887 memcpy_fromio(d, s, PAGE_SIZE); 888 io_mapping_unmap_atomic(s); 889 } else { 890 struct page *page; 891 void *s; 892 893 page = i915_gem_object_get_page(src, i); 894 895 drm_clflush_pages(&page, 1); 896 897 s = kmap_atomic(page); 898 memcpy(d, s, PAGE_SIZE); 899 kunmap_atomic(s); 900 901 drm_clflush_pages(&page, 1); 902 } 903 local_irq_restore(flags); 904 905 dst->pages[i] = d; 906 907 reloc_offset += PAGE_SIZE; 908 } 909 dst->page_count = count; 910 dst->gtt_offset = src->gtt_offset; 911 912 return dst; 913 914 unwind: 915 while (i--) 916 kfree(dst->pages[i]); 917 kfree(dst); 918 return NULL; 919 } 920 921 static void 922 i915_error_object_free(struct drm_i915_error_object *obj) 923 { 924 int page; 925 926 if (obj == NULL) 927 return; 928 929 for (page = 0; page < obj->page_count; page++) 930 kfree(obj->pages[page]); 931 932 kfree(obj); 933 } 934 935 void 936 i915_error_state_free(struct drm_device *dev, 937 struct drm_i915_error_state *error) 938 { 939 struct drm_i915_error_state *error = container_of(error_ref, 940 typeof(*error), ref); 941 int i; 942 943 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 944 i915_error_object_free(error->ring[i].batchbuffer); 945 i915_error_object_free(error->ring[i].ringbuffer); 946 kfree(error->ring[i].requests); 947 } 948 949 kfree(error->active_bo); 950 kfree(error->overlay); 951 kfree(error); 952 } 953 static void capture_bo(struct drm_i915_error_buffer *err, 954 struct drm_i915_gem_object *obj) 955 { 956 err->size = obj->base.size; 957 err->name = obj->base.name; 958 err->rseqno = obj->last_read_seqno; 959 err->wseqno = obj->last_write_seqno; 960 err->gtt_offset = obj->gtt_offset; 961 err->read_domains = obj->base.read_domains; 962 err->write_domain = obj->base.write_domain; 963 err->fence_reg = obj->fence_reg; 964 err->pinned = 0; 965 if (obj->pin_count > 0) 966 err->pinned = 1; 967 if (obj->user_pin_count > 0) 968 err->pinned = -1; 969 err->tiling = obj->tiling_mode; 970 err->dirty = obj->dirty; 971 err->purgeable = obj->madv != I915_MADV_WILLNEED; 972 err->ring = obj->ring ? obj->ring->id : -1; 973 err->cache_level = obj->cache_level; 974 } 975 976 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 977 int count, struct list_head *head) 978 { 979 struct drm_i915_gem_object *obj; 980 int i = 0; 981 982 list_for_each_entry(obj, head, mm_list) { 983 capture_bo(err++, obj); 984 if (++i == count) 985 break; 986 } 987 988 return i; 989 } 990 991 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 992 int count, struct list_head *head) 993 { 994 struct drm_i915_gem_object *obj; 995 int i = 0; 996 997 list_for_each_entry(obj, head, gtt_list) { 998 if (obj->pin_count == 0) 999 continue; 1000 1001 capture_bo(err++, obj); 1002 if (++i == count) 1003 break; 1004 } 1005 1006 return i; 1007 } 1008 1009 static void i915_gem_record_fences(struct drm_device *dev, 1010 struct drm_i915_error_state *error) 1011 { 1012 struct drm_i915_private *dev_priv = dev->dev_private; 1013 int i; 1014 1015 /* Fences */ 1016 switch (INTEL_INFO(dev)->gen) { 1017 case 7: 1018 case 6: 1019 for (i = 0; i < 16; i++) 1020 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 1021 break; 1022 case 5: 1023 case 4: 1024 for (i = 0; i < 16; i++) 1025 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 1026 break; 1027 case 3: 1028 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 1029 for (i = 0; i < 8; i++) 1030 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 1031 case 2: 1032 for (i = 0; i < 8; i++) 1033 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 1034 break; 1035 1036 } 1037 } 1038 1039 static struct drm_i915_error_object * 1040 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 1041 struct intel_ring_buffer *ring) 1042 { 1043 struct drm_i915_gem_object *obj; 1044 u32 seqno; 1045 1046 if (!ring->get_seqno) 1047 return NULL; 1048 1049 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { 1050 u32 acthd = I915_READ(ACTHD); 1051 1052 if (WARN_ON(ring->id != RCS)) 1053 return NULL; 1054 1055 obj = ring->private; 1056 if (acthd >= obj->gtt_offset && 1057 acthd < obj->gtt_offset + obj->base.size) 1058 return i915_error_object_create(dev_priv, obj); 1059 } 1060 1061 seqno = ring->get_seqno(ring, false); 1062 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 1063 if (obj->ring != ring) 1064 continue; 1065 1066 if (i915_seqno_passed(seqno, obj->last_read_seqno)) 1067 continue; 1068 1069 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 1070 continue; 1071 1072 /* We need to copy these to an anonymous buffer as the simplest 1073 * method to avoid being overwritten by userspace. 1074 */ 1075 return i915_error_object_create(dev_priv, obj); 1076 } 1077 1078 return NULL; 1079 } 1080 1081 static void i915_record_ring_state(struct drm_device *dev, 1082 struct drm_i915_error_state *error, 1083 struct intel_ring_buffer *ring) 1084 { 1085 struct drm_i915_private *dev_priv = dev->dev_private; 1086 1087 if (INTEL_INFO(dev)->gen >= 6) { 1088 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); 1089 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); 1090 error->semaphore_mboxes[ring->id][0] 1091 = I915_READ(RING_SYNC_0(ring->mmio_base)); 1092 error->semaphore_mboxes[ring->id][1] 1093 = I915_READ(RING_SYNC_1(ring->mmio_base)); 1094 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0]; 1095 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1]; 1096 } 1097 1098 if (INTEL_INFO(dev)->gen >= 4) { 1099 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 1100 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 1101 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 1102 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 1103 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 1104 if (ring->id == RCS) 1105 error->bbaddr = I915_READ64(BB_ADDR); 1106 } else { 1107 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); 1108 error->ipeir[ring->id] = I915_READ(IPEIR); 1109 error->ipehr[ring->id] = I915_READ(IPEHR); 1110 error->instdone[ring->id] = I915_READ(INSTDONE); 1111 } 1112 1113 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); 1114 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); 1115 error->seqno[ring->id] = ring->get_seqno(ring, false); 1116 error->acthd[ring->id] = intel_ring_get_active_head(ring); 1117 error->head[ring->id] = I915_READ_HEAD(ring); 1118 error->tail[ring->id] = I915_READ_TAIL(ring); 1119 error->ctl[ring->id] = I915_READ_CTL(ring); 1120 1121 error->cpu_ring_head[ring->id] = ring->head; 1122 error->cpu_ring_tail[ring->id] = ring->tail; 1123 } 1124 1125 static void i915_gem_record_rings(struct drm_device *dev, 1126 struct drm_i915_error_state *error) 1127 { 1128 struct drm_i915_private *dev_priv = dev->dev_private; 1129 struct intel_ring_buffer *ring; 1130 struct drm_i915_gem_request *request; 1131 int i, count; 1132 1133 for_each_ring(ring, dev_priv, i) { 1134 i915_record_ring_state(dev, error, ring); 1135 1136 error->ring[i].batchbuffer = 1137 i915_error_first_batchbuffer(dev_priv, ring); 1138 1139 error->ring[i].ringbuffer = 1140 i915_error_object_create(dev_priv, ring->obj); 1141 1142 count = 0; 1143 list_for_each_entry(request, &ring->request_list, list) 1144 count++; 1145 1146 error->ring[i].num_requests = count; 1147 error->ring[i].requests = 1148 kmalloc(count*sizeof(struct drm_i915_error_request), 1149 GFP_ATOMIC); 1150 if (error->ring[i].requests == NULL) { 1151 error->ring[i].num_requests = 0; 1152 continue; 1153 } 1154 1155 count = 0; 1156 list_for_each_entry(request, &ring->request_list, list) { 1157 struct drm_i915_error_request *erq; 1158 1159 erq = &error->ring[i].requests[count++]; 1160 erq->seqno = request->seqno; 1161 erq->jiffies = request->emitted_jiffies; 1162 erq->tail = request->tail; 1163 } 1164 } 1165 } 1166 1167 /** 1168 * i915_capture_error_state - capture an error record for later analysis 1169 * @dev: drm device 1170 * 1171 * Should be called when an error is detected (either a hang or an error 1172 * interrupt) to capture error state from the time of the error. Fills 1173 * out a structure which becomes available in debugfs for user level tools 1174 * to pick up. 1175 */ 1176 static void i915_capture_error_state(struct drm_device *dev) 1177 { 1178 struct drm_i915_private *dev_priv = dev->dev_private; 1179 struct drm_i915_gem_object *obj; 1180 struct drm_i915_error_state *error; 1181 unsigned long flags; 1182 int i, pipe; 1183 1184 spin_lock_irqsave(&dev_priv->error_lock, flags); 1185 error = dev_priv->first_error; 1186 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1187 if (error) 1188 return; 1189 1190 /* Account for pipe specific data like PIPE*STAT */ 1191 error = kmalloc(sizeof(*error), DRM_I915_GEM, M_NOWAIT | M_ZERO); 1192 if (!error) { 1193 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1194 return; 1195 } 1196 1197 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", 1198 dev->primary->index); 1199 1200 kref_init(&error->ref); 1201 error->eir = I915_READ(EIR); 1202 error->pgtbl_er = I915_READ(PGTBL_ER); 1203 error->ccid = I915_READ(CCID); 1204 1205 if (HAS_PCH_SPLIT(dev)) 1206 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 1207 else if (IS_VALLEYVIEW(dev)) 1208 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 1209 else if (IS_GEN2(dev)) 1210 error->ier = I915_READ16(IER); 1211 else 1212 error->ier = I915_READ(IER); 1213 1214 if (INTEL_INFO(dev)->gen >= 6) 1215 error->derrmr = I915_READ(DERRMR); 1216 1217 if (IS_VALLEYVIEW(dev)) 1218 error->forcewake = I915_READ(FORCEWAKE_VLV); 1219 else if (INTEL_INFO(dev)->gen >= 7) 1220 error->forcewake = I915_READ(FORCEWAKE_MT); 1221 else if (INTEL_INFO(dev)->gen == 6) 1222 error->forcewake = I915_READ(FORCEWAKE); 1223 1224 for_each_pipe(pipe) 1225 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 1226 1227 if (INTEL_INFO(dev)->gen >= 6) { 1228 error->error = I915_READ(ERROR_GEN6); 1229 error->done_reg = I915_READ(DONE_REG); 1230 } 1231 1232 if (INTEL_INFO(dev)->gen == 7) 1233 error->err_int = I915_READ(GEN7_ERR_INT); 1234 1235 i915_get_extra_instdone(dev, error->extra_instdone); 1236 1237 i915_gem_record_fences(dev, error); 1238 i915_gem_record_rings(dev, error); 1239 1240 /* Record buffers on the active and pinned lists. */ 1241 error->active_bo = NULL; 1242 error->pinned_bo = NULL; 1243 1244 i = 0; 1245 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 1246 i++; 1247 error->active_bo_count = i; 1248 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) 1249 if (obj->pin_count) 1250 i++; 1251 error->pinned_bo_count = i - error->active_bo_count; 1252 1253 error->active_bo = NULL; 1254 error->pinned_bo = NULL; 1255 if (i) { 1256 error->active_bo = kmalloc(sizeof(*error->active_bo)*i, 1257 GFP_ATOMIC); 1258 if (error->active_bo) 1259 error->pinned_bo = 1260 error->active_bo + error->active_bo_count; 1261 } 1262 1263 if (error->active_bo) 1264 error->active_bo_count = 1265 capture_active_bo(error->active_bo, 1266 error->active_bo_count, 1267 &dev_priv->mm.active_list); 1268 1269 if (error->pinned_bo) 1270 error->pinned_bo_count = 1271 capture_pinned_bo(error->pinned_bo, 1272 error->pinned_bo_count, 1273 &dev_priv->mm.bound_list); 1274 1275 do_gettimeofday(&error->time); 1276 1277 error->overlay = intel_overlay_capture_error_state(dev); 1278 error->display = intel_display_capture_error_state(dev); 1279 1280 spin_lock_irqsave(&dev_priv->error_lock, flags); 1281 if (dev_priv->first_error == NULL) { 1282 dev_priv->first_error = error; 1283 error = NULL; 1284 } 1285 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1286 1287 if (error) 1288 i915_error_state_free(&error->ref); 1289 } 1290 1291 void i915_destroy_error_state(struct drm_device *dev) 1292 { 1293 struct drm_i915_private *dev_priv = dev->dev_private; 1294 struct drm_i915_error_state *error; 1295 1296 lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE); 1297 error = dev_priv->first_error; 1298 dev_priv->first_error = NULL; 1299 lockmgr(&dev_priv->error_lock, LK_RELEASE); 1300 1301 if (error) 1302 i915_error_state_free(dev, error); 1303 } 1304 #else 1305 #define i915_capture_error_state(x) 1306 #endif 1307 1308 static void i915_report_and_clear_eir(struct drm_device *dev) 1309 { 1310 struct drm_i915_private *dev_priv = dev->dev_private; 1311 uint32_t instdone[I915_NUM_INSTDONE_REG]; 1312 u32 eir = I915_READ(EIR); 1313 int pipe, i; 1314 1315 if (!eir) 1316 return; 1317 1318 pr_err("render error detected, EIR: 0x%08x\n", eir); 1319 1320 i915_get_extra_instdone(dev, instdone); 1321 1322 if (IS_G4X(dev)) { 1323 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 1324 u32 ipeir = I915_READ(IPEIR_I965); 1325 1326 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 1327 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 1328 for (i = 0; i < ARRAY_SIZE(instdone); i++) 1329 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 1330 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 1331 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 1332 I915_WRITE(IPEIR_I965, ipeir); 1333 POSTING_READ(IPEIR_I965); 1334 } 1335 if (eir & GM45_ERROR_PAGE_TABLE) { 1336 u32 pgtbl_err = I915_READ(PGTBL_ER); 1337 pr_err("page table error\n"); 1338 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 1339 I915_WRITE(PGTBL_ER, pgtbl_err); 1340 POSTING_READ(PGTBL_ER); 1341 } 1342 } 1343 1344 if (!IS_GEN2(dev)) { 1345 if (eir & I915_ERROR_PAGE_TABLE) { 1346 u32 pgtbl_err = I915_READ(PGTBL_ER); 1347 pr_err("page table error\n"); 1348 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 1349 I915_WRITE(PGTBL_ER, pgtbl_err); 1350 POSTING_READ(PGTBL_ER); 1351 } 1352 } 1353 1354 if (eir & I915_ERROR_MEMORY_REFRESH) { 1355 pr_err("memory refresh error:\n"); 1356 for_each_pipe(pipe) 1357 pr_err("pipe %c stat: 0x%08x\n", 1358 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 1359 /* pipestat has already been acked */ 1360 } 1361 if (eir & I915_ERROR_INSTRUCTION) { 1362 pr_err("instruction error\n"); 1363 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); 1364 for (i = 0; i < ARRAY_SIZE(instdone); i++) 1365 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 1366 if (INTEL_INFO(dev)->gen < 4) { 1367 u32 ipeir = I915_READ(IPEIR); 1368 1369 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); 1370 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); 1371 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); 1372 I915_WRITE(IPEIR, ipeir); 1373 POSTING_READ(IPEIR); 1374 } else { 1375 u32 ipeir = I915_READ(IPEIR_I965); 1376 1377 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 1378 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 1379 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 1380 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 1381 I915_WRITE(IPEIR_I965, ipeir); 1382 POSTING_READ(IPEIR_I965); 1383 } 1384 } 1385 1386 I915_WRITE(EIR, eir); 1387 POSTING_READ(EIR); 1388 eir = I915_READ(EIR); 1389 if (eir) { 1390 /* 1391 * some errors might have become stuck, 1392 * mask them. 1393 */ 1394 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 1395 I915_WRITE(EMR, I915_READ(EMR) | eir); 1396 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 1397 } 1398 } 1399 1400 /** 1401 * i915_handle_error - handle an error interrupt 1402 * @dev: drm device 1403 * 1404 * Do some basic checking of regsiter state at error interrupt time and 1405 * dump it to the syslog. Also call i915_capture_error_state() to make 1406 * sure we get a record and make it available in debugfs. Fire a uevent 1407 * so userspace knows something bad happened (should trigger collection 1408 * of a ring dump etc.). 1409 */ 1410 void i915_handle_error(struct drm_device *dev, bool wedged) 1411 { 1412 struct drm_i915_private *dev_priv = dev->dev_private; 1413 struct intel_ring_buffer *ring; 1414 int i; 1415 1416 i915_capture_error_state(dev); 1417 i915_report_and_clear_eir(dev); 1418 1419 if (wedged) { 1420 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE); 1421 dev_priv->error_completion = 0; 1422 atomic_set(&dev_priv->mm.wedged, 1); 1423 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE); 1424 1425 /* 1426 * Wakeup waiting processes so they don't hang 1427 */ 1428 for_each_ring(ring, dev_priv, i) 1429 wake_up_all(&ring->irq_queue); 1430 } 1431 1432 queue_work(dev_priv->wq, &dev_priv->error_work); 1433 } 1434 1435 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 1436 { 1437 drm_i915_private_t *dev_priv = dev->dev_private; 1438 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1440 struct drm_i915_gem_object *obj; 1441 struct intel_unpin_work *work; 1442 bool stall_detected; 1443 1444 /* Ignore early vblank irqs */ 1445 if (intel_crtc == NULL) 1446 return; 1447 1448 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 1449 work = intel_crtc->unpin_work; 1450 1451 if (work == NULL || 1452 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || 1453 !work->enable_stall_check) { 1454 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 1455 lockmgr(&dev->event_lock, LK_RELEASE); 1456 return; 1457 } 1458 1459 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1460 obj = work->pending_flip_obj; 1461 if (INTEL_INFO(dev)->gen >= 4) { 1462 int dspsurf = DSPSURF(intel_crtc->plane); 1463 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == 1464 obj->gtt_offset; 1465 } else { 1466 int dspaddr = DSPADDR(intel_crtc->plane); 1467 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1468 crtc->y * crtc->fb->pitches[0] + 1469 crtc->x * crtc->fb->bits_per_pixel/8); 1470 } 1471 1472 lockmgr(&dev->event_lock, LK_RELEASE); 1473 1474 if (stall_detected) { 1475 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 1476 intel_prepare_page_flip(dev, intel_crtc->plane); 1477 } 1478 } 1479 1480 /* Called from drm generic code, passed 'crtc' which 1481 * we use as a pipe index 1482 */ 1483 static int i915_enable_vblank(struct drm_device *dev, int pipe) 1484 { 1485 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1486 1487 if (!i915_pipe_enabled(dev, pipe)) 1488 return -EINVAL; 1489 1490 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1491 if (INTEL_INFO(dev)->gen >= 4) 1492 i915_enable_pipestat(dev_priv, pipe, 1493 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1494 else 1495 i915_enable_pipestat(dev_priv, pipe, 1496 PIPE_VBLANK_INTERRUPT_ENABLE); 1497 1498 /* maintain vblank delivery even in deep C-states */ 1499 if (dev_priv->info->gen == 3) 1500 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); 1501 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1502 1503 return 0; 1504 } 1505 1506 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1507 { 1508 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1509 1510 if (!i915_pipe_enabled(dev, pipe)) 1511 return -EINVAL; 1512 1513 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1514 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1515 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1516 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1517 1518 return 0; 1519 } 1520 1521 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1522 { 1523 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1524 1525 if (!i915_pipe_enabled(dev, pipe)) 1526 return -EINVAL; 1527 1528 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1529 ironlake_enable_display_irq(dev_priv, 1530 DE_PIPEA_VBLANK_IVB << (5 * pipe)); 1531 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1532 1533 return 0; 1534 } 1535 1536 static int valleyview_enable_vblank(struct drm_device *dev, int pipe) 1537 { 1538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1539 u32 imr; 1540 1541 if (!i915_pipe_enabled(dev, pipe)) 1542 return -EINVAL; 1543 1544 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1545 imr = I915_READ(VLV_IMR); 1546 if (pipe == 0) 1547 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 1548 else 1549 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1550 I915_WRITE(VLV_IMR, imr); 1551 i915_enable_pipestat(dev_priv, pipe, 1552 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1553 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1554 1555 return 0; 1556 } 1557 1558 /* Called from drm generic code, passed 'crtc' which 1559 * we use as a pipe index 1560 */ 1561 static void i915_disable_vblank(struct drm_device *dev, int pipe) 1562 { 1563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1564 1565 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1566 if (dev_priv->info->gen == 3) 1567 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); 1568 1569 i915_disable_pipestat(dev_priv, pipe, 1570 PIPE_VBLANK_INTERRUPT_ENABLE | 1571 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1572 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1573 } 1574 1575 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1576 { 1577 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1578 1579 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1580 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1581 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1582 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1583 } 1584 1585 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1586 { 1587 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1588 1589 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1590 ironlake_disable_display_irq(dev_priv, 1591 DE_PIPEA_VBLANK_IVB << (pipe * 5)); 1592 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1593 } 1594 1595 static void valleyview_disable_vblank(struct drm_device *dev, int pipe) 1596 { 1597 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1598 u32 imr; 1599 1600 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1601 i915_disable_pipestat(dev_priv, pipe, 1602 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1603 imr = I915_READ(VLV_IMR); 1604 if (pipe == 0) 1605 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 1606 else 1607 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1608 I915_WRITE(VLV_IMR, imr); 1609 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1610 } 1611 1612 static u32 1613 ring_last_seqno(struct intel_ring_buffer *ring) 1614 { 1615 return list_entry(ring->request_list.prev, 1616 struct drm_i915_gem_request, list)->seqno; 1617 } 1618 1619 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) 1620 { 1621 if (list_empty(&ring->request_list) || 1622 i915_seqno_passed(ring->get_seqno(ring, false), 1623 ring_last_seqno(ring))) { 1624 /* Issue a wake-up to catch stuck h/w. */ 1625 #if 0 /* XXX From OpenBSD */ 1626 if (waitqueue_active(&ring->irq_queue)) { 1627 DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 1628 ring->name); 1629 wake_up_all(&ring->irq_queue); 1630 *err = true; 1631 } 1632 #else 1633 wake_up_all(&ring->irq_queue); 1634 #endif 1635 return true; 1636 } 1637 return false; 1638 } 1639 1640 static bool kick_ring(struct intel_ring_buffer *ring) 1641 { 1642 struct drm_device *dev = ring->dev; 1643 struct drm_i915_private *dev_priv = dev->dev_private; 1644 u32 tmp = I915_READ_CTL(ring); 1645 if (tmp & RING_WAIT) { 1646 DRM_ERROR("Kicking stuck wait on %s\n", 1647 ring->name); 1648 I915_WRITE_CTL(ring, tmp); 1649 return true; 1650 } 1651 return false; 1652 } 1653 1654 static bool i915_hangcheck_hung(struct drm_device *dev) 1655 { 1656 drm_i915_private_t *dev_priv = dev->dev_private; 1657 1658 if (dev_priv->hangcheck_count++ > 1) { 1659 bool hung = true; 1660 1661 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 1662 i915_handle_error(dev, true); 1663 1664 if (!IS_GEN2(dev)) { 1665 struct intel_ring_buffer *ring; 1666 int i; 1667 1668 /* Is the chip hanging on a WAIT_FOR_EVENT? 1669 * If so we can simply poke the RB_WAIT bit 1670 * and break the hang. This should work on 1671 * all but the second generation chipsets. 1672 */ 1673 for_each_ring(ring, dev_priv, i) 1674 hung &= !kick_ring(ring); 1675 } 1676 1677 return hung; 1678 } 1679 1680 return false; 1681 } 1682 1683 /** 1684 * This is called when the chip hasn't reported back with completed 1685 * batchbuffers in a long time. The first time this is called we simply record 1686 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1687 * again, we assume the chip is wedged and try to fix it. 1688 */ 1689 void i915_hangcheck_elapsed(unsigned long data) 1690 { 1691 struct drm_device *dev = (struct drm_device *)data; 1692 drm_i915_private_t *dev_priv = dev->dev_private; 1693 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG]; 1694 struct intel_ring_buffer *ring; 1695 bool err = false, idle; 1696 int i; 1697 1698 if (!i915_enable_hangcheck) 1699 return; 1700 1701 memset(acthd, 0, sizeof(acthd)); 1702 idle = true; 1703 for_each_ring(ring, dev_priv, i) { 1704 idle &= i915_hangcheck_ring_idle(ring, &err); 1705 acthd[i] = intel_ring_get_active_head(ring); 1706 } 1707 1708 /* If all work is done then ACTHD clearly hasn't advanced. */ 1709 if (idle) { 1710 if (err) { 1711 if (i915_hangcheck_hung(dev)) 1712 return; 1713 1714 goto repeat; 1715 } 1716 1717 dev_priv->hangcheck_count = 0; 1718 return; 1719 } 1720 1721 i915_get_extra_instdone(dev, instdone); 1722 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 && 1723 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) { 1724 if (i915_hangcheck_hung(dev)) 1725 return; 1726 } else { 1727 dev_priv->hangcheck_count = 0; 1728 1729 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd)); 1730 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone)); 1731 } 1732 1733 repeat: 1734 /* Reset timer case chip hangs without another request being added */ 1735 mod_timer(&dev_priv->hangcheck_timer, 1736 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 1737 } 1738 1739 /* drm_dma.h hooks 1740 */ 1741 static void ironlake_irq_preinstall(struct drm_device *dev) 1742 { 1743 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1744 1745 atomic_set(&dev_priv->irq_received, 0); 1746 1747 I915_WRITE(HWSTAM, 0xeffe); 1748 1749 /* XXX hotplug from PCH */ 1750 1751 I915_WRITE(DEIMR, 0xffffffff); 1752 I915_WRITE(DEIER, 0x0); 1753 POSTING_READ(DEIER); 1754 1755 /* and GT */ 1756 I915_WRITE(GTIMR, 0xffffffff); 1757 I915_WRITE(GTIER, 0x0); 1758 POSTING_READ(GTIER); 1759 1760 /* south display irq */ 1761 I915_WRITE(SDEIMR, 0xffffffff); 1762 I915_WRITE(SDEIER, 0x0); 1763 POSTING_READ(SDEIER); 1764 } 1765 1766 static void valleyview_irq_preinstall(struct drm_device *dev) 1767 { 1768 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1769 int pipe; 1770 1771 atomic_set(&dev_priv->irq_received, 0); 1772 1773 /* VLV magic */ 1774 I915_WRITE(VLV_IMR, 0); 1775 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); 1776 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); 1777 I915_WRITE(RING_IMR(BLT_RING_BASE), 0); 1778 1779 /* and GT */ 1780 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1781 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1782 I915_WRITE(GTIMR, 0xffffffff); 1783 I915_WRITE(GTIER, 0x0); 1784 POSTING_READ(GTIER); 1785 1786 I915_WRITE(DPINVGTT, 0xff); 1787 1788 I915_WRITE(PORT_HOTPLUG_EN, 0); 1789 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1790 for_each_pipe(pipe) 1791 I915_WRITE(PIPESTAT(pipe), 0xffff); 1792 I915_WRITE(VLV_IIR, 0xffffffff); 1793 I915_WRITE(VLV_IMR, 0xffffffff); 1794 I915_WRITE(VLV_IER, 0x0); 1795 POSTING_READ(VLV_IER); 1796 } 1797 1798 /* 1799 * Enable digital hotplug on the PCH, and configure the DP short pulse 1800 * duration to 2ms (which is the minimum in the Display Port spec) 1801 * 1802 * This register is the same on all known PCH chips. 1803 */ 1804 1805 static void ironlake_enable_pch_hotplug(struct drm_device *dev) 1806 { 1807 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1808 u32 hotplug; 1809 1810 hotplug = I915_READ(PCH_PORT_HOTPLUG); 1811 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 1812 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 1813 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 1814 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 1815 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 1816 } 1817 1818 static int ironlake_irq_postinstall(struct drm_device *dev) 1819 { 1820 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1821 /* enable kind of interrupts always enabled */ 1822 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1823 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1824 u32 render_irqs; 1825 u32 hotplug_mask; 1826 1827 dev_priv->irq_mask = ~display_mask; 1828 1829 /* should always can generate irq */ 1830 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1831 I915_WRITE(DEIMR, dev_priv->irq_mask); 1832 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); 1833 POSTING_READ(DEIER); 1834 1835 dev_priv->gt_irq_mask = ~0; 1836 1837 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1838 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1839 1840 if (IS_GEN6(dev)) 1841 render_irqs = 1842 GT_USER_INTERRUPT | 1843 GEN6_BSD_USER_INTERRUPT | 1844 GEN6_BLITTER_USER_INTERRUPT; 1845 else 1846 render_irqs = 1847 GT_USER_INTERRUPT | 1848 GT_PIPE_NOTIFY | 1849 GT_BSD_USER_INTERRUPT; 1850 I915_WRITE(GTIER, render_irqs); 1851 POSTING_READ(GTIER); 1852 1853 if (HAS_PCH_CPT(dev)) { 1854 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1855 SDE_PORTB_HOTPLUG_CPT | 1856 SDE_PORTC_HOTPLUG_CPT | 1857 SDE_PORTD_HOTPLUG_CPT); 1858 } else { 1859 hotplug_mask = (SDE_CRT_HOTPLUG | 1860 SDE_PORTB_HOTPLUG | 1861 SDE_PORTC_HOTPLUG | 1862 SDE_PORTD_HOTPLUG | 1863 SDE_AUX_MASK); 1864 } 1865 1866 dev_priv->pch_irq_mask = ~hotplug_mask; 1867 1868 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1869 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1870 I915_WRITE(SDEIER, hotplug_mask); 1871 POSTING_READ(SDEIER); 1872 1873 ironlake_enable_pch_hotplug(dev); 1874 1875 if (IS_IRONLAKE_M(dev)) { 1876 /* Clear & enable PCU event interrupts */ 1877 I915_WRITE(DEIIR, DE_PCU_EVENT); 1878 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); 1879 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 1880 } 1881 1882 return 0; 1883 } 1884 1885 static int ivybridge_irq_postinstall(struct drm_device *dev) 1886 { 1887 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1888 /* enable kind of interrupts always enabled */ 1889 u32 display_mask = 1890 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | 1891 DE_PLANEC_FLIP_DONE_IVB | 1892 DE_PLANEB_FLIP_DONE_IVB | 1893 DE_PLANEA_FLIP_DONE_IVB; 1894 u32 render_irqs; 1895 u32 hotplug_mask; 1896 1897 dev_priv->irq_mask = ~display_mask; 1898 1899 /* should always can generate irq */ 1900 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1901 I915_WRITE(DEIMR, dev_priv->irq_mask); 1902 I915_WRITE(DEIER, 1903 display_mask | 1904 DE_PIPEC_VBLANK_IVB | 1905 DE_PIPEB_VBLANK_IVB | 1906 DE_PIPEA_VBLANK_IVB); 1907 POSTING_READ(DEIER); 1908 1909 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 1910 1911 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1912 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1913 1914 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | 1915 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 1916 I915_WRITE(GTIER, render_irqs); 1917 POSTING_READ(GTIER); 1918 1919 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1920 SDE_PORTB_HOTPLUG_CPT | 1921 SDE_PORTC_HOTPLUG_CPT | 1922 SDE_PORTD_HOTPLUG_CPT); 1923 dev_priv->pch_irq_mask = ~hotplug_mask; 1924 1925 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1926 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1927 I915_WRITE(SDEIER, hotplug_mask); 1928 POSTING_READ(SDEIER); 1929 1930 ironlake_enable_pch_hotplug(dev); 1931 1932 return 0; 1933 } 1934 1935 static int valleyview_irq_postinstall(struct drm_device *dev) 1936 { 1937 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1938 u32 enable_mask; 1939 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1940 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; 1941 u32 render_irqs; 1942 u16 msid; 1943 1944 enable_mask = I915_DISPLAY_PORT_INTERRUPT; 1945 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1946 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 1947 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1948 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1949 1950 /* 1951 *Leave vblank interrupts masked initially. enable/disable will 1952 * toggle them based on usage. 1953 */ 1954 dev_priv->irq_mask = (~enable_mask) | 1955 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 1956 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1957 1958 dev_priv->pipestat[0] = 0; 1959 dev_priv->pipestat[1] = 0; 1960 1961 /* Hack for broken MSIs on VLV */ 1962 pci_write_config(dev_priv->dev->dev, 0x94, 0xfee00000, 4); 1963 msid = pci_read_config(dev->dev, 0x98, 2); 1964 msid &= 0xff; /* mask out delivery bits */ 1965 msid |= (1<<14); 1966 pci_write_config(dev_priv->dev->dev, 0x98, msid, 4); 1967 1968 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 1969 I915_WRITE(VLV_IER, enable_mask); 1970 I915_WRITE(VLV_IIR, 0xffffffff); 1971 I915_WRITE(PIPESTAT(0), 0xffff); 1972 I915_WRITE(PIPESTAT(1), 0xffff); 1973 POSTING_READ(VLV_IER); 1974 1975 i915_enable_pipestat(dev_priv, 0, pipestat_enable); 1976 i915_enable_pipestat(dev_priv, 1, pipestat_enable); 1977 1978 I915_WRITE(VLV_IIR, 0xffffffff); 1979 I915_WRITE(VLV_IIR, 0xffffffff); 1980 1981 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1982 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1983 1984 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | 1985 GEN6_BLITTER_USER_INTERRUPT; 1986 I915_WRITE(GTIER, render_irqs); 1987 POSTING_READ(GTIER); 1988 1989 /* ack & enable invalid PTE error interrupts */ 1990 #if 0 /* FIXME: add support to irq handler for checking these bits */ 1991 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); 1992 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); 1993 #endif 1994 1995 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 1996 /* Note HDMI and DP share bits */ 1997 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 1998 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 1999 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2000 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2001 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2002 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2003 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) 2004 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2005 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) 2006 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2007 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2008 hotplug_en |= CRT_HOTPLUG_INT_EN; 2009 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2010 } 2011 2012 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2013 2014 return 0; 2015 } 2016 2017 static void valleyview_irq_uninstall(struct drm_device *dev) 2018 { 2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2020 int pipe; 2021 2022 if (!dev_priv) 2023 return; 2024 2025 for_each_pipe(pipe) 2026 I915_WRITE(PIPESTAT(pipe), 0xffff); 2027 2028 I915_WRITE(HWSTAM, 0xffffffff); 2029 I915_WRITE(PORT_HOTPLUG_EN, 0); 2030 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2031 for_each_pipe(pipe) 2032 I915_WRITE(PIPESTAT(pipe), 0xffff); 2033 I915_WRITE(VLV_IIR, 0xffffffff); 2034 I915_WRITE(VLV_IMR, 0xffffffff); 2035 I915_WRITE(VLV_IER, 0x0); 2036 POSTING_READ(VLV_IER); 2037 } 2038 2039 static void ironlake_irq_uninstall(struct drm_device *dev) 2040 { 2041 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2042 2043 if (!dev_priv) 2044 return; 2045 2046 I915_WRITE(HWSTAM, 0xffffffff); 2047 2048 I915_WRITE(DEIMR, 0xffffffff); 2049 I915_WRITE(DEIER, 0x0); 2050 I915_WRITE(DEIIR, I915_READ(DEIIR)); 2051 2052 I915_WRITE(GTIMR, 0xffffffff); 2053 I915_WRITE(GTIER, 0x0); 2054 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2055 2056 I915_WRITE(SDEIMR, 0xffffffff); 2057 I915_WRITE(SDEIER, 0x0); 2058 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2059 } 2060 2061 static void i8xx_irq_preinstall(struct drm_device * dev) 2062 { 2063 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2064 int pipe; 2065 2066 atomic_set(&dev_priv->irq_received, 0); 2067 2068 for_each_pipe(pipe) 2069 I915_WRITE(PIPESTAT(pipe), 0); 2070 I915_WRITE16(IMR, 0xffff); 2071 I915_WRITE16(IER, 0x0); 2072 POSTING_READ16(IER); 2073 } 2074 2075 static int i8xx_irq_postinstall(struct drm_device *dev) 2076 { 2077 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2078 2079 dev_priv->pipestat[0] = 0; 2080 dev_priv->pipestat[1] = 0; 2081 2082 I915_WRITE16(EMR, 2083 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2084 2085 /* Unmask the interrupts that we always want on. */ 2086 dev_priv->irq_mask = 2087 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2088 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2089 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2090 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2091 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2092 I915_WRITE16(IMR, dev_priv->irq_mask); 2093 2094 I915_WRITE16(IER, 2095 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2096 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2097 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 2098 I915_USER_INTERRUPT); 2099 POSTING_READ16(IER); 2100 2101 return 0; 2102 } 2103 2104 static irqreturn_t i8xx_irq_handler(void *arg) 2105 { 2106 struct drm_device *dev = (struct drm_device *) arg; 2107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2108 u16 iir, new_iir; 2109 u32 pipe_stats[2]; 2110 int irq_received; 2111 int pipe; 2112 u16 flip_mask = 2113 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2114 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2115 2116 atomic_inc(&dev_priv->irq_received); 2117 2118 iir = I915_READ16(IIR); 2119 if (iir == 0) 2120 return; 2121 2122 while (iir & ~flip_mask) { 2123 /* Can't rely on pipestat interrupt bit in iir as it might 2124 * have been cleared after the pipestat interrupt was received. 2125 * It doesn't set the bit in iir again, but it still produces 2126 * interrupts (for non-MSI). 2127 */ 2128 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2129 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2130 i915_handle_error(dev, false); 2131 2132 for_each_pipe(pipe) { 2133 int reg = PIPESTAT(pipe); 2134 pipe_stats[pipe] = I915_READ(reg); 2135 2136 /* 2137 * Clear the PIPE*STAT regs before the IIR 2138 */ 2139 if (pipe_stats[pipe] & 0x8000ffff) { 2140 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2141 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2142 pipe_name(pipe)); 2143 I915_WRITE(reg, pipe_stats[pipe]); 2144 irq_received = 1; 2145 } 2146 } 2147 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2148 2149 I915_WRITE16(IIR, iir & ~flip_mask); 2150 new_iir = I915_READ16(IIR); /* Flush posted writes */ 2151 2152 i915_update_dri1_breadcrumb(dev); 2153 2154 if (iir & I915_USER_INTERRUPT) 2155 notify_ring(dev, &dev_priv->ring[RCS]); 2156 2157 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && 2158 drm_handle_vblank(dev, 0)) { 2159 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 2160 intel_prepare_page_flip(dev, 0); 2161 intel_finish_page_flip(dev, 0); 2162 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; 2163 } 2164 } 2165 2166 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && 2167 drm_handle_vblank(dev, 1)) { 2168 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 2169 intel_prepare_page_flip(dev, 1); 2170 intel_finish_page_flip(dev, 1); 2171 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2172 } 2173 } 2174 2175 iir = new_iir; 2176 } 2177 2178 return; 2179 } 2180 2181 static void i8xx_irq_uninstall(struct drm_device * dev) 2182 { 2183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2184 int pipe; 2185 2186 for_each_pipe(pipe) { 2187 /* Clear enable bits; then clear status bits */ 2188 I915_WRITE(PIPESTAT(pipe), 0); 2189 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 2190 } 2191 I915_WRITE16(IMR, 0xffff); 2192 I915_WRITE16(IER, 0x0); 2193 I915_WRITE16(IIR, I915_READ16(IIR)); 2194 } 2195 2196 static void i915_irq_preinstall(struct drm_device * dev) 2197 { 2198 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2199 int pipe; 2200 2201 atomic_set(&dev_priv->irq_received, 0); 2202 2203 if (I915_HAS_HOTPLUG(dev)) { 2204 I915_WRITE(PORT_HOTPLUG_EN, 0); 2205 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2206 } 2207 2208 I915_WRITE16(HWSTAM, 0xeffe); 2209 for_each_pipe(pipe) 2210 I915_WRITE(PIPESTAT(pipe), 0); 2211 I915_WRITE(IMR, 0xffffffff); 2212 I915_WRITE(IER, 0x0); 2213 POSTING_READ(IER); 2214 } 2215 2216 static int i915_irq_postinstall(struct drm_device *dev) 2217 { 2218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2219 u32 enable_mask; 2220 2221 dev_priv->pipestat[0] = 0; 2222 dev_priv->pipestat[1] = 0; 2223 2224 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2225 2226 /* Unmask the interrupts that we always want on. */ 2227 dev_priv->irq_mask = 2228 ~(I915_ASLE_INTERRUPT | 2229 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2230 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2231 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2232 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2233 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2234 2235 enable_mask = 2236 I915_ASLE_INTERRUPT | 2237 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2238 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2239 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 2240 I915_USER_INTERRUPT; 2241 2242 if (I915_HAS_HOTPLUG(dev)) { 2243 /* Enable in IER... */ 2244 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 2245 /* and unmask in IMR */ 2246 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 2247 } 2248 2249 I915_WRITE(IMR, dev_priv->irq_mask); 2250 I915_WRITE(IER, enable_mask); 2251 POSTING_READ(IER); 2252 2253 if (I915_HAS_HOTPLUG(dev)) { 2254 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 2255 2256 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2257 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2258 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2259 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2260 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2261 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2262 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) 2263 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2264 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) 2265 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2266 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2267 hotplug_en |= CRT_HOTPLUG_INT_EN; 2268 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2269 } 2270 2271 /* Ignore TV since it's buggy */ 2272 2273 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2274 } 2275 2276 intel_opregion_enable_asle(dev); 2277 2278 return 0; 2279 } 2280 2281 static irqreturn_t i915_irq_handler(void *arg) 2282 { 2283 struct drm_device *dev = (struct drm_device *) arg; 2284 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2285 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 2286 u32 flip_mask = 2287 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2288 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2289 u32 flip[2] = { 2290 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT, 2291 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT 2292 }; 2293 int pipe; 2294 2295 atomic_inc(&dev_priv->irq_received); 2296 2297 iir = I915_READ(IIR); 2298 do { 2299 bool irq_received = (iir & ~flip_mask) != 0; 2300 bool blc_event = false; 2301 2302 /* Can't rely on pipestat interrupt bit in iir as it might 2303 * have been cleared after the pipestat interrupt was received. 2304 * It doesn't set the bit in iir again, but it still produces 2305 * interrupts (for non-MSI). 2306 */ 2307 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2308 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2309 i915_handle_error(dev, false); 2310 2311 for_each_pipe(pipe) { 2312 int reg = PIPESTAT(pipe); 2313 pipe_stats[pipe] = I915_READ(reg); 2314 2315 /* Clear the PIPE*STAT regs before the IIR */ 2316 if (pipe_stats[pipe] & 0x8000ffff) { 2317 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2318 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2319 pipe_name(pipe)); 2320 I915_WRITE(reg, pipe_stats[pipe]); 2321 irq_received = true; 2322 } 2323 } 2324 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2325 2326 if (!irq_received) 2327 break; 2328 2329 /* Consume port. Then clear IIR or we'll miss events */ 2330 if ((I915_HAS_HOTPLUG(dev)) && 2331 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 2332 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 2333 2334 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2335 hotplug_status); 2336 if (hotplug_status & dev_priv->hotplug_supported_mask) 2337 queue_work(dev_priv->wq, 2338 &dev_priv->hotplug_work); 2339 2340 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 2341 POSTING_READ(PORT_HOTPLUG_STAT); 2342 } 2343 2344 I915_WRITE(IIR, iir & ~flip_mask); 2345 new_iir = I915_READ(IIR); /* Flush posted writes */ 2346 2347 if (iir & I915_USER_INTERRUPT) 2348 notify_ring(dev, &dev_priv->ring[RCS]); 2349 2350 for_each_pipe(pipe) { 2351 int plane = pipe; 2352 if (IS_MOBILE(dev)) 2353 plane = !plane; 2354 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 2355 drm_handle_vblank(dev, pipe)) { 2356 if (iir & flip[plane]) { 2357 intel_prepare_page_flip(dev, plane); 2358 intel_finish_page_flip(dev, pipe); 2359 flip_mask &= ~flip[plane]; 2360 } 2361 } 2362 2363 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 2364 blc_event = true; 2365 } 2366 2367 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 2368 intel_opregion_asle_intr(dev); 2369 2370 /* With MSI, interrupts are only generated when iir 2371 * transitions from zero to nonzero. If another bit got 2372 * set while we were handling the existing iir bits, then 2373 * we would never get another interrupt. 2374 * 2375 * This is fine on non-MSI as well, as if we hit this path 2376 * we avoid exiting the interrupt handler only to generate 2377 * another one. 2378 * 2379 * Note that for MSI this could cause a stray interrupt report 2380 * if an interrupt landed in the time between writing IIR and 2381 * the posting read. This should be rare enough to never 2382 * trigger the 99% of 100,000 interrupts test for disabling 2383 * stray interrupts. 2384 */ 2385 iir = new_iir; 2386 } while (iir & ~flip_mask); 2387 2388 i915_update_dri1_breadcrumb(dev); 2389 } 2390 2391 static void i915_irq_uninstall(struct drm_device * dev) 2392 { 2393 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2394 int pipe; 2395 2396 if (I915_HAS_HOTPLUG(dev)) { 2397 I915_WRITE(PORT_HOTPLUG_EN, 0); 2398 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2399 } 2400 2401 I915_WRITE16(HWSTAM, 0xffff); 2402 for_each_pipe(pipe) { 2403 /* Clear enable bits; then clear status bits */ 2404 I915_WRITE(PIPESTAT(pipe), 0); 2405 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 2406 } 2407 I915_WRITE(IMR, 0xffffffff); 2408 I915_WRITE(IER, 0x0); 2409 2410 I915_WRITE(IIR, I915_READ(IIR)); 2411 } 2412 2413 static void i965_irq_preinstall(struct drm_device * dev) 2414 { 2415 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2416 int pipe; 2417 2418 atomic_set(&dev_priv->irq_received, 0); 2419 2420 I915_WRITE(PORT_HOTPLUG_EN, 0); 2421 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2422 2423 I915_WRITE(HWSTAM, 0xeffe); 2424 for_each_pipe(pipe) 2425 I915_WRITE(PIPESTAT(pipe), 0); 2426 I915_WRITE(IMR, 0xffffffff); 2427 I915_WRITE(IER, 0x0); 2428 POSTING_READ(IER); 2429 } 2430 2431 static int i965_irq_postinstall(struct drm_device *dev) 2432 { 2433 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2434 u32 hotplug_en; 2435 u32 enable_mask; 2436 u32 error_mask; 2437 2438 /* Unmask the interrupts that we always want on. */ 2439 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | 2440 I915_DISPLAY_PORT_INTERRUPT | 2441 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2442 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2443 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2444 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2445 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2446 2447 enable_mask = ~dev_priv->irq_mask; 2448 enable_mask |= I915_USER_INTERRUPT; 2449 2450 if (IS_G4X(dev)) 2451 enable_mask |= I915_BSD_USER_INTERRUPT; 2452 2453 dev_priv->pipestat[0] = 0; 2454 dev_priv->pipestat[1] = 0; 2455 2456 /* 2457 * Enable some error detection, note the instruction error mask 2458 * bit is reserved, so we leave it masked. 2459 */ 2460 if (IS_G4X(dev)) { 2461 error_mask = ~(GM45_ERROR_PAGE_TABLE | 2462 GM45_ERROR_MEM_PRIV | 2463 GM45_ERROR_CP_PRIV | 2464 I915_ERROR_MEMORY_REFRESH); 2465 } else { 2466 error_mask = ~(I915_ERROR_PAGE_TABLE | 2467 I915_ERROR_MEMORY_REFRESH); 2468 } 2469 I915_WRITE(EMR, error_mask); 2470 2471 I915_WRITE(IMR, dev_priv->irq_mask); 2472 I915_WRITE(IER, enable_mask); 2473 POSTING_READ(IER); 2474 2475 /* Note HDMI and DP share hotplug bits */ 2476 hotplug_en = 0; 2477 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2478 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2479 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2480 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2481 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2482 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2483 if (IS_G4X(dev)) { 2484 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) 2485 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2486 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X) 2487 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2488 } else { 2489 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965) 2490 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2491 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965) 2492 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2493 } 2494 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2495 hotplug_en |= CRT_HOTPLUG_INT_EN; 2496 2497 /* Programming the CRT detection parameters tends 2498 to generate a spurious hotplug event about three 2499 seconds later. So just do it once. 2500 */ 2501 if (IS_G4X(dev)) 2502 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 2503 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2504 } 2505 2506 /* Ignore TV since it's buggy */ 2507 2508 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2509 2510 intel_opregion_enable_asle(dev); 2511 2512 return 0; 2513 } 2514 2515 static irqreturn_t i965_irq_handler(void *arg) 2516 { 2517 struct drm_device *dev = (struct drm_device *) arg; 2518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2519 u32 iir, new_iir; 2520 u32 pipe_stats[I915_MAX_PIPES]; 2521 int irq_received; 2522 int pipe; 2523 2524 atomic_inc(&dev_priv->irq_received); 2525 2526 iir = I915_READ(IIR); 2527 2528 for (;;) { 2529 bool blc_event = false; 2530 2531 irq_received = iir != 0; 2532 2533 /* Can't rely on pipestat interrupt bit in iir as it might 2534 * have been cleared after the pipestat interrupt was received. 2535 * It doesn't set the bit in iir again, but it still produces 2536 * interrupts (for non-MSI). 2537 */ 2538 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2539 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2540 i915_handle_error(dev, false); 2541 2542 for_each_pipe(pipe) { 2543 int reg = PIPESTAT(pipe); 2544 pipe_stats[pipe] = I915_READ(reg); 2545 2546 /* 2547 * Clear the PIPE*STAT regs before the IIR 2548 */ 2549 if (pipe_stats[pipe] & 0x8000ffff) { 2550 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2551 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2552 pipe_name(pipe)); 2553 I915_WRITE(reg, pipe_stats[pipe]); 2554 irq_received = 1; 2555 } 2556 } 2557 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2558 2559 if (!irq_received) 2560 break; 2561 2562 /* Consume port. Then clear IIR or we'll miss events */ 2563 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 2564 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 2565 2566 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2567 hotplug_status); 2568 if (hotplug_status & dev_priv->hotplug_supported_mask) 2569 queue_work(dev_priv->wq, 2570 &dev_priv->hotplug_work); 2571 2572 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 2573 I915_READ(PORT_HOTPLUG_STAT); 2574 } 2575 2576 I915_WRITE(IIR, iir); 2577 new_iir = I915_READ(IIR); /* Flush posted writes */ 2578 2579 if (iir & I915_USER_INTERRUPT) 2580 notify_ring(dev, &dev_priv->ring[RCS]); 2581 if (iir & I915_BSD_USER_INTERRUPT) 2582 notify_ring(dev, &dev_priv->ring[VCS]); 2583 2584 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) 2585 intel_prepare_page_flip(dev, 0); 2586 2587 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) 2588 intel_prepare_page_flip(dev, 1); 2589 2590 for_each_pipe(pipe) { 2591 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 2592 drm_handle_vblank(dev, pipe)) { 2593 i915_pageflip_stall_check(dev, pipe); 2594 intel_finish_page_flip(dev, pipe); 2595 } 2596 2597 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 2598 blc_event = true; 2599 } 2600 2601 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 2602 intel_opregion_asle_intr(dev); 2603 2604 /* With MSI, interrupts are only generated when iir 2605 * transitions from zero to nonzero. If another bit got 2606 * set while we were handling the existing iir bits, then 2607 * we would never get another interrupt. 2608 * 2609 * This is fine on non-MSI as well, as if we hit this path 2610 * we avoid exiting the interrupt handler only to generate 2611 * another one. 2612 * 2613 * Note that for MSI this could cause a stray interrupt report 2614 * if an interrupt landed in the time between writing IIR and 2615 * the posting read. This should be rare enough to never 2616 * trigger the 99% of 100,000 interrupts test for disabling 2617 * stray interrupts. 2618 */ 2619 iir = new_iir; 2620 } 2621 2622 i915_update_dri1_breadcrumb(dev); 2623 } 2624 2625 static void i965_irq_uninstall(struct drm_device * dev) 2626 { 2627 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2628 int pipe; 2629 2630 if (!dev_priv) 2631 return; 2632 2633 I915_WRITE(PORT_HOTPLUG_EN, 0); 2634 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2635 2636 I915_WRITE(HWSTAM, 0xffffffff); 2637 for_each_pipe(pipe) 2638 I915_WRITE(PIPESTAT(pipe), 0); 2639 I915_WRITE(IMR, 0xffffffff); 2640 I915_WRITE(IER, 0x0); 2641 2642 for_each_pipe(pipe) 2643 I915_WRITE(PIPESTAT(pipe), 2644 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2645 I915_WRITE(IIR, I915_READ(IIR)); 2646 } 2647 2648 void intel_irq_init(struct drm_device *dev) 2649 { 2650 struct drm_i915_private *dev_priv = dev->dev_private; 2651 2652 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 2653 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 2654 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); 2655 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 2656 2657 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2658 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2659 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 2660 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2661 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2662 } 2663 2664 if (drm_core_check_feature(dev, DRIVER_MODESET)) 2665 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 2666 else 2667 dev->driver->get_vblank_timestamp = NULL; 2668 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 2669 2670 if (IS_VALLEYVIEW(dev)) { 2671 dev->driver->irq_handler = valleyview_irq_handler; 2672 dev->driver->irq_preinstall = valleyview_irq_preinstall; 2673 dev->driver->irq_postinstall = valleyview_irq_postinstall; 2674 dev->driver->irq_uninstall = valleyview_irq_uninstall; 2675 dev->driver->enable_vblank = valleyview_enable_vblank; 2676 dev->driver->disable_vblank = valleyview_disable_vblank; 2677 } else if (IS_IVYBRIDGE(dev)) { 2678 /* Share pre & uninstall handlers with ILK/SNB */ 2679 dev->driver->irq_handler = ivybridge_irq_handler; 2680 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2681 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2682 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2683 dev->driver->enable_vblank = ivybridge_enable_vblank; 2684 dev->driver->disable_vblank = ivybridge_disable_vblank; 2685 } else if (IS_HASWELL(dev)) { 2686 /* Share interrupts handling with IVB */ 2687 dev->driver->irq_handler = ivybridge_irq_handler; 2688 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2689 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2690 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2691 dev->driver->enable_vblank = ivybridge_enable_vblank; 2692 dev->driver->disable_vblank = ivybridge_disable_vblank; 2693 } else if (HAS_PCH_SPLIT(dev)) { 2694 dev->driver->irq_handler = ironlake_irq_handler; 2695 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2696 dev->driver->irq_postinstall = ironlake_irq_postinstall; 2697 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2698 dev->driver->enable_vblank = ironlake_enable_vblank; 2699 dev->driver->disable_vblank = ironlake_disable_vblank; 2700 } else { 2701 if (INTEL_INFO(dev)->gen == 2) { 2702 dev->driver->irq_preinstall = i8xx_irq_preinstall; 2703 dev->driver->irq_postinstall = i8xx_irq_postinstall; 2704 dev->driver->irq_handler = i8xx_irq_handler; 2705 dev->driver->irq_uninstall = i8xx_irq_uninstall; 2706 } else if (INTEL_INFO(dev)->gen == 3) { 2707 dev->driver->irq_preinstall = i915_irq_preinstall; 2708 dev->driver->irq_postinstall = i915_irq_postinstall; 2709 dev->driver->irq_uninstall = i915_irq_uninstall; 2710 dev->driver->irq_handler = i915_irq_handler; 2711 } else { 2712 dev->driver->irq_preinstall = i965_irq_preinstall; 2713 dev->driver->irq_postinstall = i965_irq_postinstall; 2714 dev->driver->irq_uninstall = i965_irq_uninstall; 2715 dev->driver->irq_handler = i965_irq_handler; 2716 } 2717 dev->driver->enable_vblank = i915_enable_vblank; 2718 dev->driver->disable_vblank = i915_disable_vblank; 2719 } 2720 } 2721