1 /* 2 * Autogenerated file, DO NOT EDIT manually! 3 * 4 * Copyright (c) 2015 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 */ 26 27 #include <linux/sysfs.h> 28 29 #include "i915_drv.h" 30 #include "i915_oa_hsw.h" 31 32 enum metric_set_id { 33 METRIC_SET_ID_RENDER_BASIC = 1, 34 METRIC_SET_ID_COMPUTE_BASIC, 35 METRIC_SET_ID_COMPUTE_EXTENDED, 36 METRIC_SET_ID_MEMORY_READS, 37 METRIC_SET_ID_MEMORY_WRITES, 38 METRIC_SET_ID_SAMPLER_BALANCE, 39 }; 40 41 int i915_oa_n_builtin_metric_sets_hsw = 6; 42 43 static const struct i915_oa_reg b_counter_config_render_basic[] = { 44 { _MMIO(0x2724), 0x00800000 }, 45 { _MMIO(0x2720), 0x00000000 }, 46 { _MMIO(0x2714), 0x00800000 }, 47 { _MMIO(0x2710), 0x00000000 }, 48 }; 49 50 static const struct i915_oa_reg mux_config_render_basic[] = { 51 { _MMIO(0x253a4), 0x01600000 }, 52 { _MMIO(0x25440), 0x00100000 }, 53 { _MMIO(0x25128), 0x00000000 }, 54 { _MMIO(0x2691c), 0x00000800 }, 55 { _MMIO(0x26aa0), 0x01500000 }, 56 { _MMIO(0x26b9c), 0x00006000 }, 57 { _MMIO(0x2791c), 0x00000800 }, 58 { _MMIO(0x27aa0), 0x01500000 }, 59 { _MMIO(0x27b9c), 0x00006000 }, 60 { _MMIO(0x2641c), 0x00000400 }, 61 { _MMIO(0x25380), 0x00000010 }, 62 { _MMIO(0x2538c), 0x00000000 }, 63 { _MMIO(0x25384), 0x0800aaaa }, 64 { _MMIO(0x25400), 0x00000004 }, 65 { _MMIO(0x2540c), 0x06029000 }, 66 { _MMIO(0x25410), 0x00000002 }, 67 { _MMIO(0x25404), 0x5c30ffff }, 68 { _MMIO(0x25100), 0x00000016 }, 69 { _MMIO(0x25110), 0x00000400 }, 70 { _MMIO(0x25104), 0x00000000 }, 71 { _MMIO(0x26804), 0x00001211 }, 72 { _MMIO(0x26884), 0x00000100 }, 73 { _MMIO(0x26900), 0x00000002 }, 74 { _MMIO(0x26908), 0x00700000 }, 75 { _MMIO(0x26904), 0x00000000 }, 76 { _MMIO(0x26984), 0x00001022 }, 77 { _MMIO(0x26a04), 0x00000011 }, 78 { _MMIO(0x26a80), 0x00000006 }, 79 { _MMIO(0x26a88), 0x00000c02 }, 80 { _MMIO(0x26a84), 0x00000000 }, 81 { _MMIO(0x26b04), 0x00001000 }, 82 { _MMIO(0x26b80), 0x00000002 }, 83 { _MMIO(0x26b8c), 0x00000007 }, 84 { _MMIO(0x26b84), 0x00000000 }, 85 { _MMIO(0x27804), 0x00004844 }, 86 { _MMIO(0x27884), 0x00000400 }, 87 { _MMIO(0x27900), 0x00000002 }, 88 { _MMIO(0x27908), 0x0e000000 }, 89 { _MMIO(0x27904), 0x00000000 }, 90 { _MMIO(0x27984), 0x00004088 }, 91 { _MMIO(0x27a04), 0x00000044 }, 92 { _MMIO(0x27a80), 0x00000006 }, 93 { _MMIO(0x27a88), 0x00018040 }, 94 { _MMIO(0x27a84), 0x00000000 }, 95 { _MMIO(0x27b04), 0x00004000 }, 96 { _MMIO(0x27b80), 0x00000002 }, 97 { _MMIO(0x27b8c), 0x000000e0 }, 98 { _MMIO(0x27b84), 0x00000000 }, 99 { _MMIO(0x26104), 0x00002222 }, 100 { _MMIO(0x26184), 0x0c006666 }, 101 { _MMIO(0x26284), 0x04000000 }, 102 { _MMIO(0x26304), 0x04000000 }, 103 { _MMIO(0x26400), 0x00000002 }, 104 { _MMIO(0x26410), 0x000000a0 }, 105 { _MMIO(0x26404), 0x00000000 }, 106 { _MMIO(0x25420), 0x04108020 }, 107 { _MMIO(0x25424), 0x1284a420 }, 108 { _MMIO(0x2541c), 0x00000000 }, 109 { _MMIO(0x25428), 0x00042049 }, 110 }; 111 112 static const struct i915_oa_reg * 113 get_render_basic_mux_config(struct drm_i915_private *dev_priv, 114 int *len) 115 { 116 *len = ARRAY_SIZE(mux_config_render_basic); 117 return mux_config_render_basic; 118 } 119 120 static const struct i915_oa_reg b_counter_config_compute_basic[] = { 121 { _MMIO(0x2710), 0x00000000 }, 122 { _MMIO(0x2714), 0x00800000 }, 123 { _MMIO(0x2718), 0xaaaaaaaa }, 124 { _MMIO(0x271c), 0xaaaaaaaa }, 125 { _MMIO(0x2720), 0x00000000 }, 126 { _MMIO(0x2724), 0x00800000 }, 127 { _MMIO(0x2728), 0xaaaaaaaa }, 128 { _MMIO(0x272c), 0xaaaaaaaa }, 129 { _MMIO(0x2740), 0x00000000 }, 130 { _MMIO(0x2744), 0x00000000 }, 131 { _MMIO(0x2748), 0x00000000 }, 132 { _MMIO(0x274c), 0x00000000 }, 133 { _MMIO(0x2750), 0x00000000 }, 134 { _MMIO(0x2754), 0x00000000 }, 135 { _MMIO(0x2758), 0x00000000 }, 136 { _MMIO(0x275c), 0x00000000 }, 137 { _MMIO(0x236c), 0x00000000 }, 138 }; 139 140 static const struct i915_oa_reg mux_config_compute_basic[] = { 141 { _MMIO(0x253a4), 0x00000000 }, 142 { _MMIO(0x2681c), 0x01f00800 }, 143 { _MMIO(0x26820), 0x00001000 }, 144 { _MMIO(0x2781c), 0x01f00800 }, 145 { _MMIO(0x26520), 0x00000007 }, 146 { _MMIO(0x265a0), 0x00000007 }, 147 { _MMIO(0x25380), 0x00000010 }, 148 { _MMIO(0x2538c), 0x00300000 }, 149 { _MMIO(0x25384), 0xaa8aaaaa }, 150 { _MMIO(0x25404), 0xffffffff }, 151 { _MMIO(0x26800), 0x00004202 }, 152 { _MMIO(0x26808), 0x00605817 }, 153 { _MMIO(0x2680c), 0x10001005 }, 154 { _MMIO(0x26804), 0x00000000 }, 155 { _MMIO(0x27800), 0x00000102 }, 156 { _MMIO(0x27808), 0x0c0701e0 }, 157 { _MMIO(0x2780c), 0x000200a0 }, 158 { _MMIO(0x27804), 0x00000000 }, 159 { _MMIO(0x26484), 0x44000000 }, 160 { _MMIO(0x26704), 0x44000000 }, 161 { _MMIO(0x26500), 0x00000006 }, 162 { _MMIO(0x26510), 0x00000001 }, 163 { _MMIO(0x26504), 0x88000000 }, 164 { _MMIO(0x26580), 0x00000006 }, 165 { _MMIO(0x26590), 0x00000020 }, 166 { _MMIO(0x26584), 0x00000000 }, 167 { _MMIO(0x26104), 0x55822222 }, 168 { _MMIO(0x26184), 0xaa866666 }, 169 { _MMIO(0x25420), 0x08320c83 }, 170 { _MMIO(0x25424), 0x06820c83 }, 171 { _MMIO(0x2541c), 0x00000000 }, 172 { _MMIO(0x25428), 0x00000c03 }, 173 }; 174 175 static const struct i915_oa_reg * 176 get_compute_basic_mux_config(struct drm_i915_private *dev_priv, 177 int *len) 178 { 179 *len = ARRAY_SIZE(mux_config_compute_basic); 180 return mux_config_compute_basic; 181 } 182 183 static const struct i915_oa_reg b_counter_config_compute_extended[] = { 184 { _MMIO(0x2724), 0xf0800000 }, 185 { _MMIO(0x2720), 0x00000000 }, 186 { _MMIO(0x2714), 0xf0800000 }, 187 { _MMIO(0x2710), 0x00000000 }, 188 { _MMIO(0x2770), 0x0007fe2a }, 189 { _MMIO(0x2774), 0x0000ff00 }, 190 { _MMIO(0x2778), 0x0007fe6a }, 191 { _MMIO(0x277c), 0x0000ff00 }, 192 { _MMIO(0x2780), 0x0007fe92 }, 193 { _MMIO(0x2784), 0x0000ff00 }, 194 { _MMIO(0x2788), 0x0007fea2 }, 195 { _MMIO(0x278c), 0x0000ff00 }, 196 { _MMIO(0x2790), 0x0007fe32 }, 197 { _MMIO(0x2794), 0x0000ff00 }, 198 { _MMIO(0x2798), 0x0007fe9a }, 199 { _MMIO(0x279c), 0x0000ff00 }, 200 { _MMIO(0x27a0), 0x0007ff23 }, 201 { _MMIO(0x27a4), 0x0000ff00 }, 202 { _MMIO(0x27a8), 0x0007fff3 }, 203 { _MMIO(0x27ac), 0x0000fffe }, 204 }; 205 206 static const struct i915_oa_reg mux_config_compute_extended[] = { 207 { _MMIO(0x2681c), 0x3eb00800 }, 208 { _MMIO(0x26820), 0x00900000 }, 209 { _MMIO(0x25384), 0x02aaaaaa }, 210 { _MMIO(0x25404), 0x03ffffff }, 211 { _MMIO(0x26800), 0x00142284 }, 212 { _MMIO(0x26808), 0x0e629062 }, 213 { _MMIO(0x2680c), 0x3f6f55cb }, 214 { _MMIO(0x26810), 0x00000014 }, 215 { _MMIO(0x26804), 0x00000000 }, 216 { _MMIO(0x26104), 0x02aaaaaa }, 217 { _MMIO(0x26184), 0x02aaaaaa }, 218 { _MMIO(0x25420), 0x00000000 }, 219 { _MMIO(0x25424), 0x00000000 }, 220 { _MMIO(0x2541c), 0x00000000 }, 221 { _MMIO(0x25428), 0x00000000 }, 222 }; 223 224 static const struct i915_oa_reg * 225 get_compute_extended_mux_config(struct drm_i915_private *dev_priv, 226 int *len) 227 { 228 *len = ARRAY_SIZE(mux_config_compute_extended); 229 return mux_config_compute_extended; 230 } 231 232 static const struct i915_oa_reg b_counter_config_memory_reads[] = { 233 { _MMIO(0x2724), 0xf0800000 }, 234 { _MMIO(0x2720), 0x00000000 }, 235 { _MMIO(0x2714), 0xf0800000 }, 236 { _MMIO(0x2710), 0x00000000 }, 237 { _MMIO(0x274c), 0x76543298 }, 238 { _MMIO(0x2748), 0x98989898 }, 239 { _MMIO(0x2744), 0x000000e4 }, 240 { _MMIO(0x2740), 0x00000000 }, 241 { _MMIO(0x275c), 0x98a98a98 }, 242 { _MMIO(0x2758), 0x88888888 }, 243 { _MMIO(0x2754), 0x000c5500 }, 244 { _MMIO(0x2750), 0x00000000 }, 245 { _MMIO(0x2770), 0x0007f81a }, 246 { _MMIO(0x2774), 0x0000fc00 }, 247 { _MMIO(0x2778), 0x0007f82a }, 248 { _MMIO(0x277c), 0x0000fc00 }, 249 { _MMIO(0x2780), 0x0007f872 }, 250 { _MMIO(0x2784), 0x0000fc00 }, 251 { _MMIO(0x2788), 0x0007f8ba }, 252 { _MMIO(0x278c), 0x0000fc00 }, 253 { _MMIO(0x2790), 0x0007f87a }, 254 { _MMIO(0x2794), 0x0000fc00 }, 255 { _MMIO(0x2798), 0x0007f8ea }, 256 { _MMIO(0x279c), 0x0000fc00 }, 257 { _MMIO(0x27a0), 0x0007f8e2 }, 258 { _MMIO(0x27a4), 0x0000fc00 }, 259 { _MMIO(0x27a8), 0x0007f8f2 }, 260 { _MMIO(0x27ac), 0x0000fc00 }, 261 }; 262 263 static const struct i915_oa_reg mux_config_memory_reads[] = { 264 { _MMIO(0x253a4), 0x34300000 }, 265 { _MMIO(0x25440), 0x2d800000 }, 266 { _MMIO(0x25444), 0x00000008 }, 267 { _MMIO(0x25128), 0x0e600000 }, 268 { _MMIO(0x25380), 0x00000450 }, 269 { _MMIO(0x25390), 0x00052c43 }, 270 { _MMIO(0x25384), 0x00000000 }, 271 { _MMIO(0x25400), 0x00006144 }, 272 { _MMIO(0x25408), 0x0a418820 }, 273 { _MMIO(0x2540c), 0x000820e6 }, 274 { _MMIO(0x25404), 0xff500000 }, 275 { _MMIO(0x25100), 0x000005d6 }, 276 { _MMIO(0x2510c), 0x0ef00000 }, 277 { _MMIO(0x25104), 0x00000000 }, 278 { _MMIO(0x25420), 0x02108421 }, 279 { _MMIO(0x25424), 0x00008421 }, 280 { _MMIO(0x2541c), 0x00000000 }, 281 { _MMIO(0x25428), 0x00000000 }, 282 }; 283 284 static const struct i915_oa_reg * 285 get_memory_reads_mux_config(struct drm_i915_private *dev_priv, 286 int *len) 287 { 288 *len = ARRAY_SIZE(mux_config_memory_reads); 289 return mux_config_memory_reads; 290 } 291 292 static const struct i915_oa_reg b_counter_config_memory_writes[] = { 293 { _MMIO(0x2724), 0xf0800000 }, 294 { _MMIO(0x2720), 0x00000000 }, 295 { _MMIO(0x2714), 0xf0800000 }, 296 { _MMIO(0x2710), 0x00000000 }, 297 { _MMIO(0x274c), 0x76543298 }, 298 { _MMIO(0x2748), 0x98989898 }, 299 { _MMIO(0x2744), 0x000000e4 }, 300 { _MMIO(0x2740), 0x00000000 }, 301 { _MMIO(0x275c), 0xbabababa }, 302 { _MMIO(0x2758), 0x88888888 }, 303 { _MMIO(0x2754), 0x000c5500 }, 304 { _MMIO(0x2750), 0x00000000 }, 305 { _MMIO(0x2770), 0x0007f81a }, 306 { _MMIO(0x2774), 0x0000fc00 }, 307 { _MMIO(0x2778), 0x0007f82a }, 308 { _MMIO(0x277c), 0x0000fc00 }, 309 { _MMIO(0x2780), 0x0007f822 }, 310 { _MMIO(0x2784), 0x0000fc00 }, 311 { _MMIO(0x2788), 0x0007f8ba }, 312 { _MMIO(0x278c), 0x0000fc00 }, 313 { _MMIO(0x2790), 0x0007f87a }, 314 { _MMIO(0x2794), 0x0000fc00 }, 315 { _MMIO(0x2798), 0x0007f8ea }, 316 { _MMIO(0x279c), 0x0000fc00 }, 317 { _MMIO(0x27a0), 0x0007f8e2 }, 318 { _MMIO(0x27a4), 0x0000fc00 }, 319 { _MMIO(0x27a8), 0x0007f8f2 }, 320 { _MMIO(0x27ac), 0x0000fc00 }, 321 }; 322 323 static const struct i915_oa_reg mux_config_memory_writes[] = { 324 { _MMIO(0x253a4), 0x34300000 }, 325 { _MMIO(0x25440), 0x01500000 }, 326 { _MMIO(0x25444), 0x00000120 }, 327 { _MMIO(0x25128), 0x0c200000 }, 328 { _MMIO(0x25380), 0x00000450 }, 329 { _MMIO(0x25390), 0x00052c43 }, 330 { _MMIO(0x25384), 0x00000000 }, 331 { _MMIO(0x25400), 0x00007184 }, 332 { _MMIO(0x25408), 0x0a418820 }, 333 { _MMIO(0x2540c), 0x000820e6 }, 334 { _MMIO(0x25404), 0xff500000 }, 335 { _MMIO(0x25100), 0x000005d6 }, 336 { _MMIO(0x2510c), 0x1e700000 }, 337 { _MMIO(0x25104), 0x00000000 }, 338 { _MMIO(0x25420), 0x02108421 }, 339 { _MMIO(0x25424), 0x00008421 }, 340 { _MMIO(0x2541c), 0x00000000 }, 341 { _MMIO(0x25428), 0x00000000 }, 342 }; 343 344 static const struct i915_oa_reg * 345 get_memory_writes_mux_config(struct drm_i915_private *dev_priv, 346 int *len) 347 { 348 *len = ARRAY_SIZE(mux_config_memory_writes); 349 return mux_config_memory_writes; 350 } 351 352 static const struct i915_oa_reg b_counter_config_sampler_balance[] = { 353 { _MMIO(0x2740), 0x00000000 }, 354 { _MMIO(0x2744), 0x00800000 }, 355 { _MMIO(0x2710), 0x00000000 }, 356 { _MMIO(0x2714), 0x00800000 }, 357 { _MMIO(0x2720), 0x00000000 }, 358 { _MMIO(0x2724), 0x00800000 }, 359 }; 360 361 static const struct i915_oa_reg mux_config_sampler_balance[] = { 362 { _MMIO(0x2eb9c), 0x01906400 }, 363 { _MMIO(0x2fb9c), 0x01906400 }, 364 { _MMIO(0x253a4), 0x00000000 }, 365 { _MMIO(0x26b9c), 0x01906400 }, 366 { _MMIO(0x27b9c), 0x01906400 }, 367 { _MMIO(0x27104), 0x00a00000 }, 368 { _MMIO(0x27184), 0x00a50000 }, 369 { _MMIO(0x2e804), 0x00500000 }, 370 { _MMIO(0x2e984), 0x00500000 }, 371 { _MMIO(0x2eb04), 0x00500000 }, 372 { _MMIO(0x2eb80), 0x00000084 }, 373 { _MMIO(0x2eb8c), 0x14200000 }, 374 { _MMIO(0x2eb84), 0x00000000 }, 375 { _MMIO(0x2f804), 0x00050000 }, 376 { _MMIO(0x2f984), 0x00050000 }, 377 { _MMIO(0x2fb04), 0x00050000 }, 378 { _MMIO(0x2fb80), 0x00000084 }, 379 { _MMIO(0x2fb8c), 0x00050800 }, 380 { _MMIO(0x2fb84), 0x00000000 }, 381 { _MMIO(0x25380), 0x00000010 }, 382 { _MMIO(0x2538c), 0x000000c0 }, 383 { _MMIO(0x25384), 0xaa550000 }, 384 { _MMIO(0x25404), 0xffffc000 }, 385 { _MMIO(0x26804), 0x50000000 }, 386 { _MMIO(0x26984), 0x50000000 }, 387 { _MMIO(0x26b04), 0x50000000 }, 388 { _MMIO(0x26b80), 0x00000084 }, 389 { _MMIO(0x26b90), 0x00050800 }, 390 { _MMIO(0x26b84), 0x00000000 }, 391 { _MMIO(0x27804), 0x05000000 }, 392 { _MMIO(0x27984), 0x05000000 }, 393 { _MMIO(0x27b04), 0x05000000 }, 394 { _MMIO(0x27b80), 0x00000084 }, 395 { _MMIO(0x27b90), 0x00000142 }, 396 { _MMIO(0x27b84), 0x00000000 }, 397 { _MMIO(0x26104), 0xa0000000 }, 398 { _MMIO(0x26184), 0xa5000000 }, 399 { _MMIO(0x25424), 0x00008620 }, 400 { _MMIO(0x2541c), 0x00000000 }, 401 { _MMIO(0x25428), 0x0004a54a }, 402 }; 403 404 static const struct i915_oa_reg * 405 get_sampler_balance_mux_config(struct drm_i915_private *dev_priv, 406 int *len) 407 { 408 *len = ARRAY_SIZE(mux_config_sampler_balance); 409 return mux_config_sampler_balance; 410 } 411 412 int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) 413 { 414 dev_priv->perf.oa.mux_regs = NULL; 415 dev_priv->perf.oa.mux_regs_len = 0; 416 dev_priv->perf.oa.b_counter_regs = NULL; 417 dev_priv->perf.oa.b_counter_regs_len = 0; 418 419 switch (dev_priv->perf.oa.metrics_set) { 420 case METRIC_SET_ID_RENDER_BASIC: 421 dev_priv->perf.oa.mux_regs = 422 get_render_basic_mux_config(dev_priv, 423 &dev_priv->perf.oa.mux_regs_len); 424 if (!dev_priv->perf.oa.mux_regs) { 425 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set"); 426 427 /* EINVAL because *_register_sysfs already checked this 428 * and so it wouldn't have been advertised so userspace and 429 * so shouldn't have been requested 430 */ 431 return -EINVAL; 432 } 433 434 dev_priv->perf.oa.b_counter_regs = 435 b_counter_config_render_basic; 436 dev_priv->perf.oa.b_counter_regs_len = 437 ARRAY_SIZE(b_counter_config_render_basic); 438 439 return 0; 440 case METRIC_SET_ID_COMPUTE_BASIC: 441 dev_priv->perf.oa.mux_regs = 442 get_compute_basic_mux_config(dev_priv, 443 &dev_priv->perf.oa.mux_regs_len); 444 if (!dev_priv->perf.oa.mux_regs) { 445 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set"); 446 447 /* EINVAL because *_register_sysfs already checked this 448 * and so it wouldn't have been advertised so userspace and 449 * so shouldn't have been requested 450 */ 451 return -EINVAL; 452 } 453 454 dev_priv->perf.oa.b_counter_regs = 455 b_counter_config_compute_basic; 456 dev_priv->perf.oa.b_counter_regs_len = 457 ARRAY_SIZE(b_counter_config_compute_basic); 458 459 return 0; 460 case METRIC_SET_ID_COMPUTE_EXTENDED: 461 dev_priv->perf.oa.mux_regs = 462 get_compute_extended_mux_config(dev_priv, 463 &dev_priv->perf.oa.mux_regs_len); 464 if (!dev_priv->perf.oa.mux_regs) { 465 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set"); 466 467 /* EINVAL because *_register_sysfs already checked this 468 * and so it wouldn't have been advertised so userspace and 469 * so shouldn't have been requested 470 */ 471 return -EINVAL; 472 } 473 474 dev_priv->perf.oa.b_counter_regs = 475 b_counter_config_compute_extended; 476 dev_priv->perf.oa.b_counter_regs_len = 477 ARRAY_SIZE(b_counter_config_compute_extended); 478 479 return 0; 480 case METRIC_SET_ID_MEMORY_READS: 481 dev_priv->perf.oa.mux_regs = 482 get_memory_reads_mux_config(dev_priv, 483 &dev_priv->perf.oa.mux_regs_len); 484 if (!dev_priv->perf.oa.mux_regs) { 485 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set"); 486 487 /* EINVAL because *_register_sysfs already checked this 488 * and so it wouldn't have been advertised so userspace and 489 * so shouldn't have been requested 490 */ 491 return -EINVAL; 492 } 493 494 dev_priv->perf.oa.b_counter_regs = 495 b_counter_config_memory_reads; 496 dev_priv->perf.oa.b_counter_regs_len = 497 ARRAY_SIZE(b_counter_config_memory_reads); 498 499 return 0; 500 case METRIC_SET_ID_MEMORY_WRITES: 501 dev_priv->perf.oa.mux_regs = 502 get_memory_writes_mux_config(dev_priv, 503 &dev_priv->perf.oa.mux_regs_len); 504 if (!dev_priv->perf.oa.mux_regs) { 505 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set"); 506 507 /* EINVAL because *_register_sysfs already checked this 508 * and so it wouldn't have been advertised so userspace and 509 * so shouldn't have been requested 510 */ 511 return -EINVAL; 512 } 513 514 dev_priv->perf.oa.b_counter_regs = 515 b_counter_config_memory_writes; 516 dev_priv->perf.oa.b_counter_regs_len = 517 ARRAY_SIZE(b_counter_config_memory_writes); 518 519 return 0; 520 case METRIC_SET_ID_SAMPLER_BALANCE: 521 dev_priv->perf.oa.mux_regs = 522 get_sampler_balance_mux_config(dev_priv, 523 &dev_priv->perf.oa.mux_regs_len); 524 if (!dev_priv->perf.oa.mux_regs) { 525 DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_BALANCE\" metric set"); 526 527 /* EINVAL because *_register_sysfs already checked this 528 * and so it wouldn't have been advertised so userspace and 529 * so shouldn't have been requested 530 */ 531 return -EINVAL; 532 } 533 534 dev_priv->perf.oa.b_counter_regs = 535 b_counter_config_sampler_balance; 536 dev_priv->perf.oa.b_counter_regs_len = 537 ARRAY_SIZE(b_counter_config_sampler_balance); 538 539 return 0; 540 default: 541 return -ENODEV; 542 } 543 } 544 545 #if 0 546 static ssize_t 547 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) 548 { 549 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); 550 } 551 552 static struct device_attribute dev_attr_render_basic_id = { 553 .attr = { .name = "id", .mode = 0444 }, 554 .show = show_render_basic_id, 555 .store = NULL, 556 }; 557 558 static struct attribute *attrs_render_basic[] = { 559 &dev_attr_render_basic_id.attr, 560 NULL, 561 }; 562 563 static struct attribute_group group_render_basic = { 564 .name = "403d8832-1a27-4aa6-a64e-f5389ce7b212", 565 .attrs = attrs_render_basic, 566 }; 567 568 static ssize_t 569 show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) 570 { 571 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); 572 } 573 574 static struct device_attribute dev_attr_compute_basic_id = { 575 .attr = { .name = "id", .mode = 0444 }, 576 .show = show_compute_basic_id, 577 .store = NULL, 578 }; 579 580 static struct attribute *attrs_compute_basic[] = { 581 &dev_attr_compute_basic_id.attr, 582 NULL, 583 }; 584 585 static struct attribute_group group_compute_basic = { 586 .name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b", 587 .attrs = attrs_compute_basic, 588 }; 589 590 static ssize_t 591 show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) 592 { 593 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); 594 } 595 596 static struct device_attribute dev_attr_compute_extended_id = { 597 .attr = { .name = "id", .mode = 0444 }, 598 .show = show_compute_extended_id, 599 .store = NULL, 600 }; 601 602 static struct attribute *attrs_compute_extended[] = { 603 &dev_attr_compute_extended_id.attr, 604 NULL, 605 }; 606 607 static struct attribute_group group_compute_extended = { 608 .name = "3865be28-6982-49fe-9494-e4d1b4795413", 609 .attrs = attrs_compute_extended, 610 }; 611 612 static ssize_t 613 show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) 614 { 615 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); 616 } 617 618 static struct device_attribute dev_attr_memory_reads_id = { 619 .attr = { .name = "id", .mode = 0444 }, 620 .show = show_memory_reads_id, 621 .store = NULL, 622 }; 623 624 static struct attribute *attrs_memory_reads[] = { 625 &dev_attr_memory_reads_id.attr, 626 NULL, 627 }; 628 629 static struct attribute_group group_memory_reads = { 630 .name = "bb5ed49b-2497-4095-94f6-26ba294db88a", 631 .attrs = attrs_memory_reads, 632 }; 633 634 static ssize_t 635 show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) 636 { 637 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); 638 } 639 640 static struct device_attribute dev_attr_memory_writes_id = { 641 .attr = { .name = "id", .mode = 0444 }, 642 .show = show_memory_writes_id, 643 .store = NULL, 644 }; 645 646 static struct attribute *attrs_memory_writes[] = { 647 &dev_attr_memory_writes_id.attr, 648 NULL, 649 }; 650 651 static struct attribute_group group_memory_writes = { 652 .name = "3358d639-9b5f-45ab-976d-9b08cbfc6240", 653 .attrs = attrs_memory_writes, 654 }; 655 656 static ssize_t 657 show_sampler_balance_id(struct device *kdev, struct device_attribute *attr, char *buf) 658 { 659 return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_BALANCE); 660 } 661 662 static struct device_attribute dev_attr_sampler_balance_id = { 663 .attr = { .name = "id", .mode = 0444 }, 664 .show = show_sampler_balance_id, 665 .store = NULL, 666 }; 667 668 static struct attribute *attrs_sampler_balance[] = { 669 &dev_attr_sampler_balance_id.attr, 670 NULL, 671 }; 672 673 static struct attribute_group group_sampler_balance = { 674 .name = "bc274488-b4b6-40c7-90da-b77d7ad16189", 675 .attrs = attrs_sampler_balance, 676 }; 677 678 int 679 i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv) 680 { 681 int mux_len; 682 int ret = 0; 683 684 if (get_render_basic_mux_config(dev_priv, &mux_len)) { 685 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); 686 if (ret) 687 goto error_render_basic; 688 } 689 if (get_compute_basic_mux_config(dev_priv, &mux_len)) { 690 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); 691 if (ret) 692 goto error_compute_basic; 693 } 694 if (get_compute_extended_mux_config(dev_priv, &mux_len)) { 695 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); 696 if (ret) 697 goto error_compute_extended; 698 } 699 if (get_memory_reads_mux_config(dev_priv, &mux_len)) { 700 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); 701 if (ret) 702 goto error_memory_reads; 703 } 704 if (get_memory_writes_mux_config(dev_priv, &mux_len)) { 705 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); 706 if (ret) 707 goto error_memory_writes; 708 } 709 if (get_sampler_balance_mux_config(dev_priv, &mux_len)) { 710 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); 711 if (ret) 712 goto error_sampler_balance; 713 } 714 715 return 0; 716 717 error_sampler_balance: 718 if (get_sampler_balance_mux_config(dev_priv, &mux_len)) 719 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); 720 error_memory_writes: 721 if (get_sampler_balance_mux_config(dev_priv, &mux_len)) 722 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); 723 error_memory_reads: 724 if (get_sampler_balance_mux_config(dev_priv, &mux_len)) 725 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); 726 error_compute_extended: 727 if (get_sampler_balance_mux_config(dev_priv, &mux_len)) 728 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); 729 error_compute_basic: 730 if (get_sampler_balance_mux_config(dev_priv, &mux_len)) 731 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); 732 error_render_basic: 733 return ret; 734 } 735 736 void 737 i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv) 738 { 739 int mux_len; 740 741 if (get_render_basic_mux_config(dev_priv, &mux_len)) 742 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); 743 if (get_compute_basic_mux_config(dev_priv, &mux_len)) 744 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); 745 if (get_compute_extended_mux_config(dev_priv, &mux_len)) 746 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); 747 if (get_memory_reads_mux_config(dev_priv, &mux_len)) 748 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); 749 if (get_memory_writes_mux_config(dev_priv, &mux_len)) 750 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); 751 if (get_sampler_balance_mux_config(dev_priv, &mux_len)) 752 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); 753 } 754 #endif 755