xref: /dragonfly/sys/dev/drm/i915/i915_oa_hsw.c (revision 3ea159d2)
1 /*
2  * Autogenerated file by GPU Top : https://github.com/rib/gputop
3  * DO NOT EDIT manually!
4  *
5  *
6  * Copyright (c) 2015 Intel Corporation
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25  * IN THE SOFTWARE.
26  *
27  */
28 
29 #include <linux/sysfs.h>
30 
31 #include "i915_drv.h"
32 #include "i915_oa_hsw.h"
33 
34 #if 0
35 static const struct i915_oa_reg b_counter_config_render_basic[] = {
36 	{ _MMIO(0x2724), 0x00800000 },
37 	{ _MMIO(0x2720), 0x00000000 },
38 	{ _MMIO(0x2714), 0x00800000 },
39 	{ _MMIO(0x2710), 0x00000000 },
40 };
41 
42 static const struct i915_oa_reg flex_eu_config_render_basic[] = {
43 };
44 
45 static const struct i915_oa_reg mux_config_render_basic[] = {
46 	{ _MMIO(0x9840), 0x00000080 },
47 	{ _MMIO(0x253a4), 0x01600000 },
48 	{ _MMIO(0x25440), 0x00100000 },
49 	{ _MMIO(0x25128), 0x00000000 },
50 	{ _MMIO(0x2691c), 0x00000800 },
51 	{ _MMIO(0x26aa0), 0x01500000 },
52 	{ _MMIO(0x26b9c), 0x00006000 },
53 	{ _MMIO(0x2791c), 0x00000800 },
54 	{ _MMIO(0x27aa0), 0x01500000 },
55 	{ _MMIO(0x27b9c), 0x00006000 },
56 	{ _MMIO(0x2641c), 0x00000400 },
57 	{ _MMIO(0x25380), 0x00000010 },
58 	{ _MMIO(0x2538c), 0x00000000 },
59 	{ _MMIO(0x25384), 0x0800aaaa },
60 	{ _MMIO(0x25400), 0x00000004 },
61 	{ _MMIO(0x2540c), 0x06029000 },
62 	{ _MMIO(0x25410), 0x00000002 },
63 	{ _MMIO(0x25404), 0x5c30ffff },
64 	{ _MMIO(0x25100), 0x00000016 },
65 	{ _MMIO(0x25110), 0x00000400 },
66 	{ _MMIO(0x25104), 0x00000000 },
67 	{ _MMIO(0x26804), 0x00001211 },
68 	{ _MMIO(0x26884), 0x00000100 },
69 	{ _MMIO(0x26900), 0x00000002 },
70 	{ _MMIO(0x26908), 0x00700000 },
71 	{ _MMIO(0x26904), 0x00000000 },
72 	{ _MMIO(0x26984), 0x00001022 },
73 	{ _MMIO(0x26a04), 0x00000011 },
74 	{ _MMIO(0x26a80), 0x00000006 },
75 	{ _MMIO(0x26a88), 0x00000c02 },
76 	{ _MMIO(0x26a84), 0x00000000 },
77 	{ _MMIO(0x26b04), 0x00001000 },
78 	{ _MMIO(0x26b80), 0x00000002 },
79 	{ _MMIO(0x26b8c), 0x00000007 },
80 	{ _MMIO(0x26b84), 0x00000000 },
81 	{ _MMIO(0x27804), 0x00004844 },
82 	{ _MMIO(0x27884), 0x00000400 },
83 	{ _MMIO(0x27900), 0x00000002 },
84 	{ _MMIO(0x27908), 0x0e000000 },
85 	{ _MMIO(0x27904), 0x00000000 },
86 	{ _MMIO(0x27984), 0x00004088 },
87 	{ _MMIO(0x27a04), 0x00000044 },
88 	{ _MMIO(0x27a80), 0x00000006 },
89 	{ _MMIO(0x27a88), 0x00018040 },
90 	{ _MMIO(0x27a84), 0x00000000 },
91 	{ _MMIO(0x27b04), 0x00004000 },
92 	{ _MMIO(0x27b80), 0x00000002 },
93 	{ _MMIO(0x27b8c), 0x000000e0 },
94 	{ _MMIO(0x27b84), 0x00000000 },
95 	{ _MMIO(0x26104), 0x00002222 },
96 	{ _MMIO(0x26184), 0x0c006666 },
97 	{ _MMIO(0x26284), 0x04000000 },
98 	{ _MMIO(0x26304), 0x04000000 },
99 	{ _MMIO(0x26400), 0x00000002 },
100 	{ _MMIO(0x26410), 0x000000a0 },
101 	{ _MMIO(0x26404), 0x00000000 },
102 	{ _MMIO(0x25420), 0x04108020 },
103 	{ _MMIO(0x25424), 0x1284a420 },
104 	{ _MMIO(0x2541c), 0x00000000 },
105 	{ _MMIO(0x25428), 0x00042049 },
106 };
107 
108 static ssize_t
109 show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
110 {
111 	return sprintf(buf, "1\n");
112 }
113 
114 void
115 i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv)
116 {
117 	strncpy(dev_priv->perf.oa.test_config.uuid,
118 		"403d8832-1a27-4aa6-a64e-f5389ce7b212",
119 		UUID_STRING_LEN);
120 	dev_priv->perf.oa.test_config.id = 1;
121 
122 	dev_priv->perf.oa.test_config.mux_regs = mux_config_render_basic;
123 	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic);
124 
125 	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_render_basic;
126 	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic);
127 
128 	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_render_basic;
129 	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic);
130 
131 	dev_priv->perf.oa.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212";
132 	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
133 
134 	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
135 
136 	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
137 	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
138 	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_render_basic_id;
139 }
140 #endif
141