1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 31 #define GEN_DEFAULT_PIPEOFFSETS \ 32 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 33 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 34 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 35 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 36 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 37 38 #define GEN_CHV_PIPEOFFSETS \ 39 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 40 CHV_PIPE_C_OFFSET }, \ 41 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 42 CHV_TRANSCODER_C_OFFSET, }, \ 43 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 44 CHV_PALETTE_C_OFFSET } 45 46 #define CURSOR_OFFSETS \ 47 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 48 49 #define IVB_CURSOR_OFFSETS \ 50 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 51 52 #define BDW_COLORS \ 53 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 54 #define CHV_COLORS \ 55 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 56 57 #define GEN2_FEATURES \ 58 .gen = 2, .num_pipes = 1, \ 59 .has_overlay = 1, .overlay_needs_physical = 1, \ 60 .has_gmch_display = 1, \ 61 .hws_needs_physical = 1, \ 62 .ring_mask = RENDER_RING, \ 63 GEN_DEFAULT_PIPEOFFSETS, \ 64 CURSOR_OFFSETS 65 66 static const struct intel_device_info intel_i830_info = { 67 GEN2_FEATURES, 68 .is_mobile = 1, .cursor_needs_physical = 1, 69 .num_pipes = 2, /* legal, last one wins */ 70 }; 71 72 static const struct intel_device_info intel_845g_info = { 73 GEN2_FEATURES, 74 }; 75 76 static const struct intel_device_info intel_i85x_info = { 77 GEN2_FEATURES, 78 .is_i85x = 1, .is_mobile = 1, 79 .num_pipes = 2, /* legal, last one wins */ 80 .cursor_needs_physical = 1, 81 .has_fbc = 1, 82 }; 83 84 static const struct intel_device_info intel_i865g_info = { 85 GEN2_FEATURES, 86 }; 87 88 #define GEN3_FEATURES \ 89 .gen = 3, .num_pipes = 2, \ 90 .has_gmch_display = 1, \ 91 .ring_mask = RENDER_RING, \ 92 GEN_DEFAULT_PIPEOFFSETS, \ 93 CURSOR_OFFSETS 94 95 static const struct intel_device_info intel_i915g_info = { 96 GEN3_FEATURES, 97 .is_i915g = 1, .cursor_needs_physical = 1, 98 .has_overlay = 1, .overlay_needs_physical = 1, 99 .hws_needs_physical = 1, 100 }; 101 static const struct intel_device_info intel_i915gm_info = { 102 GEN3_FEATURES, 103 .is_mobile = 1, 104 .cursor_needs_physical = 1, 105 .has_overlay = 1, .overlay_needs_physical = 1, 106 .supports_tv = 1, 107 .has_fbc = 1, 108 .hws_needs_physical = 1, 109 }; 110 static const struct intel_device_info intel_i945g_info = { 111 GEN3_FEATURES, 112 .has_hotplug = 1, .cursor_needs_physical = 1, 113 .has_overlay = 1, .overlay_needs_physical = 1, 114 .hws_needs_physical = 1, 115 }; 116 static const struct intel_device_info intel_i945gm_info = { 117 GEN3_FEATURES, 118 .is_i945gm = 1, .is_mobile = 1, 119 .has_hotplug = 1, .cursor_needs_physical = 1, 120 .has_overlay = 1, .overlay_needs_physical = 1, 121 .supports_tv = 1, 122 .has_fbc = 1, 123 .hws_needs_physical = 1, 124 }; 125 126 #define GEN4_FEATURES \ 127 .gen = 4, .num_pipes = 2, \ 128 .has_hotplug = 1, \ 129 .has_gmch_display = 1, \ 130 .ring_mask = RENDER_RING, \ 131 GEN_DEFAULT_PIPEOFFSETS, \ 132 CURSOR_OFFSETS 133 134 static const struct intel_device_info intel_i965g_info = { 135 GEN4_FEATURES, 136 .is_broadwater = 1, 137 .has_overlay = 1, 138 .hws_needs_physical = 1, 139 }; 140 141 static const struct intel_device_info intel_i965gm_info = { 142 GEN4_FEATURES, 143 .is_crestline = 1, 144 .is_mobile = 1, .has_fbc = 1, 145 .has_overlay = 1, 146 .supports_tv = 1, 147 .hws_needs_physical = 1, 148 }; 149 150 static const struct intel_device_info intel_g33_info = { 151 GEN3_FEATURES, 152 .is_g33 = 1, 153 .has_hotplug = 1, 154 .has_overlay = 1, 155 }; 156 157 static const struct intel_device_info intel_g45_info = { 158 GEN4_FEATURES, 159 .is_g4x = 1, 160 .has_pipe_cxsr = 1, 161 .ring_mask = RENDER_RING | BSD_RING, 162 }; 163 164 static const struct intel_device_info intel_gm45_info = { 165 GEN4_FEATURES, 166 .is_g4x = 1, 167 .is_mobile = 1, .has_fbc = 1, 168 .has_pipe_cxsr = 1, 169 .supports_tv = 1, 170 .ring_mask = RENDER_RING | BSD_RING, 171 }; 172 173 static const struct intel_device_info intel_pineview_info = { 174 GEN3_FEATURES, 175 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, 176 .has_hotplug = 1, 177 .has_overlay = 1, 178 }; 179 180 #define GEN5_FEATURES \ 181 .gen = 5, .num_pipes = 2, \ 182 .has_hotplug = 1, \ 183 .has_gmbus_irq = 1, \ 184 .ring_mask = RENDER_RING | BSD_RING, \ 185 GEN_DEFAULT_PIPEOFFSETS, \ 186 CURSOR_OFFSETS 187 188 static const struct intel_device_info intel_ironlake_d_info = { 189 GEN5_FEATURES, 190 }; 191 192 static const struct intel_device_info intel_ironlake_m_info = { 193 GEN5_FEATURES, 194 .is_mobile = 1, 195 }; 196 197 #define GEN6_FEATURES \ 198 .gen = 6, .num_pipes = 2, \ 199 .has_hotplug = 1, \ 200 .has_fbc = 1, \ 201 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 202 .has_llc = 1, \ 203 .has_rc6 = 1, \ 204 .has_rc6p = 1, \ 205 .has_gmbus_irq = 1, \ 206 .has_hw_contexts = 1, \ 207 GEN_DEFAULT_PIPEOFFSETS, \ 208 CURSOR_OFFSETS 209 210 static const struct intel_device_info intel_sandybridge_d_info = { 211 GEN6_FEATURES, 212 }; 213 214 static const struct intel_device_info intel_sandybridge_m_info = { 215 GEN6_FEATURES, 216 .is_mobile = 1, 217 }; 218 219 #define GEN7_FEATURES \ 220 .gen = 7, .num_pipes = 3, \ 221 .has_hotplug = 1, \ 222 .has_fbc = 1, \ 223 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 224 .has_llc = 1, \ 225 .has_rc6 = 1, \ 226 .has_rc6p = 1, \ 227 .has_gmbus_irq = 1, \ 228 .has_hw_contexts = 1, \ 229 GEN_DEFAULT_PIPEOFFSETS, \ 230 IVB_CURSOR_OFFSETS 231 232 static const struct intel_device_info intel_ivybridge_d_info = { 233 GEN7_FEATURES, 234 .is_ivybridge = 1, 235 .has_l3_dpf = 1, 236 }; 237 238 static const struct intel_device_info intel_ivybridge_m_info = { 239 GEN7_FEATURES, 240 .is_ivybridge = 1, 241 .is_mobile = 1, 242 .has_l3_dpf = 1, 243 }; 244 245 static const struct intel_device_info intel_ivybridge_q_info = { 246 GEN7_FEATURES, 247 .is_ivybridge = 1, 248 .num_pipes = 0, /* legal, last one wins */ 249 .has_l3_dpf = 1, 250 }; 251 252 #define VLV_FEATURES \ 253 .gen = 7, .num_pipes = 2, \ 254 .has_psr = 1, \ 255 .has_runtime_pm = 1, \ 256 .has_rc6 = 1, \ 257 .has_gmbus_irq = 1, \ 258 .has_hw_contexts = 1, \ 259 .has_gmch_display = 1, \ 260 .has_hotplug = 1, \ 261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 262 .display_mmio_offset = VLV_DISPLAY_BASE, \ 263 GEN_DEFAULT_PIPEOFFSETS, \ 264 CURSOR_OFFSETS 265 266 static const struct intel_device_info intel_valleyview_info = { 267 VLV_FEATURES, 268 .is_valleyview = 1, 269 }; 270 271 #define HSW_FEATURES \ 272 GEN7_FEATURES, \ 273 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 274 .has_ddi = 1, \ 275 .has_fpga_dbg = 1, \ 276 .has_psr = 1, \ 277 .has_resource_streamer = 1, \ 278 .has_dp_mst = 1, \ 279 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 280 .has_runtime_pm = 1 281 282 static const struct intel_device_info intel_haswell_info = { 283 HSW_FEATURES, 284 .is_haswell = 1, 285 .has_l3_dpf = 1, 286 }; 287 288 #define BDW_FEATURES \ 289 HSW_FEATURES, \ 290 BDW_COLORS, \ 291 .has_logical_ring_contexts = 1 292 293 static const struct intel_device_info intel_broadwell_info = { 294 BDW_FEATURES, 295 .gen = 8, 296 .is_broadwell = 1, 297 }; 298 299 static const struct intel_device_info intel_broadwell_gt3_info = { 300 BDW_FEATURES, 301 .gen = 8, 302 .is_broadwell = 1, 303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 304 }; 305 306 static const struct intel_device_info intel_cherryview_info = { 307 .gen = 8, .num_pipes = 3, 308 .has_hotplug = 1, 309 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 310 .is_cherryview = 1, 311 .has_psr = 1, 312 .has_runtime_pm = 1, 313 .has_resource_streamer = 1, 314 .has_rc6 = 1, 315 .has_gmbus_irq = 1, 316 .has_hw_contexts = 1, 317 .has_logical_ring_contexts = 1, 318 .has_gmch_display = 1, 319 .display_mmio_offset = VLV_DISPLAY_BASE, 320 GEN_CHV_PIPEOFFSETS, 321 CURSOR_OFFSETS, 322 CHV_COLORS, 323 }; 324 325 #define GEN9_FEATURES \ 326 BDW_FEATURES, \ 327 .gen = 9, \ 328 .ddb_size = 896 329 330 static const struct intel_device_info intel_skylake_info = { 331 BDW_FEATURES, 332 .is_skylake = 1, 333 .gen = 9, 334 .has_csr = 1, 335 .has_guc = 1, 336 .ddb_size = 896, 337 }; 338 339 static const struct intel_device_info intel_skylake_gt3_info = { 340 BDW_FEATURES, 341 .is_skylake = 1, 342 .gen = 9, 343 .has_csr = 1, 344 .has_guc = 1, 345 .ddb_size = 896, 346 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 347 }; 348 349 static const struct intel_device_info intel_broxton_info = { 350 .is_broxton = 1, 351 .gen = 9, 352 .has_hotplug = 1, 353 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 354 .num_pipes = 3, 355 .has_ddi = 1, 356 .has_fpga_dbg = 1, 357 .has_fbc = 1, 358 .has_runtime_pm = 1, 359 .has_pooled_eu = 0, 360 .has_csr = 1, 361 .has_resource_streamer = 1, 362 .has_rc6 = 1, 363 .has_dp_mst = 1, 364 .has_gmbus_irq = 1, 365 .has_hw_contexts = 1, 366 .has_logical_ring_contexts = 1, 367 .has_guc = 1, 368 .ddb_size = 512, 369 GEN_DEFAULT_PIPEOFFSETS, 370 IVB_CURSOR_OFFSETS, 371 BDW_COLORS, 372 }; 373 374 #define KBL_PLATFORM \ 375 GEN9_FEATURES, \ 376 .is_kabylake = 1 377 378 static const struct intel_device_info intel_kabylake_gt1_info = { 379 KBL_PLATFORM, 380 }; 381 382 static const struct intel_device_info intel_kabylake_gt2_info = { 383 BDW_FEATURES, 384 .is_kabylake = 1, 385 .gen = 9, 386 .has_csr = 1, 387 .has_guc = 1, 388 .ddb_size = 896, 389 }; 390 391 static const struct intel_device_info intel_kabylake_gt3_info = { 392 BDW_FEATURES, 393 .is_kabylake = 1, 394 .gen = 9, 395 .has_csr = 1, 396 .has_guc = 1, 397 .ddb_size = 896, 398 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 399 }; 400 401 #define CFL_PLATFORM \ 402 GEN9_FEATURES, \ 403 .is_kabylake = 1 404 405 static const struct intel_device_info intel_coffeelake_gt1_info = { 406 CFL_PLATFORM, 407 }; 408 409 static const struct intel_device_info intel_coffeelake_gt2_info = { 410 CFL_PLATFORM, 411 }; 412 413 static const struct intel_device_info intel_coffeelake_gt3_info = { 414 CFL_PLATFORM, 415 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 416 }; 417 418 /* 419 * Make sure any device matches here are from most specific to most 420 * general. For example, since the Quanta match is based on the subsystem 421 * and subvendor IDs, we need it to come before the more general IVB 422 * PCI ID matches, otherwise we'll use the wrong info struct above. 423 */ 424 static const struct pci_device_id pciidlist[] = { 425 INTEL_I830_IDS(&intel_i830_info), 426 INTEL_I845G_IDS(&intel_845g_info), 427 INTEL_I85X_IDS(&intel_i85x_info), 428 INTEL_I865G_IDS(&intel_i865g_info), 429 INTEL_I915G_IDS(&intel_i915g_info), 430 INTEL_I915GM_IDS(&intel_i915gm_info), 431 INTEL_I945G_IDS(&intel_i945g_info), 432 INTEL_I945GM_IDS(&intel_i945gm_info), 433 INTEL_I965G_IDS(&intel_i965g_info), 434 INTEL_G33_IDS(&intel_g33_info), 435 INTEL_I965GM_IDS(&intel_i965gm_info), 436 INTEL_GM45_IDS(&intel_gm45_info), 437 INTEL_G45_IDS(&intel_g45_info), 438 INTEL_PINEVIEW_IDS(&intel_pineview_info), 439 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 440 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 441 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 442 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 443 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 444 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 445 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 446 INTEL_HSW_IDS(&intel_haswell_info), 447 INTEL_VLV_IDS(&intel_valleyview_info), 448 INTEL_BDW_GT12_IDS(&intel_broadwell_info), 449 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info), 450 INTEL_CHV_IDS(&intel_cherryview_info), 451 INTEL_SKL_GT1_IDS(&intel_skylake_info), 452 INTEL_SKL_GT2_IDS(&intel_skylake_info), 453 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 454 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 455 INTEL_BXT_IDS(&intel_broxton_info), 456 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 457 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 458 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 459 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 460 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info), 461 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 462 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 463 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info), 464 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 465 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 466 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 467 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 468 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 469 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info), 470 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 471 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info), 472 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info), 473 {0, 0, 0} 474 }; 475 MODULE_DEVICE_TABLE(pci, pciidlist); 476 477 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 478 { 479 struct intel_device_info *intel_info = 480 (struct intel_device_info *) ent->driver_data; 481 482 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { 483 DRM_INFO("This hardware requires preliminary hardware support.\n" 484 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); 485 return -ENODEV; 486 } 487 488 /* Only bind to function 0 of the device. Early generations 489 * used function 1 as a placeholder for multi-head. This causes 490 * us confusion instead, especially on the systems where both 491 * functions have the same PCI-ID! 492 */ 493 if (PCI_FUNC(pdev->devfn)) 494 return -ENODEV; 495 496 /* 497 * apple-gmux is needed on dual GPU MacBook Pro 498 * to probe the panel if we're the inactive GPU. 499 */ 500 if (vga_switcheroo_client_probe_defer(pdev)) 501 return -EPROBE_DEFER; 502 503 return i915_driver_load(pdev, ent); 504 } 505 506 static void i915_pci_remove(struct pci_dev *pdev) 507 { 508 struct drm_device *dev = pci_get_drvdata(pdev); 509 510 i915_driver_unload(dev); 511 drm_dev_unref(dev); 512 } 513 514 static struct pci_driver i915_pci_driver = { 515 .name = DRIVER_NAME, 516 .id_table = pciidlist, 517 .probe = i915_pci_probe, 518 .remove = i915_pci_remove, 519 #if 0 520 .driver.pm = &i915_pm_ops, 521 #endif 522 }; 523 524 static int __init i915_init(void) 525 { 526 bool use_kms = true; 527 528 /* 529 * Enable KMS by default, unless explicitly overriden by 530 * either the i915.modeset prarameter or by the 531 * vga_text_mode_force boot option. 532 */ 533 534 if (i915.modeset == 0) 535 use_kms = false; 536 537 if (vgacon_text_force() && i915.modeset == -1) 538 use_kms = false; 539 540 if (!use_kms) { 541 /* Silently fail loading to not upset userspace. */ 542 DRM_DEBUG_DRIVER("KMS disabled.\n"); 543 return 0; 544 } 545 546 return pci_register_driver(&i915_pci_driver); 547 } 548 549 static void __exit i915_exit(void) 550 { 551 #if 0 552 if (!i915_pci_driver.driver.owner) 553 return; 554 #endif 555 556 pci_unregister_driver(&i915_pci_driver); 557 } 558 559 module_init(i915_init); 560 module_exit(i915_exit); 561 562 MODULE_AUTHOR("Tungsten Graphics, Inc."); 563 MODULE_AUTHOR("Intel Corporation"); 564 565 static int 566 i915_pci_probe_dfly(device_t kdev) 567 { 568 int device, i = 0; 569 const struct pci_device_id *ent; 570 static struct pci_dev *pdev = NULL; 571 static device_t bsddev; 572 573 if (pci_get_class(kdev) != PCIC_DISPLAY) 574 return ENXIO; 575 576 if (pci_get_vendor(kdev) != PCI_VENDOR_ID_INTEL) 577 return ENXIO; 578 579 device = pci_get_device(kdev); 580 581 for (i = 0; pciidlist[i].device != 0; i++) { 582 if (pciidlist[i].device == device) { 583 ent = &pciidlist[i]; 584 goto found; 585 } 586 } 587 588 return ENXIO; 589 found: 590 if (!strcmp(device_get_name(kdev), "drmsub")) 591 bsddev = device_get_parent(kdev); 592 else 593 bsddev = kdev; 594 595 drm_init_pdev(bsddev, &pdev); 596 597 /* Print the contents of pdev struct. */ 598 drm_print_pdev(pdev); 599 600 return i915_pci_probe(pdev, ent); 601 } 602 603 static int i915_driver_attach(device_t kdev) 604 { 605 return 0; 606 } 607 608 static device_method_t i915_methods[] = { 609 /* Device interface */ 610 DEVMETHOD(device_probe, i915_pci_probe_dfly), 611 DEVMETHOD(device_attach, i915_driver_attach), 612 DEVMETHOD(device_suspend, i915_suspend_switcheroo), 613 DEVMETHOD(device_resume, i915_resume_switcheroo), 614 DEVMETHOD(device_detach, drm_release), 615 DEVMETHOD_END 616 }; 617 618 static driver_t i915_driver = { 619 "drm", 620 i915_methods, 621 sizeof(struct drm_softc) 622 }; 623 624 extern devclass_t drm_devclass; 625 626 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY); 627 MODULE_DEPEND(i915, drm, 1, 1, 1); 628 #ifdef CONFIG_ACPI 629 MODULE_DEPEND(i915, acpi, 1, 1, 1); 630 #endif 631