1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/console.h> 26 #include <linux/vgaarb.h> 27 #include <linux/vga_switcheroo.h> 28 29 #include "i915_drv.h" 30 31 #define GEN_DEFAULT_PIPEOFFSETS \ 32 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 33 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 34 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 35 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 36 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 37 38 #define GEN_CHV_PIPEOFFSETS \ 39 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 40 CHV_PIPE_C_OFFSET }, \ 41 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 42 CHV_TRANSCODER_C_OFFSET, }, \ 43 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 44 CHV_PALETTE_C_OFFSET } 45 46 #define CURSOR_OFFSETS \ 47 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 48 49 #define IVB_CURSOR_OFFSETS \ 50 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 51 52 #define BDW_COLORS \ 53 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 54 #define CHV_COLORS \ 55 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 56 57 static const struct intel_device_info intel_i830_info = { 58 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 59 .has_overlay = 1, .overlay_needs_physical = 1, 60 .ring_mask = RENDER_RING, 61 GEN_DEFAULT_PIPEOFFSETS, 62 CURSOR_OFFSETS, 63 }; 64 65 static const struct intel_device_info intel_845g_info = { 66 .gen = 2, .num_pipes = 1, 67 .has_overlay = 1, .overlay_needs_physical = 1, 68 .ring_mask = RENDER_RING, 69 GEN_DEFAULT_PIPEOFFSETS, 70 CURSOR_OFFSETS, 71 }; 72 73 static const struct intel_device_info intel_i85x_info = { 74 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, 75 .cursor_needs_physical = 1, 76 .has_overlay = 1, .overlay_needs_physical = 1, 77 .has_fbc = 1, 78 .ring_mask = RENDER_RING, 79 GEN_DEFAULT_PIPEOFFSETS, 80 CURSOR_OFFSETS, 81 }; 82 83 static const struct intel_device_info intel_i865g_info = { 84 .gen = 2, .num_pipes = 1, 85 .has_overlay = 1, .overlay_needs_physical = 1, 86 .ring_mask = RENDER_RING, 87 GEN_DEFAULT_PIPEOFFSETS, 88 CURSOR_OFFSETS, 89 }; 90 91 static const struct intel_device_info intel_i915g_info = { 92 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, 93 .has_overlay = 1, .overlay_needs_physical = 1, 94 .ring_mask = RENDER_RING, 95 GEN_DEFAULT_PIPEOFFSETS, 96 CURSOR_OFFSETS, 97 }; 98 static const struct intel_device_info intel_i915gm_info = { 99 .gen = 3, .is_mobile = 1, .num_pipes = 2, 100 .cursor_needs_physical = 1, 101 .has_overlay = 1, .overlay_needs_physical = 1, 102 .supports_tv = 1, 103 .has_fbc = 1, 104 .ring_mask = RENDER_RING, 105 GEN_DEFAULT_PIPEOFFSETS, 106 CURSOR_OFFSETS, 107 }; 108 static const struct intel_device_info intel_i945g_info = { 109 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, 110 .has_overlay = 1, .overlay_needs_physical = 1, 111 .ring_mask = RENDER_RING, 112 GEN_DEFAULT_PIPEOFFSETS, 113 CURSOR_OFFSETS, 114 }; 115 static const struct intel_device_info intel_i945gm_info = { 116 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, 117 .has_hotplug = 1, .cursor_needs_physical = 1, 118 .has_overlay = 1, .overlay_needs_physical = 1, 119 .supports_tv = 1, 120 .has_fbc = 1, 121 .ring_mask = RENDER_RING, 122 GEN_DEFAULT_PIPEOFFSETS, 123 CURSOR_OFFSETS, 124 }; 125 126 static const struct intel_device_info intel_i965g_info = { 127 .gen = 4, .is_broadwater = 1, .num_pipes = 2, 128 .has_hotplug = 1, 129 .has_overlay = 1, 130 .ring_mask = RENDER_RING, 131 GEN_DEFAULT_PIPEOFFSETS, 132 CURSOR_OFFSETS, 133 }; 134 135 static const struct intel_device_info intel_i965gm_info = { 136 .gen = 4, .is_crestline = 1, .num_pipes = 2, 137 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 138 .has_overlay = 1, 139 .supports_tv = 1, 140 .ring_mask = RENDER_RING, 141 GEN_DEFAULT_PIPEOFFSETS, 142 CURSOR_OFFSETS, 143 }; 144 145 static const struct intel_device_info intel_g33_info = { 146 .gen = 3, .is_g33 = 1, .num_pipes = 2, 147 .need_gfx_hws = 1, .has_hotplug = 1, 148 .has_overlay = 1, 149 .ring_mask = RENDER_RING, 150 GEN_DEFAULT_PIPEOFFSETS, 151 CURSOR_OFFSETS, 152 }; 153 154 static const struct intel_device_info intel_g45_info = { 155 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, 156 .has_pipe_cxsr = 1, .has_hotplug = 1, 157 .ring_mask = RENDER_RING | BSD_RING, 158 GEN_DEFAULT_PIPEOFFSETS, 159 CURSOR_OFFSETS, 160 }; 161 162 static const struct intel_device_info intel_gm45_info = { 163 .gen = 4, .is_g4x = 1, .num_pipes = 2, 164 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 165 .has_pipe_cxsr = 1, .has_hotplug = 1, 166 .supports_tv = 1, 167 .ring_mask = RENDER_RING | BSD_RING, 168 GEN_DEFAULT_PIPEOFFSETS, 169 CURSOR_OFFSETS, 170 }; 171 172 static const struct intel_device_info intel_pineview_info = { 173 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, 174 .need_gfx_hws = 1, .has_hotplug = 1, 175 .has_overlay = 1, 176 GEN_DEFAULT_PIPEOFFSETS, 177 CURSOR_OFFSETS, 178 }; 179 180 static const struct intel_device_info intel_ironlake_d_info = { 181 .gen = 5, .num_pipes = 2, 182 .need_gfx_hws = 1, .has_hotplug = 1, 183 .ring_mask = RENDER_RING | BSD_RING, 184 GEN_DEFAULT_PIPEOFFSETS, 185 CURSOR_OFFSETS, 186 }; 187 188 static const struct intel_device_info intel_ironlake_m_info = { 189 .gen = 5, .is_mobile = 1, .num_pipes = 2, 190 .need_gfx_hws = 1, .has_hotplug = 1, 191 .has_fbc = 1, 192 .ring_mask = RENDER_RING | BSD_RING, 193 GEN_DEFAULT_PIPEOFFSETS, 194 CURSOR_OFFSETS, 195 }; 196 197 static const struct intel_device_info intel_sandybridge_d_info = { 198 .gen = 6, .num_pipes = 2, 199 .need_gfx_hws = 1, .has_hotplug = 1, 200 .has_fbc = 1, 201 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 202 .has_llc = 1, 203 GEN_DEFAULT_PIPEOFFSETS, 204 CURSOR_OFFSETS, 205 }; 206 207 static const struct intel_device_info intel_sandybridge_m_info = { 208 .gen = 6, .is_mobile = 1, .num_pipes = 2, 209 .need_gfx_hws = 1, .has_hotplug = 1, 210 .has_fbc = 1, 211 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 212 .has_llc = 1, 213 GEN_DEFAULT_PIPEOFFSETS, 214 CURSOR_OFFSETS, 215 }; 216 217 #define GEN7_FEATURES \ 218 .gen = 7, .num_pipes = 3, \ 219 .need_gfx_hws = 1, .has_hotplug = 1, \ 220 .has_fbc = 1, \ 221 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 222 .has_llc = 1, \ 223 GEN_DEFAULT_PIPEOFFSETS, \ 224 IVB_CURSOR_OFFSETS 225 226 static const struct intel_device_info intel_ivybridge_d_info = { 227 GEN7_FEATURES, 228 .is_ivybridge = 1, 229 }; 230 231 static const struct intel_device_info intel_ivybridge_m_info = { 232 GEN7_FEATURES, 233 .is_ivybridge = 1, 234 .is_mobile = 1, 235 }; 236 237 static const struct intel_device_info intel_ivybridge_q_info = { 238 GEN7_FEATURES, 239 .is_ivybridge = 1, 240 .num_pipes = 0, /* legal, last one wins */ 241 }; 242 243 #define VLV_FEATURES \ 244 .gen = 7, .num_pipes = 2, \ 245 .need_gfx_hws = 1, .has_hotplug = 1, \ 246 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 247 .display_mmio_offset = VLV_DISPLAY_BASE, \ 248 GEN_DEFAULT_PIPEOFFSETS, \ 249 CURSOR_OFFSETS 250 251 static const struct intel_device_info intel_valleyview_m_info = { 252 VLV_FEATURES, 253 .is_valleyview = 1, 254 .is_mobile = 1, 255 }; 256 257 static const struct intel_device_info intel_valleyview_d_info = { 258 VLV_FEATURES, 259 .is_valleyview = 1, 260 }; 261 262 #define HSW_FEATURES \ 263 GEN7_FEATURES, \ 264 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 265 .has_ddi = 1, \ 266 .has_fpga_dbg = 1 267 268 static const struct intel_device_info intel_haswell_d_info = { 269 HSW_FEATURES, 270 .is_haswell = 1, 271 }; 272 273 static const struct intel_device_info intel_haswell_m_info = { 274 HSW_FEATURES, 275 .is_haswell = 1, 276 .is_mobile = 1, 277 }; 278 279 #define BDW_FEATURES \ 280 HSW_FEATURES, \ 281 BDW_COLORS 282 283 static const struct intel_device_info intel_broadwell_d_info = { 284 BDW_FEATURES, 285 .gen = 8, 286 .is_broadwell = 1, 287 }; 288 289 static const struct intel_device_info intel_broadwell_m_info = { 290 BDW_FEATURES, 291 .gen = 8, .is_mobile = 1, 292 .is_broadwell = 1, 293 }; 294 295 static const struct intel_device_info intel_broadwell_gt3d_info = { 296 BDW_FEATURES, 297 .gen = 8, 298 .is_broadwell = 1, 299 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 300 }; 301 302 static const struct intel_device_info intel_broadwell_gt3m_info = { 303 BDW_FEATURES, 304 .gen = 8, .is_mobile = 1, 305 .is_broadwell = 1, 306 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 307 }; 308 309 static const struct intel_device_info intel_cherryview_info = { 310 .gen = 8, .num_pipes = 3, 311 .need_gfx_hws = 1, .has_hotplug = 1, 312 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 313 .is_cherryview = 1, 314 .display_mmio_offset = VLV_DISPLAY_BASE, 315 GEN_CHV_PIPEOFFSETS, 316 CURSOR_OFFSETS, 317 CHV_COLORS, 318 }; 319 320 static const struct intel_device_info intel_skylake_info = { 321 BDW_FEATURES, 322 .is_skylake = 1, 323 .gen = 9, 324 }; 325 326 static const struct intel_device_info intel_skylake_gt3_info = { 327 BDW_FEATURES, 328 .is_skylake = 1, 329 .gen = 9, 330 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 331 }; 332 333 static const struct intel_device_info intel_broxton_info = { 334 .is_broxton = 1, 335 .gen = 9, 336 .need_gfx_hws = 1, .has_hotplug = 1, 337 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 338 .num_pipes = 3, 339 .has_ddi = 1, 340 .has_fpga_dbg = 1, 341 .has_fbc = 1, 342 .has_pooled_eu = 0, 343 GEN_DEFAULT_PIPEOFFSETS, 344 IVB_CURSOR_OFFSETS, 345 BDW_COLORS, 346 }; 347 348 static const struct intel_device_info intel_kabylake_gt1_info = { 349 BDW_FEATURES, 350 .is_kabylake = 1, 351 .gen = 9, 352 }; 353 354 static const struct intel_device_info intel_kabylake_gt2_info = { 355 BDW_FEATURES, 356 .is_kabylake = 1, 357 .gen = 9, 358 }; 359 360 static const struct intel_device_info intel_kabylake_gt3_info = { 361 BDW_FEATURES, 362 .is_kabylake = 1, 363 .gen = 9, 364 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 365 }; 366 367 static const struct intel_device_info intel_coffeelake_gt1_info = { 368 BDW_FEATURES, \ 369 .is_kabylake = 1, 370 .gen = 9, 371 }; 372 373 static const struct intel_device_info intel_coffeelake_gt2_info = { 374 BDW_FEATURES, \ 375 .is_kabylake = 1, 376 .gen = 9, 377 }; 378 379 static const struct intel_device_info intel_coffeelake_gt3_info = { 380 BDW_FEATURES, \ 381 .is_kabylake = 1, 382 .gen = 9, 383 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 384 }; 385 386 /* 387 * Make sure any device matches here are from most specific to most 388 * general. For example, since the Quanta match is based on the subsystem 389 * and subvendor IDs, we need it to come before the more general IVB 390 * PCI ID matches, otherwise we'll use the wrong info struct above. 391 */ 392 static const struct pci_device_id pciidlist[] = { 393 INTEL_I830_IDS(&intel_i830_info), 394 INTEL_I845G_IDS(&intel_845g_info), 395 INTEL_I85X_IDS(&intel_i85x_info), 396 INTEL_I865G_IDS(&intel_i865g_info), 397 INTEL_I915G_IDS(&intel_i915g_info), 398 INTEL_I915GM_IDS(&intel_i915gm_info), 399 INTEL_I945G_IDS(&intel_i945g_info), 400 INTEL_I945GM_IDS(&intel_i945gm_info), 401 INTEL_I965G_IDS(&intel_i965g_info), 402 INTEL_G33_IDS(&intel_g33_info), 403 INTEL_I965GM_IDS(&intel_i965gm_info), 404 INTEL_GM45_IDS(&intel_gm45_info), 405 INTEL_G45_IDS(&intel_g45_info), 406 INTEL_PINEVIEW_IDS(&intel_pineview_info), 407 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 408 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 409 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 410 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 411 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 412 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 413 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 414 INTEL_HSW_D_IDS(&intel_haswell_d_info), 415 INTEL_HSW_M_IDS(&intel_haswell_m_info), 416 INTEL_VLV_M_IDS(&intel_valleyview_m_info), 417 INTEL_VLV_D_IDS(&intel_valleyview_d_info), 418 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), 419 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), 420 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), 421 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), 422 INTEL_CHV_IDS(&intel_cherryview_info), 423 INTEL_SKL_GT1_IDS(&intel_skylake_info), 424 INTEL_SKL_GT2_IDS(&intel_skylake_info), 425 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 426 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 427 INTEL_BXT_IDS(&intel_broxton_info), 428 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info), 429 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info), 430 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 431 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 432 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info), 433 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 434 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 435 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info), 436 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 437 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 438 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 439 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 440 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 441 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info), 442 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 443 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info), 444 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info), 445 {0, 0, 0} 446 }; 447 MODULE_DEVICE_TABLE(pci, pciidlist); 448 449 extern int i915_driver_load(struct pci_dev *pdev, 450 const struct pci_device_id *ent); 451 452 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 453 { 454 struct intel_device_info *intel_info = 455 (struct intel_device_info *) ent->driver_data; 456 457 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { 458 DRM_INFO("This hardware requires preliminary hardware support.\n" 459 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); 460 return -ENODEV; 461 } 462 463 /* Only bind to function 0 of the device. Early generations 464 * used function 1 as a placeholder for multi-head. This causes 465 * us confusion instead, especially on the systems where both 466 * functions have the same PCI-ID! 467 */ 468 if (PCI_FUNC(pdev->devfn)) 469 return -ENODEV; 470 471 /* 472 * apple-gmux is needed on dual GPU MacBook Pro 473 * to probe the panel if we're the inactive GPU. 474 */ 475 if (vga_switcheroo_client_probe_defer(pdev)) 476 return -EPROBE_DEFER; 477 478 return i915_driver_load(pdev, ent); 479 } 480 481 extern void i915_driver_unload(struct drm_device *dev); 482 483 static void i915_pci_remove(struct pci_dev *pdev) 484 { 485 struct drm_device *dev = pci_get_drvdata(pdev); 486 487 i915_driver_unload(dev); 488 drm_dev_unref(dev); 489 } 490 491 extern const struct dev_pm_ops i915_pm_ops; 492 493 static struct pci_driver i915_pci_driver = { 494 .name = DRIVER_NAME, 495 .id_table = pciidlist, 496 .probe = i915_pci_probe, 497 .remove = i915_pci_remove, 498 #if 0 499 .driver.pm = &i915_pm_ops, 500 #endif 501 }; 502 503 static int __init i915_init(void) 504 { 505 bool use_kms = true; 506 507 /* 508 * Enable KMS by default, unless explicitly overriden by 509 * either the i915.modeset prarameter or by the 510 * vga_text_mode_force boot option. 511 */ 512 513 if (i915.modeset == 0) 514 use_kms = false; 515 516 if (vgacon_text_force() && i915.modeset == -1) 517 use_kms = false; 518 519 if (!use_kms) { 520 /* Silently fail loading to not upset userspace. */ 521 DRM_DEBUG_DRIVER("KMS disabled.\n"); 522 return 0; 523 } 524 525 return pci_register_driver(&i915_pci_driver); 526 } 527 528 static void __exit i915_exit(void) 529 { 530 #if 0 531 if (!i915_pci_driver.driver.owner) 532 return; 533 #endif 534 535 pci_unregister_driver(&i915_pci_driver); 536 } 537 538 module_init(i915_init); 539 module_exit(i915_exit); 540 541 MODULE_AUTHOR("Tungsten Graphics, Inc."); 542 MODULE_AUTHOR("Intel Corporation"); 543 544 static int 545 i915_pci_probe_dfly(device_t kdev) 546 { 547 int device, i = 0; 548 const struct pci_device_id *ent; 549 static struct pci_dev *pdev = NULL; 550 static device_t bsddev; 551 552 if (pci_get_class(kdev) != PCIC_DISPLAY) 553 return ENXIO; 554 555 if (pci_get_vendor(kdev) != PCI_VENDOR_ID_INTEL) 556 return ENXIO; 557 558 device = pci_get_device(kdev); 559 560 for (i = 0; pciidlist[i].device != 0; i++) { 561 if (pciidlist[i].device == device) { 562 ent = &pciidlist[i]; 563 goto found; 564 } 565 } 566 567 return ENXIO; 568 found: 569 if (!strcmp(device_get_name(kdev), "drmsub")) 570 bsddev = device_get_parent(kdev); 571 else 572 bsddev = kdev; 573 574 drm_init_pdev(bsddev, &pdev); 575 576 /* Print the contents of pdev struct. */ 577 drm_print_pdev(pdev); 578 579 return i915_pci_probe(pdev, ent); 580 } 581 582 static int i915_driver_attach(device_t kdev) 583 { 584 return 0; 585 } 586 587 static device_method_t i915_methods[] = { 588 /* Device interface */ 589 DEVMETHOD(device_probe, i915_pci_probe_dfly), 590 DEVMETHOD(device_attach, i915_driver_attach), 591 DEVMETHOD(device_suspend, i915_suspend_switcheroo), 592 DEVMETHOD(device_resume, i915_resume_switcheroo), 593 DEVMETHOD(device_detach, drm_release), 594 DEVMETHOD_END 595 }; 596 597 static driver_t i915_driver = { 598 "drm", 599 i915_methods, 600 sizeof(struct drm_softc) 601 }; 602 603 extern devclass_t drm_devclass; 604 605 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY); 606 MODULE_DEPEND(i915, drm, 1, 1, 1); 607 #ifdef CONFIG_ACPI 608 MODULE_DEPEND(i915, acpi, 1, 1, 1); 609 #endif 610