1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * $FreeBSD: src/sys/dev/drm2/i915/i915_reg.h,v 1.1 2012/05/22 11:07:44 kib Exp $" 25 */ 26 27 #ifndef _I915_REG_H_ 28 #define _I915_REG_H_ 29 30 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 31 32 /* 33 * The Bridge device's PCI config space has information about the 34 * fb aperture size and the amount of pre-reserved memory. 35 * This is all handled in the intel-gtt.ko module. i915.ko only 36 * cares about the vga bit for the vga rbiter. 37 */ 38 #define INTEL_GMCH_CTRL 0x52 39 #define INTEL_GMCH_VGA_DISABLE (1 << 1) 40 41 /* PCI config space */ 42 43 #define HPLLCC 0xc0 /* 855 only */ 44 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 45 #define GC_CLOCK_133_200 (0 << 0) 46 #define GC_CLOCK_100_200 (1 << 0) 47 #define GC_CLOCK_100_133 (2 << 0) 48 #define GC_CLOCK_166_250 (3 << 0) 49 #define GCFGC2 0xda 50 #define GCFGC 0xf0 /* 915+ only */ 51 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 52 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 53 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 54 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 55 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 56 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 57 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 58 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 59 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 60 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 61 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 62 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 63 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 64 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 65 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 66 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 67 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 68 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 69 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 70 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 71 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 72 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 73 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 74 #define LBB 0xf4 75 76 /* Graphics reset regs */ 77 #define I965_GDRST 0xc0 /* PCI config register */ 78 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 79 #define GRDOM_FULL (0<<2) 80 #define GRDOM_RENDER (1<<2) 81 #define GRDOM_MEDIA (3<<2) 82 83 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 84 #define GEN6_MBC_SNPCR_SHIFT 21 85 #define GEN6_MBC_SNPCR_MASK (3<<21) 86 #define GEN6_MBC_SNPCR_MAX (0<<21) 87 #define GEN6_MBC_SNPCR_MED (1<<21) 88 #define GEN6_MBC_SNPCR_LOW (2<<21) 89 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 90 91 #define GEN6_MBCTL 0x0907c 92 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 93 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 94 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 95 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 96 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 97 98 #define GEN6_GDRST 0x941c 99 #define GEN6_GRDOM_FULL (1 << 0) 100 #define GEN6_GRDOM_RENDER (1 << 1) 101 #define GEN6_GRDOM_MEDIA (1 << 2) 102 #define GEN6_GRDOM_BLT (1 << 3) 103 104 /* PPGTT stuff */ 105 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 106 107 #define GEN6_PDE_VALID (1 << 0) 108 #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */ 109 /* gen6+ has bit 11-4 for physical addr bit 39-32 */ 110 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 111 112 #define GEN6_PTE_VALID (1 << 0) 113 #define GEN6_PTE_UNCACHED (1 << 1) 114 #define GEN6_PTE_CACHE_LLC (2 << 1) 115 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) 116 #define GEN6_PTE_CACHE_BITS (3 << 1) 117 #define GEN6_PTE_GFDT (1 << 3) 118 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 119 120 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 121 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 122 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 123 #define PP_DIR_DCLV_2G 0xffffffff 124 125 #define GAM_ECOCHK 0x4090 126 #define ECOCHK_SNB_BIT (1<<10) 127 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 128 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 129 130 /* VGA stuff */ 131 132 #define VGA_ST01_MDA 0x3ba 133 #define VGA_ST01_CGA 0x3da 134 135 #define VGA_MSR_WRITE 0x3c2 136 #define VGA_MSR_READ 0x3cc 137 #define VGA_MSR_MEM_EN (1<<1) 138 #define VGA_MSR_CGA_MODE (1<<0) 139 140 #define VGA_SR_INDEX 0x3c4 141 #define VGA_SR_DATA 0x3c5 142 143 #define VGA_AR_INDEX 0x3c0 144 #define VGA_AR_VID_EN (1<<5) 145 #define VGA_AR_DATA_WRITE 0x3c0 146 #define VGA_AR_DATA_READ 0x3c1 147 148 #define VGA_GR_INDEX 0x3ce 149 #define VGA_GR_DATA 0x3cf 150 /* GR05 */ 151 #define VGA_GR_MEM_READ_MODE_SHIFT 3 152 #define VGA_GR_MEM_READ_MODE_PLANE 1 153 /* GR06 */ 154 #define VGA_GR_MEM_MODE_MASK 0xc 155 #define VGA_GR_MEM_MODE_SHIFT 2 156 #define VGA_GR_MEM_A0000_AFFFF 0 157 #define VGA_GR_MEM_A0000_BFFFF 1 158 #define VGA_GR_MEM_B0000_B7FFF 2 159 #define VGA_GR_MEM_B0000_BFFFF 3 160 161 #define VGA_DACMASK 0x3c6 162 #define VGA_DACRX 0x3c7 163 #define VGA_DACWX 0x3c8 164 #define VGA_DACDATA 0x3c9 165 166 #define VGA_CR_INDEX_MDA 0x3b4 167 #define VGA_CR_DATA_MDA 0x3b5 168 #define VGA_CR_INDEX_CGA 0x3d4 169 #define VGA_CR_DATA_CGA 0x3d5 170 171 /* 172 * Memory interface instructions used by the kernel 173 */ 174 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 175 176 #define MI_NOOP MI_INSTR(0, 0) 177 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 178 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 179 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 180 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 181 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 182 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 183 #define MI_FLUSH MI_INSTR(0x04, 0) 184 #define MI_READ_FLUSH (1 << 0) 185 #define MI_EXE_FLUSH (1 << 1) 186 #define MI_NO_WRITE_FLUSH (1 << 2) 187 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 188 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 189 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 190 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 191 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 192 #define MI_SUSPEND_FLUSH_EN (1<<0) 193 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 194 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 195 #define MI_OVERLAY_CONTINUE (0x0<<21) 196 #define MI_OVERLAY_ON (0x1<<21) 197 #define MI_OVERLAY_OFF (0x2<<21) 198 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 199 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 200 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 201 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 202 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 203 #define MI_MM_SPACE_GTT (1<<8) 204 #define MI_MM_SPACE_PHYSICAL (0<<8) 205 #define MI_SAVE_EXT_STATE_EN (1<<3) 206 #define MI_RESTORE_EXT_STATE_EN (1<<2) 207 #define MI_FORCE_RESTORE (1<<1) 208 #define MI_RESTORE_INHIBIT (1<<0) 209 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 210 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 211 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 212 #define MI_STORE_DWORD_INDEX_SHIFT 2 213 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 214 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 215 * simply ignores the register load under certain conditions. 216 * - One can actually load arbitrary many arbitrary registers: Simply issue x 217 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 218 */ 219 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 220 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 221 #define MI_INVALIDATE_TLB (1<<18) 222 #define MI_INVALIDATE_BSD (1<<7) 223 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 224 #define MI_BATCH_NON_SECURE (1) 225 #define MI_BATCH_NON_SECURE_I965 (1<<8) 226 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 227 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 228 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 229 #define MI_SEMAPHORE_UPDATE (1<<21) 230 #define MI_SEMAPHORE_COMPARE (1<<20) 231 #define MI_SEMAPHORE_REGISTER (1<<18) 232 #define MI_SEMAPHORE_SYNC_RV (2<<16) 233 #define MI_SEMAPHORE_SYNC_RB (0<<16) 234 #define MI_SEMAPHORE_SYNC_VR (0<<16) 235 #define MI_SEMAPHORE_SYNC_VB (2<<16) 236 #define MI_SEMAPHORE_SYNC_BR (2<<16) 237 #define MI_SEMAPHORE_SYNC_BV (0<<16) 238 #define MI_SEMAPHORE_SYNC_INVALID (1<<0) 239 /* 240 * 3D instructions used by the kernel 241 */ 242 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 243 244 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 245 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 246 #define SC_UPDATE_SCISSOR (0x1<<1) 247 #define SC_ENABLE_MASK (0x1<<0) 248 #define SC_ENABLE (0x1<<0) 249 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 250 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 251 #define SCI_YMIN_MASK (0xffff<<16) 252 #define SCI_XMIN_MASK (0xffff<<0) 253 #define SCI_YMAX_MASK (0xffff<<16) 254 #define SCI_XMAX_MASK (0xffff<<0) 255 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 256 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 257 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 258 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 259 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 260 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 261 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 262 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 263 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 264 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 265 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 266 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 267 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 268 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 269 #define BLT_DEPTH_8 (0<<24) 270 #define BLT_DEPTH_16_565 (1<<24) 271 #define BLT_DEPTH_16_1555 (2<<24) 272 #define BLT_DEPTH_32 (3<<24) 273 #define BLT_ROP_GXCOPY (0xcc<<16) 274 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 275 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 276 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 277 #define ASYNC_FLIP (1<<22) 278 #define DISPLAY_PLANE_A (0<<20) 279 #define DISPLAY_PLANE_B (1<<20) 280 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 281 #define PIPE_CONTROL_CS_STALL (1<<20) 282 #define PIPE_CONTROL_QW_WRITE (1<<14) 283 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 284 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 285 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 286 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 287 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 288 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 289 #define PIPE_CONTROL_NOTIFY (1<<8) 290 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 291 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 292 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 293 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 294 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 295 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 296 297 298 /* 299 * Reset registers 300 */ 301 #define DEBUG_RESET_I830 0x6070 302 #define DEBUG_RESET_FULL (1<<7) 303 #define DEBUG_RESET_RENDER (1<<8) 304 #define DEBUG_RESET_DISPLAY (1<<9) 305 306 307 /* 308 * Fence registers 309 */ 310 #define FENCE_REG_830_0 0x2000 311 #define FENCE_REG_945_8 0x3000 312 #define I830_FENCE_START_MASK 0x07f80000 313 #define I830_FENCE_TILING_Y_SHIFT 12 314 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 315 #define I830_FENCE_PITCH_SHIFT 4 316 #define I830_FENCE_REG_VALID (1<<0) 317 #define I915_FENCE_MAX_PITCH_VAL 4 318 #define I830_FENCE_MAX_PITCH_VAL 6 319 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 320 321 #define I915_FENCE_START_MASK 0x0ff00000 322 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 323 324 #define FENCE_REG_965_0 0x03000 325 #define I965_FENCE_PITCH_SHIFT 2 326 #define I965_FENCE_TILING_Y_SHIFT 1 327 #define I965_FENCE_REG_VALID (1<<0) 328 #define I965_FENCE_MAX_PITCH_VAL 0x0400 329 330 #define FENCE_REG_SANDYBRIDGE_0 0x100000 331 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 332 333 /* control register for cpu gtt access */ 334 #define TILECTL 0x101000 335 #define TILECTL_SWZCTL (1 << 0) 336 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 337 #define TILECTL_BACKSNOOP_DIS (1 << 3) 338 339 /* 340 * Instruction and interrupt control regs 341 */ 342 #define PGTBL_ER 0x02024 343 #define RENDER_RING_BASE 0x02000 344 #define BSD_RING_BASE 0x04000 345 #define GEN6_BSD_RING_BASE 0x12000 346 #define BLT_RING_BASE 0x22000 347 #define RING_TAIL(base) ((base)+0x30) 348 #define RING_HEAD(base) ((base)+0x34) 349 #define RING_START(base) ((base)+0x38) 350 #define RING_CTL(base) ((base)+0x3c) 351 #define RING_SYNC_0(base) ((base)+0x40) 352 #define RING_SYNC_1(base) ((base)+0x44) 353 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 354 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 355 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 356 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 357 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 358 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 359 #define RING_MAX_IDLE(base) ((base)+0x54) 360 #define RING_HWS_PGA(base) ((base)+0x80) 361 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 362 #define ARB_MODE 0x04030 363 #define ARB_MODE_SWIZZLE_SNB (1<<4) 364 #define ARB_MODE_SWIZZLE_IVB (1<<5) 365 #define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) 366 #define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) 367 #define RENDER_HWS_PGA_GEN7 (0x04080) 368 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 369 #define DONE_REG 0x40b0 370 #define BSD_HWS_PGA_GEN7 (0x04180) 371 #define BLT_HWS_PGA_GEN7 (0x04280) 372 #define RING_ACTHD(base) ((base)+0x74) 373 #define RING_NOPID(base) ((base)+0x94) 374 #define RING_IMR(base) ((base)+0xa8) 375 #define TAIL_ADDR 0x001FFFF8 376 #define HEAD_WRAP_COUNT 0xFFE00000 377 #define HEAD_WRAP_ONE 0x00200000 378 #define HEAD_ADDR 0x001FFFFC 379 #define RING_NR_PAGES 0x001FF000 380 #define RING_REPORT_MASK 0x00000006 381 #define RING_REPORT_64K 0x00000002 382 #define RING_REPORT_128K 0x00000004 383 #define RING_NO_REPORT 0x00000000 384 #define RING_VALID_MASK 0x00000001 385 #define RING_VALID 0x00000001 386 #define RING_INVALID 0x00000000 387 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 388 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 389 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 390 #if 0 391 #define PRB0_TAIL 0x02030 392 #define PRB0_HEAD 0x02034 393 #define PRB0_START 0x02038 394 #define PRB0_CTL 0x0203c 395 #define PRB1_TAIL 0x02040 /* 915+ only */ 396 #define PRB1_HEAD 0x02044 /* 915+ only */ 397 #define PRB1_START 0x02048 /* 915+ only */ 398 #define PRB1_CTL 0x0204c /* 915+ only */ 399 #endif 400 #define IPEIR_I965 0x02064 401 #define IPEHR_I965 0x02068 402 #define INSTDONE_I965 0x0206c 403 #define RING_IPEIR(base) ((base)+0x64) 404 #define RING_IPEHR(base) ((base)+0x68) 405 #define RING_INSTDONE(base) ((base)+0x6c) 406 #define RING_INSTPS(base) ((base)+0x70) 407 #define RING_DMA_FADD(base) ((base)+0x78) 408 #define RING_INSTPM(base) ((base)+0xc0) 409 #define INSTPS 0x02070 /* 965+ only */ 410 #define INSTDONE1 0x0207c /* 965+ only */ 411 #define ACTHD_I965 0x02074 412 #define HWS_PGA 0x02080 413 #define HWS_ADDRESS_MASK 0xfffff000 414 #define HWS_START_ADDRESS_SHIFT 4 415 #define PWRCTXA 0x2088 /* 965GM+ only */ 416 #define PWRCTX_EN (1<<0) 417 #define IPEIR 0x02088 418 #define IPEHR 0x0208c 419 #define INSTDONE 0x02090 420 #define NOPID 0x02094 421 #define HWSTAM 0x02098 422 423 #define ERROR_GEN6 0x040a0 424 425 /* GM45+ chicken bits -- debug workaround bits that may be required 426 * for various sorts of correct behavior. The top 16 bits of each are 427 * the enables for writing to the corresponding low bit. 428 */ 429 #define _3D_CHICKEN 0x02084 430 #define _3D_CHICKEN2 0x0208c 431 /* Disables pipelining of read flushes past the SF-WIZ interface. 432 * Required on all Ironlake steppings according to the B-Spec, but the 433 * particular danger of not doing so is not specified. 434 */ 435 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 436 #define _3D_CHICKEN3 0x02090 437 438 #define MI_MODE 0x0209c 439 # define VS_TIMER_DISPATCH (1 << 6) 440 # define MI_FLUSH_ENABLE (1 << 12) 441 442 #define GFX_MODE 0x02520 443 #define GFX_MODE_GEN7 0x0229c 444 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 445 #define GFX_RUN_LIST_ENABLE (1<<15) 446 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 447 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 448 #define GFX_REPLAY_MODE (1<<11) 449 #define GFX_PSMI_GRANULARITY (1<<10) 450 #define GFX_PPGTT_ENABLE (1<<9) 451 452 #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) 453 #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) 454 455 #define SCPD0 0x0209c /* 915+ only */ 456 #define IER 0x020a0 457 #define IIR 0x020a4 458 #define IMR 0x020a8 459 #define ISR 0x020ac 460 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 461 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 462 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 463 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 464 #define I915_HWB_OOM_INTERRUPT (1<<13) 465 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 466 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 467 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 468 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 469 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 470 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 471 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 472 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 473 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 474 #define I915_DEBUG_INTERRUPT (1<<2) 475 #define I915_USER_INTERRUPT (1<<1) 476 #define I915_ASLE_INTERRUPT (1<<0) 477 #define I915_BSD_USER_INTERRUPT (1<<25) 478 #define EIR 0x020b0 479 #define EMR 0x020b4 480 #define ESR 0x020b8 481 #define GM45_ERROR_PAGE_TABLE (1<<5) 482 #define GM45_ERROR_MEM_PRIV (1<<4) 483 #define I915_ERROR_PAGE_TABLE (1<<4) 484 #define GM45_ERROR_CP_PRIV (1<<3) 485 #define I915_ERROR_MEMORY_REFRESH (1<<1) 486 #define I915_ERROR_INSTRUCTION (1<<0) 487 #define INSTPM 0x020c0 488 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 489 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts 490 will not assert AGPBUSY# and will only 491 be delivered when out of C3. */ 492 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 493 #define ACTHD 0x020c8 494 #define FW_BLC 0x020d8 495 #define FW_BLC2 0x020dc 496 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 497 #define FW_BLC_SELF_EN_MASK (1<<31) 498 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 499 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 500 #define MM_BURST_LENGTH 0x00700000 501 #define MM_FIFO_WATERMARK 0x0001F000 502 #define LM_BURST_LENGTH 0x00000700 503 #define LM_FIFO_WATERMARK 0x0000001F 504 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 505 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ 506 507 /* Make render/texture TLB fetches lower priorty than associated data 508 * fetches. This is not turned on by default 509 */ 510 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 511 512 /* Isoch request wait on GTT enable (Display A/B/C streams). 513 * Make isoch requests stall on the TLB update. May cause 514 * display underruns (test mode only) 515 */ 516 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 517 518 /* Block grant count for isoch requests when block count is 519 * set to a finite value. 520 */ 521 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 522 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 523 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 524 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 525 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 526 527 /* Enable render writes to complete in C2/C3/C4 power states. 528 * If this isn't enabled, render writes are prevented in low 529 * power states. That seems bad to me. 530 */ 531 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 532 533 /* This acknowledges an async flip immediately instead 534 * of waiting for 2TLB fetches. 535 */ 536 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 537 538 /* Enables non-sequential data reads through arbiter 539 */ 540 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 541 542 /* Disable FSB snooping of cacheable write cycles from binner/render 543 * command stream 544 */ 545 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 546 547 /* Arbiter time slice for non-isoch streams */ 548 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 549 #define MI_ARB_TIME_SLICE_1 (0 << 5) 550 #define MI_ARB_TIME_SLICE_2 (1 << 5) 551 #define MI_ARB_TIME_SLICE_4 (2 << 5) 552 #define MI_ARB_TIME_SLICE_6 (3 << 5) 553 #define MI_ARB_TIME_SLICE_8 (4 << 5) 554 #define MI_ARB_TIME_SLICE_10 (5 << 5) 555 #define MI_ARB_TIME_SLICE_14 (6 << 5) 556 #define MI_ARB_TIME_SLICE_16 (7 << 5) 557 558 /* Low priority grace period page size */ 559 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 560 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 561 562 /* Disable display A/B trickle feed */ 563 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 564 565 /* Set display plane priority */ 566 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 567 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 568 569 #define CACHE_MODE_0 0x02120 /* 915+ only */ 570 #define CM0_MASK_SHIFT 16 571 #define CM0_IZ_OPT_DISABLE (1<<6) 572 #define CM0_ZR_OPT_DISABLE (1<<5) 573 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 574 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 575 #define CM0_COLOR_EVICT_DISABLE (1<<3) 576 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 577 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 578 #define BB_ADDR 0x02140 /* 8 bytes */ 579 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 580 #define ECOSKPD 0x021d0 581 #define ECO_GATING_CX_ONLY (1<<3) 582 #define ECO_FLIP_DONE (1<<0) 583 584 /* GEN6 interrupt control */ 585 #define GEN6_RENDER_HWSTAM 0x2098 586 #define GEN6_RENDER_IMR 0x20a8 587 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) 588 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) 589 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) 590 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) 591 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) 592 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) 593 #define GEN6_RENDER_SYNC_STATUS (1 << 2) 594 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) 595 #define GEN6_RENDER_USER_INTERRUPT (1 << 0) 596 597 #define GEN6_BLITTER_HWSTAM 0x22098 598 #define GEN6_BLITTER_IMR 0x220a8 599 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) 600 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) 601 #define GEN6_BLITTER_SYNC_STATUS (1 << 24) 602 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) 603 604 #define GEN6_BLITTER_ECOSKPD 0x221d0 605 #define GEN6_BLITTER_LOCK_SHIFT 16 606 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 607 608 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 609 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) 610 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) 611 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 612 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) 613 614 #define GEN6_BSD_HWSTAM 0x12098 615 #define GEN6_BSD_IMR 0x120a8 616 #define GEN6_BSD_USER_INTERRUPT (1 << 12) 617 618 #define GEN6_BSD_RNCID 0x12198 619 620 /* 621 * Framebuffer compression (915+ only) 622 */ 623 624 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 625 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 626 #define FBC_CONTROL 0x03208 627 #define FBC_CTL_EN (1<<31) 628 #define FBC_CTL_PERIODIC (1<<30) 629 #define FBC_CTL_INTERVAL_SHIFT (16) 630 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 631 #define FBC_CTL_C3_IDLE (1<<13) 632 #define FBC_CTL_STRIDE_SHIFT (5) 633 #define FBC_CTL_FENCENO (1<<0) 634 #define FBC_COMMAND 0x0320c 635 #define FBC_CMD_COMPRESS (1<<0) 636 #define FBC_STATUS 0x03210 637 #define FBC_STAT_COMPRESSING (1<<31) 638 #define FBC_STAT_COMPRESSED (1<<30) 639 #define FBC_STAT_MODIFIED (1<<29) 640 #define FBC_STAT_CURRENT_LINE (1<<0) 641 #define FBC_CONTROL2 0x03214 642 #define FBC_CTL_FENCE_DBL (0<<4) 643 #define FBC_CTL_IDLE_IMM (0<<2) 644 #define FBC_CTL_IDLE_FULL (1<<2) 645 #define FBC_CTL_IDLE_LINE (2<<2) 646 #define FBC_CTL_IDLE_DEBUG (3<<2) 647 #define FBC_CTL_CPU_FENCE (1<<1) 648 #define FBC_CTL_PLANEA (0<<0) 649 #define FBC_CTL_PLANEB (1<<0) 650 #define FBC_FENCE_OFF 0x0321b 651 #define FBC_TAG 0x03300 652 653 #define FBC_LL_SIZE (1536) 654 655 /* Framebuffer compression for GM45+ */ 656 #define DPFC_CB_BASE 0x3200 657 #define DPFC_CONTROL 0x3208 658 #define DPFC_CTL_EN (1<<31) 659 #define DPFC_CTL_PLANEA (0<<30) 660 #define DPFC_CTL_PLANEB (1<<30) 661 #define DPFC_CTL_FENCE_EN (1<<29) 662 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 663 #define DPFC_SR_EN (1<<10) 664 #define DPFC_CTL_LIMIT_1X (0<<6) 665 #define DPFC_CTL_LIMIT_2X (1<<6) 666 #define DPFC_CTL_LIMIT_4X (2<<6) 667 #define DPFC_RECOMP_CTL 0x320c 668 #define DPFC_RECOMP_STALL_EN (1<<27) 669 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 670 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 671 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 672 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 673 #define DPFC_STATUS 0x3210 674 #define DPFC_INVAL_SEG_SHIFT (16) 675 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 676 #define DPFC_COMP_SEG_SHIFT (0) 677 #define DPFC_COMP_SEG_MASK (0x000003ff) 678 #define DPFC_STATUS2 0x3214 679 #define DPFC_FENCE_YOFF 0x3218 680 #define DPFC_CHICKEN 0x3224 681 #define DPFC_HT_MODIFY (1<<31) 682 683 /* Framebuffer compression for Ironlake */ 684 #define ILK_DPFC_CB_BASE 0x43200 685 #define ILK_DPFC_CONTROL 0x43208 686 /* The bit 28-8 is reserved */ 687 #define DPFC_RESERVED (0x1FFFFF00) 688 #define ILK_DPFC_RECOMP_CTL 0x4320c 689 #define ILK_DPFC_STATUS 0x43210 690 #define ILK_DPFC_FENCE_YOFF 0x43218 691 #define ILK_DPFC_CHICKEN 0x43224 692 #define ILK_FBC_RT_BASE 0x2128 693 #define ILK_FBC_RT_VALID (1<<0) 694 695 #define ILK_DISPLAY_CHICKEN1 0x42000 696 #define ILK_FBCQ_DIS (1<<22) 697 #define ILK_PABSTRETCH_DIS (1<<21) 698 699 700 /* 701 * Framebuffer compression for Sandybridge 702 * 703 * The following two registers are of type GTTMMADR 704 */ 705 #define SNB_DPFC_CTL_SA 0x100100 706 #define SNB_CPU_FENCE_ENABLE (1<<29) 707 #define DPFC_CPU_FENCE_OFFSET 0x100104 708 709 710 /* 711 * GPIO regs 712 */ 713 #define GPIOA 0x5010 714 #define GPIOB 0x5014 715 #define GPIOC 0x5018 716 #define GPIOD 0x501c 717 #define GPIOE 0x5020 718 #define GPIOF 0x5024 719 #define GPIOG 0x5028 720 #define GPIOH 0x502c 721 # define GPIO_CLOCK_DIR_MASK (1 << 0) 722 # define GPIO_CLOCK_DIR_IN (0 << 1) 723 # define GPIO_CLOCK_DIR_OUT (1 << 1) 724 # define GPIO_CLOCK_VAL_MASK (1 << 2) 725 # define GPIO_CLOCK_VAL_OUT (1 << 3) 726 # define GPIO_CLOCK_VAL_IN (1 << 4) 727 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 728 # define GPIO_DATA_DIR_MASK (1 << 8) 729 # define GPIO_DATA_DIR_IN (0 << 9) 730 # define GPIO_DATA_DIR_OUT (1 << 9) 731 # define GPIO_DATA_VAL_MASK (1 << 10) 732 # define GPIO_DATA_VAL_OUT (1 << 11) 733 # define GPIO_DATA_VAL_IN (1 << 12) 734 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 735 736 #define GMBUS0 0x5100 /* clock/port select */ 737 #define GMBUS_RATE_100KHZ (0<<8) 738 #define GMBUS_RATE_50KHZ (1<<8) 739 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 740 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 741 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 742 #define GMBUS_PORT_DISABLED 0 743 #define GMBUS_PORT_SSC 1 744 #define GMBUS_PORT_VGADDC 2 745 #define GMBUS_PORT_PANEL 3 746 #define GMBUS_PORT_DPC 4 /* HDMIC */ 747 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 748 /* 6 reserved */ 749 #define GMBUS_PORT_DPD 7 /* HDMID */ 750 #define GMBUS_NUM_PORTS 8 751 #define GMBUS1 0x5104 /* command/status */ 752 #define GMBUS_SW_CLR_INT (1<<31) 753 #define GMBUS_SW_RDY (1<<30) 754 #define GMBUS_ENT (1<<29) /* enable timeout */ 755 #define GMBUS_CYCLE_NONE (0<<25) 756 #define GMBUS_CYCLE_WAIT (1<<25) 757 #define GMBUS_CYCLE_INDEX (2<<25) 758 #define GMBUS_CYCLE_STOP (4<<25) 759 #define GMBUS_BYTE_COUNT_SHIFT 16 760 #define GMBUS_SLAVE_INDEX_SHIFT 8 761 #define GMBUS_SLAVE_ADDR_SHIFT 1 762 #define GMBUS_SLAVE_READ (1<<0) 763 #define GMBUS_SLAVE_WRITE (0<<0) 764 #define GMBUS2 0x5108 /* status */ 765 #define GMBUS_INUSE (1<<15) 766 #define GMBUS_HW_WAIT_PHASE (1<<14) 767 #define GMBUS_STALL_TIMEOUT (1<<13) 768 #define GMBUS_INT (1<<12) 769 #define GMBUS_HW_RDY (1<<11) 770 #define GMBUS_SATOER (1<<10) 771 #define GMBUS_ACTIVE (1<<9) 772 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 773 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 774 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 775 #define GMBUS_NAK_EN (1<<3) 776 #define GMBUS_IDLE_EN (1<<2) 777 #define GMBUS_HW_WAIT_EN (1<<1) 778 #define GMBUS_HW_RDY_EN (1<<0) 779 #define GMBUS5 0x5120 /* byte index */ 780 #define GMBUS_2BYTE_INDEX_EN (1<<31) 781 782 /* 783 * Clock control & power management 784 */ 785 786 #define VGA0 0x6000 787 #define VGA1 0x6004 788 #define VGA_PD 0x6010 789 #define VGA0_PD_P2_DIV_4 (1 << 7) 790 #define VGA0_PD_P1_DIV_2 (1 << 5) 791 #define VGA0_PD_P1_SHIFT 0 792 #define VGA0_PD_P1_MASK (0x1f << 0) 793 #define VGA1_PD_P2_DIV_4 (1 << 15) 794 #define VGA1_PD_P1_DIV_2 (1 << 13) 795 #define VGA1_PD_P1_SHIFT 8 796 #define VGA1_PD_P1_MASK (0x1f << 8) 797 #define _DPLL_A 0x06014 798 #define _DPLL_B 0x06018 799 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) 800 #define DPLL_VCO_ENABLE (1 << 31) 801 #define DPLL_DVO_HIGH_SPEED (1 << 30) 802 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 803 #define DPLL_VGA_MODE_DIS (1 << 28) 804 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 805 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 806 #define DPLL_MODE_MASK (3 << 26) 807 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 808 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 809 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 810 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 811 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 812 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 813 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 814 815 #define SRX_INDEX 0x3c4 816 #define SRX_DATA 0x3c5 817 #define SR01 1 818 #define SR01_SCREEN_OFF (1<<5) 819 820 #define PPCR 0x61204 821 #define PPCR_ON (1<<0) 822 823 #define DVOB 0x61140 824 #define DVOB_ON (1<<31) 825 #define DVOC 0x61160 826 #define DVOC_ON (1<<31) 827 #define LVDS 0x61180 828 #define LVDS_ON (1<<31) 829 830 /* Scratch pad debug 0 reg: 831 */ 832 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 833 /* 834 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 835 * this field (only one bit may be set). 836 */ 837 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 838 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 839 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 840 /* i830, required in DVO non-gang */ 841 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 842 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 843 #define PLL_REF_INPUT_DREFCLK (0 << 13) 844 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 845 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 846 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 847 #define PLL_REF_INPUT_MASK (3 << 13) 848 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 849 /* Ironlake */ 850 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 851 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 852 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 853 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 854 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 855 856 /* 857 * Parallel to Serial Load Pulse phase selection. 858 * Selects the phase for the 10X DPLL clock for the PCIe 859 * digital display port. The range is 4 to 13; 10 or more 860 * is just a flip delay. The default is 6 861 */ 862 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 863 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 864 /* 865 * SDVO multiplier for 945G/GM. Not used on 965. 866 */ 867 #define SDVO_MULTIPLIER_MASK 0x000000ff 868 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 869 #define SDVO_MULTIPLIER_SHIFT_VGA 0 870 #define _DPLL_A_MD 0x0601c /* 965+ only */ 871 /* 872 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 873 * 874 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 875 */ 876 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 877 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 878 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 879 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 880 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 881 /* 882 * SDVO/UDI pixel multiplier. 883 * 884 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 885 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 886 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 887 * dummy bytes in the datastream at an increased clock rate, with both sides of 888 * the link knowing how many bytes are fill. 889 * 890 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 891 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 892 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 893 * through an SDVO command. 894 * 895 * This register field has values of multiplication factor minus 1, with 896 * a maximum multiplier of 5 for SDVO. 897 */ 898 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 899 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 900 /* 901 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 902 * This best be set to the default value (3) or the CRT won't work. No, 903 * I don't entirely understand what this does... 904 */ 905 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 906 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 907 #define _DPLL_B_MD 0x06020 /* 965+ only */ 908 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) 909 #define _FPA0 0x06040 910 #define _FPA1 0x06044 911 #define _FPB0 0x06048 912 #define _FPB1 0x0604c 913 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 914 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 915 #define FP_N_DIV_MASK 0x003f0000 916 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 917 #define FP_N_DIV_SHIFT 16 918 #define FP_M1_DIV_MASK 0x00003f00 919 #define FP_M1_DIV_SHIFT 8 920 #define FP_M2_DIV_MASK 0x0000003f 921 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 922 #define FP_M2_DIV_SHIFT 0 923 #define DPLL_TEST 0x606c 924 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 925 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 926 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 927 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 928 #define DPLLB_TEST_N_BYPASS (1 << 19) 929 #define DPLLB_TEST_M_BYPASS (1 << 18) 930 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 931 #define DPLLA_TEST_N_BYPASS (1 << 3) 932 #define DPLLA_TEST_M_BYPASS (1 << 2) 933 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 934 #define D_STATE 0x6104 935 #define DSTATE_GFX_RESET_I830 (1<<6) 936 #define DSTATE_PLL_D3_OFF (1<<3) 937 #define DSTATE_GFX_CLOCK_GATING (1<<1) 938 #define DSTATE_DOT_CLOCK_GATING (1<<0) 939 #define DSPCLK_GATE_D 0x6200 940 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 941 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 942 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 943 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 944 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 945 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 946 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 947 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 948 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 949 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 950 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 951 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 952 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 953 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 954 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 955 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 956 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 957 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 958 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 959 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 960 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 961 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 962 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 963 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 964 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 965 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 966 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 967 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 968 /** 969 * This bit must be set on the 830 to prevent hangs when turning off the 970 * overlay scaler. 971 */ 972 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 973 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 974 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 975 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 976 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 977 978 #define RENCLK_GATE_D1 0x6204 979 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 980 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 981 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 982 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 983 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 984 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 985 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 986 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 987 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 988 /** This bit must be unset on 855,865 */ 989 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 990 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 991 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 992 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 993 /** This bit must be set on 855,865. */ 994 # define SV_CLOCK_GATE_DISABLE (1 << 0) 995 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 996 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 997 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 998 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 999 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1000 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1001 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1002 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1003 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1004 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1005 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1006 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1007 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1008 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1009 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1010 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1011 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1012 1013 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1014 /** This bit must always be set on 965G/965GM */ 1015 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1016 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1017 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1018 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1019 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1020 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1021 /** This bit must always be set on 965G */ 1022 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1023 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1024 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1025 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1026 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1027 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1028 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1029 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1030 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1031 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1032 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1033 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1034 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1035 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1036 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1037 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1038 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1039 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1040 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1041 1042 #define RENCLK_GATE_D2 0x6208 1043 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1044 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1045 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1046 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 1047 #define DEUC 0x6214 /* CRL only */ 1048 1049 /* 1050 * Palette regs 1051 */ 1052 1053 #define _PALETTE_A 0x0a000 1054 #define _PALETTE_B 0x0a800 1055 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) 1056 1057 /* MCH MMIO space */ 1058 1059 /* 1060 * MCHBAR mirror. 1061 * 1062 * This mirrors the MCHBAR MMIO space whose location is determined by 1063 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1064 * every way. It is not accessible from the CP register read instructions. 1065 * 1066 */ 1067 #define MCHBAR_MIRROR_BASE 0x10000 1068 1069 #define MCHBAR_MIRROR_BASE_SNB 0x140000 1070 1071 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 1072 #define DCC 0x10200 1073 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1074 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1075 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1076 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1077 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1078 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1079 1080 /** Pineview MCH register contains DDR3 setting */ 1081 #define CSHRDDR3CTL 0x101a8 1082 #define CSHRDDR3CTL_DDR3 (1 << 2) 1083 1084 /** 965 MCH register controlling DRAM channel configuration */ 1085 #define C0DRB3 0x10206 1086 #define C1DRB3 0x10606 1087 1088 /** snb MCH registers for reading the DRAM channel configuration */ 1089 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 1090 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 1091 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 1092 #define MAD_DIMM_ECC_MASK (0x3 << 24) 1093 #define MAD_DIMM_ECC_OFF (0x0 << 24) 1094 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 1095 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 1096 #define MAD_DIMM_ECC_ON (0x3 << 24) 1097 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 1098 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 1099 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 1100 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 1101 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 1102 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 1103 #define MAD_DIMM_A_SELECT (0x1 << 16) 1104 /* DIMM sizes are in multiples of 256mb. */ 1105 #define MAD_DIMM_B_SIZE_SHIFT 8 1106 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 1107 #define MAD_DIMM_A_SIZE_SHIFT 0 1108 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 1109 1110 1111 /* Clocking configuration register */ 1112 #define CLKCFG 0x10c00 1113 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1114 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1115 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1116 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1117 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1118 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1119 /* Note, below two are guess */ 1120 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1121 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1122 #define CLKCFG_FSB_MASK (7 << 0) 1123 #define CLKCFG_MEM_533 (1 << 4) 1124 #define CLKCFG_MEM_667 (2 << 4) 1125 #define CLKCFG_MEM_800 (3 << 4) 1126 #define CLKCFG_MEM_MASK (7 << 4) 1127 1128 #define TSC1 0x11001 1129 #define TSE (1<<0) 1130 #define I915_TR1 0x11006 1131 #define TSFS 0x11020 1132 #define TSFS_SLOPE_MASK 0x0000ff00 1133 #define TSFS_SLOPE_SHIFT 8 1134 #define TSFS_INTR_MASK 0x000000ff 1135 1136 #define CRSTANDVID 0x11100 1137 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1138 #define PXVFREQ_PX_MASK 0x7f000000 1139 #define PXVFREQ_PX_SHIFT 24 1140 #define VIDFREQ_BASE 0x11110 1141 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1142 #define VIDFREQ2 0x11114 1143 #define VIDFREQ3 0x11118 1144 #define VIDFREQ4 0x1111c 1145 #define VIDFREQ_P0_MASK 0x1f000000 1146 #define VIDFREQ_P0_SHIFT 24 1147 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1148 #define VIDFREQ_P0_CSCLK_SHIFT 20 1149 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1150 #define VIDFREQ_P0_CRCLK_SHIFT 16 1151 #define VIDFREQ_P1_MASK 0x00001f00 1152 #define VIDFREQ_P1_SHIFT 8 1153 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1154 #define VIDFREQ_P1_CSCLK_SHIFT 4 1155 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1156 #define INTTOEXT_BASE_ILK 0x11300 1157 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1158 #define INTTOEXT_MAP3_SHIFT 24 1159 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1160 #define INTTOEXT_MAP2_SHIFT 16 1161 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1162 #define INTTOEXT_MAP1_SHIFT 8 1163 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1164 #define INTTOEXT_MAP0_SHIFT 0 1165 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1166 #define MEMSWCTL 0x11170 /* Ironlake only */ 1167 #define MEMCTL_CMD_MASK 0xe000 1168 #define MEMCTL_CMD_SHIFT 13 1169 #define MEMCTL_CMD_RCLK_OFF 0 1170 #define MEMCTL_CMD_RCLK_ON 1 1171 #define MEMCTL_CMD_CHFREQ 2 1172 #define MEMCTL_CMD_CHVID 3 1173 #define MEMCTL_CMD_VMMOFF 4 1174 #define MEMCTL_CMD_VMMON 5 1175 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 1176 when command complete */ 1177 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1178 #define MEMCTL_FREQ_SHIFT 8 1179 #define MEMCTL_SFCAVM (1<<7) 1180 #define MEMCTL_TGT_VID_MASK 0x007f 1181 #define MEMIHYST 0x1117c 1182 #define MEMINTREN 0x11180 /* 16 bits */ 1183 #define MEMINT_RSEXIT_EN (1<<8) 1184 #define MEMINT_CX_SUPR_EN (1<<7) 1185 #define MEMINT_CONT_BUSY_EN (1<<6) 1186 #define MEMINT_AVG_BUSY_EN (1<<5) 1187 #define MEMINT_EVAL_CHG_EN (1<<4) 1188 #define MEMINT_MON_IDLE_EN (1<<3) 1189 #define MEMINT_UP_EVAL_EN (1<<2) 1190 #define MEMINT_DOWN_EVAL_EN (1<<1) 1191 #define MEMINT_SW_CMD_EN (1<<0) 1192 #define MEMINTRSTR 0x11182 /* 16 bits */ 1193 #define MEM_RSEXIT_MASK 0xc000 1194 #define MEM_RSEXIT_SHIFT 14 1195 #define MEM_CONT_BUSY_MASK 0x3000 1196 #define MEM_CONT_BUSY_SHIFT 12 1197 #define MEM_AVG_BUSY_MASK 0x0c00 1198 #define MEM_AVG_BUSY_SHIFT 10 1199 #define MEM_EVAL_CHG_MASK 0x0300 1200 #define MEM_EVAL_BUSY_SHIFT 8 1201 #define MEM_MON_IDLE_MASK 0x00c0 1202 #define MEM_MON_IDLE_SHIFT 6 1203 #define MEM_UP_EVAL_MASK 0x0030 1204 #define MEM_UP_EVAL_SHIFT 4 1205 #define MEM_DOWN_EVAL_MASK 0x000c 1206 #define MEM_DOWN_EVAL_SHIFT 2 1207 #define MEM_SW_CMD_MASK 0x0003 1208 #define MEM_INT_STEER_GFX 0 1209 #define MEM_INT_STEER_CMR 1 1210 #define MEM_INT_STEER_SMI 2 1211 #define MEM_INT_STEER_SCI 3 1212 #define MEMINTRSTS 0x11184 1213 #define MEMINT_RSEXIT (1<<7) 1214 #define MEMINT_CONT_BUSY (1<<6) 1215 #define MEMINT_AVG_BUSY (1<<5) 1216 #define MEMINT_EVAL_CHG (1<<4) 1217 #define MEMINT_MON_IDLE (1<<3) 1218 #define MEMINT_UP_EVAL (1<<2) 1219 #define MEMINT_DOWN_EVAL (1<<1) 1220 #define MEMINT_SW_CMD (1<<0) 1221 #define MEMMODECTL 0x11190 1222 #define MEMMODE_BOOST_EN (1<<31) 1223 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1224 #define MEMMODE_BOOST_FREQ_SHIFT 24 1225 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1226 #define MEMMODE_IDLE_MODE_SHIFT 16 1227 #define MEMMODE_IDLE_MODE_EVAL 0 1228 #define MEMMODE_IDLE_MODE_CONT 1 1229 #define MEMMODE_HWIDLE_EN (1<<15) 1230 #define MEMMODE_SWMODE_EN (1<<14) 1231 #define MEMMODE_RCLK_GATE (1<<13) 1232 #define MEMMODE_HW_UPDATE (1<<12) 1233 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1234 #define MEMMODE_FSTART_SHIFT 8 1235 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1236 #define MEMMODE_FMAX_SHIFT 4 1237 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1238 #define RCBMAXAVG 0x1119c 1239 #define MEMSWCTL2 0x1119e /* Cantiga only */ 1240 #define SWMEMCMD_RENDER_OFF (0 << 13) 1241 #define SWMEMCMD_RENDER_ON (1 << 13) 1242 #define SWMEMCMD_SWFREQ (2 << 13) 1243 #define SWMEMCMD_TARVID (3 << 13) 1244 #define SWMEMCMD_VRM_OFF (4 << 13) 1245 #define SWMEMCMD_VRM_ON (5 << 13) 1246 #define CMDSTS (1<<12) 1247 #define SFCAVM (1<<11) 1248 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1249 #define SWFREQ_SHIFT 7 1250 #define TARVID_MASK 0x001f 1251 #define MEMSTAT_CTG 0x111a0 1252 #define RCBMINAVG 0x111a0 1253 #define RCUPEI 0x111b0 1254 #define RCDNEI 0x111b4 1255 #define RSTDBYCTL 0x111b8 1256 #define RS1EN (1<<31) 1257 #define RS2EN (1<<30) 1258 #define RS3EN (1<<29) 1259 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 1260 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 1261 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 1262 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 1263 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 1264 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 1265 #define RSX_STATUS_MASK (7<<20) 1266 #define RSX_STATUS_ON (0<<20) 1267 #define RSX_STATUS_RC1 (1<<20) 1268 #define RSX_STATUS_RC1E (2<<20) 1269 #define RSX_STATUS_RS1 (3<<20) 1270 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 1271 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 1272 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 1273 #define RSX_STATUS_RSVD2 (7<<20) 1274 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 1275 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 1276 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 1277 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 1278 #define RS1CONTSAV_MASK (3<<14) 1279 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 1280 #define RS1CONTSAV_RSVD (1<<14) 1281 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 1282 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 1283 #define NORMSLEXLAT_MASK (3<<12) 1284 #define SLOW_RS123 (0<<12) 1285 #define SLOW_RS23 (1<<12) 1286 #define SLOW_RS3 (2<<12) 1287 #define NORMAL_RS123 (3<<12) 1288 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 1289 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1290 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 1291 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 1292 #define RS_CSTATE_MASK (3<<4) 1293 #define RS_CSTATE_C367_RS1 (0<<4) 1294 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 1295 #define RS_CSTATE_RSVD (2<<4) 1296 #define RS_CSTATE_C367_RS2 (3<<4) 1297 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 1298 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 1299 #define VIDCTL 0x111c0 1300 #define VIDSTS 0x111c8 1301 #define VIDSTART 0x111cc /* 8 bits */ 1302 #define MEMSTAT_ILK 0x111f8 1303 #define MEMSTAT_VID_MASK 0x7f00 1304 #define MEMSTAT_VID_SHIFT 8 1305 #define MEMSTAT_PSTATE_MASK 0x00f8 1306 #define MEMSTAT_PSTATE_SHIFT 3 1307 #define MEMSTAT_MON_ACTV (1<<2) 1308 #define MEMSTAT_SRC_CTL_MASK 0x0003 1309 #define MEMSTAT_SRC_CTL_CORE 0 1310 #define MEMSTAT_SRC_CTL_TRB 1 1311 #define MEMSTAT_SRC_CTL_THM 2 1312 #define MEMSTAT_SRC_CTL_STDBY 3 1313 #define RCPREVBSYTUPAVG 0x113b8 1314 #define RCPREVBSYTDNAVG 0x113bc 1315 #define PMMISC 0x11214 1316 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 1317 #define SDEW 0x1124c 1318 #define CSIEW0 0x11250 1319 #define CSIEW1 0x11254 1320 #define CSIEW2 0x11258 1321 #define PEW 0x1125c 1322 #define DEW 0x11270 1323 #define MCHAFE 0x112c0 1324 #define CSIEC 0x112e0 1325 #define DMIEC 0x112e4 1326 #define DDREC 0x112e8 1327 #define PEG0EC 0x112ec 1328 #define PEG1EC 0x112f0 1329 #define GFXEC 0x112f4 1330 #define RPPREVBSYTUPAVG 0x113b8 1331 #define RPPREVBSYTDNAVG 0x113bc 1332 #define ECR 0x11600 1333 #define ECR_GPFE (1<<31) 1334 #define ECR_IMONE (1<<30) 1335 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1336 #define OGW0 0x11608 1337 #define OGW1 0x1160c 1338 #define EG0 0x11610 1339 #define EG1 0x11614 1340 #define EG2 0x11618 1341 #define EG3 0x1161c 1342 #define EG4 0x11620 1343 #define EG5 0x11624 1344 #define EG6 0x11628 1345 #define EG7 0x1162c 1346 #define PXW 0x11664 1347 #define PXWL 0x11680 1348 #define LCFUSE02 0x116c0 1349 #define LCFUSE_HIV_MASK 0x000000ff 1350 #define CSIPLL0 0x12c10 1351 #define DDRMPLL1 0X12c20 1352 #define PEG_BAND_GAP_DATA 0x14d68 1353 1354 #define GEN6_GT_PERF_STATUS 0x145948 1355 #define GEN6_RP_STATE_LIMITS 0x145994 1356 #define GEN6_RP_STATE_CAP 0x145998 1357 1358 /* 1359 * Logical Context regs 1360 */ 1361 #define CCID 0x2180 1362 #define CCID_EN (1<<0) 1363 /* 1364 * Overlay regs 1365 */ 1366 1367 #define OVADD 0x30000 1368 #define DOVSTA 0x30008 1369 #define OC_BUF (0x3<<20) 1370 #define OGAMC5 0x30010 1371 #define OGAMC4 0x30014 1372 #define OGAMC3 0x30018 1373 #define OGAMC2 0x3001c 1374 #define OGAMC1 0x30020 1375 #define OGAMC0 0x30024 1376 1377 /* 1378 * Display engine regs 1379 */ 1380 1381 /* Pipe A timing regs */ 1382 #define _HTOTAL_A 0x60000 1383 #define _HBLANK_A 0x60004 1384 #define _HSYNC_A 0x60008 1385 #define _VTOTAL_A 0x6000c 1386 #define _VBLANK_A 0x60010 1387 #define _VSYNC_A 0x60014 1388 #define _PIPEASRC 0x6001c 1389 #define _BCLRPAT_A 0x60020 1390 #define _VSYNCSHIFT_A 0x60028 1391 1392 /* Pipe B timing regs */ 1393 #define _HTOTAL_B 0x61000 1394 #define _HBLANK_B 0x61004 1395 #define _HSYNC_B 0x61008 1396 #define _VTOTAL_B 0x6100c 1397 #define _VBLANK_B 0x61010 1398 #define _VSYNC_B 0x61014 1399 #define _PIPEBSRC 0x6101c 1400 #define _BCLRPAT_B 0x61020 1401 #define _VSYNCSHIFT_B 0x61028 1402 1403 1404 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) 1405 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) 1406 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) 1407 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) 1408 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) 1409 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) 1410 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1411 #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B) 1412 1413 /* VGA port control */ 1414 #define ADPA 0x61100 1415 #define ADPA_DAC_ENABLE (1<<31) 1416 #define ADPA_DAC_DISABLE 0 1417 #define ADPA_PIPE_SELECT_MASK (1<<30) 1418 #define ADPA_PIPE_A_SELECT 0 1419 #define ADPA_PIPE_B_SELECT (1<<30) 1420 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 1421 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1422 #define ADPA_SETS_HVPOLARITY 0 1423 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1424 #define ADPA_VSYNC_CNTL_ENABLE 0 1425 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1426 #define ADPA_HSYNC_CNTL_ENABLE 0 1427 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1428 #define ADPA_VSYNC_ACTIVE_LOW 0 1429 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1430 #define ADPA_HSYNC_ACTIVE_LOW 0 1431 #define ADPA_DPMS_MASK (~(3<<10)) 1432 #define ADPA_DPMS_ON (0<<10) 1433 #define ADPA_DPMS_SUSPEND (1<<10) 1434 #define ADPA_DPMS_STANDBY (2<<10) 1435 #define ADPA_DPMS_OFF (3<<10) 1436 1437 1438 /* Hotplug control (945+ only) */ 1439 #define PORT_HOTPLUG_EN 0x61110 1440 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 1441 #define DPB_HOTPLUG_INT_EN (1 << 29) 1442 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 1443 #define DPC_HOTPLUG_INT_EN (1 << 28) 1444 #define HDMID_HOTPLUG_INT_EN (1 << 27) 1445 #define DPD_HOTPLUG_INT_EN (1 << 27) 1446 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 1447 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 1448 #define TV_HOTPLUG_INT_EN (1 << 18) 1449 #define CRT_HOTPLUG_INT_EN (1 << 9) 1450 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1451 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1452 /* must use period 64 on GM45 according to docs */ 1453 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1454 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1455 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1456 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1457 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1458 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1459 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1460 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1461 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1462 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1463 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1464 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1465 1466 #define PORT_HOTPLUG_STAT 0x61114 1467 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1468 #define DPB_HOTPLUG_INT_STATUS (1 << 29) 1469 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1470 #define DPC_HOTPLUG_INT_STATUS (1 << 28) 1471 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1472 #define DPD_HOTPLUG_INT_STATUS (1 << 27) 1473 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 1474 #define TV_HOTPLUG_INT_STATUS (1 << 10) 1475 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1476 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1477 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1478 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1479 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1480 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1481 1482 /* SDVO port control */ 1483 #define SDVOB 0x61140 1484 #define SDVOC 0x61160 1485 #define SDVO_ENABLE (1 << 31) 1486 #define SDVO_PIPE_B_SELECT (1 << 30) 1487 #define SDVO_STALL_SELECT (1 << 29) 1488 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1489 /** 1490 * 915G/GM SDVO pixel multiplier. 1491 * 1492 * Programmed value is multiplier - 1, up to 5x. 1493 * 1494 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1495 */ 1496 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1497 #define SDVO_PORT_MULTIPLY_SHIFT 23 1498 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1499 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1500 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1501 #define SDVOC_GANG_MODE (1 << 16) 1502 #define SDVO_ENCODING_SDVO (0x0 << 10) 1503 #define SDVO_ENCODING_HDMI (0x2 << 10) 1504 /** Requird for HDMI operation */ 1505 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1506 #define SDVO_COLOR_RANGE_16_235 (1 << 8) 1507 #define SDVO_BORDER_ENABLE (1 << 7) 1508 #define SDVO_AUDIO_ENABLE (1 << 6) 1509 /** New with 965, default is to be set */ 1510 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1511 /** New with 965, default is to be set */ 1512 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1513 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1514 #define SDVO_DETECTED (1 << 2) 1515 /* Bits to be preserved when writing */ 1516 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 1517 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 1518 1519 /* DVO port control */ 1520 #define DVOA 0x61120 1521 #define DVOB 0x61140 1522 #define DVOC 0x61160 1523 #define DVO_ENABLE (1 << 31) 1524 #define DVO_PIPE_B_SELECT (1 << 30) 1525 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1526 #define DVO_PIPE_STALL (1 << 28) 1527 #define DVO_PIPE_STALL_TV (2 << 28) 1528 #define DVO_PIPE_STALL_MASK (3 << 28) 1529 #define DVO_USE_VGA_SYNC (1 << 15) 1530 #define DVO_DATA_ORDER_I740 (0 << 14) 1531 #define DVO_DATA_ORDER_FP (1 << 14) 1532 #define DVO_VSYNC_DISABLE (1 << 11) 1533 #define DVO_HSYNC_DISABLE (1 << 10) 1534 #define DVO_VSYNC_TRISTATE (1 << 9) 1535 #define DVO_HSYNC_TRISTATE (1 << 8) 1536 #define DVO_BORDER_ENABLE (1 << 7) 1537 #define DVO_DATA_ORDER_GBRG (1 << 6) 1538 #define DVO_DATA_ORDER_RGGB (0 << 6) 1539 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1540 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1541 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1542 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1543 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1544 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1545 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1546 #define DVO_PRESERVE_MASK (0x7<<24) 1547 #define DVOA_SRCDIM 0x61124 1548 #define DVOB_SRCDIM 0x61144 1549 #define DVOC_SRCDIM 0x61164 1550 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1551 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1552 1553 /* LVDS port control */ 1554 #define LVDS 0x61180 1555 /* 1556 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1557 * the DPLL semantics change when the LVDS is assigned to that pipe. 1558 */ 1559 #define LVDS_PORT_EN (1 << 31) 1560 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1561 #define LVDS_PIPEB_SELECT (1 << 30) 1562 #define LVDS_PIPE_MASK (1 << 30) 1563 #define LVDS_PIPE(pipe) ((pipe) << 30) 1564 /* LVDS dithering flag on 965/g4x platform */ 1565 #define LVDS_ENABLE_DITHER (1 << 25) 1566 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 1567 #define LVDS_VSYNC_POLARITY (1 << 21) 1568 #define LVDS_HSYNC_POLARITY (1 << 20) 1569 1570 /* Enable border for unscaled (or aspect-scaled) display */ 1571 #define LVDS_BORDER_ENABLE (1 << 15) 1572 /* 1573 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1574 * pixel. 1575 */ 1576 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1577 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1578 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1579 /* 1580 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1581 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1582 * on. 1583 */ 1584 #define LVDS_A3_POWER_MASK (3 << 6) 1585 #define LVDS_A3_POWER_DOWN (0 << 6) 1586 #define LVDS_A3_POWER_UP (3 << 6) 1587 /* 1588 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1589 * is set. 1590 */ 1591 #define LVDS_CLKB_POWER_MASK (3 << 4) 1592 #define LVDS_CLKB_POWER_DOWN (0 << 4) 1593 #define LVDS_CLKB_POWER_UP (3 << 4) 1594 /* 1595 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1596 * setting for whether we are in dual-channel mode. The B3 pair will 1597 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1598 */ 1599 #define LVDS_B0B3_POWER_MASK (3 << 2) 1600 #define LVDS_B0B3_POWER_DOWN (0 << 2) 1601 #define LVDS_B0B3_POWER_UP (3 << 2) 1602 1603 /* Video Data Island Packet control */ 1604 #define VIDEO_DIP_DATA 0x61178 1605 #define VIDEO_DIP_CTL 0x61170 1606 #define VIDEO_DIP_ENABLE (1 << 31) 1607 #define VIDEO_DIP_PORT_B (1 << 29) 1608 #define VIDEO_DIP_PORT_C (2 << 29) 1609 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 1610 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 1611 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 1612 #define VIDEO_DIP_SELECT_MASK (3 << 19) 1613 #define VIDEO_DIP_SELECT_AVI (0 << 19) 1614 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 1615 #define VIDEO_DIP_SELECT_SPD (3 << 19) 1616 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 1617 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 1618 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 1619 1620 /* Panel power sequencing */ 1621 #define PP_STATUS 0x61200 1622 #define PP_ON (1 << 31) 1623 /* 1624 * Indicates that all dependencies of the panel are on: 1625 * 1626 * - PLL enabled 1627 * - pipe enabled 1628 * - LVDS/DVOB/DVOC on 1629 */ 1630 #define PP_READY (1 << 30) 1631 #define PP_SEQUENCE_NONE (0 << 28) 1632 #define PP_SEQUENCE_POWER_UP (1 << 28) 1633 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 1634 #define PP_SEQUENCE_MASK (3 << 28) 1635 #define PP_SEQUENCE_SHIFT 28 1636 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 1637 #define PP_SEQUENCE_STATE_MASK 0x0000000f 1638 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 1639 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 1640 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 1641 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 1642 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 1643 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 1644 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 1645 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 1646 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 1647 #define PP_CONTROL 0x61204 1648 #define POWER_TARGET_ON (1 << 0) 1649 #define PP_ON_DELAYS 0x61208 1650 #define PP_OFF_DELAYS 0x6120c 1651 #define PP_DIVISOR 0x61210 1652 1653 /* Panel fitting */ 1654 #define PFIT_CONTROL 0x61230 1655 #define PFIT_ENABLE (1 << 31) 1656 #define PFIT_PIPE_MASK (3 << 29) 1657 #define PFIT_PIPE_SHIFT 29 1658 #define VERT_INTERP_DISABLE (0 << 10) 1659 #define VERT_INTERP_BILINEAR (1 << 10) 1660 #define VERT_INTERP_MASK (3 << 10) 1661 #define VERT_AUTO_SCALE (1 << 9) 1662 #define HORIZ_INTERP_DISABLE (0 << 6) 1663 #define HORIZ_INTERP_BILINEAR (1 << 6) 1664 #define HORIZ_INTERP_MASK (3 << 6) 1665 #define HORIZ_AUTO_SCALE (1 << 5) 1666 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 1667 #define PFIT_FILTER_FUZZY (0 << 24) 1668 #define PFIT_SCALING_AUTO (0 << 26) 1669 #define PFIT_SCALING_PROGRAMMED (1 << 26) 1670 #define PFIT_SCALING_PILLAR (2 << 26) 1671 #define PFIT_SCALING_LETTER (3 << 26) 1672 #define PFIT_PGM_RATIOS 0x61234 1673 #define PFIT_VERT_SCALE_MASK 0xfff00000 1674 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1675 /* Pre-965 */ 1676 #define PFIT_VERT_SCALE_SHIFT 20 1677 #define PFIT_VERT_SCALE_MASK 0xfff00000 1678 #define PFIT_HORIZ_SCALE_SHIFT 4 1679 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 1680 /* 965+ */ 1681 #define PFIT_VERT_SCALE_SHIFT_965 16 1682 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 1683 #define PFIT_HORIZ_SCALE_SHIFT_965 0 1684 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 1685 1686 #define PFIT_AUTO_RATIOS 0x61238 1687 1688 /* Backlight control */ 1689 #define BLC_PWM_CTL 0x61254 1690 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1691 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1692 #define BLM_COMBINATION_MODE (1 << 30) 1693 /* 1694 * This is the most significant 15 bits of the number of backlight cycles in a 1695 * complete cycle of the modulated backlight control. 1696 * 1697 * The actual value is this field multiplied by two. 1698 */ 1699 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1700 #define BLM_LEGACY_MODE (1 << 16) 1701 /* 1702 * This is the number of cycles out of the backlight modulation cycle for which 1703 * the backlight is on. 1704 * 1705 * This field must be no greater than the number of cycles in the complete 1706 * backlight modulation cycle. 1707 */ 1708 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1709 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1710 1711 #define BLC_HIST_CTL 0x61260 1712 1713 /* TV port control */ 1714 #define TV_CTL 0x68000 1715 /** Enables the TV encoder */ 1716 # define TV_ENC_ENABLE (1 << 31) 1717 /** Sources the TV encoder input from pipe B instead of A. */ 1718 # define TV_ENC_PIPEB_SELECT (1 << 30) 1719 /** Outputs composite video (DAC A only) */ 1720 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1721 /** Outputs SVideo video (DAC B/C) */ 1722 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1723 /** Outputs Component video (DAC A/B/C) */ 1724 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1725 /** Outputs Composite and SVideo (DAC A/B/C) */ 1726 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1727 # define TV_TRILEVEL_SYNC (1 << 21) 1728 /** Enables slow sync generation (945GM only) */ 1729 # define TV_SLOW_SYNC (1 << 20) 1730 /** Selects 4x oversampling for 480i and 576p */ 1731 # define TV_OVERSAMPLE_4X (0 << 18) 1732 /** Selects 2x oversampling for 720p and 1080i */ 1733 # define TV_OVERSAMPLE_2X (1 << 18) 1734 /** Selects no oversampling for 1080p */ 1735 # define TV_OVERSAMPLE_NONE (2 << 18) 1736 /** Selects 8x oversampling */ 1737 # define TV_OVERSAMPLE_8X (3 << 18) 1738 /** Selects progressive mode rather than interlaced */ 1739 # define TV_PROGRESSIVE (1 << 17) 1740 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1741 # define TV_PAL_BURST (1 << 16) 1742 /** Field for setting delay of Y compared to C */ 1743 # define TV_YC_SKEW_MASK (7 << 12) 1744 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1745 # define TV_ENC_SDP_FIX (1 << 11) 1746 /** 1747 * Enables a fix for the 915GM only. 1748 * 1749 * Not sure what it does. 1750 */ 1751 # define TV_ENC_C0_FIX (1 << 10) 1752 /** Bits that must be preserved by software */ 1753 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1754 # define TV_FUSE_STATE_MASK (3 << 4) 1755 /** Read-only state that reports all features enabled */ 1756 # define TV_FUSE_STATE_ENABLED (0 << 4) 1757 /** Read-only state that reports that Macrovision is disabled in hardware*/ 1758 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1759 /** Read-only state that reports that TV-out is disabled in hardware. */ 1760 # define TV_FUSE_STATE_DISABLED (2 << 4) 1761 /** Normal operation */ 1762 # define TV_TEST_MODE_NORMAL (0 << 0) 1763 /** Encoder test pattern 1 - combo pattern */ 1764 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1765 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 1766 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1767 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 1768 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1769 /** Encoder test pattern 4 - random noise */ 1770 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1771 /** Encoder test pattern 5 - linear color ramps */ 1772 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1773 /** 1774 * This test mode forces the DACs to 50% of full output. 1775 * 1776 * This is used for load detection in combination with TVDAC_SENSE_MASK 1777 */ 1778 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1779 # define TV_TEST_MODE_MASK (7 << 0) 1780 1781 #define TV_DAC 0x68004 1782 # define TV_DAC_SAVE 0x00ffff00 1783 /** 1784 * Reports that DAC state change logic has reported change (RO). 1785 * 1786 * This gets cleared when TV_DAC_STATE_EN is cleared 1787 */ 1788 # define TVDAC_STATE_CHG (1 << 31) 1789 # define TVDAC_SENSE_MASK (7 << 28) 1790 /** Reports that DAC A voltage is above the detect threshold */ 1791 # define TVDAC_A_SENSE (1 << 30) 1792 /** Reports that DAC B voltage is above the detect threshold */ 1793 # define TVDAC_B_SENSE (1 << 29) 1794 /** Reports that DAC C voltage is above the detect threshold */ 1795 # define TVDAC_C_SENSE (1 << 28) 1796 /** 1797 * Enables DAC state detection logic, for load-based TV detection. 1798 * 1799 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1800 * to off, for load detection to work. 1801 */ 1802 # define TVDAC_STATE_CHG_EN (1 << 27) 1803 /** Sets the DAC A sense value to high */ 1804 # define TVDAC_A_SENSE_CTL (1 << 26) 1805 /** Sets the DAC B sense value to high */ 1806 # define TVDAC_B_SENSE_CTL (1 << 25) 1807 /** Sets the DAC C sense value to high */ 1808 # define TVDAC_C_SENSE_CTL (1 << 24) 1809 /** Overrides the ENC_ENABLE and DAC voltage levels */ 1810 # define DAC_CTL_OVERRIDE (1 << 7) 1811 /** Sets the slew rate. Must be preserved in software */ 1812 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1813 # define DAC_A_1_3_V (0 << 4) 1814 # define DAC_A_1_1_V (1 << 4) 1815 # define DAC_A_0_7_V (2 << 4) 1816 # define DAC_A_MASK (3 << 4) 1817 # define DAC_B_1_3_V (0 << 2) 1818 # define DAC_B_1_1_V (1 << 2) 1819 # define DAC_B_0_7_V (2 << 2) 1820 # define DAC_B_MASK (3 << 2) 1821 # define DAC_C_1_3_V (0 << 0) 1822 # define DAC_C_1_1_V (1 << 0) 1823 # define DAC_C_0_7_V (2 << 0) 1824 # define DAC_C_MASK (3 << 0) 1825 1826 /** 1827 * CSC coefficients are stored in a floating point format with 9 bits of 1828 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 1829 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1830 * -1 (0x3) being the only legal negative value. 1831 */ 1832 #define TV_CSC_Y 0x68010 1833 # define TV_RY_MASK 0x07ff0000 1834 # define TV_RY_SHIFT 16 1835 # define TV_GY_MASK 0x00000fff 1836 # define TV_GY_SHIFT 0 1837 1838 #define TV_CSC_Y2 0x68014 1839 # define TV_BY_MASK 0x07ff0000 1840 # define TV_BY_SHIFT 16 1841 /** 1842 * Y attenuation for component video. 1843 * 1844 * Stored in 1.9 fixed point. 1845 */ 1846 # define TV_AY_MASK 0x000003ff 1847 # define TV_AY_SHIFT 0 1848 1849 #define TV_CSC_U 0x68018 1850 # define TV_RU_MASK 0x07ff0000 1851 # define TV_RU_SHIFT 16 1852 # define TV_GU_MASK 0x000007ff 1853 # define TV_GU_SHIFT 0 1854 1855 #define TV_CSC_U2 0x6801c 1856 # define TV_BU_MASK 0x07ff0000 1857 # define TV_BU_SHIFT 16 1858 /** 1859 * U attenuation for component video. 1860 * 1861 * Stored in 1.9 fixed point. 1862 */ 1863 # define TV_AU_MASK 0x000003ff 1864 # define TV_AU_SHIFT 0 1865 1866 #define TV_CSC_V 0x68020 1867 # define TV_RV_MASK 0x0fff0000 1868 # define TV_RV_SHIFT 16 1869 # define TV_GV_MASK 0x000007ff 1870 # define TV_GV_SHIFT 0 1871 1872 #define TV_CSC_V2 0x68024 1873 # define TV_BV_MASK 0x07ff0000 1874 # define TV_BV_SHIFT 16 1875 /** 1876 * V attenuation for component video. 1877 * 1878 * Stored in 1.9 fixed point. 1879 */ 1880 # define TV_AV_MASK 0x000007ff 1881 # define TV_AV_SHIFT 0 1882 1883 #define TV_CLR_KNOBS 0x68028 1884 /** 2s-complement brightness adjustment */ 1885 # define TV_BRIGHTNESS_MASK 0xff000000 1886 # define TV_BRIGHTNESS_SHIFT 24 1887 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 1888 # define TV_CONTRAST_MASK 0x00ff0000 1889 # define TV_CONTRAST_SHIFT 16 1890 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1891 # define TV_SATURATION_MASK 0x0000ff00 1892 # define TV_SATURATION_SHIFT 8 1893 /** Hue adjustment, as an integer phase angle in degrees */ 1894 # define TV_HUE_MASK 0x000000ff 1895 # define TV_HUE_SHIFT 0 1896 1897 #define TV_CLR_LEVEL 0x6802c 1898 /** Controls the DAC level for black */ 1899 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1900 # define TV_BLACK_LEVEL_SHIFT 16 1901 /** Controls the DAC level for blanking */ 1902 # define TV_BLANK_LEVEL_MASK 0x000001ff 1903 # define TV_BLANK_LEVEL_SHIFT 0 1904 1905 #define TV_H_CTL_1 0x68030 1906 /** Number of pixels in the hsync. */ 1907 # define TV_HSYNC_END_MASK 0x1fff0000 1908 # define TV_HSYNC_END_SHIFT 16 1909 /** Total number of pixels minus one in the line (display and blanking). */ 1910 # define TV_HTOTAL_MASK 0x00001fff 1911 # define TV_HTOTAL_SHIFT 0 1912 1913 #define TV_H_CTL_2 0x68034 1914 /** Enables the colorburst (needed for non-component color) */ 1915 # define TV_BURST_ENA (1 << 31) 1916 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1917 # define TV_HBURST_START_SHIFT 16 1918 # define TV_HBURST_START_MASK 0x1fff0000 1919 /** Length of the colorburst */ 1920 # define TV_HBURST_LEN_SHIFT 0 1921 # define TV_HBURST_LEN_MASK 0x0001fff 1922 1923 #define TV_H_CTL_3 0x68038 1924 /** End of hblank, measured in pixels minus one from start of hsync */ 1925 # define TV_HBLANK_END_SHIFT 16 1926 # define TV_HBLANK_END_MASK 0x1fff0000 1927 /** Start of hblank, measured in pixels minus one from start of hsync */ 1928 # define TV_HBLANK_START_SHIFT 0 1929 # define TV_HBLANK_START_MASK 0x0001fff 1930 1931 #define TV_V_CTL_1 0x6803c 1932 /** XXX */ 1933 # define TV_NBR_END_SHIFT 16 1934 # define TV_NBR_END_MASK 0x07ff0000 1935 /** XXX */ 1936 # define TV_VI_END_F1_SHIFT 8 1937 # define TV_VI_END_F1_MASK 0x00003f00 1938 /** XXX */ 1939 # define TV_VI_END_F2_SHIFT 0 1940 # define TV_VI_END_F2_MASK 0x0000003f 1941 1942 #define TV_V_CTL_2 0x68040 1943 /** Length of vsync, in half lines */ 1944 # define TV_VSYNC_LEN_MASK 0x07ff0000 1945 # define TV_VSYNC_LEN_SHIFT 16 1946 /** Offset of the start of vsync in field 1, measured in one less than the 1947 * number of half lines. 1948 */ 1949 # define TV_VSYNC_START_F1_MASK 0x00007f00 1950 # define TV_VSYNC_START_F1_SHIFT 8 1951 /** 1952 * Offset of the start of vsync in field 2, measured in one less than the 1953 * number of half lines. 1954 */ 1955 # define TV_VSYNC_START_F2_MASK 0x0000007f 1956 # define TV_VSYNC_START_F2_SHIFT 0 1957 1958 #define TV_V_CTL_3 0x68044 1959 /** Enables generation of the equalization signal */ 1960 # define TV_EQUAL_ENA (1 << 31) 1961 /** Length of vsync, in half lines */ 1962 # define TV_VEQ_LEN_MASK 0x007f0000 1963 # define TV_VEQ_LEN_SHIFT 16 1964 /** Offset of the start of equalization in field 1, measured in one less than 1965 * the number of half lines. 1966 */ 1967 # define TV_VEQ_START_F1_MASK 0x0007f00 1968 # define TV_VEQ_START_F1_SHIFT 8 1969 /** 1970 * Offset of the start of equalization in field 2, measured in one less than 1971 * the number of half lines. 1972 */ 1973 # define TV_VEQ_START_F2_MASK 0x000007f 1974 # define TV_VEQ_START_F2_SHIFT 0 1975 1976 #define TV_V_CTL_4 0x68048 1977 /** 1978 * Offset to start of vertical colorburst, measured in one less than the 1979 * number of lines from vertical start. 1980 */ 1981 # define TV_VBURST_START_F1_MASK 0x003f0000 1982 # define TV_VBURST_START_F1_SHIFT 16 1983 /** 1984 * Offset to the end of vertical colorburst, measured in one less than the 1985 * number of lines from the start of NBR. 1986 */ 1987 # define TV_VBURST_END_F1_MASK 0x000000ff 1988 # define TV_VBURST_END_F1_SHIFT 0 1989 1990 #define TV_V_CTL_5 0x6804c 1991 /** 1992 * Offset to start of vertical colorburst, measured in one less than the 1993 * number of lines from vertical start. 1994 */ 1995 # define TV_VBURST_START_F2_MASK 0x003f0000 1996 # define TV_VBURST_START_F2_SHIFT 16 1997 /** 1998 * Offset to the end of vertical colorburst, measured in one less than the 1999 * number of lines from the start of NBR. 2000 */ 2001 # define TV_VBURST_END_F2_MASK 0x000000ff 2002 # define TV_VBURST_END_F2_SHIFT 0 2003 2004 #define TV_V_CTL_6 0x68050 2005 /** 2006 * Offset to start of vertical colorburst, measured in one less than the 2007 * number of lines from vertical start. 2008 */ 2009 # define TV_VBURST_START_F3_MASK 0x003f0000 2010 # define TV_VBURST_START_F3_SHIFT 16 2011 /** 2012 * Offset to the end of vertical colorburst, measured in one less than the 2013 * number of lines from the start of NBR. 2014 */ 2015 # define TV_VBURST_END_F3_MASK 0x000000ff 2016 # define TV_VBURST_END_F3_SHIFT 0 2017 2018 #define TV_V_CTL_7 0x68054 2019 /** 2020 * Offset to start of vertical colorburst, measured in one less than the 2021 * number of lines from vertical start. 2022 */ 2023 # define TV_VBURST_START_F4_MASK 0x003f0000 2024 # define TV_VBURST_START_F4_SHIFT 16 2025 /** 2026 * Offset to the end of vertical colorburst, measured in one less than the 2027 * number of lines from the start of NBR. 2028 */ 2029 # define TV_VBURST_END_F4_MASK 0x000000ff 2030 # define TV_VBURST_END_F4_SHIFT 0 2031 2032 #define TV_SC_CTL_1 0x68060 2033 /** Turns on the first subcarrier phase generation DDA */ 2034 # define TV_SC_DDA1_EN (1 << 31) 2035 /** Turns on the first subcarrier phase generation DDA */ 2036 # define TV_SC_DDA2_EN (1 << 30) 2037 /** Turns on the first subcarrier phase generation DDA */ 2038 # define TV_SC_DDA3_EN (1 << 29) 2039 /** Sets the subcarrier DDA to reset frequency every other field */ 2040 # define TV_SC_RESET_EVERY_2 (0 << 24) 2041 /** Sets the subcarrier DDA to reset frequency every fourth field */ 2042 # define TV_SC_RESET_EVERY_4 (1 << 24) 2043 /** Sets the subcarrier DDA to reset frequency every eighth field */ 2044 # define TV_SC_RESET_EVERY_8 (2 << 24) 2045 /** Sets the subcarrier DDA to never reset the frequency */ 2046 # define TV_SC_RESET_NEVER (3 << 24) 2047 /** Sets the peak amplitude of the colorburst.*/ 2048 # define TV_BURST_LEVEL_MASK 0x00ff0000 2049 # define TV_BURST_LEVEL_SHIFT 16 2050 /** Sets the increment of the first subcarrier phase generation DDA */ 2051 # define TV_SCDDA1_INC_MASK 0x00000fff 2052 # define TV_SCDDA1_INC_SHIFT 0 2053 2054 #define TV_SC_CTL_2 0x68064 2055 /** Sets the rollover for the second subcarrier phase generation DDA */ 2056 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 2057 # define TV_SCDDA2_SIZE_SHIFT 16 2058 /** Sets the increent of the second subcarrier phase generation DDA */ 2059 # define TV_SCDDA2_INC_MASK 0x00007fff 2060 # define TV_SCDDA2_INC_SHIFT 0 2061 2062 #define TV_SC_CTL_3 0x68068 2063 /** Sets the rollover for the third subcarrier phase generation DDA */ 2064 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 2065 # define TV_SCDDA3_SIZE_SHIFT 16 2066 /** Sets the increent of the third subcarrier phase generation DDA */ 2067 # define TV_SCDDA3_INC_MASK 0x00007fff 2068 # define TV_SCDDA3_INC_SHIFT 0 2069 2070 #define TV_WIN_POS 0x68070 2071 /** X coordinate of the display from the start of horizontal active */ 2072 # define TV_XPOS_MASK 0x1fff0000 2073 # define TV_XPOS_SHIFT 16 2074 /** Y coordinate of the display from the start of vertical active (NBR) */ 2075 # define TV_YPOS_MASK 0x00000fff 2076 # define TV_YPOS_SHIFT 0 2077 2078 #define TV_WIN_SIZE 0x68074 2079 /** Horizontal size of the display window, measured in pixels*/ 2080 # define TV_XSIZE_MASK 0x1fff0000 2081 # define TV_XSIZE_SHIFT 16 2082 /** 2083 * Vertical size of the display window, measured in pixels. 2084 * 2085 * Must be even for interlaced modes. 2086 */ 2087 # define TV_YSIZE_MASK 0x00000fff 2088 # define TV_YSIZE_SHIFT 0 2089 2090 #define TV_FILTER_CTL_1 0x68080 2091 /** 2092 * Enables automatic scaling calculation. 2093 * 2094 * If set, the rest of the registers are ignored, and the calculated values can 2095 * be read back from the register. 2096 */ 2097 # define TV_AUTO_SCALE (1 << 31) 2098 /** 2099 * Disables the vertical filter. 2100 * 2101 * This is required on modes more than 1024 pixels wide */ 2102 # define TV_V_FILTER_BYPASS (1 << 29) 2103 /** Enables adaptive vertical filtering */ 2104 # define TV_VADAPT (1 << 28) 2105 # define TV_VADAPT_MODE_MASK (3 << 26) 2106 /** Selects the least adaptive vertical filtering mode */ 2107 # define TV_VADAPT_MODE_LEAST (0 << 26) 2108 /** Selects the moderately adaptive vertical filtering mode */ 2109 # define TV_VADAPT_MODE_MODERATE (1 << 26) 2110 /** Selects the most adaptive vertical filtering mode */ 2111 # define TV_VADAPT_MODE_MOST (3 << 26) 2112 /** 2113 * Sets the horizontal scaling factor. 2114 * 2115 * This should be the fractional part of the horizontal scaling factor divided 2116 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 2117 * 2118 * (src width - 1) / ((oversample * dest width) - 1) 2119 */ 2120 # define TV_HSCALE_FRAC_MASK 0x00003fff 2121 # define TV_HSCALE_FRAC_SHIFT 0 2122 2123 #define TV_FILTER_CTL_2 0x68084 2124 /** 2125 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2126 * 2127 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 2128 */ 2129 # define TV_VSCALE_INT_MASK 0x00038000 2130 # define TV_VSCALE_INT_SHIFT 15 2131 /** 2132 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2133 * 2134 * \sa TV_VSCALE_INT_MASK 2135 */ 2136 # define TV_VSCALE_FRAC_MASK 0x00007fff 2137 # define TV_VSCALE_FRAC_SHIFT 0 2138 2139 #define TV_FILTER_CTL_3 0x68088 2140 /** 2141 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2142 * 2143 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2144 * 2145 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2146 */ 2147 # define TV_VSCALE_IP_INT_MASK 0x00038000 2148 # define TV_VSCALE_IP_INT_SHIFT 15 2149 /** 2150 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2151 * 2152 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2153 * 2154 * \sa TV_VSCALE_IP_INT_MASK 2155 */ 2156 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2157 # define TV_VSCALE_IP_FRAC_SHIFT 0 2158 2159 #define TV_CC_CONTROL 0x68090 2160 # define TV_CC_ENABLE (1 << 31) 2161 /** 2162 * Specifies which field to send the CC data in. 2163 * 2164 * CC data is usually sent in field 0. 2165 */ 2166 # define TV_CC_FID_MASK (1 << 27) 2167 # define TV_CC_FID_SHIFT 27 2168 /** Sets the horizontal position of the CC data. Usually 135. */ 2169 # define TV_CC_HOFF_MASK 0x03ff0000 2170 # define TV_CC_HOFF_SHIFT 16 2171 /** Sets the vertical position of the CC data. Usually 21 */ 2172 # define TV_CC_LINE_MASK 0x0000003f 2173 # define TV_CC_LINE_SHIFT 0 2174 2175 #define TV_CC_DATA 0x68094 2176 # define TV_CC_RDY (1 << 31) 2177 /** Second word of CC data to be transmitted. */ 2178 # define TV_CC_DATA_2_MASK 0x007f0000 2179 # define TV_CC_DATA_2_SHIFT 16 2180 /** First word of CC data to be transmitted. */ 2181 # define TV_CC_DATA_1_MASK 0x0000007f 2182 # define TV_CC_DATA_1_SHIFT 0 2183 2184 #define TV_H_LUMA_0 0x68100 2185 #define TV_H_LUMA_59 0x681ec 2186 #define TV_H_CHROMA_0 0x68200 2187 #define TV_H_CHROMA_59 0x682ec 2188 #define TV_V_LUMA_0 0x68300 2189 #define TV_V_LUMA_42 0x683a8 2190 #define TV_V_CHROMA_0 0x68400 2191 #define TV_V_CHROMA_42 0x684a8 2192 2193 /* Display Port */ 2194 #define DP_A 0x64000 /* eDP */ 2195 #define DP_B 0x64100 2196 #define DP_C 0x64200 2197 #define DP_D 0x64300 2198 2199 #define DP_PORT_EN (1 << 31) 2200 #define DP_PIPEB_SELECT (1 << 30) 2201 #define DP_PIPE_MASK (1 << 30) 2202 2203 /* Link training mode - select a suitable mode for each stage */ 2204 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 2205 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 2206 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 2207 #define DP_LINK_TRAIN_OFF (3 << 28) 2208 #define DP_LINK_TRAIN_MASK (3 << 28) 2209 #define DP_LINK_TRAIN_SHIFT 28 2210 2211 /* CPT Link training mode */ 2212 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 2213 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 2214 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 2215 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 2216 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 2217 #define DP_LINK_TRAIN_SHIFT_CPT 8 2218 2219 /* Signal voltages. These are mostly controlled by the other end */ 2220 #define DP_VOLTAGE_0_4 (0 << 25) 2221 #define DP_VOLTAGE_0_6 (1 << 25) 2222 #define DP_VOLTAGE_0_8 (2 << 25) 2223 #define DP_VOLTAGE_1_2 (3 << 25) 2224 #define DP_VOLTAGE_MASK (7 << 25) 2225 #define DP_VOLTAGE_SHIFT 25 2226 2227 /* Signal pre-emphasis levels, like voltages, the other end tells us what 2228 * they want 2229 */ 2230 #define DP_PRE_EMPHASIS_0 (0 << 22) 2231 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 2232 #define DP_PRE_EMPHASIS_6 (2 << 22) 2233 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 2234 #define DP_PRE_EMPHASIS_MASK (7 << 22) 2235 #define DP_PRE_EMPHASIS_SHIFT 22 2236 2237 /* How many wires to use. I guess 3 was too hard */ 2238 #define DP_PORT_WIDTH_1 (0 << 19) 2239 #define DP_PORT_WIDTH_2 (1 << 19) 2240 #define DP_PORT_WIDTH_4 (3 << 19) 2241 #define DP_PORT_WIDTH_MASK (7 << 19) 2242 2243 /* Mystic DPCD version 1.1 special mode */ 2244 #define DP_ENHANCED_FRAMING (1 << 18) 2245 2246 /* eDP */ 2247 #define DP_PLL_FREQ_270MHZ (0 << 16) 2248 #define DP_PLL_FREQ_160MHZ (1 << 16) 2249 #define DP_PLL_FREQ_MASK (3 << 16) 2250 2251 /** locked once port is enabled */ 2252 #define DP_PORT_REVERSAL (1 << 15) 2253 2254 /* eDP */ 2255 #define DP_PLL_ENABLE (1 << 14) 2256 2257 /** sends the clock on lane 15 of the PEG for debug */ 2258 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 2259 2260 #define DP_SCRAMBLING_DISABLE (1 << 12) 2261 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 2262 2263 /** limit RGB values to avoid confusing TVs */ 2264 #define DP_COLOR_RANGE_16_235 (1 << 8) 2265 2266 /** Turn on the audio link */ 2267 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 2268 2269 /** vs and hs sync polarity */ 2270 #define DP_SYNC_VS_HIGH (1 << 4) 2271 #define DP_SYNC_HS_HIGH (1 << 3) 2272 2273 /** A fantasy */ 2274 #define DP_DETECTED (1 << 2) 2275 2276 /** The aux channel provides a way to talk to the 2277 * signal sink for DDC etc. Max packet size supported 2278 * is 20 bytes in each direction, hence the 5 fixed 2279 * data registers 2280 */ 2281 #define DPA_AUX_CH_CTL 0x64010 2282 #define DPA_AUX_CH_DATA1 0x64014 2283 #define DPA_AUX_CH_DATA2 0x64018 2284 #define DPA_AUX_CH_DATA3 0x6401c 2285 #define DPA_AUX_CH_DATA4 0x64020 2286 #define DPA_AUX_CH_DATA5 0x64024 2287 2288 #define DPB_AUX_CH_CTL 0x64110 2289 #define DPB_AUX_CH_DATA1 0x64114 2290 #define DPB_AUX_CH_DATA2 0x64118 2291 #define DPB_AUX_CH_DATA3 0x6411c 2292 #define DPB_AUX_CH_DATA4 0x64120 2293 #define DPB_AUX_CH_DATA5 0x64124 2294 2295 #define DPC_AUX_CH_CTL 0x64210 2296 #define DPC_AUX_CH_DATA1 0x64214 2297 #define DPC_AUX_CH_DATA2 0x64218 2298 #define DPC_AUX_CH_DATA3 0x6421c 2299 #define DPC_AUX_CH_DATA4 0x64220 2300 #define DPC_AUX_CH_DATA5 0x64224 2301 2302 #define DPD_AUX_CH_CTL 0x64310 2303 #define DPD_AUX_CH_DATA1 0x64314 2304 #define DPD_AUX_CH_DATA2 0x64318 2305 #define DPD_AUX_CH_DATA3 0x6431c 2306 #define DPD_AUX_CH_DATA4 0x64320 2307 #define DPD_AUX_CH_DATA5 0x64324 2308 2309 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 2310 #define DP_AUX_CH_CTL_DONE (1 << 30) 2311 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 2312 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 2313 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 2314 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 2315 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 2316 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 2317 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 2318 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 2319 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 2320 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 2321 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 2322 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 2323 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 2324 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 2325 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 2326 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 2327 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 2328 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 2329 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 2330 2331 /* 2332 * Computing GMCH M and N values for the Display Port link 2333 * 2334 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2335 * 2336 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2337 * 2338 * The GMCH value is used internally 2339 * 2340 * bytes_per_pixel is the number of bytes coming out of the plane, 2341 * which is after the LUTs, so we want the bytes for our color format. 2342 * For our current usage, this is always 3, one byte for R, G and B. 2343 */ 2344 #define _PIPEA_GMCH_DATA_M 0x70050 2345 #define _PIPEB_GMCH_DATA_M 0x71050 2346 2347 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2348 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2349 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2350 2351 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2352 2353 #define _PIPEA_GMCH_DATA_N 0x70054 2354 #define _PIPEB_GMCH_DATA_N 0x71054 2355 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2356 2357 /* 2358 * Computing Link M and N values for the Display Port link 2359 * 2360 * Link M / N = pixel_clock / ls_clk 2361 * 2362 * (the DP spec calls pixel_clock the 'strm_clk') 2363 * 2364 * The Link value is transmitted in the Main Stream 2365 * Attributes and VB-ID. 2366 */ 2367 2368 #define _PIPEA_DP_LINK_M 0x70060 2369 #define _PIPEB_DP_LINK_M 0x71060 2370 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2371 2372 #define _PIPEA_DP_LINK_N 0x70064 2373 #define _PIPEB_DP_LINK_N 0x71064 2374 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2375 2376 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) 2377 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) 2378 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) 2379 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) 2380 2381 /* Display & cursor control */ 2382 2383 /* Pipe A */ 2384 #define _PIPEADSL 0x70000 2385 #define DSL_LINEMASK 0x00000fff 2386 #define _PIPEACONF 0x70008 2387 #define PIPECONF_ENABLE (1<<31) 2388 #define PIPECONF_DISABLE 0 2389 #define PIPECONF_DOUBLE_WIDE (1<<30) 2390 #define I965_PIPECONF_ACTIVE (1<<30) 2391 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 2392 #define PIPECONF_SINGLE_WIDE 0 2393 #define PIPECONF_PIPE_UNLOCKED 0 2394 #define PIPECONF_PIPE_LOCKED (1<<25) 2395 #define PIPECONF_PALETTE 0 2396 #define PIPECONF_GAMMA (1<<24) 2397 #define PIPECONF_FORCE_BORDER (1<<25) 2398 #define PIPECONF_INTERLACE_MASK (7 << 21) 2399 /* Note that pre-gen3 does not support interlaced display directly. Panel 2400 * fitting must be disabled on pre-ilk for interlaced. */ 2401 #define PIPECONF_PROGRESSIVE (0 << 21) 2402 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 2403 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 2404 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2405 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 2406 /* Ironlake and later have a complete new set of values for interlaced. PFIT 2407 * means panel fitter required, PF means progressive fetch, DBL means power 2408 * saving pixel doubling. */ 2409 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 2410 #define PIPECONF_INTERLACED_ILK (3 << 21) 2411 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 2412 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 2413 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2414 #define PIPECONF_BPP_MASK (0x000000e0) 2415 #define PIPECONF_BPP_8 (0<<5) 2416 #define PIPECONF_BPP_10 (1<<5) 2417 #define PIPECONF_BPP_6 (2<<5) 2418 #define PIPECONF_BPP_12 (3<<5) 2419 #define PIPECONF_DITHER_EN (1<<4) 2420 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 2421 #define PIPECONF_DITHER_TYPE_SP (0<<2) 2422 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 2423 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 2424 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 2425 #define _PIPEASTAT 0x70024 2426 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 2427 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 2428 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 2429 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 2430 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 2431 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 2432 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 2433 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 2434 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 2435 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 2436 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 2437 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 2438 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 2439 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 2440 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 2441 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 2442 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 2443 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 2444 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 2445 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 2446 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 2447 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 2448 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 2449 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 2450 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 2451 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 2452 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 2453 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 2454 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 2455 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */ 2456 #define PIPE_8BPC (0 << 5) 2457 #define PIPE_10BPC (1 << 5) 2458 #define PIPE_6BPC (2 << 5) 2459 #define PIPE_12BPC (3 << 5) 2460 2461 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) 2462 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) 2463 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) 2464 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) 2465 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) 2466 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) 2467 2468 #define DSPARB 0x70030 2469 #define DSPARB_CSTART_MASK (0x7f << 7) 2470 #define DSPARB_CSTART_SHIFT 7 2471 #define DSPARB_BSTART_MASK (0x7f) 2472 #define DSPARB_BSTART_SHIFT 0 2473 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2474 #define DSPARB_AEND_SHIFT 0 2475 2476 #define DSPFW1 0x70034 2477 #define DSPFW_SR_SHIFT 23 2478 #define DSPFW_SR_MASK (0x1ff<<23) 2479 #define DSPFW_CURSORB_SHIFT 16 2480 #define DSPFW_CURSORB_MASK (0x3f<<16) 2481 #define DSPFW_PLANEB_SHIFT 8 2482 #define DSPFW_PLANEB_MASK (0x7f<<8) 2483 #define DSPFW_PLANEA_MASK (0x7f) 2484 #define DSPFW2 0x70038 2485 #define DSPFW_CURSORA_MASK 0x00003f00 2486 #define DSPFW_CURSORA_SHIFT 8 2487 #define DSPFW_PLANEC_MASK (0x7f) 2488 #define DSPFW3 0x7003c 2489 #define DSPFW_HPLL_SR_EN (1<<31) 2490 #define DSPFW_CURSOR_SR_SHIFT 24 2491 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 2492 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 2493 #define DSPFW_HPLL_CURSOR_SHIFT 16 2494 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 2495 #define DSPFW_HPLL_SR_MASK (0x1ff) 2496 2497 /* FIFO watermark sizes etc */ 2498 #define G4X_FIFO_LINE_SIZE 64 2499 #define I915_FIFO_LINE_SIZE 64 2500 #define I830_FIFO_LINE_SIZE 32 2501 2502 #define G4X_FIFO_SIZE 127 2503 #define I965_FIFO_SIZE 512 2504 #define I945_FIFO_SIZE 127 2505 #define I915_FIFO_SIZE 95 2506 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 2507 #define I830_FIFO_SIZE 95 2508 2509 #define G4X_MAX_WM 0x3f 2510 #define I915_MAX_WM 0x3f 2511 2512 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 2513 #define PINEVIEW_FIFO_LINE_SIZE 64 2514 #define PINEVIEW_MAX_WM 0x1ff 2515 #define PINEVIEW_DFT_WM 0x3f 2516 #define PINEVIEW_DFT_HPLLOFF_WM 0 2517 #define PINEVIEW_GUARD_WM 10 2518 #define PINEVIEW_CURSOR_FIFO 64 2519 #define PINEVIEW_CURSOR_MAX_WM 0x3f 2520 #define PINEVIEW_CURSOR_DFT_WM 0 2521 #define PINEVIEW_CURSOR_GUARD_WM 5 2522 2523 #define I965_CURSOR_FIFO 64 2524 #define I965_CURSOR_MAX_WM 32 2525 #define I965_CURSOR_DFT_WM 8 2526 2527 /* define the Watermark register on Ironlake */ 2528 #define WM0_PIPEA_ILK 0x45100 2529 #define WM0_PIPE_PLANE_MASK (0x7f<<16) 2530 #define WM0_PIPE_PLANE_SHIFT 16 2531 #define WM0_PIPE_SPRITE_MASK (0x3f<<8) 2532 #define WM0_PIPE_SPRITE_SHIFT 8 2533 #define WM0_PIPE_CURSOR_MASK (0x1f) 2534 2535 #define WM0_PIPEB_ILK 0x45104 2536 #define WM0_PIPEC_IVB 0x45200 2537 #define WM1_LP_ILK 0x45108 2538 #define WM1_LP_SR_EN (1<<31) 2539 #define WM1_LP_LATENCY_SHIFT 24 2540 #define WM1_LP_LATENCY_MASK (0x7f<<24) 2541 #define WM1_LP_FBC_MASK (0xf<<20) 2542 #define WM1_LP_FBC_SHIFT 20 2543 #define WM1_LP_SR_MASK (0x1ff<<8) 2544 #define WM1_LP_SR_SHIFT 8 2545 #define WM1_LP_CURSOR_MASK (0x3f) 2546 #define WM2_LP_ILK 0x4510c 2547 #define WM2_LP_EN (1<<31) 2548 #define WM3_LP_ILK 0x45110 2549 #define WM3_LP_EN (1<<31) 2550 #define WM1S_LP_ILK 0x45120 2551 #define WM2S_LP_IVB 0x45124 2552 #define WM3S_LP_IVB 0x45128 2553 #define WM1S_LP_EN (1<<31) 2554 2555 /* Memory latency timer register */ 2556 #define MLTR_ILK 0x11222 2557 #define MLTR_WM1_SHIFT 0 2558 #define MLTR_WM2_SHIFT 8 2559 /* the unit of memory self-refresh latency time is 0.5us */ 2560 #define ILK_SRLT_MASK 0x3f 2561 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK) 2562 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT) 2563 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT) 2564 2565 /* define the fifo size on Ironlake */ 2566 #define ILK_DISPLAY_FIFO 128 2567 #define ILK_DISPLAY_MAXWM 64 2568 #define ILK_DISPLAY_DFTWM 8 2569 #define ILK_CURSOR_FIFO 32 2570 #define ILK_CURSOR_MAXWM 16 2571 #define ILK_CURSOR_DFTWM 8 2572 2573 #define ILK_DISPLAY_SR_FIFO 512 2574 #define ILK_DISPLAY_MAX_SRWM 0x1ff 2575 #define ILK_DISPLAY_DFT_SRWM 0x3f 2576 #define ILK_CURSOR_SR_FIFO 64 2577 #define ILK_CURSOR_MAX_SRWM 0x3f 2578 #define ILK_CURSOR_DFT_SRWM 8 2579 2580 #define ILK_FIFO_LINE_SIZE 64 2581 2582 /* define the WM info on Sandybridge */ 2583 #define SNB_DISPLAY_FIFO 128 2584 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */ 2585 #define SNB_DISPLAY_DFTWM 8 2586 #define SNB_CURSOR_FIFO 32 2587 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */ 2588 #define SNB_CURSOR_DFTWM 8 2589 2590 #define SNB_DISPLAY_SR_FIFO 512 2591 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */ 2592 #define SNB_DISPLAY_DFT_SRWM 0x3f 2593 #define SNB_CURSOR_SR_FIFO 64 2594 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */ 2595 #define SNB_CURSOR_DFT_SRWM 8 2596 2597 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */ 2598 2599 #define SNB_FIFO_LINE_SIZE 64 2600 2601 2602 /* the address where we get all kinds of latency value */ 2603 #define SSKPD 0x5d10 2604 #define SSKPD_WM_MASK 0x3f 2605 #define SSKPD_WM0_SHIFT 0 2606 #define SSKPD_WM1_SHIFT 8 2607 #define SSKPD_WM2_SHIFT 16 2608 #define SSKPD_WM3_SHIFT 24 2609 2610 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK) 2611 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT) 2612 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT) 2613 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT) 2614 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT) 2615 2616 /* 2617 * The two pipe frame counter registers are not synchronized, so 2618 * reading a stable value is somewhat tricky. The following code 2619 * should work: 2620 * 2621 * do { 2622 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2623 * PIPE_FRAME_HIGH_SHIFT; 2624 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 2625 * PIPE_FRAME_LOW_SHIFT); 2626 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 2627 * PIPE_FRAME_HIGH_SHIFT); 2628 * } while (high1 != high2); 2629 * frame = (high1 << 8) | low1; 2630 */ 2631 #define _PIPEAFRAMEHIGH 0x70040 2632 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2633 #define PIPE_FRAME_HIGH_SHIFT 0 2634 #define _PIPEAFRAMEPIXEL 0x70044 2635 #define PIPE_FRAME_LOW_MASK 0xff000000 2636 #define PIPE_FRAME_LOW_SHIFT 24 2637 #define PIPE_PIXEL_MASK 0x00ffffff 2638 #define PIPE_PIXEL_SHIFT 0 2639 /* GM45+ just has to be different */ 2640 #define _PIPEA_FRMCOUNT_GM45 0x70040 2641 #define _PIPEA_FLIPCOUNT_GM45 0x70044 2642 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) 2643 2644 /* Cursor A & B regs */ 2645 #define _CURACNTR 0x70080 2646 /* Old style CUR*CNTR flags (desktop 8xx) */ 2647 #define CURSOR_ENABLE 0x80000000 2648 #define CURSOR_GAMMA_ENABLE 0x40000000 2649 #define CURSOR_STRIDE_MASK 0x30000000 2650 #define CURSOR_FORMAT_SHIFT 24 2651 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 2652 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 2653 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 2654 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 2655 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 2656 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 2657 /* New style CUR*CNTR flags */ 2658 #define CURSOR_MODE 0x27 2659 #define CURSOR_MODE_DISABLE 0x00 2660 #define CURSOR_MODE_64_32B_AX 0x07 2661 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 2662 #define MCURSOR_PIPE_SELECT (1 << 28) 2663 #define MCURSOR_PIPE_A 0x00 2664 #define MCURSOR_PIPE_B (1 << 28) 2665 #define MCURSOR_GAMMA_ENABLE (1 << 26) 2666 #define _CURABASE 0x70084 2667 #define _CURAPOS 0x70088 2668 #define CURSOR_POS_MASK 0x007FF 2669 #define CURSOR_POS_SIGN 0x8000 2670 #define CURSOR_X_SHIFT 0 2671 #define CURSOR_Y_SHIFT 16 2672 #define CURSIZE 0x700a0 2673 #define _CURBCNTR 0x700c0 2674 #define _CURBBASE 0x700c4 2675 #define _CURBPOS 0x700c8 2676 2677 #define _CURBCNTR_IVB 0x71080 2678 #define _CURBBASE_IVB 0x71084 2679 #define _CURBPOS_IVB 0x71088 2680 2681 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR) 2682 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE) 2683 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS) 2684 2685 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB) 2686 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB) 2687 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) 2688 2689 /* Display A control */ 2690 #define _DSPACNTR 0x70180 2691 #define DISPLAY_PLANE_ENABLE (1<<31) 2692 #define DISPLAY_PLANE_DISABLE 0 2693 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2694 #define DISPPLANE_GAMMA_DISABLE 0 2695 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2696 #define DISPPLANE_8BPP (0x2<<26) 2697 #define DISPPLANE_15_16BPP (0x4<<26) 2698 #define DISPPLANE_16BPP (0x5<<26) 2699 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2700 #define DISPPLANE_32BPP (0x7<<26) 2701 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) 2702 #define DISPPLANE_STEREO_ENABLE (1<<25) 2703 #define DISPPLANE_STEREO_DISABLE 0 2704 #define DISPPLANE_SEL_PIPE_SHIFT 24 2705 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 2706 #define DISPPLANE_SEL_PIPE_A 0 2707 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 2708 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2709 #define DISPPLANE_SRC_KEY_DISABLE 0 2710 #define DISPPLANE_LINE_DOUBLE (1<<20) 2711 #define DISPPLANE_NO_LINE_DOUBLE 0 2712 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2713 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2714 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 2715 #define DISPPLANE_TILED (1<<10) 2716 #define _DSPAADDR 0x70184 2717 #define _DSPASTRIDE 0x70188 2718 #define _DSPAPOS 0x7018C /* reserved */ 2719 #define _DSPASIZE 0x70190 2720 #define _DSPASURF 0x7019C /* 965+ only */ 2721 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 2722 2723 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) 2724 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) 2725 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) 2726 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) 2727 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) 2728 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) 2729 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) 2730 2731 /* VBIOS flags */ 2732 #define SWF00 0x71410 2733 #define SWF01 0x71414 2734 #define SWF02 0x71418 2735 #define SWF03 0x7141c 2736 #define SWF04 0x71420 2737 #define SWF05 0x71424 2738 #define SWF06 0x71428 2739 #define SWF10 0x70410 2740 #define SWF11 0x70414 2741 #define SWF14 0x71420 2742 #define SWF30 0x72414 2743 #define SWF31 0x72418 2744 #define SWF32 0x7241c 2745 2746 /* Pipe B */ 2747 #define _PIPEBDSL 0x71000 2748 #define _PIPEBCONF 0x71008 2749 #define _PIPEBSTAT 0x71024 2750 #define _PIPEBFRAMEHIGH 0x71040 2751 #define _PIPEBFRAMEPIXEL 0x71044 2752 #define _PIPEB_FRMCOUNT_GM45 0x71040 2753 #define _PIPEB_FLIPCOUNT_GM45 0x71044 2754 2755 2756 /* Display B control */ 2757 #define _DSPBCNTR 0x71180 2758 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2759 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2760 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 2761 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2762 #define _DSPBADDR 0x71184 2763 #define _DSPBSTRIDE 0x71188 2764 #define _DSPBPOS 0x7118C 2765 #define _DSPBSIZE 0x71190 2766 #define _DSPBSURF 0x7119C 2767 #define _DSPBTILEOFF 0x711A4 2768 2769 /* Sprite A control */ 2770 #define _DVSACNTR 0x72180 2771 #define DVS_ENABLE (1<<31) 2772 #define DVS_GAMMA_ENABLE (1<<30) 2773 #define DVS_PIXFORMAT_MASK (3<<25) 2774 #define DVS_FORMAT_YUV422 (0<<25) 2775 #define DVS_FORMAT_RGBX101010 (1<<25) 2776 #define DVS_FORMAT_RGBX888 (2<<25) 2777 #define DVS_FORMAT_RGBX161616 (3<<25) 2778 #define DVS_SOURCE_KEY (1<<22) 2779 #define DVS_RGB_ORDER_XBGR (1<<20) 2780 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 2781 #define DVS_YUV_ORDER_YUYV (0<<16) 2782 #define DVS_YUV_ORDER_UYVY (1<<16) 2783 #define DVS_YUV_ORDER_YVYU (2<<16) 2784 #define DVS_YUV_ORDER_VYUY (3<<16) 2785 #define DVS_DEST_KEY (1<<2) 2786 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 2787 #define DVS_TILED (1<<10) 2788 #define _DVSALINOFF 0x72184 2789 #define _DVSASTRIDE 0x72188 2790 #define _DVSAPOS 0x7218c 2791 #define _DVSASIZE 0x72190 2792 #define _DVSAKEYVAL 0x72194 2793 #define _DVSAKEYMSK 0x72198 2794 #define _DVSASURF 0x7219c 2795 #define _DVSAKEYMAXVAL 0x721a0 2796 #define _DVSATILEOFF 0x721a4 2797 #define _DVSASURFLIVE 0x721ac 2798 #define _DVSASCALE 0x72204 2799 #define DVS_SCALE_ENABLE (1<<31) 2800 #define DVS_FILTER_MASK (3<<29) 2801 #define DVS_FILTER_MEDIUM (0<<29) 2802 #define DVS_FILTER_ENHANCING (1<<29) 2803 #define DVS_FILTER_SOFTENING (2<<29) 2804 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 2805 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 2806 #define _DVSAGAMC 0x72300 2807 2808 #define _DVSBCNTR 0x73180 2809 #define _DVSBLINOFF 0x73184 2810 #define _DVSBSTRIDE 0x73188 2811 #define _DVSBPOS 0x7318c 2812 #define _DVSBSIZE 0x73190 2813 #define _DVSBKEYVAL 0x73194 2814 #define _DVSBKEYMSK 0x73198 2815 #define _DVSBSURF 0x7319c 2816 #define _DVSBKEYMAXVAL 0x731a0 2817 #define _DVSBTILEOFF 0x731a4 2818 #define _DVSBSURFLIVE 0x731ac 2819 #define _DVSBSCALE 0x73204 2820 #define _DVSBGAMC 0x73300 2821 2822 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 2823 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 2824 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 2825 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 2826 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 2827 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 2828 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 2829 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 2830 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 2831 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 2832 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 2833 2834 #define _SPRA_CTL 0x70280 2835 #define SPRITE_ENABLE (1<<31) 2836 #define SPRITE_GAMMA_ENABLE (1<<30) 2837 #define SPRITE_PIXFORMAT_MASK (7<<25) 2838 #define SPRITE_FORMAT_YUV422 (0<<25) 2839 #define SPRITE_FORMAT_RGBX101010 (1<<25) 2840 #define SPRITE_FORMAT_RGBX888 (2<<25) 2841 #define SPRITE_FORMAT_RGBX161616 (3<<25) 2842 #define SPRITE_FORMAT_YUV444 (4<<25) 2843 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 2844 #define SPRITE_CSC_ENABLE (1<<24) 2845 #define SPRITE_SOURCE_KEY (1<<22) 2846 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 2847 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 2848 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 2849 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 2850 #define SPRITE_YUV_ORDER_YUYV (0<<16) 2851 #define SPRITE_YUV_ORDER_UYVY (1<<16) 2852 #define SPRITE_YUV_ORDER_YVYU (2<<16) 2853 #define SPRITE_YUV_ORDER_VYUY (3<<16) 2854 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 2855 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 2856 #define SPRITE_TILED (1<<10) 2857 #define SPRITE_DEST_KEY (1<<2) 2858 #define _SPRA_LINOFF 0x70284 2859 #define _SPRA_STRIDE 0x70288 2860 #define _SPRA_POS 0x7028c 2861 #define _SPRA_SIZE 0x70290 2862 #define _SPRA_KEYVAL 0x70294 2863 #define _SPRA_KEYMSK 0x70298 2864 #define _SPRA_SURF 0x7029c 2865 #define _SPRA_KEYMAX 0x702a0 2866 #define _SPRA_TILEOFF 0x702a4 2867 #define _SPRA_SCALE 0x70304 2868 #define SPRITE_SCALE_ENABLE (1<<31) 2869 #define SPRITE_FILTER_MASK (3<<29) 2870 #define SPRITE_FILTER_MEDIUM (0<<29) 2871 #define SPRITE_FILTER_ENHANCING (1<<29) 2872 #define SPRITE_FILTER_SOFTENING (2<<29) 2873 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 2874 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 2875 #define _SPRA_GAMC 0x70400 2876 2877 #define _SPRB_CTL 0x71280 2878 #define _SPRB_LINOFF 0x71284 2879 #define _SPRB_STRIDE 0x71288 2880 #define _SPRB_POS 0x7128c 2881 #define _SPRB_SIZE 0x71290 2882 #define _SPRB_KEYVAL 0x71294 2883 #define _SPRB_KEYMSK 0x71298 2884 #define _SPRB_SURF 0x7129c 2885 #define _SPRB_KEYMAX 0x712a0 2886 #define _SPRB_TILEOFF 0x712a4 2887 #define _SPRB_SCALE 0x71304 2888 #define _SPRB_GAMC 0x71400 2889 2890 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 2891 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 2892 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 2893 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 2894 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 2895 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 2896 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 2897 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 2898 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 2899 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 2900 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 2901 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 2902 2903 /* VBIOS regs */ 2904 #define VGACNTRL 0x71400 2905 # define VGA_DISP_DISABLE (1 << 31) 2906 # define VGA_2X_MODE (1 << 30) 2907 # define VGA_PIPE_B_SELECT (1 << 29) 2908 2909 /* Ironlake */ 2910 2911 #define CPU_VGACNTRL 0x41000 2912 2913 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 2914 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2915 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 2916 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 2917 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 2918 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 2919 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 2920 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 2921 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2922 2923 /* refresh rate hardware control */ 2924 #define RR_HW_CTL 0x45300 2925 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2926 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2927 2928 #define FDI_PLL_BIOS_0 0x46000 2929 #define FDI_PLL_FB_CLOCK_MASK 0xff 2930 #define FDI_PLL_BIOS_1 0x46004 2931 #define FDI_PLL_BIOS_2 0x46008 2932 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2933 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 2934 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 2935 2936 #define PCH_DSPCLK_GATE_D 0x42020 2937 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 2938 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 2939 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) 2940 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) 2941 2942 #define PCH_3DCGDIS0 0x46020 2943 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 2944 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 2945 2946 #define PCH_3DCGDIS1 0x46024 2947 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 2948 2949 #define FDI_PLL_FREQ_CTL 0x46030 2950 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2951 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2952 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2953 2954 2955 #define _PIPEA_DATA_M1 0x60030 2956 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2957 #define TU_SIZE_MASK 0x7e000000 2958 #define PIPE_DATA_M1_OFFSET 0 2959 #define _PIPEA_DATA_N1 0x60034 2960 #define PIPE_DATA_N1_OFFSET 0 2961 2962 #define _PIPEA_DATA_M2 0x60038 2963 #define PIPE_DATA_M2_OFFSET 0 2964 #define _PIPEA_DATA_N2 0x6003c 2965 #define PIPE_DATA_N2_OFFSET 0 2966 2967 #define _PIPEA_LINK_M1 0x60040 2968 #define PIPE_LINK_M1_OFFSET 0 2969 #define _PIPEA_LINK_N1 0x60044 2970 #define PIPE_LINK_N1_OFFSET 0 2971 2972 #define _PIPEA_LINK_M2 0x60048 2973 #define PIPE_LINK_M2_OFFSET 0 2974 #define _PIPEA_LINK_N2 0x6004c 2975 #define PIPE_LINK_N2_OFFSET 0 2976 2977 /* PIPEB timing regs are same start from 0x61000 */ 2978 2979 #define _PIPEB_DATA_M1 0x61030 2980 #define _PIPEB_DATA_N1 0x61034 2981 2982 #define _PIPEB_DATA_M2 0x61038 2983 #define _PIPEB_DATA_N2 0x6103c 2984 2985 #define _PIPEB_LINK_M1 0x61040 2986 #define _PIPEB_LINK_N1 0x61044 2987 2988 #define _PIPEB_LINK_M2 0x61048 2989 #define _PIPEB_LINK_N2 0x6104c 2990 2991 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) 2992 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) 2993 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2) 2994 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2) 2995 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1) 2996 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1) 2997 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2) 2998 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2) 2999 3000 /* CPU panel fitter */ 3001 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 3002 #define _PFA_CTL_1 0x68080 3003 #define _PFB_CTL_1 0x68880 3004 #define PF_ENABLE (1<<31) 3005 #define PF_FILTER_MASK (3<<23) 3006 #define PF_FILTER_PROGRAMMED (0<<23) 3007 #define PF_FILTER_MED_3x3 (1<<23) 3008 #define PF_FILTER_EDGE_ENHANCE (2<<23) 3009 #define PF_FILTER_EDGE_SOFTEN (3<<23) 3010 #define _PFA_WIN_SZ 0x68074 3011 #define _PFB_WIN_SZ 0x68874 3012 #define _PFA_WIN_POS 0x68070 3013 #define _PFB_WIN_POS 0x68870 3014 #define _PFA_VSCALE 0x68084 3015 #define _PFB_VSCALE 0x68884 3016 #define _PFA_HSCALE 0x68090 3017 #define _PFB_HSCALE 0x68890 3018 3019 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 3020 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 3021 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 3022 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 3023 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 3024 3025 /* legacy palette */ 3026 #define _LGC_PALETTE_A 0x4a000 3027 #define _LGC_PALETTE_B 0x4a800 3028 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 3029 3030 /* interrupts */ 3031 #define DE_MASTER_IRQ_CONTROL (1 << 31) 3032 #define DE_SPRITEB_FLIP_DONE (1 << 29) 3033 #define DE_SPRITEA_FLIP_DONE (1 << 28) 3034 #define DE_PLANEB_FLIP_DONE (1 << 27) 3035 #define DE_PLANEA_FLIP_DONE (1 << 26) 3036 #define DE_PCU_EVENT (1 << 25) 3037 #define DE_GTT_FAULT (1 << 24) 3038 #define DE_POISON (1 << 23) 3039 #define DE_PERFORM_COUNTER (1 << 22) 3040 #define DE_PCH_EVENT (1 << 21) 3041 #define DE_AUX_CHANNEL_A (1 << 20) 3042 #define DE_DP_A_HOTPLUG (1 << 19) 3043 #define DE_GSE (1 << 18) 3044 #define DE_PIPEB_VBLANK (1 << 15) 3045 #define DE_PIPEB_EVEN_FIELD (1 << 14) 3046 #define DE_PIPEB_ODD_FIELD (1 << 13) 3047 #define DE_PIPEB_LINE_COMPARE (1 << 12) 3048 #define DE_PIPEB_VSYNC (1 << 11) 3049 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 3050 #define DE_PIPEA_VBLANK (1 << 7) 3051 #define DE_PIPEA_EVEN_FIELD (1 << 6) 3052 #define DE_PIPEA_ODD_FIELD (1 << 5) 3053 #define DE_PIPEA_LINE_COMPARE (1 << 4) 3054 #define DE_PIPEA_VSYNC (1 << 3) 3055 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 3056 3057 /* More Ivybridge lolz */ 3058 #define DE_ERR_DEBUG_IVB (1<<30) 3059 #define DE_GSE_IVB (1<<29) 3060 #define DE_PCH_EVENT_IVB (1<<28) 3061 #define DE_DP_A_HOTPLUG_IVB (1<<27) 3062 #define DE_AUX_CHANNEL_A_IVB (1<<26) 3063 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 3064 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 3065 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 3066 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 3067 #define DE_PIPEB_VBLANK_IVB (1<<5) 3068 #define DE_PIPEA_VBLANK_IVB (1<<0) 3069 3070 #define DEISR 0x44000 3071 #define DEIMR 0x44004 3072 #define DEIIR 0x44008 3073 #define DEIER 0x4400c 3074 3075 /* GT interrupt */ 3076 #define GT_PIPE_NOTIFY (1 << 4) 3077 #define GT_RENDER_CS_ERROR (1 << 3) 3078 #define GT_SYNC_STATUS (1 << 2) 3079 #define GT_USER_INTERRUPT (1 << 0) 3080 #define GT_BSD_USER_INTERRUPT (1 << 5) 3081 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) 3082 #define GT_BLT_USER_INTERRUPT (1 << 22) 3083 3084 #define GTISR 0x44010 3085 #define GTIMR 0x44014 3086 #define GTIIR 0x44018 3087 #define GTIER 0x4401c 3088 3089 #define ILK_DISPLAY_CHICKEN2 0x42004 3090 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 3091 #define ILK_ELPIN_409_SELECT (1 << 25) 3092 #define ILK_DPARB_GATE (1<<22) 3093 #define ILK_VSDPFD_FULL (1<<21) 3094 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014 3095 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 3096 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 3097 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 3098 #define ILK_HDCP_DISABLE (1<<25) 3099 #define ILK_eDP_A_DISABLE (1<<24) 3100 #define ILK_DESKTOP (1<<23) 3101 #define ILK_DSPCLK_GATE 0x42020 3102 #define IVB_VRHUNIT_CLK_GATE (1<<28) 3103 #define ILK_DPARB_CLK_GATE (1<<5) 3104 #define ILK_DPFD_CLK_GATE (1<<7) 3105 3106 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ 3107 #define ILK_CLK_FBC (1<<7) 3108 #define ILK_DPFC_DIS1 (1<<8) 3109 #define ILK_DPFC_DIS2 (1<<9) 3110 3111 #define IVB_CHICKEN3 0x4200c 3112 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 3113 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 3114 3115 #define DISP_ARB_CTL 0x45000 3116 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 3117 #define DISP_FBC_WM_DIS (1<<15) 3118 3119 /* GEN7 chicken */ 3120 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 3121 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 3122 3123 #define GEN7_L3CNTLREG1 0xB01C 3124 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C 3125 3126 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 3127 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 3128 3129 /* WaCatErrorRejectionIssue */ 3130 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3131 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3132 3133 /* PCH */ 3134 3135 /* south display engine interrupt */ 3136 #define SDE_AUDIO_POWER_D (1 << 27) 3137 #define SDE_AUDIO_POWER_C (1 << 26) 3138 #define SDE_AUDIO_POWER_B (1 << 25) 3139 #define SDE_AUDIO_POWER_SHIFT (25) 3140 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 3141 #define SDE_GMBUS (1 << 24) 3142 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 3143 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 3144 #define SDE_AUDIO_HDCP_MASK (3 << 22) 3145 #define SDE_AUDIO_TRANSB (1 << 21) 3146 #define SDE_AUDIO_TRANSA (1 << 20) 3147 #define SDE_AUDIO_TRANS_MASK (3 << 20) 3148 #define SDE_POISON (1 << 19) 3149 /* 18 reserved */ 3150 #define SDE_FDI_RXB (1 << 17) 3151 #define SDE_FDI_RXA (1 << 16) 3152 #define SDE_FDI_MASK (3 << 16) 3153 #define SDE_AUXD (1 << 15) 3154 #define SDE_AUXC (1 << 14) 3155 #define SDE_AUXB (1 << 13) 3156 #define SDE_AUX_MASK (7 << 13) 3157 /* 12 reserved */ 3158 #define SDE_CRT_HOTPLUG (1 << 11) 3159 #define SDE_PORTD_HOTPLUG (1 << 10) 3160 #define SDE_PORTC_HOTPLUG (1 << 9) 3161 #define SDE_PORTB_HOTPLUG (1 << 8) 3162 #define SDE_SDVOB_HOTPLUG (1 << 6) 3163 #define SDE_HOTPLUG_MASK (0xf << 8) 3164 #define SDE_TRANSB_CRC_DONE (1 << 5) 3165 #define SDE_TRANSB_CRC_ERR (1 << 4) 3166 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 3167 #define SDE_TRANSA_CRC_DONE (1 << 2) 3168 #define SDE_TRANSA_CRC_ERR (1 << 1) 3169 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 3170 #define SDE_TRANS_MASK (0x3f) 3171 /* CPT */ 3172 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 3173 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3174 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3175 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3176 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3177 SDE_PORTD_HOTPLUG_CPT | \ 3178 SDE_PORTC_HOTPLUG_CPT | \ 3179 SDE_PORTB_HOTPLUG_CPT) 3180 3181 #define SDEISR 0xc4000 3182 #define SDEIMR 0xc4004 3183 #define SDEIIR 0xc4008 3184 #define SDEIER 0xc400c 3185 3186 /* digital port hotplug */ 3187 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 3188 #define PORTD_HOTPLUG_ENABLE (1 << 20) 3189 #define PORTD_PULSE_DURATION_2ms (0) 3190 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 3191 #define PORTD_PULSE_DURATION_6ms (2 << 18) 3192 #define PORTD_PULSE_DURATION_100ms (3 << 18) 3193 #define PORTD_PULSE_DURATION_MASK (3 << 18) 3194 #define PORTD_HOTPLUG_NO_DETECT (0) 3195 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 3196 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 3197 #define PORTC_HOTPLUG_ENABLE (1 << 12) 3198 #define PORTC_PULSE_DURATION_2ms (0) 3199 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 3200 #define PORTC_PULSE_DURATION_6ms (2 << 10) 3201 #define PORTC_PULSE_DURATION_100ms (3 << 10) 3202 #define PORTC_PULSE_DURATION_MASK (3 << 10) 3203 #define PORTC_HOTPLUG_NO_DETECT (0) 3204 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 3205 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 3206 #define PORTB_HOTPLUG_ENABLE (1 << 4) 3207 #define PORTB_PULSE_DURATION_2ms (0) 3208 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 3209 #define PORTB_PULSE_DURATION_6ms (2 << 2) 3210 #define PORTB_PULSE_DURATION_100ms (3 << 2) 3211 #define PORTB_PULSE_DURATION_MASK (3 << 2) 3212 #define PORTB_HOTPLUG_NO_DETECT (0) 3213 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 3214 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 3215 3216 #define PCH_GPIOA 0xc5010 3217 #define PCH_GPIOB 0xc5014 3218 #define PCH_GPIOC 0xc5018 3219 #define PCH_GPIOD 0xc501c 3220 #define PCH_GPIOE 0xc5020 3221 #define PCH_GPIOF 0xc5024 3222 3223 #define PCH_GMBUS0 0xc5100 3224 #define PCH_GMBUS1 0xc5104 3225 #define PCH_GMBUS2 0xc5108 3226 #define PCH_GMBUS3 0xc510c 3227 #define PCH_GMBUS4 0xc5110 3228 #define PCH_GMBUS5 0xc5120 3229 3230 #define _PCH_DPLL_A 0xc6014 3231 #define _PCH_DPLL_B 0xc6018 3232 #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 3233 3234 #define _PCH_FPA0 0xc6040 3235 #define FP_CB_TUNE (0x3<<22) 3236 #define _PCH_FPA1 0xc6044 3237 #define _PCH_FPB0 0xc6048 3238 #define _PCH_FPB1 0xc604c 3239 #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) 3240 #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1) 3241 3242 #define PCH_DPLL_TEST 0xc606c 3243 3244 #define PCH_DREF_CONTROL 0xC6200 3245 #define DREF_CONTROL_MASK 0x7fc3 3246 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 3247 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 3248 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 3249 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 3250 #define DREF_SSC_SOURCE_DISABLE (0<<11) 3251 #define DREF_SSC_SOURCE_ENABLE (2<<11) 3252 #define DREF_SSC_SOURCE_MASK (3<<11) 3253 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 3254 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 3255 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 3256 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 3257 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 3258 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 3259 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 3260 #define DREF_SSC4_DOWNSPREAD (0<<6) 3261 #define DREF_SSC4_CENTERSPREAD (1<<6) 3262 #define DREF_SSC1_DISABLE (0<<1) 3263 #define DREF_SSC1_ENABLE (1<<1) 3264 #define DREF_SSC4_DISABLE (0) 3265 #define DREF_SSC4_ENABLE (1) 3266 3267 #define PCH_RAWCLK_FREQ 0xc6204 3268 #define FDL_TP1_TIMER_SHIFT 12 3269 #define FDL_TP1_TIMER_MASK (3<<12) 3270 #define FDL_TP2_TIMER_SHIFT 10 3271 #define FDL_TP2_TIMER_MASK (3<<10) 3272 #define RAWCLK_FREQ_MASK 0x3ff 3273 3274 #define PCH_DPLL_TMR_CFG 0xc6208 3275 3276 #define PCH_SSC4_PARMS 0xc6210 3277 #define PCH_SSC4_AUX_PARMS 0xc6214 3278 3279 #define PCH_DPLL_SEL 0xc7000 3280 #define TRANSA_DPLL_ENABLE (1<<3) 3281 #define TRANSA_DPLLB_SEL (1<<0) 3282 #define TRANSA_DPLLA_SEL 0 3283 #define TRANSB_DPLL_ENABLE (1<<7) 3284 #define TRANSB_DPLLB_SEL (1<<4) 3285 #define TRANSB_DPLLA_SEL (0) 3286 #define TRANSC_DPLL_ENABLE (1<<11) 3287 #define TRANSC_DPLLB_SEL (1<<8) 3288 #define TRANSC_DPLLA_SEL (0) 3289 3290 /* transcoder */ 3291 3292 #define _TRANS_HTOTAL_A 0xe0000 3293 #define TRANS_HTOTAL_SHIFT 16 3294 #define TRANS_HACTIVE_SHIFT 0 3295 #define _TRANS_HBLANK_A 0xe0004 3296 #define TRANS_HBLANK_END_SHIFT 16 3297 #define TRANS_HBLANK_START_SHIFT 0 3298 #define _TRANS_HSYNC_A 0xe0008 3299 #define TRANS_HSYNC_END_SHIFT 16 3300 #define TRANS_HSYNC_START_SHIFT 0 3301 #define _TRANS_VTOTAL_A 0xe000c 3302 #define TRANS_VTOTAL_SHIFT 16 3303 #define TRANS_VACTIVE_SHIFT 0 3304 #define _TRANS_VBLANK_A 0xe0010 3305 #define TRANS_VBLANK_END_SHIFT 16 3306 #define TRANS_VBLANK_START_SHIFT 0 3307 #define _TRANS_VSYNC_A 0xe0014 3308 #define TRANS_VSYNC_END_SHIFT 16 3309 #define TRANS_VSYNC_START_SHIFT 0 3310 #define _TRANS_VSYNCSHIFT_A 0xe0028 3311 3312 #define _TRANSA_DATA_M1 0xe0030 3313 #define _TRANSA_DATA_N1 0xe0034 3314 #define _TRANSA_DATA_M2 0xe0038 3315 #define _TRANSA_DATA_N2 0xe003c 3316 #define _TRANSA_DP_LINK_M1 0xe0040 3317 #define _TRANSA_DP_LINK_N1 0xe0044 3318 #define _TRANSA_DP_LINK_M2 0xe0048 3319 #define _TRANSA_DP_LINK_N2 0xe004c 3320 3321 /* Per-transcoder DIP controls */ 3322 3323 #define _VIDEO_DIP_CTL_A 0xe0200 3324 #define _VIDEO_DIP_DATA_A 0xe0208 3325 #define _VIDEO_DIP_GCP_A 0xe0210 3326 3327 #define _VIDEO_DIP_CTL_B 0xe1200 3328 #define _VIDEO_DIP_DATA_B 0xe1208 3329 #define _VIDEO_DIP_GCP_B 0xe1210 3330 3331 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 3332 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 3333 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 3334 3335 #define _TRANS_HTOTAL_B 0xe1000 3336 #define _TRANS_HBLANK_B 0xe1004 3337 #define _TRANS_HSYNC_B 0xe1008 3338 #define _TRANS_VTOTAL_B 0xe100c 3339 #define _TRANS_VBLANK_B 0xe1010 3340 #define _TRANS_VSYNC_B 0xe1014 3341 #define _TRANS_VSYNCSHIFT_B 0xe1028 3342 3343 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) 3344 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) 3345 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B) 3346 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) 3347 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) 3348 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) 3349 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ 3350 _TRANS_VSYNCSHIFT_B) 3351 3352 #define _TRANSB_DATA_M1 0xe1030 3353 #define _TRANSB_DATA_N1 0xe1034 3354 #define _TRANSB_DATA_M2 0xe1038 3355 #define _TRANSB_DATA_N2 0xe103c 3356 #define _TRANSB_DP_LINK_M1 0xe1040 3357 #define _TRANSB_DP_LINK_N1 0xe1044 3358 #define _TRANSB_DP_LINK_M2 0xe1048 3359 #define _TRANSB_DP_LINK_N2 0xe104c 3360 3361 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) 3362 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) 3363 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2) 3364 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2) 3365 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1) 3366 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1) 3367 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) 3368 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2) 3369 3370 #define _TRANSACONF 0xf0008 3371 #define _TRANSBCONF 0xf1008 3372 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) 3373 #define TRANS_DISABLE (0<<31) 3374 #define TRANS_ENABLE (1<<31) 3375 #define TRANS_STATE_MASK (1<<30) 3376 #define TRANS_STATE_DISABLE (0<<30) 3377 #define TRANS_STATE_ENABLE (1<<30) 3378 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 3379 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 3380 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 3381 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 3382 #define TRANS_DP_AUDIO_ONLY (1<<26) 3383 #define TRANS_DP_VIDEO_AUDIO (0<<26) 3384 #define TRANS_INTERLACE_MASK (7<<21) 3385 #define TRANS_PROGRESSIVE (0<<21) 3386 #define TRANS_INTERLACED (3<<21) 3387 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 3388 #define TRANS_8BPC (0<<5) 3389 #define TRANS_10BPC (1<<5) 3390 #define TRANS_6BPC (2<<5) 3391 #define TRANS_12BPC (3<<5) 3392 3393 #define _TRANSA_CHICKEN2 0xf0064 3394 #define _TRANSB_CHICKEN2 0xf1064 3395 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 3396 #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) 3397 3398 #define SOUTH_CHICKEN1 0xc2000 3399 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 3400 #define FDIA_PHASE_SYNC_SHIFT_EN 18 3401 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 3402 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 3403 #define SOUTH_CHICKEN2 0xc2004 3404 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 3405 3406 #define _FDI_RXA_CHICKEN 0xc200c 3407 #define _FDI_RXB_CHICKEN 0xc2010 3408 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 3409 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 3410 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 3411 3412 #define SOUTH_DSPCLK_GATE_D 0xc2020 3413 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 3414 3415 /* CPU: FDI_TX */ 3416 #define _FDI_TXA_CTL 0x60100 3417 #define _FDI_TXB_CTL 0x61100 3418 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 3419 #define FDI_TX_DISABLE (0<<31) 3420 #define FDI_TX_ENABLE (1<<31) 3421 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3422 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3423 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3424 #define FDI_LINK_TRAIN_NONE (3<<28) 3425 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3426 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3427 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3428 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3429 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3430 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3431 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3432 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3433 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3434 SNB has different settings. */ 3435 /* SNB A-stepping */ 3436 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3437 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3438 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3439 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3440 /* SNB B-stepping */ 3441 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3442 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3443 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3444 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3445 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3446 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3447 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3448 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3449 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3450 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3451 /* Ironlake: hardwired to 1 */ 3452 #define FDI_TX_PLL_ENABLE (1<<14) 3453 3454 /* Ivybridge has different bits for lolz */ 3455 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 3456 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 3457 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 3458 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 3459 3460 /* both Tx and Rx */ 3461 #define FDI_COMPOSITE_SYNC (1<<11) 3462 #define FDI_LINK_TRAIN_AUTO (1<<10) 3463 #define FDI_SCRAMBLING_ENABLE (0<<7) 3464 #define FDI_SCRAMBLING_DISABLE (1<<7) 3465 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3466 #define _FDI_RXA_CTL 0xf000c 3467 #define _FDI_RXB_CTL 0xf100c 3468 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 3469 #define FDI_RX_ENABLE (1<<31) 3470 /* train, dp width same as FDI_TX */ 3471 #define FDI_FS_ERRC_ENABLE (1<<27) 3472 #define FDI_FE_ERRC_ENABLE (1<<26) 3473 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3474 #define FDI_8BPC (0<<16) 3475 #define FDI_10BPC (1<<16) 3476 #define FDI_6BPC (2<<16) 3477 #define FDI_12BPC (3<<16) 3478 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3479 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3480 #define FDI_RX_PLL_ENABLE (1<<13) 3481 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3482 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3483 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3484 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3485 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3486 #define FDI_PCDCLK (1<<4) 3487 /* CPT */ 3488 #define FDI_AUTO_TRAINING (1<<10) 3489 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3490 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3491 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3492 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3493 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3494 3495 #define _FDI_RXA_MISC 0xf0010 3496 #define _FDI_RXB_MISC 0xf1010 3497 #define _FDI_RXA_TUSIZE1 0xf0030 3498 #define _FDI_RXA_TUSIZE2 0xf0038 3499 #define _FDI_RXB_TUSIZE1 0xf1030 3500 #define _FDI_RXB_TUSIZE2 0xf1038 3501 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 3502 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 3503 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 3504 3505 /* FDI_RX interrupt register format */ 3506 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3507 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3508 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3509 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3510 #define FDI_RX_FS_CODE_ERR (1<<6) 3511 #define FDI_RX_FE_CODE_ERR (1<<5) 3512 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3513 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3514 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3515 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3516 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3517 3518 #define _FDI_RXA_IIR 0xf0014 3519 #define _FDI_RXA_IMR 0xf0018 3520 #define _FDI_RXB_IIR 0xf1014 3521 #define _FDI_RXB_IMR 0xf1018 3522 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 3523 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 3524 3525 #define FDI_PLL_CTL_1 0xfe000 3526 #define FDI_PLL_CTL_2 0xfe004 3527 3528 /* CRT */ 3529 #define PCH_ADPA 0xe1100 3530 #define ADPA_TRANS_SELECT_MASK (1<<30) 3531 #define ADPA_TRANS_A_SELECT 0 3532 #define ADPA_TRANS_B_SELECT (1<<30) 3533 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3534 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3535 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3536 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3537 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3538 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3539 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3540 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3541 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3542 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3543 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3544 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3545 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3546 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3547 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3548 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3549 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3550 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3551 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3552 3553 /* or SDVOB */ 3554 #define HDMIB 0xe1140 3555 #define PORT_ENABLE (1 << 31) 3556 #define TRANSCODER(pipe) ((pipe) << 30) 3557 #define TRANSCODER_CPT(pipe) ((pipe) << 29) 3558 #define TRANSCODER_MASK (1 << 30) 3559 #define TRANSCODER_MASK_CPT (3 << 29) 3560 #define COLOR_FORMAT_8bpc (0) 3561 #define COLOR_FORMAT_12bpc (3 << 26) 3562 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3563 #define SDVO_ENCODING (0) 3564 #define TMDS_ENCODING (2 << 10) 3565 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3566 /* CPT */ 3567 #define HDMI_MODE_SELECT (1 << 9) 3568 #define DVI_MODE_SELECT (0) 3569 #define SDVOB_BORDER_ENABLE (1 << 7) 3570 #define AUDIO_ENABLE (1 << 6) 3571 #define VSYNC_ACTIVE_HIGH (1 << 4) 3572 #define HSYNC_ACTIVE_HIGH (1 << 3) 3573 #define PORT_DETECTED (1 << 2) 3574 3575 /* PCH SDVOB multiplex with HDMIB */ 3576 #define PCH_SDVOB HDMIB 3577 3578 #define HDMIC 0xe1150 3579 #define HDMID 0xe1160 3580 3581 #define PCH_LVDS 0xe1180 3582 #define LVDS_DETECTED (1 << 1) 3583 3584 #define BLC_PWM_CPU_CTL2 0x48250 3585 #define PWM_ENABLE (1 << 31) 3586 #define PWM_PIPE_A (0 << 29) 3587 #define PWM_PIPE_B (1 << 29) 3588 #define BLC_PWM_CPU_CTL 0x48254 3589 3590 #define BLC_PWM_PCH_CTL1 0xc8250 3591 #define PWM_PCH_ENABLE (1 << 31) 3592 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 3593 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 3594 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 3595 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 3596 3597 #define BLC_PWM_PCH_CTL2 0xc8254 3598 3599 #define PCH_PP_STATUS 0xc7200 3600 #define PCH_PP_CONTROL 0xc7204 3601 #define PANEL_UNLOCK_REGS (0xabcd << 16) 3602 #define PANEL_UNLOCK_MASK (0xffff << 16) 3603 #define EDP_FORCE_VDD (1 << 3) 3604 #define EDP_BLC_ENABLE (1 << 2) 3605 #define PANEL_POWER_RESET (1 << 1) 3606 #define PANEL_POWER_OFF (0 << 0) 3607 #define PANEL_POWER_ON (1 << 0) 3608 #define PCH_PP_ON_DELAYS 0xc7208 3609 #define PANEL_PORT_SELECT_MASK (3 << 30) 3610 #define PANEL_PORT_SELECT_LVDS (0 << 30) 3611 #define PANEL_PORT_SELECT_DPA (1 << 30) 3612 #define EDP_PANEL (1 << 30) 3613 #define PANEL_PORT_SELECT_DPC (2 << 30) 3614 #define PANEL_PORT_SELECT_DPD (3 << 30) 3615 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 3616 #define PANEL_POWER_UP_DELAY_SHIFT 16 3617 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 3618 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 3619 3620 #define PCH_PP_OFF_DELAYS 0xc720c 3621 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 3622 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 3623 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 3624 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 3625 3626 #define PCH_PP_DIVISOR 0xc7210 3627 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 3628 #define PP_REFERENCE_DIVIDER_SHIFT 8 3629 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 3630 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 3631 3632 #define PCH_DP_B 0xe4100 3633 #define PCH_DPB_AUX_CH_CTL 0xe4110 3634 #define PCH_DPB_AUX_CH_DATA1 0xe4114 3635 #define PCH_DPB_AUX_CH_DATA2 0xe4118 3636 #define PCH_DPB_AUX_CH_DATA3 0xe411c 3637 #define PCH_DPB_AUX_CH_DATA4 0xe4120 3638 #define PCH_DPB_AUX_CH_DATA5 0xe4124 3639 3640 #define PCH_DP_C 0xe4200 3641 #define PCH_DPC_AUX_CH_CTL 0xe4210 3642 #define PCH_DPC_AUX_CH_DATA1 0xe4214 3643 #define PCH_DPC_AUX_CH_DATA2 0xe4218 3644 #define PCH_DPC_AUX_CH_DATA3 0xe421c 3645 #define PCH_DPC_AUX_CH_DATA4 0xe4220 3646 #define PCH_DPC_AUX_CH_DATA5 0xe4224 3647 3648 #define PCH_DP_D 0xe4300 3649 #define PCH_DPD_AUX_CH_CTL 0xe4310 3650 #define PCH_DPD_AUX_CH_DATA1 0xe4314 3651 #define PCH_DPD_AUX_CH_DATA2 0xe4318 3652 #define PCH_DPD_AUX_CH_DATA3 0xe431c 3653 #define PCH_DPD_AUX_CH_DATA4 0xe4320 3654 #define PCH_DPD_AUX_CH_DATA5 0xe4324 3655 3656 /* CPT */ 3657 #define PORT_TRANS_A_SEL_CPT 0 3658 #define PORT_TRANS_B_SEL_CPT (1<<29) 3659 #define PORT_TRANS_C_SEL_CPT (2<<29) 3660 #define PORT_TRANS_SEL_MASK (3<<29) 3661 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 3662 3663 #define TRANS_DP_CTL_A 0xe0300 3664 #define TRANS_DP_CTL_B 0xe1300 3665 #define TRANS_DP_CTL_C 0xe2300 3666 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000) 3667 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 3668 #define TRANS_DP_PORT_SEL_B (0<<29) 3669 #define TRANS_DP_PORT_SEL_C (1<<29) 3670 #define TRANS_DP_PORT_SEL_D (2<<29) 3671 #define TRANS_DP_PORT_SEL_NONE (3<<29) 3672 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3673 #define TRANS_DP_AUDIO_ONLY (1<<26) 3674 #define TRANS_DP_ENH_FRAMING (1<<18) 3675 #define TRANS_DP_8BPC (0<<9) 3676 #define TRANS_DP_10BPC (1<<9) 3677 #define TRANS_DP_6BPC (2<<9) 3678 #define TRANS_DP_12BPC (3<<9) 3679 #define TRANS_DP_BPC_MASK (3<<9) 3680 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3681 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3682 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3683 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3684 #define TRANS_DP_SYNC_MASK (3<<3) 3685 3686 /* SNB eDP training params */ 3687 /* SNB A-stepping */ 3688 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3689 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3690 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3691 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3692 /* SNB B-stepping */ 3693 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 3694 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 3695 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 3696 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 3697 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 3698 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 3699 3700 /* IVB */ 3701 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 3702 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 3703 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 3704 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 3705 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 3706 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 3707 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22) 3708 3709 /* legacy values */ 3710 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 3711 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 3712 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 3713 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 3714 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 3715 3716 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 3717 3718 #define FORCEWAKE 0xA18C 3719 #define FORCEWAKE_ACK 0x130090 3720 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 3721 #define FORCEWAKE_MT_ACK 0x130040 3722 #define ECOBUS 0xa180 3723 #define FORCEWAKE_MT_ENABLE (1<<5) 3724 3725 #define GTFIFODBG 0x120000 3726 #define GT_FIFO_CPU_ERROR_MASK 7 3727 #define GT_FIFO_OVFERR (1<<2) 3728 #define GT_FIFO_IAWRERR (1<<1) 3729 #define GT_FIFO_IARDERR (1<<0) 3730 3731 #define GT_FIFO_FREE_ENTRIES 0x120008 3732 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 3733 3734 #define GEN6_UCGCTL1 0x9400 3735 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 3736 3737 #define GEN6_UCGCTL2 0x9404 3738 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 3739 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 3740 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 3741 3742 #define GEN6_RPNSWREQ 0xA008 3743 #define GEN6_TURBO_DISABLE (1<<31) 3744 #define GEN6_FREQUENCY(x) ((x)<<25) 3745 #define GEN6_OFFSET(x) ((x)<<19) 3746 #define GEN6_AGGRESSIVE_TURBO (0<<15) 3747 #define GEN6_RC_VIDEO_FREQ 0xA00C 3748 #define GEN6_RC_CONTROL 0xA090 3749 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 3750 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 3751 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 3752 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 3753 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 3754 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 3755 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 3756 #define GEN6_RP_DOWN_TIMEOUT 0xA010 3757 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 3758 #define GEN6_RPSTAT1 0xA01C 3759 #define GEN6_CAGF_SHIFT 8 3760 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 3761 #define GEN6_RP_CONTROL 0xA024 3762 #define GEN6_RP_MEDIA_TURBO (1<<11) 3763 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 3764 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 3765 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 3766 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 3767 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 3768 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 3769 #define GEN6_RP_ENABLE (1<<7) 3770 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 3771 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 3772 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 3773 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 3774 #define GEN6_RP_UP_THRESHOLD 0xA02C 3775 #define GEN6_RP_DOWN_THRESHOLD 0xA030 3776 #define GEN6_RP_CUR_UP_EI 0xA050 3777 #define GEN6_CURICONT_MASK 0xffffff 3778 #define GEN6_RP_CUR_UP 0xA054 3779 #define GEN6_CURBSYTAVG_MASK 0xffffff 3780 #define GEN6_RP_PREV_UP 0xA058 3781 #define GEN6_RP_CUR_DOWN_EI 0xA05C 3782 #define GEN6_CURIAVG_MASK 0xffffff 3783 #define GEN6_RP_CUR_DOWN 0xA060 3784 #define GEN6_RP_PREV_DOWN 0xA064 3785 #define GEN6_RP_UP_EI 0xA068 3786 #define GEN6_RP_DOWN_EI 0xA06C 3787 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 3788 #define GEN6_RC_STATE 0xA094 3789 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 3790 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 3791 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 3792 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 3793 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 3794 #define GEN6_RC_SLEEP 0xA0B0 3795 #define GEN6_RC1e_THRESHOLD 0xA0B4 3796 #define GEN6_RC6_THRESHOLD 0xA0B8 3797 #define GEN6_RC6p_THRESHOLD 0xA0BC 3798 #define GEN6_RC6pp_THRESHOLD 0xA0C0 3799 #define GEN6_PMINTRMSK 0xA168 3800 3801 #define GEN6_PMISR 0x44020 3802 #define GEN6_PMIMR 0x44024 /* rps_lock */ 3803 #define GEN6_PMIIR 0x44028 3804 #define GEN6_PMIER 0x4402C 3805 #define GEN6_PM_MBOX_EVENT (1<<25) 3806 #define GEN6_PM_THERMAL_EVENT (1<<24) 3807 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 3808 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 3809 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 3810 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 3811 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 3812 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 3813 GEN6_PM_RP_DOWN_THRESHOLD | \ 3814 GEN6_PM_RP_DOWN_TIMEOUT) 3815 3816 #define GEN6_PCODE_MAILBOX 0x138124 3817 #define GEN6_PCODE_READY (1<<31) 3818 #define GEN6_READ_OC_PARAMS 0xc 3819 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 3820 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 3821 #define GEN6_PCODE_DATA 0x138128 3822 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 3823 3824 #define GEN6_GT_CORE_STATUS 0x138060 3825 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 3826 #define GEN6_RCn_MASK 7 3827 #define GEN6_RC0 0 3828 #define GEN6_RC3 2 3829 #define GEN6_RC6 3 3830 #define GEN6_RC7 4 3831 3832 #define G4X_AUD_VID_DID 0x62020 3833 #define INTEL_AUDIO_DEVCL 0x808629FB 3834 #define INTEL_AUDIO_DEVBLC 0x80862801 3835 #define INTEL_AUDIO_DEVCTG 0x80862802 3836 3837 #define G4X_AUD_CNTL_ST 0x620B4 3838 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 3839 #define G4X_ELDV_DEVCTG (1 << 14) 3840 #define G4X_ELD_ADDR (0xf << 5) 3841 #define G4X_ELD_ACK (1 << 4) 3842 #define G4X_HDMIW_HDMIEDID 0x6210C 3843 3844 #define IBX_HDMIW_HDMIEDID_A 0xE2050 3845 #define IBX_AUD_CNTL_ST_A 0xE20B4 3846 #define IBX_ELD_BUFFER_SIZE (0x1f << 10) 3847 #define IBX_ELD_ADDRESS (0x1f << 5) 3848 #define IBX_ELD_ACK (1 << 4) 3849 #define IBX_AUD_CNTL_ST2 0xE20C0 3850 #define IBX_ELD_VALIDB (1 << 0) 3851 #define IBX_CP_READYB (1 << 1) 3852 3853 #define CPT_HDMIW_HDMIEDID_A 0xE5050 3854 #define CPT_AUD_CNTL_ST_A 0xE50B4 3855 #define CPT_AUD_CNTRL_ST2 0xE50C0 3856 3857 /* These are the 4 32-bit write offset registers for each stream 3858 * output buffer. It determines the offset from the 3859 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 3860 */ 3861 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 3862 3863 #define IBX_AUD_CONFIG_A 0xe2000 3864 #define CPT_AUD_CONFIG_A 0xe5000 3865 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 3866 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 3867 #define AUD_CONFIG_UPPER_N_SHIFT 20 3868 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) 3869 #define AUD_CONFIG_LOWER_N_SHIFT 4 3870 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) 3871 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 3872 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) 3873 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 3874 3875 #endif /* _I915_REG_H_ */ 3876