1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 /* 29 * The Bridge device's PCI config space has information about the 30 * fb aperture size and the amount of pre-reserved memory. 31 */ 32 #define INTEL_GMCH_CTRL 0x52 33 #define INTEL_GMCH_ENABLED 0x4 34 #define INTEL_GMCH_MEM_MASK 0x1 35 #define INTEL_GMCH_MEM_64M 0x1 36 #define INTEL_GMCH_MEM_128M 0 37 38 #define INTEL_GMCH_GMS_MASK (0xf << 4) 39 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) 40 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) 41 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) 42 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) 43 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) 44 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) 45 46 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) 47 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) 48 #define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4) 49 #define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4) 50 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 51 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 52 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 53 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 54 55 /* PCI config space */ 56 57 #define HPLLCC 0xc0 /* 855 only */ 58 #define GC_CLOCK_CONTROL_MASK (3 << 0) 59 #define GC_CLOCK_133_200 (0 << 0) 60 #define GC_CLOCK_100_200 (1 << 0) 61 #define GC_CLOCK_100_133 (2 << 0) 62 #define GC_CLOCK_166_250 (3 << 0) 63 #define GCFGC 0xf0 /* 915+ only */ 64 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 65 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 66 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 67 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 68 #define LBB 0xf4 69 70 /* VGA stuff */ 71 72 #define VGA_ST01_MDA 0x3ba 73 #define VGA_ST01_CGA 0x3da 74 75 #define VGA_MSR_WRITE 0x3c2 76 #define VGA_MSR_READ 0x3cc 77 #define VGA_MSR_MEM_EN (1<<1) 78 #define VGA_MSR_CGA_MODE (1<<0) 79 80 #define VGA_SR_INDEX 0x3c4 81 #define VGA_SR_DATA 0x3c5 82 83 #define VGA_AR_INDEX 0x3c0 84 #define VGA_AR_VID_EN (1<<5) 85 #define VGA_AR_DATA_WRITE 0x3c0 86 #define VGA_AR_DATA_READ 0x3c1 87 88 #define VGA_GR_INDEX 0x3ce 89 #define VGA_GR_DATA 0x3cf 90 /* GR05 */ 91 #define VGA_GR_MEM_READ_MODE_SHIFT 3 92 #define VGA_GR_MEM_READ_MODE_PLANE 1 93 /* GR06 */ 94 #define VGA_GR_MEM_MODE_MASK 0xc 95 #define VGA_GR_MEM_MODE_SHIFT 2 96 #define VGA_GR_MEM_A0000_AFFFF 0 97 #define VGA_GR_MEM_A0000_BFFFF 1 98 #define VGA_GR_MEM_B0000_B7FFF 2 99 #define VGA_GR_MEM_B0000_BFFFF 3 100 101 #define VGA_DACMASK 0x3c6 102 #define VGA_DACRX 0x3c7 103 #define VGA_DACWX 0x3c8 104 #define VGA_DACDATA 0x3c9 105 106 #define VGA_CR_INDEX_MDA 0x3b4 107 #define VGA_CR_DATA_MDA 0x3b5 108 #define VGA_CR_INDEX_CGA 0x3d4 109 #define VGA_CR_DATA_CGA 0x3d5 110 111 /* 112 * Memory interface instructions used by the kernel 113 */ 114 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 115 116 #define MI_NOOP MI_INSTR(0, 0) 117 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 118 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 119 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 120 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 121 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 122 #define MI_FLUSH MI_INSTR(0x04, 0) 123 #define MI_READ_FLUSH (1 << 0) 124 #define MI_EXE_FLUSH (1 << 1) 125 #define MI_NO_WRITE_FLUSH (1 << 2) 126 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 127 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 128 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 129 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 130 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 131 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 132 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 133 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 134 #define MI_STORE_DWORD_INDEX_SHIFT 2 135 #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) 136 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 137 #define MI_BATCH_NON_SECURE (1) 138 #define MI_BATCH_NON_SECURE_I965 (1<<8) 139 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 140 141 /* 142 * 3D instructions used by the kernel 143 */ 144 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 145 146 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 147 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 148 #define SC_UPDATE_SCISSOR (0x1<<1) 149 #define SC_ENABLE_MASK (0x1<<0) 150 #define SC_ENABLE (0x1<<0) 151 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 152 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 153 #define SCI_YMIN_MASK (0xffff<<16) 154 #define SCI_XMIN_MASK (0xffff<<0) 155 #define SCI_YMAX_MASK (0xffff<<16) 156 #define SCI_XMAX_MASK (0xffff<<0) 157 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 158 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 159 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 160 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 161 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 162 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 163 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 164 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 165 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 166 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 167 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 168 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 169 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 170 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 171 #define BLT_DEPTH_8 (0<<24) 172 #define BLT_DEPTH_16_565 (1<<24) 173 #define BLT_DEPTH_16_1555 (2<<24) 174 #define BLT_DEPTH_32 (3<<24) 175 #define BLT_ROP_GXCOPY (0xcc<<16) 176 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 177 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 178 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 179 #define ASYNC_FLIP (1<<22) 180 #define DISPLAY_PLANE_A (0<<20) 181 #define DISPLAY_PLANE_B (1<<20) 182 183 /* 184 * Fence registers 185 */ 186 #define FENCE_REG_830_0 0x2000 187 #define FENCE_REG_945_8 0x3000 188 #define I830_FENCE_START_MASK 0x07f80000 189 #define I830_FENCE_TILING_Y_SHIFT 12 190 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 191 #define I830_FENCE_PITCH_SHIFT 4 192 #define I830_FENCE_REG_VALID (1<<0) 193 194 #define I915_FENCE_START_MASK 0x0ff00000 195 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 196 197 #define FENCE_REG_965_0 0x03000 198 #define I965_FENCE_PITCH_SHIFT 2 199 #define I965_FENCE_TILING_Y_SHIFT 1 200 #define I965_FENCE_REG_VALID (1<<0) 201 202 /* 203 * Instruction and interrupt control regs 204 */ 205 #define PRB0_TAIL 0x02030 206 #define PRB0_HEAD 0x02034 207 #define PRB0_START 0x02038 208 #define PRB0_CTL 0x0203c 209 #define TAIL_ADDR 0x001FFFF8 210 #define HEAD_WRAP_COUNT 0xFFE00000 211 #define HEAD_WRAP_ONE 0x00200000 212 #define HEAD_ADDR 0x001FFFFC 213 #define RING_NR_PAGES 0x001FF000 214 #define RING_REPORT_MASK 0x00000006 215 #define RING_REPORT_64K 0x00000002 216 #define RING_REPORT_128K 0x00000004 217 #define RING_NO_REPORT 0x00000000 218 #define RING_VALID_MASK 0x00000001 219 #define RING_VALID 0x00000001 220 #define RING_INVALID 0x00000000 221 #define PRB1_TAIL 0x02040 /* 915+ only */ 222 #define PRB1_HEAD 0x02044 /* 915+ only */ 223 #define PRB1_START 0x02048 /* 915+ only */ 224 #define PRB1_CTL 0x0204c /* 915+ only */ 225 #define ACTHD_I965 0x02074 226 #define HWS_PGA 0x02080 227 #define HWS_ADDRESS_MASK 0xfffff000 228 #define HWS_START_ADDRESS_SHIFT 4 229 #define IPEIR 0x02088 230 #define NOPID 0x02094 231 #define HWSTAM 0x02098 232 #define SCPD0 0x0209c /* 915+ only */ 233 #define IER 0x020a0 234 #define IIR 0x020a4 235 #define IMR 0x020a8 236 #define ISR 0x020ac 237 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 238 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 239 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 240 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 241 #define I915_HWB_OOM_INTERRUPT (1<<13) 242 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 243 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 244 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 245 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 246 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 247 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 248 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 249 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 250 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 251 #define I915_DEBUG_INTERRUPT (1<<2) 252 #define I915_USER_INTERRUPT (1<<1) 253 #define I915_ASLE_INTERRUPT (1<<0) 254 #define EIR 0x020b0 255 #define EMR 0x020b4 256 #define ESR 0x020b8 257 #define INSTPM 0x020c0 258 #define ACTHD 0x020c8 259 #define FW_BLC 0x020d8 260 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 261 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 262 #define CACHE_MODE_0 0x02120 /* 915+ only */ 263 #define CM0_MASK_SHIFT 16 264 #define CM0_IZ_OPT_DISABLE (1<<6) 265 #define CM0_ZR_OPT_DISABLE (1<<5) 266 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 267 #define CM0_COLOR_EVICT_DISABLE (1<<3) 268 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 269 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 270 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 271 272 273 /* 274 * Framebuffer compression (915+ only) 275 */ 276 277 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 278 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 279 #define FBC_CONTROL 0x03208 280 #define FBC_CTL_EN (1<<31) 281 #define FBC_CTL_PERIODIC (1<<30) 282 #define FBC_CTL_INTERVAL_SHIFT (16) 283 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 284 #define FBC_CTL_STRIDE_SHIFT (5) 285 #define FBC_CTL_FENCENO (1<<0) 286 #define FBC_COMMAND 0x0320c 287 #define FBC_CMD_COMPRESS (1<<0) 288 #define FBC_STATUS 0x03210 289 #define FBC_STAT_COMPRESSING (1<<31) 290 #define FBC_STAT_COMPRESSED (1<<30) 291 #define FBC_STAT_MODIFIED (1<<29) 292 #define FBC_STAT_CURRENT_LINE (1<<0) 293 #define FBC_CONTROL2 0x03214 294 #define FBC_CTL_FENCE_DBL (0<<4) 295 #define FBC_CTL_IDLE_IMM (0<<2) 296 #define FBC_CTL_IDLE_FULL (1<<2) 297 #define FBC_CTL_IDLE_LINE (2<<2) 298 #define FBC_CTL_IDLE_DEBUG (3<<2) 299 #define FBC_CTL_CPU_FENCE (1<<1) 300 #define FBC_CTL_PLANEA (0<<0) 301 #define FBC_CTL_PLANEB (1<<0) 302 #define FBC_FENCE_OFF 0x0321b 303 304 #define FBC_LL_SIZE (1536) 305 306 /* 307 * GPIO regs 308 */ 309 #define GPIOA 0x5010 310 #define GPIOB 0x5014 311 #define GPIOC 0x5018 312 #define GPIOD 0x501c 313 #define GPIOE 0x5020 314 #define GPIOF 0x5024 315 #define GPIOG 0x5028 316 #define GPIOH 0x502c 317 # define GPIO_CLOCK_DIR_MASK (1 << 0) 318 # define GPIO_CLOCK_DIR_IN (0 << 1) 319 # define GPIO_CLOCK_DIR_OUT (1 << 1) 320 # define GPIO_CLOCK_VAL_MASK (1 << 2) 321 # define GPIO_CLOCK_VAL_OUT (1 << 3) 322 # define GPIO_CLOCK_VAL_IN (1 << 4) 323 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 324 # define GPIO_DATA_DIR_MASK (1 << 8) 325 # define GPIO_DATA_DIR_IN (0 << 9) 326 # define GPIO_DATA_DIR_OUT (1 << 9) 327 # define GPIO_DATA_VAL_MASK (1 << 10) 328 # define GPIO_DATA_VAL_OUT (1 << 11) 329 # define GPIO_DATA_VAL_IN (1 << 12) 330 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 331 332 /* 333 * Clock control & power management 334 */ 335 336 #define VGA0 0x6000 337 #define VGA1 0x6004 338 #define VGA_PD 0x6010 339 #define VGA0_PD_P2_DIV_4 (1 << 7) 340 #define VGA0_PD_P1_DIV_2 (1 << 5) 341 #define VGA0_PD_P1_SHIFT 0 342 #define VGA0_PD_P1_MASK (0x1f << 0) 343 #define VGA1_PD_P2_DIV_4 (1 << 15) 344 #define VGA1_PD_P1_DIV_2 (1 << 13) 345 #define VGA1_PD_P1_SHIFT 8 346 #define VGA1_PD_P1_MASK (0x1f << 8) 347 #define DPLL_A 0x06014 348 #define DPLL_B 0x06018 349 #define DPLL_VCO_ENABLE (1 << 31) 350 #define DPLL_DVO_HIGH_SPEED (1 << 30) 351 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 352 #define DPLL_VGA_MODE_DIS (1 << 28) 353 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 354 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 355 #define DPLL_MODE_MASK (3 << 26) 356 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 357 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 358 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 359 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 360 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 361 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 362 #define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ 363 364 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 365 #define I915_CRC_ERROR_ENABLE (1UL<<29) 366 #define I915_CRC_DONE_ENABLE (1UL<<28) 367 #define I915_GMBUS_EVENT_ENABLE (1UL<<27) 368 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 369 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 370 #define I915_DPST_EVENT_ENABLE (1UL<<23) 371 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 372 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 373 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 374 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 375 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 376 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 377 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 378 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 379 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 380 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 381 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 382 #define I915_DPST_EVENT_STATUS (1UL<<7) 383 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 384 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 385 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 386 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 387 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) 388 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 389 390 #define SRX_INDEX 0x3c4 391 #define SRX_DATA 0x3c5 392 #define SR01 1 393 #define SR01_SCREEN_OFF (1<<5) 394 395 #define PPCR 0x61204 396 #define PPCR_ON (1<<0) 397 398 #define DVOB 0x61140 399 #define DVOB_ON (1<<31) 400 #define DVOC 0x61160 401 #define DVOC_ON (1<<31) 402 #define LVDS 0x61180 403 #define LVDS_ON (1<<31) 404 405 #define ADPA 0x61100 406 #define ADPA_DPMS_MASK (~(3<<10)) 407 #define ADPA_DPMS_ON (0<<10) 408 #define ADPA_DPMS_SUSPEND (1<<10) 409 #define ADPA_DPMS_STANDBY (2<<10) 410 #define ADPA_DPMS_OFF (3<<10) 411 412 #define RING_TAIL 0x00 413 #define TAIL_ADDR 0x001FFFF8 414 #define RING_HEAD 0x04 415 #define HEAD_WRAP_COUNT 0xFFE00000 416 #define HEAD_WRAP_ONE 0x00200000 417 #define HEAD_ADDR 0x001FFFFC 418 #define RING_START 0x08 419 #define START_ADDR 0xFFFFF000 420 #define RING_LEN 0x0C 421 #define RING_NR_PAGES 0x001FF000 422 #define RING_REPORT_MASK 0x00000006 423 #define RING_REPORT_64K 0x00000002 424 #define RING_REPORT_128K 0x00000004 425 #define RING_NO_REPORT 0x00000000 426 #define RING_VALID_MASK 0x00000001 427 #define RING_VALID 0x00000001 428 #define RING_INVALID 0x00000000 429 430 /* Scratch pad debug 0 reg: 431 */ 432 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 433 /* 434 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 435 * this field (only one bit may be set). 436 */ 437 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 438 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 439 #define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 440 /* i830, required in DVO non-gang */ 441 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 442 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 443 #define PLL_REF_INPUT_DREFCLK (0 << 13) 444 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 445 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 446 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 447 #define PLL_REF_INPUT_MASK (3 << 13) 448 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 449 /* 450 * Parallel to Serial Load Pulse phase selection. 451 * Selects the phase for the 10X DPLL clock for the PCIe 452 * digital display port. The range is 4 to 13; 10 or more 453 * is just a flip delay. The default is 6 454 */ 455 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 456 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 457 /* 458 * SDVO multiplier for 945G/GM. Not used on 965. 459 */ 460 #define SDVO_MULTIPLIER_MASK 0x000000ff 461 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 462 #define SDVO_MULTIPLIER_SHIFT_VGA 0 463 #define DPLL_A_MD 0x0601c /* 965+ only */ 464 /* 465 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 466 * 467 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 468 */ 469 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 470 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 471 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 472 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 473 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 474 /* 475 * SDVO/UDI pixel multiplier. 476 * 477 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 478 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 479 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 480 * dummy bytes in the datastream at an increased clock rate, with both sides of 481 * the link knowing how many bytes are fill. 482 * 483 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 484 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 485 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 486 * through an SDVO command. 487 * 488 * This register field has values of multiplication factor minus 1, with 489 * a maximum multiplier of 5 for SDVO. 490 */ 491 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 492 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 493 /* 494 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 495 * This best be set to the default value (3) or the CRT won't work. No, 496 * I don't entirely understand what this does... 497 */ 498 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 499 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 500 #define DPLL_B_MD 0x06020 /* 965+ only */ 501 #define FPA0 0x06040 502 #define FPA1 0x06044 503 #define FPB0 0x06048 504 #define FPB1 0x0604c 505 #define FP_N_DIV_MASK 0x003f0000 506 #define FP_N_IGD_DIV_MASK 0x00ff0000 507 #define FP_N_DIV_SHIFT 16 508 #define FP_M1_DIV_MASK 0x00003f00 509 #define FP_M1_DIV_SHIFT 8 510 #define FP_M2_DIV_MASK 0x0000003f 511 #define FP_M2_IGD_DIV_MASK 0x000000ff 512 #define FP_M2_DIV_SHIFT 0 513 #define DPLL_TEST 0x606c 514 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 515 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 516 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 517 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 518 #define DPLLB_TEST_N_BYPASS (1 << 19) 519 #define DPLLB_TEST_M_BYPASS (1 << 18) 520 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 521 #define DPLLA_TEST_N_BYPASS (1 << 3) 522 #define DPLLA_TEST_M_BYPASS (1 << 2) 523 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 524 #define D_STATE 0x6104 525 #define CG_2D_DIS 0x6200 526 #define CG_3D_DIS 0x6204 527 528 /* 529 * Palette regs 530 */ 531 532 #define PALETTE_A 0x0a000 533 #define PALETTE_B 0x0a800 534 535 /* MCH MMIO space */ 536 537 /* 538 * MCHBAR mirror. 539 * 540 * This mirrors the MCHBAR MMIO space whose location is determined by 541 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 542 * every way. It is not accessible from the CP register read instructions. 543 * 544 */ 545 #define MCHBAR_MIRROR_BASE 0x10000 546 547 /** 915-945 and GM965 MCH register controlling DRAM channel access */ 548 #define DCC 0x10200 549 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 550 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 551 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 552 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 553 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 554 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 555 556 /** 965 MCH register controlling DRAM channel configuration */ 557 #define C0DRB3 0x10206 558 #define C1DRB3 0x10606 559 560 /** GM965 GM45 render standby register */ 561 #define MCHBAR_RENDER_STANDBY 0x111B8 562 563 #define PEG_BAND_GAP_DATA 0x14d68 564 565 /* 566 * Overlay regs 567 */ 568 569 #define OVADD 0x30000 570 #define DOVSTA 0x30008 571 #define OC_BUF (0x3<<20) 572 #define OGAMC5 0x30010 573 #define OGAMC4 0x30014 574 #define OGAMC3 0x30018 575 #define OGAMC2 0x3001c 576 #define OGAMC1 0x30020 577 #define OGAMC0 0x30024 578 579 /* 580 * Display engine regs 581 */ 582 583 /* Pipe A timing regs */ 584 #define HTOTAL_A 0x60000 585 #define HBLANK_A 0x60004 586 #define HSYNC_A 0x60008 587 #define VTOTAL_A 0x6000c 588 #define VBLANK_A 0x60010 589 #define VSYNC_A 0x60014 590 #define PIPEASRC 0x6001c 591 #define BCLRPAT_A 0x60020 592 593 /* Pipe B timing regs */ 594 #define HTOTAL_B 0x61000 595 #define HBLANK_B 0x61004 596 #define HSYNC_B 0x61008 597 #define VTOTAL_B 0x6100c 598 #define VBLANK_B 0x61010 599 #define VSYNC_B 0x61014 600 #define PIPEBSRC 0x6101c 601 #define BCLRPAT_B 0x61020 602 603 /* VGA port control */ 604 #define ADPA 0x61100 605 #define ADPA_DAC_ENABLE (1<<31) 606 #define ADPA_DAC_DISABLE 0 607 #define ADPA_PIPE_SELECT_MASK (1<<30) 608 #define ADPA_PIPE_A_SELECT 0 609 #define ADPA_PIPE_B_SELECT (1<<30) 610 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 611 #define ADPA_SETS_HVPOLARITY 0 612 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 613 #define ADPA_VSYNC_CNTL_ENABLE 0 614 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 615 #define ADPA_HSYNC_CNTL_ENABLE 0 616 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 617 #define ADPA_VSYNC_ACTIVE_LOW 0 618 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 619 #define ADPA_HSYNC_ACTIVE_LOW 0 620 #define ADPA_DPMS_MASK (~(3<<10)) 621 #define ADPA_DPMS_ON (0<<10) 622 #define ADPA_DPMS_SUSPEND (1<<10) 623 #define ADPA_DPMS_STANDBY (2<<10) 624 #define ADPA_DPMS_OFF (3<<10) 625 626 /* Hotplug control (945+ only) */ 627 #define PORT_HOTPLUG_EN 0x61110 628 #define HDMIB_HOTPLUG_INT_EN (1 << 29) 629 #define HDMIC_HOTPLUG_INT_EN (1 << 28) 630 #define HDMID_HOTPLUG_INT_EN (1 << 27) 631 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 632 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 633 #define TV_HOTPLUG_INT_EN (1 << 18) 634 #define CRT_HOTPLUG_INT_EN (1 << 9) 635 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 636 637 #define PORT_HOTPLUG_STAT 0x61114 638 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 639 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 640 #define HDMID_HOTPLUG_INT_STATUS (1 << 27) 641 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 642 #define TV_HOTPLUG_INT_STATUS (1 << 10) 643 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 644 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 645 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 646 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 647 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 648 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 649 650 /* SDVO port control */ 651 #define SDVOB 0x61140 652 #define SDVOC 0x61160 653 #define SDVO_ENABLE (1 << 31) 654 #define SDVO_PIPE_B_SELECT (1 << 30) 655 #define SDVO_STALL_SELECT (1 << 29) 656 #define SDVO_INTERRUPT_ENABLE (1 << 26) 657 /** 658 * 915G/GM SDVO pixel multiplier. 659 * 660 * Programmed value is multiplier - 1, up to 5x. 661 * 662 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 663 */ 664 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 665 #define SDVO_PORT_MULTIPLY_SHIFT 23 666 #define SDVO_PHASE_SELECT_MASK (15 << 19) 667 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 668 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 669 #define SDVOC_GANG_MODE (1 << 16) 670 #define SDVO_ENCODING_SDVO (0x0 << 10) 671 #define SDVO_ENCODING_HDMI (0x2 << 10) 672 /** Requird for HDMI operation */ 673 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 674 #define SDVO_BORDER_ENABLE (1 << 7) 675 #define SDVO_AUDIO_ENABLE (1 << 6) 676 /** New with 965, default is to be set */ 677 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 678 /** New with 965, default is to be set */ 679 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 680 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 681 #define SDVO_DETECTED (1 << 2) 682 /* Bits to be preserved when writing */ 683 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) 684 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) 685 686 /* DVO port control */ 687 #define DVOA 0x61120 688 #define DVOB 0x61140 689 #define DVOC 0x61160 690 #define DVO_ENABLE (1 << 31) 691 #define DVO_PIPE_B_SELECT (1 << 30) 692 #define DVO_PIPE_STALL_UNUSED (0 << 28) 693 #define DVO_PIPE_STALL (1 << 28) 694 #define DVO_PIPE_STALL_TV (2 << 28) 695 #define DVO_PIPE_STALL_MASK (3 << 28) 696 #define DVO_USE_VGA_SYNC (1 << 15) 697 #define DVO_DATA_ORDER_I740 (0 << 14) 698 #define DVO_DATA_ORDER_FP (1 << 14) 699 #define DVO_VSYNC_DISABLE (1 << 11) 700 #define DVO_HSYNC_DISABLE (1 << 10) 701 #define DVO_VSYNC_TRISTATE (1 << 9) 702 #define DVO_HSYNC_TRISTATE (1 << 8) 703 #define DVO_BORDER_ENABLE (1 << 7) 704 #define DVO_DATA_ORDER_GBRG (1 << 6) 705 #define DVO_DATA_ORDER_RGGB (0 << 6) 706 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 707 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 708 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 709 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 710 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 711 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 712 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 713 #define DVO_PRESERVE_MASK (0x7<<24) 714 #define DVOA_SRCDIM 0x61124 715 #define DVOB_SRCDIM 0x61144 716 #define DVOC_SRCDIM 0x61164 717 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 718 #define DVO_SRCDIM_VERTICAL_SHIFT 0 719 720 /* LVDS port control */ 721 #define LVDS 0x61180 722 /* 723 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 724 * the DPLL semantics change when the LVDS is assigned to that pipe. 725 */ 726 #define LVDS_PORT_EN (1 << 31) 727 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 728 #define LVDS_PIPEB_SELECT (1 << 30) 729 /* 730 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 731 * pixel. 732 */ 733 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 734 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 735 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 736 /* 737 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 738 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 739 * on. 740 */ 741 #define LVDS_A3_POWER_MASK (3 << 6) 742 #define LVDS_A3_POWER_DOWN (0 << 6) 743 #define LVDS_A3_POWER_UP (3 << 6) 744 /* 745 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 746 * is set. 747 */ 748 #define LVDS_CLKB_POWER_MASK (3 << 4) 749 #define LVDS_CLKB_POWER_DOWN (0 << 4) 750 #define LVDS_CLKB_POWER_UP (3 << 4) 751 /* 752 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 753 * setting for whether we are in dual-channel mode. The B3 pair will 754 * additionally only be powered up when LVDS_A3_POWER_UP is set. 755 */ 756 #define LVDS_B0B3_POWER_MASK (3 << 2) 757 #define LVDS_B0B3_POWER_DOWN (0 << 2) 758 #define LVDS_B0B3_POWER_UP (3 << 2) 759 760 /* Panel power sequencing */ 761 #define PP_STATUS 0x61200 762 #define PP_ON (1 << 31) 763 /* 764 * Indicates that all dependencies of the panel are on: 765 * 766 * - PLL enabled 767 * - pipe enabled 768 * - LVDS/DVOB/DVOC on 769 */ 770 #define PP_READY (1 << 30) 771 #define PP_SEQUENCE_NONE (0 << 28) 772 #define PP_SEQUENCE_ON (1 << 28) 773 #define PP_SEQUENCE_OFF (2 << 28) 774 #define PP_SEQUENCE_MASK 0x30000000 775 #define PP_CONTROL 0x61204 776 #define POWER_TARGET_ON (1 << 0) 777 #define PP_ON_DELAYS 0x61208 778 #define PP_OFF_DELAYS 0x6120c 779 #define PP_DIVISOR 0x61210 780 781 /* Panel fitting */ 782 #define PFIT_CONTROL 0x61230 783 #define PFIT_ENABLE (1 << 31) 784 #define PFIT_PIPE_MASK (3 << 29) 785 #define PFIT_PIPE_SHIFT 29 786 #define VERT_INTERP_DISABLE (0 << 10) 787 #define VERT_INTERP_BILINEAR (1 << 10) 788 #define VERT_INTERP_MASK (3 << 10) 789 #define VERT_AUTO_SCALE (1 << 9) 790 #define HORIZ_INTERP_DISABLE (0 << 6) 791 #define HORIZ_INTERP_BILINEAR (1 << 6) 792 #define HORIZ_INTERP_MASK (3 << 6) 793 #define HORIZ_AUTO_SCALE (1 << 5) 794 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 795 #define PFIT_PGM_RATIOS 0x61234 796 #define PFIT_VERT_SCALE_MASK 0xfff00000 797 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 798 #define PFIT_AUTO_RATIOS 0x61238 799 800 /* Backlight control */ 801 #define BLC_PWM_CTL 0x61254 802 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 803 #define BLC_PWM_CTL2 0x61250 /* 965+ only */ 804 #define BLM_COMBINATION_MODE (1 << 30) 805 /* 806 * This is the most significant 15 bits of the number of backlight cycles in a 807 * complete cycle of the modulated backlight control. 808 * 809 * The actual value is this field multiplied by two. 810 */ 811 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 812 #define BLM_LEGACY_MODE (1 << 16) 813 /* 814 * This is the number of cycles out of the backlight modulation cycle for which 815 * the backlight is on. 816 * 817 * This field must be no greater than the number of cycles in the complete 818 * backlight modulation cycle. 819 */ 820 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 821 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 822 823 /* TV port control */ 824 #define TV_CTL 0x68000 825 /** Enables the TV encoder */ 826 # define TV_ENC_ENABLE (1 << 31) 827 /** Sources the TV encoder input from pipe B instead of A. */ 828 # define TV_ENC_PIPEB_SELECT (1 << 30) 829 /** Outputs composite video (DAC A only) */ 830 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 831 /** Outputs SVideo video (DAC B/C) */ 832 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 833 /** Outputs Component video (DAC A/B/C) */ 834 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 835 /** Outputs Composite and SVideo (DAC A/B/C) */ 836 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 837 # define TV_TRILEVEL_SYNC (1 << 21) 838 /** Enables slow sync generation (945GM only) */ 839 # define TV_SLOW_SYNC (1 << 20) 840 /** Selects 4x oversampling for 480i and 576p */ 841 # define TV_OVERSAMPLE_4X (0 << 18) 842 /** Selects 2x oversampling for 720p and 1080i */ 843 # define TV_OVERSAMPLE_2X (1 << 18) 844 /** Selects no oversampling for 1080p */ 845 # define TV_OVERSAMPLE_NONE (2 << 18) 846 /** Selects 8x oversampling */ 847 # define TV_OVERSAMPLE_8X (3 << 18) 848 /** Selects progressive mode rather than interlaced */ 849 # define TV_PROGRESSIVE (1 << 17) 850 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 851 # define TV_PAL_BURST (1 << 16) 852 /** Field for setting delay of Y compared to C */ 853 # define TV_YC_SKEW_MASK (7 << 12) 854 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */ 855 # define TV_ENC_SDP_FIX (1 << 11) 856 /** 857 * Enables a fix for the 915GM only. 858 * 859 * Not sure what it does. 860 */ 861 # define TV_ENC_C0_FIX (1 << 10) 862 /** Bits that must be preserved by software */ 863 # define TV_CTL_SAVE ((3 << 8) | (3 << 6)) 864 # define TV_FUSE_STATE_MASK (3 << 4) 865 /** Read-only state that reports all features enabled */ 866 # define TV_FUSE_STATE_ENABLED (0 << 4) 867 /** Read-only state that reports that Macrovision is disabled in hardware*/ 868 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 869 /** Read-only state that reports that TV-out is disabled in hardware. */ 870 # define TV_FUSE_STATE_DISABLED (2 << 4) 871 /** Normal operation */ 872 # define TV_TEST_MODE_NORMAL (0 << 0) 873 /** Encoder test pattern 1 - combo pattern */ 874 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 875 /** Encoder test pattern 2 - full screen vertical 75% color bars */ 876 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 877 /** Encoder test pattern 3 - full screen horizontal 75% color bars */ 878 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 879 /** Encoder test pattern 4 - random noise */ 880 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 881 /** Encoder test pattern 5 - linear color ramps */ 882 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 883 /** 884 * This test mode forces the DACs to 50% of full output. 885 * 886 * This is used for load detection in combination with TVDAC_SENSE_MASK 887 */ 888 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 889 # define TV_TEST_MODE_MASK (7 << 0) 890 891 #define TV_DAC 0x68004 892 /** 893 * Reports that DAC state change logic has reported change (RO). 894 * 895 * This gets cleared when TV_DAC_STATE_EN is cleared 896 */ 897 # define TVDAC_STATE_CHG (1 << 31) 898 # define TVDAC_SENSE_MASK (7 << 28) 899 /** Reports that DAC A voltage is above the detect threshold */ 900 # define TVDAC_A_SENSE (1 << 30) 901 /** Reports that DAC B voltage is above the detect threshold */ 902 # define TVDAC_B_SENSE (1 << 29) 903 /** Reports that DAC C voltage is above the detect threshold */ 904 # define TVDAC_C_SENSE (1 << 28) 905 /** 906 * Enables DAC state detection logic, for load-based TV detection. 907 * 908 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 909 * to off, for load detection to work. 910 */ 911 # define TVDAC_STATE_CHG_EN (1 << 27) 912 /** Sets the DAC A sense value to high */ 913 # define TVDAC_A_SENSE_CTL (1 << 26) 914 /** Sets the DAC B sense value to high */ 915 # define TVDAC_B_SENSE_CTL (1 << 25) 916 /** Sets the DAC C sense value to high */ 917 # define TVDAC_C_SENSE_CTL (1 << 24) 918 /** Overrides the ENC_ENABLE and DAC voltage levels */ 919 # define DAC_CTL_OVERRIDE (1 << 7) 920 /** Sets the slew rate. Must be preserved in software */ 921 # define ENC_TVDAC_SLEW_FAST (1 << 6) 922 # define DAC_A_1_3_V (0 << 4) 923 # define DAC_A_1_1_V (1 << 4) 924 # define DAC_A_0_7_V (2 << 4) 925 # define DAC_A_OFF (3 << 4) 926 # define DAC_B_1_3_V (0 << 2) 927 # define DAC_B_1_1_V (1 << 2) 928 # define DAC_B_0_7_V (2 << 2) 929 # define DAC_B_OFF (3 << 2) 930 # define DAC_C_1_3_V (0 << 0) 931 # define DAC_C_1_1_V (1 << 0) 932 # define DAC_C_0_7_V (2 << 0) 933 # define DAC_C_OFF (3 << 0) 934 935 /** 936 * CSC coefficients are stored in a floating point format with 9 bits of 937 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 938 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 939 * -1 (0x3) being the only legal negative value. 940 */ 941 #define TV_CSC_Y 0x68010 942 # define TV_RY_MASK 0x07ff0000 943 # define TV_RY_SHIFT 16 944 # define TV_GY_MASK 0x00000fff 945 # define TV_GY_SHIFT 0 946 947 #define TV_CSC_Y2 0x68014 948 # define TV_BY_MASK 0x07ff0000 949 # define TV_BY_SHIFT 16 950 /** 951 * Y attenuation for component video. 952 * 953 * Stored in 1.9 fixed point. 954 */ 955 # define TV_AY_MASK 0x000003ff 956 # define TV_AY_SHIFT 0 957 958 #define TV_CSC_U 0x68018 959 # define TV_RU_MASK 0x07ff0000 960 # define TV_RU_SHIFT 16 961 # define TV_GU_MASK 0x000007ff 962 # define TV_GU_SHIFT 0 963 964 #define TV_CSC_U2 0x6801c 965 # define TV_BU_MASK 0x07ff0000 966 # define TV_BU_SHIFT 16 967 /** 968 * U attenuation for component video. 969 * 970 * Stored in 1.9 fixed point. 971 */ 972 # define TV_AU_MASK 0x000003ff 973 # define TV_AU_SHIFT 0 974 975 #define TV_CSC_V 0x68020 976 # define TV_RV_MASK 0x0fff0000 977 # define TV_RV_SHIFT 16 978 # define TV_GV_MASK 0x000007ff 979 # define TV_GV_SHIFT 0 980 981 #define TV_CSC_V2 0x68024 982 # define TV_BV_MASK 0x07ff0000 983 # define TV_BV_SHIFT 16 984 /** 985 * V attenuation for component video. 986 * 987 * Stored in 1.9 fixed point. 988 */ 989 # define TV_AV_MASK 0x000007ff 990 # define TV_AV_SHIFT 0 991 992 #define TV_CLR_KNOBS 0x68028 993 /** 2s-complement brightness adjustment */ 994 # define TV_BRIGHTNESS_MASK 0xff000000 995 # define TV_BRIGHTNESS_SHIFT 24 996 /** Contrast adjustment, as a 2.6 unsigned floating point number */ 997 # define TV_CONTRAST_MASK 0x00ff0000 998 # define TV_CONTRAST_SHIFT 16 999 /** Saturation adjustment, as a 2.6 unsigned floating point number */ 1000 # define TV_SATURATION_MASK 0x0000ff00 1001 # define TV_SATURATION_SHIFT 8 1002 /** Hue adjustment, as an integer phase angle in degrees */ 1003 # define TV_HUE_MASK 0x000000ff 1004 # define TV_HUE_SHIFT 0 1005 1006 #define TV_CLR_LEVEL 0x6802c 1007 /** Controls the DAC level for black */ 1008 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1009 # define TV_BLACK_LEVEL_SHIFT 16 1010 /** Controls the DAC level for blanking */ 1011 # define TV_BLANK_LEVEL_MASK 0x000001ff 1012 # define TV_BLANK_LEVEL_SHIFT 0 1013 1014 #define TV_H_CTL_1 0x68030 1015 /** Number of pixels in the hsync. */ 1016 # define TV_HSYNC_END_MASK 0x1fff0000 1017 # define TV_HSYNC_END_SHIFT 16 1018 /** Total number of pixels minus one in the line (display and blanking). */ 1019 # define TV_HTOTAL_MASK 0x00001fff 1020 # define TV_HTOTAL_SHIFT 0 1021 1022 #define TV_H_CTL_2 0x68034 1023 /** Enables the colorburst (needed for non-component color) */ 1024 # define TV_BURST_ENA (1 << 31) 1025 /** Offset of the colorburst from the start of hsync, in pixels minus one. */ 1026 # define TV_HBURST_START_SHIFT 16 1027 # define TV_HBURST_START_MASK 0x1fff0000 1028 /** Length of the colorburst */ 1029 # define TV_HBURST_LEN_SHIFT 0 1030 # define TV_HBURST_LEN_MASK 0x0001fff 1031 1032 #define TV_H_CTL_3 0x68038 1033 /** End of hblank, measured in pixels minus one from start of hsync */ 1034 # define TV_HBLANK_END_SHIFT 16 1035 # define TV_HBLANK_END_MASK 0x1fff0000 1036 /** Start of hblank, measured in pixels minus one from start of hsync */ 1037 # define TV_HBLANK_START_SHIFT 0 1038 # define TV_HBLANK_START_MASK 0x0001fff 1039 1040 #define TV_V_CTL_1 0x6803c 1041 /** XXX */ 1042 # define TV_NBR_END_SHIFT 16 1043 # define TV_NBR_END_MASK 0x07ff0000 1044 /** XXX */ 1045 # define TV_VI_END_F1_SHIFT 8 1046 # define TV_VI_END_F1_MASK 0x00003f00 1047 /** XXX */ 1048 # define TV_VI_END_F2_SHIFT 0 1049 # define TV_VI_END_F2_MASK 0x0000003f 1050 1051 #define TV_V_CTL_2 0x68040 1052 /** Length of vsync, in half lines */ 1053 # define TV_VSYNC_LEN_MASK 0x07ff0000 1054 # define TV_VSYNC_LEN_SHIFT 16 1055 /** Offset of the start of vsync in field 1, measured in one less than the 1056 * number of half lines. 1057 */ 1058 # define TV_VSYNC_START_F1_MASK 0x00007f00 1059 # define TV_VSYNC_START_F1_SHIFT 8 1060 /** 1061 * Offset of the start of vsync in field 2, measured in one less than the 1062 * number of half lines. 1063 */ 1064 # define TV_VSYNC_START_F2_MASK 0x0000007f 1065 # define TV_VSYNC_START_F2_SHIFT 0 1066 1067 #define TV_V_CTL_3 0x68044 1068 /** Enables generation of the equalization signal */ 1069 # define TV_EQUAL_ENA (1 << 31) 1070 /** Length of vsync, in half lines */ 1071 # define TV_VEQ_LEN_MASK 0x007f0000 1072 # define TV_VEQ_LEN_SHIFT 16 1073 /** Offset of the start of equalization in field 1, measured in one less than 1074 * the number of half lines. 1075 */ 1076 # define TV_VEQ_START_F1_MASK 0x0007f00 1077 # define TV_VEQ_START_F1_SHIFT 8 1078 /** 1079 * Offset of the start of equalization in field 2, measured in one less than 1080 * the number of half lines. 1081 */ 1082 # define TV_VEQ_START_F2_MASK 0x000007f 1083 # define TV_VEQ_START_F2_SHIFT 0 1084 1085 #define TV_V_CTL_4 0x68048 1086 /** 1087 * Offset to start of vertical colorburst, measured in one less than the 1088 * number of lines from vertical start. 1089 */ 1090 # define TV_VBURST_START_F1_MASK 0x003f0000 1091 # define TV_VBURST_START_F1_SHIFT 16 1092 /** 1093 * Offset to the end of vertical colorburst, measured in one less than the 1094 * number of lines from the start of NBR. 1095 */ 1096 # define TV_VBURST_END_F1_MASK 0x000000ff 1097 # define TV_VBURST_END_F1_SHIFT 0 1098 1099 #define TV_V_CTL_5 0x6804c 1100 /** 1101 * Offset to start of vertical colorburst, measured in one less than the 1102 * number of lines from vertical start. 1103 */ 1104 # define TV_VBURST_START_F2_MASK 0x003f0000 1105 # define TV_VBURST_START_F2_SHIFT 16 1106 /** 1107 * Offset to the end of vertical colorburst, measured in one less than the 1108 * number of lines from the start of NBR. 1109 */ 1110 # define TV_VBURST_END_F2_MASK 0x000000ff 1111 # define TV_VBURST_END_F2_SHIFT 0 1112 1113 #define TV_V_CTL_6 0x68050 1114 /** 1115 * Offset to start of vertical colorburst, measured in one less than the 1116 * number of lines from vertical start. 1117 */ 1118 # define TV_VBURST_START_F3_MASK 0x003f0000 1119 # define TV_VBURST_START_F3_SHIFT 16 1120 /** 1121 * Offset to the end of vertical colorburst, measured in one less than the 1122 * number of lines from the start of NBR. 1123 */ 1124 # define TV_VBURST_END_F3_MASK 0x000000ff 1125 # define TV_VBURST_END_F3_SHIFT 0 1126 1127 #define TV_V_CTL_7 0x68054 1128 /** 1129 * Offset to start of vertical colorburst, measured in one less than the 1130 * number of lines from vertical start. 1131 */ 1132 # define TV_VBURST_START_F4_MASK 0x003f0000 1133 # define TV_VBURST_START_F4_SHIFT 16 1134 /** 1135 * Offset to the end of vertical colorburst, measured in one less than the 1136 * number of lines from the start of NBR. 1137 */ 1138 # define TV_VBURST_END_F4_MASK 0x000000ff 1139 # define TV_VBURST_END_F4_SHIFT 0 1140 1141 #define TV_SC_CTL_1 0x68060 1142 /** Turns on the first subcarrier phase generation DDA */ 1143 # define TV_SC_DDA1_EN (1 << 31) 1144 /** Turns on the first subcarrier phase generation DDA */ 1145 # define TV_SC_DDA2_EN (1 << 30) 1146 /** Turns on the first subcarrier phase generation DDA */ 1147 # define TV_SC_DDA3_EN (1 << 29) 1148 /** Sets the subcarrier DDA to reset frequency every other field */ 1149 # define TV_SC_RESET_EVERY_2 (0 << 24) 1150 /** Sets the subcarrier DDA to reset frequency every fourth field */ 1151 # define TV_SC_RESET_EVERY_4 (1 << 24) 1152 /** Sets the subcarrier DDA to reset frequency every eighth field */ 1153 # define TV_SC_RESET_EVERY_8 (2 << 24) 1154 /** Sets the subcarrier DDA to never reset the frequency */ 1155 # define TV_SC_RESET_NEVER (3 << 24) 1156 /** Sets the peak amplitude of the colorburst.*/ 1157 # define TV_BURST_LEVEL_MASK 0x00ff0000 1158 # define TV_BURST_LEVEL_SHIFT 16 1159 /** Sets the increment of the first subcarrier phase generation DDA */ 1160 # define TV_SCDDA1_INC_MASK 0x00000fff 1161 # define TV_SCDDA1_INC_SHIFT 0 1162 1163 #define TV_SC_CTL_2 0x68064 1164 /** Sets the rollover for the second subcarrier phase generation DDA */ 1165 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 1166 # define TV_SCDDA2_SIZE_SHIFT 16 1167 /** Sets the increent of the second subcarrier phase generation DDA */ 1168 # define TV_SCDDA2_INC_MASK 0x00007fff 1169 # define TV_SCDDA2_INC_SHIFT 0 1170 1171 #define TV_SC_CTL_3 0x68068 1172 /** Sets the rollover for the third subcarrier phase generation DDA */ 1173 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 1174 # define TV_SCDDA3_SIZE_SHIFT 16 1175 /** Sets the increent of the third subcarrier phase generation DDA */ 1176 # define TV_SCDDA3_INC_MASK 0x00007fff 1177 # define TV_SCDDA3_INC_SHIFT 0 1178 1179 #define TV_WIN_POS 0x68070 1180 /** X coordinate of the display from the start of horizontal active */ 1181 # define TV_XPOS_MASK 0x1fff0000 1182 # define TV_XPOS_SHIFT 16 1183 /** Y coordinate of the display from the start of vertical active (NBR) */ 1184 # define TV_YPOS_MASK 0x00000fff 1185 # define TV_YPOS_SHIFT 0 1186 1187 #define TV_WIN_SIZE 0x68074 1188 /** Horizontal size of the display window, measured in pixels*/ 1189 # define TV_XSIZE_MASK 0x1fff0000 1190 # define TV_XSIZE_SHIFT 16 1191 /** 1192 * Vertical size of the display window, measured in pixels. 1193 * 1194 * Must be even for interlaced modes. 1195 */ 1196 # define TV_YSIZE_MASK 0x00000fff 1197 # define TV_YSIZE_SHIFT 0 1198 1199 #define TV_FILTER_CTL_1 0x68080 1200 /** 1201 * Enables automatic scaling calculation. 1202 * 1203 * If set, the rest of the registers are ignored, and the calculated values can 1204 * be read back from the register. 1205 */ 1206 # define TV_AUTO_SCALE (1 << 31) 1207 /** 1208 * Disables the vertical filter. 1209 * 1210 * This is required on modes more than 1024 pixels wide */ 1211 # define TV_V_FILTER_BYPASS (1 << 29) 1212 /** Enables adaptive vertical filtering */ 1213 # define TV_VADAPT (1 << 28) 1214 # define TV_VADAPT_MODE_MASK (3 << 26) 1215 /** Selects the least adaptive vertical filtering mode */ 1216 # define TV_VADAPT_MODE_LEAST (0 << 26) 1217 /** Selects the moderately adaptive vertical filtering mode */ 1218 # define TV_VADAPT_MODE_MODERATE (1 << 26) 1219 /** Selects the most adaptive vertical filtering mode */ 1220 # define TV_VADAPT_MODE_MOST (3 << 26) 1221 /** 1222 * Sets the horizontal scaling factor. 1223 * 1224 * This should be the fractional part of the horizontal scaling factor divided 1225 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 1226 * 1227 * (src width - 1) / ((oversample * dest width) - 1) 1228 */ 1229 # define TV_HSCALE_FRAC_MASK 0x00003fff 1230 # define TV_HSCALE_FRAC_SHIFT 0 1231 1232 #define TV_FILTER_CTL_2 0x68084 1233 /** 1234 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1235 * 1236 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 1237 */ 1238 # define TV_VSCALE_INT_MASK 0x00038000 1239 # define TV_VSCALE_INT_SHIFT 15 1240 /** 1241 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1242 * 1243 * \sa TV_VSCALE_INT_MASK 1244 */ 1245 # define TV_VSCALE_FRAC_MASK 0x00007fff 1246 # define TV_VSCALE_FRAC_SHIFT 0 1247 1248 #define TV_FILTER_CTL_3 0x68088 1249 /** 1250 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 1251 * 1252 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 1253 * 1254 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1255 */ 1256 # define TV_VSCALE_IP_INT_MASK 0x00038000 1257 # define TV_VSCALE_IP_INT_SHIFT 15 1258 /** 1259 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 1260 * 1261 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 1262 * 1263 * \sa TV_VSCALE_IP_INT_MASK 1264 */ 1265 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 1266 # define TV_VSCALE_IP_FRAC_SHIFT 0 1267 1268 #define TV_CC_CONTROL 0x68090 1269 # define TV_CC_ENABLE (1 << 31) 1270 /** 1271 * Specifies which field to send the CC data in. 1272 * 1273 * CC data is usually sent in field 0. 1274 */ 1275 # define TV_CC_FID_MASK (1 << 27) 1276 # define TV_CC_FID_SHIFT 27 1277 /** Sets the horizontal position of the CC data. Usually 135. */ 1278 # define TV_CC_HOFF_MASK 0x03ff0000 1279 # define TV_CC_HOFF_SHIFT 16 1280 /** Sets the vertical position of the CC data. Usually 21 */ 1281 # define TV_CC_LINE_MASK 0x0000003f 1282 # define TV_CC_LINE_SHIFT 0 1283 1284 #define TV_CC_DATA 0x68094 1285 # define TV_CC_RDY (1 << 31) 1286 /** Second word of CC data to be transmitted. */ 1287 # define TV_CC_DATA_2_MASK 0x007f0000 1288 # define TV_CC_DATA_2_SHIFT 16 1289 /** First word of CC data to be transmitted. */ 1290 # define TV_CC_DATA_1_MASK 0x0000007f 1291 # define TV_CC_DATA_1_SHIFT 0 1292 1293 #define TV_H_LUMA_0 0x68100 1294 #define TV_H_LUMA_59 0x681ec 1295 #define TV_H_CHROMA_0 0x68200 1296 #define TV_H_CHROMA_59 0x682ec 1297 #define TV_V_LUMA_0 0x68300 1298 #define TV_V_LUMA_42 0x683a8 1299 #define TV_V_CHROMA_0 0x68400 1300 #define TV_V_CHROMA_42 0x684a8 1301 1302 /* Display & cursor control */ 1303 1304 /* Pipe A */ 1305 #define PIPEADSL 0x70000 1306 #define PIPEACONF 0x70008 1307 #define PIPEACONF_ENABLE (1<<31) 1308 #define PIPEACONF_DISABLE 0 1309 #define PIPEACONF_DOUBLE_WIDE (1<<30) 1310 #define I965_PIPECONF_ACTIVE (1<<30) 1311 #define PIPEACONF_SINGLE_WIDE 0 1312 #define PIPEACONF_PIPE_UNLOCKED 0 1313 #define PIPEACONF_PIPE_LOCKED (1<<25) 1314 #define PIPEACONF_PALETTE 0 1315 #define PIPEACONF_GAMMA (1<<24) 1316 #define PIPECONF_FORCE_BORDER (1<<25) 1317 #define PIPECONF_PROGRESSIVE (0 << 21) 1318 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1319 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1320 #define PIPEASTAT 0x70024 1321 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 1322 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 1323 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 1324 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 1325 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 1326 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1327 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1328 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 1329 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1330 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1331 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1332 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 1333 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1334 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1335 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 1336 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1337 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1338 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 1339 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 1340 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 1341 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1342 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 1343 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1344 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1345 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1346 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 1347 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1348 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1349 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 1350 1351 #define DSPARB 0x70030 1352 #define DSPARB_CSTART_MASK (0x7f << 7) 1353 #define DSPARB_CSTART_SHIFT 7 1354 #define DSPARB_BSTART_MASK (0x7f) 1355 #define DSPARB_BSTART_SHIFT 0 1356 /* 1357 * The two pipe frame counter registers are not synchronized, so 1358 * reading a stable value is somewhat tricky. The following code 1359 * should work: 1360 * 1361 * do { 1362 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1363 * PIPE_FRAME_HIGH_SHIFT; 1364 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 1365 * PIPE_FRAME_LOW_SHIFT); 1366 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 1367 * PIPE_FRAME_HIGH_SHIFT); 1368 * } while (high1 != high2); 1369 * frame = (high1 << 8) | low1; 1370 */ 1371 #define PIPEAFRAMEHIGH 0x70040 1372 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 1373 #define PIPE_FRAME_HIGH_SHIFT 0 1374 #define PIPEAFRAMEPIXEL 0x70044 1375 #define PIPE_FRAME_LOW_MASK 0xff000000 1376 #define PIPE_FRAME_LOW_SHIFT 24 1377 #define PIPE_PIXEL_MASK 0x00ffffff 1378 #define PIPE_PIXEL_SHIFT 0 1379 /* GM45+ just has to be different */ 1380 #define PIPEA_FRMCOUNT_GM45 0x70040 1381 #define PIPEA_FLIPCOUNT_GM45 0x70044 1382 1383 /* Cursor A & B regs */ 1384 #define CURACNTR 0x70080 1385 #define CURSOR_MODE_DISABLE 0x00 1386 #define CURSOR_MODE_64_32B_AX 0x07 1387 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 1388 #define MCURSOR_GAMMA_ENABLE (1 << 26) 1389 #define CURABASE 0x70084 1390 #define CURAPOS 0x70088 1391 #define CURSOR_POS_MASK 0x007FF 1392 #define CURSOR_POS_SIGN 0x8000 1393 #define CURSOR_X_SHIFT 0 1394 #define CURSOR_Y_SHIFT 16 1395 #define CURBCNTR 0x700c0 1396 #define CURBBASE 0x700c4 1397 #define CURBPOS 0x700c8 1398 1399 /* Display A control */ 1400 #define DSPACNTR 0x70180 1401 #define DISPLAY_PLANE_ENABLE (1<<31) 1402 #define DISPLAY_PLANE_DISABLE 0 1403 #define DISPPLANE_GAMMA_ENABLE (1<<30) 1404 #define DISPPLANE_GAMMA_DISABLE 0 1405 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 1406 #define DISPPLANE_8BPP (0x2<<26) 1407 #define DISPPLANE_15_16BPP (0x4<<26) 1408 #define DISPPLANE_16BPP (0x5<<26) 1409 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1410 #define DISPPLANE_32BPP (0x7<<26) 1411 #define DISPPLANE_STEREO_ENABLE (1<<25) 1412 #define DISPPLANE_STEREO_DISABLE 0 1413 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 1414 #define DISPPLANE_SEL_PIPE_A 0 1415 #define DISPPLANE_SEL_PIPE_B (1<<24) 1416 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 1417 #define DISPPLANE_SRC_KEY_DISABLE 0 1418 #define DISPPLANE_LINE_DOUBLE (1<<20) 1419 #define DISPPLANE_NO_LINE_DOUBLE 0 1420 #define DISPPLANE_STEREO_POLARITY_FIRST 0 1421 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1422 #define DSPAADDR 0x70184 1423 #define DSPASTRIDE 0x70188 1424 #define DSPAPOS 0x7018C /* reserved */ 1425 #define DSPASIZE 0x70190 1426 #define DSPASURF 0x7019C /* 965+ only */ 1427 #define DSPATILEOFF 0x701A4 /* 965+ only */ 1428 1429 /* VBIOS flags */ 1430 #define SWF00 0x71410 1431 #define SWF01 0x71414 1432 #define SWF02 0x71418 1433 #define SWF03 0x7141c 1434 #define SWF04 0x71420 1435 #define SWF05 0x71424 1436 #define SWF06 0x71428 1437 #define SWF10 0x70410 1438 #define SWF11 0x70414 1439 #define SWF14 0x71420 1440 #define SWF30 0x72414 1441 #define SWF31 0x72418 1442 #define SWF32 0x7241c 1443 1444 /* Pipe B */ 1445 #define PIPEBDSL 0x71000 1446 #define PIPEBCONF 0x71008 1447 #define PIPEBSTAT 0x71024 1448 #define PIPEBFRAMEHIGH 0x71040 1449 #define PIPEBFRAMEPIXEL 0x71044 1450 #define PIPEB_FRMCOUNT_GM45 0x71040 1451 #define PIPEB_FLIPCOUNT_GM45 0x71044 1452 1453 1454 /* Display B control */ 1455 #define DSPBCNTR 0x71180 1456 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 1457 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 1458 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 1459 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 1460 #define DSPBADDR 0x71184 1461 #define DSPBSTRIDE 0x71188 1462 #define DSPBPOS 0x7118C 1463 #define DSPBSIZE 0x71190 1464 #define DSPBSURF 0x7119C 1465 #define DSPBTILEOFF 0x711A4 1466 1467 /* VBIOS regs */ 1468 #define VGACNTRL 0x71400 1469 # define VGA_DISP_DISABLE (1 << 31) 1470 # define VGA_2X_MODE (1 << 30) 1471 # define VGA_PIPE_B_SELECT (1 << 29) 1472 1473 #endif /* _I915_REG_H_ */ 1474