1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) 30 31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 32 #define _PIPE3(pipe, a, b, c) (pipe < 2 ? _PIPE(pipe, a, b) : c) 33 #define _PORT3(port, a, b, c) (port < 2 ? _PORT(port, a, b) : c) 34 35 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) 36 #define _MASKED_BIT_DISABLE(a) ((a) << 16) 37 38 /* PCI config space */ 39 40 #define HPLLCC 0xc0 /* 855 only */ 41 #define GC_CLOCK_CONTROL_MASK (0xf << 0) 42 #define GC_CLOCK_133_200 (0 << 0) 43 #define GC_CLOCK_100_200 (1 << 0) 44 #define GC_CLOCK_100_133 (2 << 0) 45 #define GC_CLOCK_166_250 (3 << 0) 46 #define GCFGC2 0xda 47 #define GCFGC 0xf0 /* 915+ only */ 48 #define GC_LOW_FREQUENCY_ENABLE (1 << 7) 49 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 50 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 51 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 52 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 53 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 54 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 55 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 56 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 57 #define GC_DISPLAY_CLOCK_MASK (7 << 4) 58 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 59 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 60 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 61 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 62 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 63 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 64 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 65 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 66 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 67 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 68 #define I945_GC_RENDER_CLOCK_MASK (7 << 0) 69 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 70 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 71 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 72 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 73 #define I915_GC_RENDER_CLOCK_MASK (7 << 0) 74 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 75 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 76 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 77 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 78 79 80 /* Graphics reset regs */ 81 #define I965_GDRST 0xc0 /* PCI config register */ 82 #define GRDOM_FULL (0<<2) 83 #define GRDOM_RENDER (1<<2) 84 #define GRDOM_MEDIA (3<<2) 85 #define GRDOM_MASK (3<<2) 86 #define GRDOM_RESET_ENABLE (1<<0) 87 88 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 89 #define ILK_GRDOM_FULL (0<<1) 90 #define ILK_GRDOM_RENDER (1<<1) 91 #define ILK_GRDOM_MEDIA (3<<1) 92 #define ILK_GRDOM_MASK (3<<1) 93 #define ILK_GRDOM_RESET_ENABLE (1<<0) 94 95 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 96 #define GEN6_MBC_SNPCR_SHIFT 21 97 #define GEN6_MBC_SNPCR_MASK (3<<21) 98 #define GEN6_MBC_SNPCR_MAX (0<<21) 99 #define GEN6_MBC_SNPCR_MED (1<<21) 100 #define GEN6_MBC_SNPCR_LOW (2<<21) 101 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 102 103 #define VLV_G3DCTL 0x9024 104 #define VLV_GSCKGCTL 0x9028 105 106 #define GEN6_MBCTL 0x0907c 107 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 108 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 109 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 110 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 111 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 112 113 #define GEN6_GDRST 0x941c 114 #define GEN6_GRDOM_FULL (1 << 0) 115 #define GEN6_GRDOM_RENDER (1 << 1) 116 #define GEN6_GRDOM_MEDIA (1 << 2) 117 #define GEN6_GRDOM_BLT (1 << 3) 118 119 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 120 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 121 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 122 #define PP_DIR_DCLV_2G 0xffffffff 123 124 #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) 125 #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) 126 127 #define GAM_ECOCHK 0x4090 128 #define ECOCHK_SNB_BIT (1<<10) 129 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 130 #define ECOCHK_PPGTT_CACHE64B (0x3<<3) 131 #define ECOCHK_PPGTT_CACHE4B (0x0<<3) 132 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 133 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 134 #define ECOCHK_PPGTT_UC_HSW (0x1<<3) 135 #define ECOCHK_PPGTT_WT_HSW (0x2<<3) 136 #define ECOCHK_PPGTT_WB_HSW (0x3<<3) 137 138 #define GAC_ECO_BITS 0x14090 139 #define ECOBITS_SNB_BIT (1<<13) 140 #define ECOBITS_PPGTT_CACHE64B (3<<8) 141 #define ECOBITS_PPGTT_CACHE4B (0<<8) 142 143 #define GAB_CTL 0x24000 144 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 145 146 /* VGA stuff */ 147 148 #define VGA_ST01_MDA 0x3ba 149 #define VGA_ST01_CGA 0x3da 150 151 #define VGA_MSR_WRITE 0x3c2 152 #define VGA_MSR_READ 0x3cc 153 #define VGA_MSR_MEM_EN (1<<1) 154 #define VGA_MSR_CGA_MODE (1<<0) 155 156 #define VGA_SR_INDEX 0x3c4 157 #define SR01 1 158 #define VGA_SR_DATA 0x3c5 159 160 #define VGA_AR_INDEX 0x3c0 161 #define VGA_AR_VID_EN (1<<5) 162 #define VGA_AR_DATA_WRITE 0x3c0 163 #define VGA_AR_DATA_READ 0x3c1 164 165 #define VGA_GR_INDEX 0x3ce 166 #define VGA_GR_DATA 0x3cf 167 /* GR05 */ 168 #define VGA_GR_MEM_READ_MODE_SHIFT 3 169 #define VGA_GR_MEM_READ_MODE_PLANE 1 170 /* GR06 */ 171 #define VGA_GR_MEM_MODE_MASK 0xc 172 #define VGA_GR_MEM_MODE_SHIFT 2 173 #define VGA_GR_MEM_A0000_AFFFF 0 174 #define VGA_GR_MEM_A0000_BFFFF 1 175 #define VGA_GR_MEM_B0000_B7FFF 2 176 #define VGA_GR_MEM_B0000_BFFFF 3 177 178 #define VGA_DACMASK 0x3c6 179 #define VGA_DACRX 0x3c7 180 #define VGA_DACWX 0x3c8 181 #define VGA_DACDATA 0x3c9 182 183 #define VGA_CR_INDEX_MDA 0x3b4 184 #define VGA_CR_DATA_MDA 0x3b5 185 #define VGA_CR_INDEX_CGA 0x3d4 186 #define VGA_CR_DATA_CGA 0x3d5 187 188 /* 189 * Instruction field definitions used by the command parser 190 */ 191 #define INSTR_CLIENT_SHIFT 29 192 #define INSTR_CLIENT_MASK 0xE0000000 193 #define INSTR_MI_CLIENT 0x0 194 #define INSTR_BC_CLIENT 0x2 195 #define INSTR_RC_CLIENT 0x3 196 #define INSTR_SUBCLIENT_SHIFT 27 197 #define INSTR_SUBCLIENT_MASK 0x18000000 198 #define INSTR_MEDIA_SUBCLIENT 0x2 199 200 /* 201 * Memory interface instructions used by the kernel 202 */ 203 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 204 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 205 #define MI_GLOBAL_GTT (1<<22) 206 207 #define MI_NOOP MI_INSTR(0, 0) 208 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 209 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 210 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 211 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 212 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 213 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 214 #define MI_FLUSH MI_INSTR(0x04, 0) 215 #define MI_READ_FLUSH (1 << 0) 216 #define MI_EXE_FLUSH (1 << 1) 217 #define MI_NO_WRITE_FLUSH (1 << 2) 218 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 219 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 220 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 221 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 222 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 223 #define MI_ARB_ENABLE (1<<0) 224 #define MI_ARB_DISABLE (0<<0) 225 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 226 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 227 #define MI_SUSPEND_FLUSH_EN (1<<0) 228 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 229 #define MI_OVERLAY_CONTINUE (0x0<<21) 230 #define MI_OVERLAY_ON (0x1<<21) 231 #define MI_OVERLAY_OFF (0x2<<21) 232 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 233 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 234 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 235 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 236 /* IVB has funny definitions for which plane to flip. */ 237 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 238 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 239 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 240 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 241 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 242 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 243 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ 244 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 245 #define MI_SEMAPHORE_UPDATE (1<<21) 246 #define MI_SEMAPHORE_COMPARE (1<<20) 247 #define MI_SEMAPHORE_REGISTER (1<<18) 248 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 249 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 250 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 251 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 252 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 253 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 254 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 255 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 256 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 257 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 258 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 259 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 260 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 261 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 262 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 263 #define MI_MM_SPACE_GTT (1<<8) 264 #define MI_MM_SPACE_PHYSICAL (0<<8) 265 #define MI_SAVE_EXT_STATE_EN (1<<3) 266 #define MI_RESTORE_EXT_STATE_EN (1<<2) 267 #define MI_FORCE_RESTORE (1<<1) 268 #define MI_RESTORE_INHIBIT (1<<0) 269 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 270 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 271 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 272 #define MI_STORE_DWORD_INDEX_SHIFT 2 273 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 274 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 275 * simply ignores the register load under certain conditions. 276 * - One can actually load arbitrary many arbitrary registers: Simply issue x 277 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 278 */ 279 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 280 #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) 281 #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) 282 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 283 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 284 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 285 #define MI_INVALIDATE_TLB (1<<18) 286 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 287 #define MI_FLUSH_DW_OP_MASK (3<<14) 288 #define MI_FLUSH_DW_NOTIFY (1<<8) 289 #define MI_INVALIDATE_BSD (1<<7) 290 #define MI_FLUSH_DW_USE_GTT (1<<2) 291 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 292 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 293 #define MI_BATCH_NON_SECURE (1) 294 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 295 #define MI_BATCH_NON_SECURE_I965 (1<<8) 296 #define MI_BATCH_PPGTT_HSW (1<<8) 297 #define MI_BATCH_NON_SECURE_HSW (1<<13) 298 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 299 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 300 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 301 302 303 #define MI_PREDICATE_RESULT_2 (0x2214) 304 #define LOWER_SLICE_ENABLED (1<<0) 305 #define LOWER_SLICE_DISABLED (0<<0) 306 307 /* 308 * 3D instructions used by the kernel 309 */ 310 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 311 312 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 313 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 314 #define SC_UPDATE_SCISSOR (0x1<<1) 315 #define SC_ENABLE_MASK (0x1<<0) 316 #define SC_ENABLE (0x1<<0) 317 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 318 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 319 #define SCI_YMIN_MASK (0xffff<<16) 320 #define SCI_XMIN_MASK (0xffff<<0) 321 #define SCI_YMAX_MASK (0xffff<<16) 322 #define SCI_XMAX_MASK (0xffff<<0) 323 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 324 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 325 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 326 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 327 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 328 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 329 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 330 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 331 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 332 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 333 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 334 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 335 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 336 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 337 #define BLT_DEPTH_8 (0<<24) 338 #define BLT_DEPTH_16_565 (1<<24) 339 #define BLT_DEPTH_16_1555 (2<<24) 340 #define BLT_DEPTH_32 (3<<24) 341 #define BLT_ROP_GXCOPY (0xcc<<16) 342 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 343 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 344 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 345 #define ASYNC_FLIP (1<<22) 346 #define DISPLAY_PLANE_A (0<<20) 347 #define DISPLAY_PLANE_B (1<<20) 348 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 349 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 350 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 351 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 352 #define PIPE_CONTROL_CS_STALL (1<<20) 353 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 354 #define PIPE_CONTROL_QW_WRITE (1<<14) 355 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 356 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 357 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 358 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 359 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 360 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 361 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 362 #define PIPE_CONTROL_NOTIFY (1<<8) 363 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 364 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 365 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 366 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 367 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 368 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 369 370 /* 371 * Commands used only by the command parser 372 */ 373 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 374 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 375 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 376 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 377 #define MI_PREDICATE MI_INSTR(0x0C, 0) 378 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 379 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 380 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 381 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 382 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 383 #define MI_CLFLUSH MI_INSTR(0x27, 0) 384 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 385 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 386 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) 387 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 388 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 389 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 390 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 391 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 392 393 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 394 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 395 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 396 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 397 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 398 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 399 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 400 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 401 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 402 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 403 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 404 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 405 406 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 407 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 408 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 409 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 410 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 411 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 412 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 413 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 414 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 415 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 416 417 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 418 419 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 420 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 421 422 /* 423 * Registers used only by the command parser 424 */ 425 #define BCS_SWCTRL 0x22200 426 427 #define HS_INVOCATION_COUNT 0x2300 428 #define DS_INVOCATION_COUNT 0x2308 429 #define IA_VERTICES_COUNT 0x2310 430 #define IA_PRIMITIVES_COUNT 0x2318 431 #define VS_INVOCATION_COUNT 0x2320 432 #define GS_INVOCATION_COUNT 0x2328 433 #define GS_PRIMITIVES_COUNT 0x2330 434 #define CL_INVOCATION_COUNT 0x2338 435 #define CL_PRIMITIVES_COUNT 0x2340 436 #define PS_INVOCATION_COUNT 0x2348 437 #define PS_DEPTH_COUNT 0x2350 438 439 /* There are the 4 64-bit counter registers, one for each stream output */ 440 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) 441 442 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) 443 444 #define GEN7_3DPRIM_END_OFFSET 0x2420 445 #define GEN7_3DPRIM_START_VERTEX 0x2430 446 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 447 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 448 #define GEN7_3DPRIM_START_INSTANCE 0x243C 449 #define GEN7_3DPRIM_BASE_VERTEX 0x2440 450 451 #define OACONTROL 0x2360 452 453 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 454 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 455 #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ 456 _GEN7_PIPEA_DE_LOAD_SL, \ 457 _GEN7_PIPEB_DE_LOAD_SL) 458 459 /* 460 * Reset registers 461 */ 462 #define DEBUG_RESET_I830 0x6070 463 #define DEBUG_RESET_FULL (1<<7) 464 #define DEBUG_RESET_RENDER (1<<8) 465 #define DEBUG_RESET_DISPLAY (1<<9) 466 467 /* 468 * IOSF sideband 469 */ 470 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) 471 #define IOSF_DEVFN_SHIFT 24 472 #define IOSF_OPCODE_SHIFT 16 473 #define IOSF_PORT_SHIFT 8 474 #define IOSF_BYTE_ENABLES_SHIFT 4 475 #define IOSF_BAR_SHIFT 1 476 #define IOSF_SB_BUSY (1<<0) 477 #define IOSF_PORT_BUNIT 0x3 478 #define IOSF_PORT_PUNIT 0x4 479 #define IOSF_PORT_NC 0x11 480 #define IOSF_PORT_DPIO 0x12 481 #define IOSF_PORT_DPIO_2 0x1a 482 #define IOSF_PORT_GPIO_NC 0x13 483 #define IOSF_PORT_CCK 0x14 484 #define IOSF_PORT_CCU 0xA9 485 #define IOSF_PORT_GPS_CORE 0x48 486 #define IOSF_PORT_FLISDSI 0x1B 487 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 488 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 489 490 /* See configdb bunit SB addr map */ 491 #define BUNIT_REG_BISOC 0x11 492 493 #define PUNIT_REG_DSPFREQ 0x36 494 #define DSPFREQSTAT_SHIFT 30 495 #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 496 #define DSPFREQGUAR_SHIFT 14 497 #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 498 499 /* See the PUNIT HAS v0.8 for the below bits */ 500 enum punit_power_well { 501 PUNIT_POWER_WELL_RENDER = 0, 502 PUNIT_POWER_WELL_MEDIA = 1, 503 PUNIT_POWER_WELL_DISP2D = 3, 504 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 505 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 506 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 507 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 508 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 509 PUNIT_POWER_WELL_DPIO_RX0 = 10, 510 PUNIT_POWER_WELL_DPIO_RX1 = 11, 511 512 PUNIT_POWER_WELL_NUM, 513 }; 514 515 #define PUNIT_REG_PWRGT_CTRL 0x60 516 #define PUNIT_REG_PWRGT_STATUS 0x61 517 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 518 #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 519 #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 520 #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 521 #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 522 523 #define PUNIT_REG_GPU_LFM 0xd3 524 #define PUNIT_REG_GPU_FREQ_REQ 0xd4 525 #define PUNIT_REG_GPU_FREQ_STS 0xd8 526 #define GENFREQSTATUS (1<<0) 527 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 528 529 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 530 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 531 532 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 533 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 534 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 535 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 536 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 537 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 538 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 539 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 540 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 541 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 542 543 /* vlv2 north clock has */ 544 #define CCK_FUSE_REG 0x8 545 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 546 #define CCK_REG_DSI_PLL_FUSE 0x44 547 #define CCK_REG_DSI_PLL_CONTROL 0x48 548 #define DSI_PLL_VCO_EN (1 << 31) 549 #define DSI_PLL_LDO_GATE (1 << 30) 550 #define DSI_PLL_P1_POST_DIV_SHIFT 17 551 #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 552 #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 553 #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 554 #define DSI_PLL_MUX_MASK (3 << 9) 555 #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 556 #define DSI_PLL_MUX_DSI0_CCK (1 << 10) 557 #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 558 #define DSI_PLL_MUX_DSI1_CCK (1 << 9) 559 #define DSI_PLL_CLK_GATE_MASK (0xf << 5) 560 #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 561 #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 562 #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 563 #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 564 #define DSI_PLL_LOCK (1 << 0) 565 #define CCK_REG_DSI_PLL_DIVIDER 0x4c 566 #define DSI_PLL_LFSR (1 << 31) 567 #define DSI_PLL_FRACTION_EN (1 << 30) 568 #define DSI_PLL_FRAC_COUNTER_SHIFT 27 569 #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 570 #define DSI_PLL_USYNC_CNT_SHIFT 18 571 #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 572 #define DSI_PLL_N1_DIV_SHIFT 16 573 #define DSI_PLL_N1_DIV_MASK (3 << 16) 574 #define DSI_PLL_M1_DIV_SHIFT 0 575 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 576 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b 577 578 /** 579 * DOC: DPIO 580 * 581 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI 582 * ports. DPIO is the name given to such a display PHY. These PHYs 583 * don't follow the standard programming model using direct MMIO 584 * registers, and instead their registers must be accessed trough IOSF 585 * sideband. VLV has one such PHY for driving ports B and C, and CHV 586 * adds another PHY for driving port D. Each PHY responds to specific 587 * IOSF-SB port. 588 * 589 * Each display PHY is made up of one or two channels. Each channel 590 * houses a common lane part which contains the PLL and other common 591 * logic. CH0 common lane also contains the IOSF-SB logic for the 592 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 593 * must be running when any DPIO registers are accessed. 594 * 595 * In addition to having their own registers, the PHYs are also 596 * controlled through some dedicated signals from the display 597 * controller. These include PLL reference clock enable, PLL enable, 598 * and CRI clock selection, for example. 599 * 600 * Eeach channel also has two splines (also called data lanes), and 601 * each spline is made up of one Physical Access Coding Sub-Layer 602 * (PCS) block and two TX lanes. So each channel has two PCS blocks 603 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 604 * data/clock pairs depending on the output type. 605 * 606 * Additionally the PHY also contains an AUX lane with AUX blocks 607 * for each channel. This is used for DP AUX communication, but 608 * this fact isn't really relevant for the driver since AUX is 609 * controlled from the display controller side. No DPIO registers 610 * need to be accessed during AUX communication, 611 * 612 * Generally the common lane corresponds to the pipe and 613 * the spline (PCS/TX) correponds to the port. 614 * 615 * For dual channel PHY (VLV/CHV): 616 * 617 * pipe A == CMN/PLL/REF CH0 618 * 619 * pipe B == CMN/PLL/REF CH1 620 * 621 * port B == PCS/TX CH0 622 * 623 * port C == PCS/TX CH1 624 * 625 * This is especially important when we cross the streams 626 * ie. drive port B with pipe B, or port C with pipe A. 627 * 628 * For single channel PHY (CHV): 629 * 630 * pipe C == CMN/PLL/REF CH0 631 * 632 * port D == PCS/TX CH0 633 * 634 * Note: digital port B is DDI0, digital port C is DDI1, 635 * digital port D is DDI2 636 */ 637 /* 638 * Dual channel PHY (VLV/CHV) 639 * --------------------------------- 640 * | CH0 | CH1 | 641 * | CMN/PLL/REF | CMN/PLL/REF | 642 * |---------------|---------------| Display PHY 643 * | PCS01 | PCS23 | PCS01 | PCS23 | 644 * |-------|-------|-------|-------| 645 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 646 * --------------------------------- 647 * | DDI0 | DDI1 | DP/HDMI ports 648 * --------------------------------- 649 * 650 * Single channel PHY (CHV) 651 * ----------------- 652 * | CH0 | 653 * | CMN/PLL/REF | 654 * |---------------| Display PHY 655 * | PCS01 | PCS23 | 656 * |-------|-------| 657 * |TX0|TX1|TX2|TX3| 658 * ----------------- 659 * | DDI2 | DP/HDMI port 660 * ----------------- 661 */ 662 #define DPIO_DEVFN 0 663 664 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) 665 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 666 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 667 #define DPIO_SFR_BYPASS (1<<1) 668 #define DPIO_CMNRST (1<<0) 669 670 #define DPIO_PHY(pipe) ((pipe) >> 1) 671 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 672 673 /* 674 * Per pipe/PLL DPIO regs 675 */ 676 #define _VLV_PLL_DW3_CH0 0x800c 677 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 678 #define DPIO_POST_DIV_DAC 0 679 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 680 #define DPIO_POST_DIV_LVDS1 2 681 #define DPIO_POST_DIV_LVDS2 3 682 #define DPIO_K_SHIFT (24) /* 4 bits */ 683 #define DPIO_P1_SHIFT (21) /* 3 bits */ 684 #define DPIO_P2_SHIFT (16) /* 5 bits */ 685 #define DPIO_N_SHIFT (12) /* 4 bits */ 686 #define DPIO_ENABLE_CALIBRATION (1<<11) 687 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 688 #define DPIO_M2DIV_MASK 0xff 689 #define _VLV_PLL_DW3_CH1 0x802c 690 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 691 692 #define _VLV_PLL_DW5_CH0 0x8014 693 #define DPIO_REFSEL_OVERRIDE 27 694 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 695 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 696 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 697 #define DPIO_PLL_REFCLK_SEL_MASK 3 698 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 699 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 700 #define _VLV_PLL_DW5_CH1 0x8034 701 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 702 703 #define _VLV_PLL_DW7_CH0 0x801c 704 #define _VLV_PLL_DW7_CH1 0x803c 705 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 706 707 #define _VLV_PLL_DW8_CH0 0x8040 708 #define _VLV_PLL_DW8_CH1 0x8060 709 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 710 711 #define VLV_PLL_DW9_BCAST 0xc044 712 #define _VLV_PLL_DW9_CH0 0x8044 713 #define _VLV_PLL_DW9_CH1 0x8064 714 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 715 716 #define _VLV_PLL_DW10_CH0 0x8048 717 #define _VLV_PLL_DW10_CH1 0x8068 718 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 719 720 #define _VLV_PLL_DW11_CH0 0x804c 721 #define _VLV_PLL_DW11_CH1 0x806c 722 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 723 724 /* Spec for ref block start counts at DW10 */ 725 #define VLV_REF_DW13 0x80ac 726 727 #define VLV_CMN_DW0 0x8100 728 729 /* 730 * Per DDI channel DPIO regs 731 */ 732 733 #define _VLV_PCS_DW0_CH0 0x8200 734 #define _VLV_PCS_DW0_CH1 0x8400 735 #define DPIO_PCS_TX_LANE2_RESET (1<<16) 736 #define DPIO_PCS_TX_LANE1_RESET (1<<7) 737 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 738 739 #define _VLV_PCS01_DW0_CH0 0x200 740 #define _VLV_PCS23_DW0_CH0 0x400 741 #define _VLV_PCS01_DW0_CH1 0x2600 742 #define _VLV_PCS23_DW0_CH1 0x2800 743 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 744 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 745 746 #define _VLV_PCS_DW1_CH0 0x8204 747 #define _VLV_PCS_DW1_CH1 0x8404 748 #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 749 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 750 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 751 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 752 #define DPIO_PCS_CLK_SOFT_RESET (1<<5) 753 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 754 755 #define _VLV_PCS01_DW1_CH0 0x204 756 #define _VLV_PCS23_DW1_CH0 0x404 757 #define _VLV_PCS01_DW1_CH1 0x2604 758 #define _VLV_PCS23_DW1_CH1 0x2804 759 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 760 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 761 762 #define _VLV_PCS_DW8_CH0 0x8220 763 #define _VLV_PCS_DW8_CH1 0x8420 764 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 765 766 #define _VLV_PCS01_DW8_CH0 0x0220 767 #define _VLV_PCS23_DW8_CH0 0x0420 768 #define _VLV_PCS01_DW8_CH1 0x2620 769 #define _VLV_PCS23_DW8_CH1 0x2820 770 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 771 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 772 773 #define _VLV_PCS_DW9_CH0 0x8224 774 #define _VLV_PCS_DW9_CH1 0x8424 775 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 776 777 #define _CHV_PCS_DW10_CH0 0x8228 778 #define _CHV_PCS_DW10_CH1 0x8428 779 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 780 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 781 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 782 783 #define _VLV_PCS01_DW10_CH0 0x0228 784 #define _VLV_PCS23_DW10_CH0 0x0428 785 #define _VLV_PCS01_DW10_CH1 0x2628 786 #define _VLV_PCS23_DW10_CH1 0x2828 787 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 788 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 789 790 #define _VLV_PCS_DW11_CH0 0x822c 791 #define _VLV_PCS_DW11_CH1 0x842c 792 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 793 794 #define _VLV_PCS_DW12_CH0 0x8230 795 #define _VLV_PCS_DW12_CH1 0x8430 796 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 797 798 #define _VLV_PCS_DW14_CH0 0x8238 799 #define _VLV_PCS_DW14_CH1 0x8438 800 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 801 802 #define _VLV_PCS_DW23_CH0 0x825c 803 #define _VLV_PCS_DW23_CH1 0x845c 804 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 805 806 #define _VLV_TX_DW2_CH0 0x8288 807 #define _VLV_TX_DW2_CH1 0x8488 808 #define DPIO_SWING_MARGIN_SHIFT 16 809 #define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT) 810 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 811 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 812 813 #define _VLV_TX_DW3_CH0 0x828c 814 #define _VLV_TX_DW3_CH1 0x848c 815 /* The following bit for CHV phy */ 816 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 817 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 818 819 #define _VLV_TX_DW4_CH0 0x8290 820 #define _VLV_TX_DW4_CH1 0x8490 821 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 822 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 823 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 824 825 #define _VLV_TX3_DW4_CH0 0x690 826 #define _VLV_TX3_DW4_CH1 0x2a90 827 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 828 829 #define _VLV_TX_DW5_CH0 0x8294 830 #define _VLV_TX_DW5_CH1 0x8494 831 #define DPIO_TX_OCALINIT_EN (1<<31) 832 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 833 834 #define _VLV_TX_DW11_CH0 0x82ac 835 #define _VLV_TX_DW11_CH1 0x84ac 836 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 837 838 #define _VLV_TX_DW14_CH0 0x82b8 839 #define _VLV_TX_DW14_CH1 0x84b8 840 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 841 842 /* CHV dpPhy registers */ 843 #define _CHV_PLL_DW0_CH0 0x8000 844 #define _CHV_PLL_DW0_CH1 0x8180 845 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 846 847 #define _CHV_PLL_DW1_CH0 0x8004 848 #define _CHV_PLL_DW1_CH1 0x8184 849 #define DPIO_CHV_N_DIV_SHIFT 8 850 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 851 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 852 853 #define _CHV_PLL_DW2_CH0 0x8008 854 #define _CHV_PLL_DW2_CH1 0x8188 855 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 856 857 #define _CHV_PLL_DW3_CH0 0x800c 858 #define _CHV_PLL_DW3_CH1 0x818c 859 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 860 #define DPIO_CHV_FIRST_MOD (0 << 8) 861 #define DPIO_CHV_SECOND_MOD (1 << 8) 862 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 863 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 864 865 #define _CHV_PLL_DW6_CH0 0x8018 866 #define _CHV_PLL_DW6_CH1 0x8198 867 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 868 #define DPIO_CHV_INT_COEFF_SHIFT 8 869 #define DPIO_CHV_PROP_COEFF_SHIFT 0 870 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 871 872 #define _CHV_CMN_DW13_CH0 0x8134 873 #define _CHV_CMN_DW0_CH1 0x8080 874 #define DPIO_CHV_S1_DIV_SHIFT 21 875 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 876 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 877 #define DPIO_CHV_K_DIV_SHIFT 4 878 #define DPIO_PLL_FREQLOCK (1 << 1) 879 #define DPIO_PLL_LOCK (1 << 0) 880 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 881 882 #define _CHV_CMN_DW14_CH0 0x8138 883 #define _CHV_CMN_DW1_CH1 0x8084 884 #define DPIO_AFC_RECAL (1 << 14) 885 #define DPIO_DCLKP_EN (1 << 13) 886 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 887 888 #define CHV_CMN_DW30 0x8178 889 #define DPIO_LRC_BYPASS (1 << 3) 890 891 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 892 (lane) * 0x200 + (offset)) 893 894 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 895 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 896 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 897 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 898 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 899 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 900 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 901 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 902 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 903 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 904 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 905 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 906 #define DPIO_FRC_LATENCY_SHFIT 8 907 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 908 #define DPIO_UPAR_SHIFT 30 909 /* 910 * Fence registers 911 */ 912 #define FENCE_REG_830_0 0x2000 913 #define FENCE_REG_945_8 0x3000 914 #define I830_FENCE_START_MASK 0x07f80000 915 #define I830_FENCE_TILING_Y_SHIFT 12 916 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 917 #define I830_FENCE_PITCH_SHIFT 4 918 #define I830_FENCE_REG_VALID (1<<0) 919 #define I915_FENCE_MAX_PITCH_VAL 4 920 #define I830_FENCE_MAX_PITCH_VAL 6 921 #define I830_FENCE_MAX_SIZE_VAL (1<<8) 922 923 #define I915_FENCE_START_MASK 0x0ff00000 924 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 925 926 #define FENCE_REG_965_0 0x03000 927 #define I965_FENCE_PITCH_SHIFT 2 928 #define I965_FENCE_TILING_Y_SHIFT 1 929 #define I965_FENCE_REG_VALID (1<<0) 930 #define I965_FENCE_MAX_PITCH_VAL 0x0400 931 932 #define FENCE_REG_SANDYBRIDGE_0 0x100000 933 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 934 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 935 936 /* control register for cpu gtt access */ 937 #define TILECTL 0x101000 938 #define TILECTL_SWZCTL (1 << 0) 939 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 940 #define TILECTL_BACKSNOOP_DIS (1 << 3) 941 942 /* 943 * Instruction and interrupt control regs 944 */ 945 #define PGTBL_CTL 0x02020 946 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 947 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 948 #define PGTBL_ER 0x02024 949 #define RENDER_RING_BASE 0x02000 950 #define BSD_RING_BASE 0x04000 951 #define GEN6_BSD_RING_BASE 0x12000 952 #define GEN8_BSD2_RING_BASE 0x1c000 953 #define VEBOX_RING_BASE 0x1a000 954 #define BLT_RING_BASE 0x22000 955 #define RING_TAIL(base) ((base)+0x30) 956 #define RING_HEAD(base) ((base)+0x34) 957 #define RING_START(base) ((base)+0x38) 958 #define RING_CTL(base) ((base)+0x3c) 959 #define RING_SYNC_0(base) ((base)+0x40) 960 #define RING_SYNC_1(base) ((base)+0x44) 961 #define RING_SYNC_2(base) ((base)+0x48) 962 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 963 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 964 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 965 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 966 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 967 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 968 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 969 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 970 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 971 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 972 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 973 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 974 #define GEN6_NOSYNC 0 975 #define RING_MAX_IDLE(base) ((base)+0x54) 976 #define RING_HWS_PGA(base) ((base)+0x80) 977 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 978 979 #define GEN7_WR_WATERMARK 0x4028 980 #define GEN7_GFX_PRIO_CTRL 0x402C 981 #define ARB_MODE 0x4030 982 #define ARB_MODE_SWIZZLE_SNB (1<<4) 983 #define ARB_MODE_SWIZZLE_IVB (1<<5) 984 #define GEN7_GFX_PEND_TLB0 0x4034 985 #define GEN7_GFX_PEND_TLB1 0x4038 986 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 987 #define GEN7_LRA_LIMITS_BASE 0x403C 988 #define GEN7_LRA_LIMITS_REG_NUM 13 989 #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 990 #define GEN7_GFX_MAX_REQ_COUNT 0x4074 991 992 #define GAMTARBMODE 0x04a08 993 #define ARB_MODE_BWGTLB_DISABLE (1<<9) 994 #define ARB_MODE_SWIZZLE_BDW (1<<1) 995 #define RENDER_HWS_PGA_GEN7 (0x04080) 996 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 997 #define RING_FAULT_GTTSEL_MASK (1<<11) 998 #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) 999 #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) 1000 #define RING_FAULT_VALID (1<<0) 1001 #define DONE_REG 0x40b0 1002 #define GEN8_PRIVATE_PAT 0x40e0 1003 #define BSD_HWS_PGA_GEN7 (0x04180) 1004 #define BLT_HWS_PGA_GEN7 (0x04280) 1005 #define VEBOX_HWS_PGA_GEN7 (0x04380) 1006 #define RING_ACTHD(base) ((base)+0x74) 1007 #define RING_ACTHD_UDW(base) ((base)+0x5c) 1008 #define RING_NOPID(base) ((base)+0x94) 1009 #define RING_IMR(base) ((base)+0xa8) 1010 #define RING_TIMESTAMP(base) ((base)+0x358) 1011 #define TAIL_ADDR 0x001FFFF8 1012 #define HEAD_WRAP_COUNT 0xFFE00000 1013 #define HEAD_WRAP_ONE 0x00200000 1014 #define HEAD_ADDR 0x001FFFFC 1015 #define RING_NR_PAGES 0x001FF000 1016 #define RING_REPORT_MASK 0x00000006 1017 #define RING_REPORT_64K 0x00000002 1018 #define RING_REPORT_128K 0x00000004 1019 #define RING_NO_REPORT 0x00000000 1020 #define RING_VALID_MASK 0x00000001 1021 #define RING_VALID 0x00000001 1022 #define RING_INVALID 0x00000000 1023 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 1024 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 1025 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 1026 1027 #define GEN7_TLB_RD_ADDR 0x4700 1028 1029 #if 0 1030 #define PRB0_TAIL 0x02030 1031 #define PRB0_HEAD 0x02034 1032 #define PRB0_START 0x02038 1033 #define PRB0_CTL 0x0203c 1034 #define PRB1_TAIL 0x02040 /* 915+ only */ 1035 #define PRB1_HEAD 0x02044 /* 915+ only */ 1036 #define PRB1_START 0x02048 /* 915+ only */ 1037 #define PRB1_CTL 0x0204c /* 915+ only */ 1038 #endif 1039 #define IPEIR_I965 0x02064 1040 #define IPEHR_I965 0x02068 1041 #define INSTDONE_I965 0x0206c 1042 #define GEN7_INSTDONE_1 0x0206c 1043 #define GEN7_SC_INSTDONE 0x07100 1044 #define GEN7_SAMPLER_INSTDONE 0x0e160 1045 #define GEN7_ROW_INSTDONE 0x0e164 1046 #define I915_NUM_INSTDONE_REG 4 1047 #define RING_IPEIR(base) ((base)+0x64) 1048 #define RING_IPEHR(base) ((base)+0x68) 1049 #define RING_INSTDONE(base) ((base)+0x6c) 1050 #define RING_INSTPS(base) ((base)+0x70) 1051 #define RING_DMA_FADD(base) ((base)+0x78) 1052 #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ 1053 #define RING_INSTPM(base) ((base)+0xc0) 1054 #define RING_MI_MODE(base) ((base)+0x9c) 1055 #define INSTPS 0x02070 /* 965+ only */ 1056 #define INSTDONE1 0x0207c /* 965+ only */ 1057 #define ACTHD_I965 0x02074 1058 #define HWS_PGA 0x02080 1059 #define HWS_ADDRESS_MASK 0xfffff000 1060 #define HWS_START_ADDRESS_SHIFT 4 1061 #define PWRCTXA 0x2088 /* 965GM+ only */ 1062 #define PWRCTX_EN (1<<0) 1063 #define IPEIR 0x02088 1064 #define IPEHR 0x0208c 1065 #define INSTDONE 0x02090 1066 #define NOPID 0x02094 1067 #define HWSTAM 0x02098 1068 #define DMA_FADD_I8XX 0x020d0 1069 #define RING_BBSTATE(base) ((base)+0x110) 1070 #define RING_BBADDR(base) ((base)+0x140) 1071 #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ 1072 1073 #define ERROR_GEN6 0x040a0 1074 #define GEN7_ERR_INT 0x44040 1075 #define ERR_INT_POISON (1<<31) 1076 #define ERR_INT_MMIO_UNCLAIMED (1<<13) 1077 #define ERR_INT_PIPE_CRC_DONE_C (1<<8) 1078 #define ERR_INT_FIFO_UNDERRUN_C (1<<6) 1079 #define ERR_INT_PIPE_CRC_DONE_B (1<<5) 1080 #define ERR_INT_FIFO_UNDERRUN_B (1<<3) 1081 #define ERR_INT_PIPE_CRC_DONE_A (1<<2) 1082 #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) 1083 #define ERR_INT_FIFO_UNDERRUN_A (1<<0) 1084 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 1085 1086 #define FPGA_DBG 0x42300 1087 #define FPGA_DBG_RM_NOCLAIM (1<<31) 1088 1089 #define DERRMR 0x44050 1090 /* Note that HBLANK events are reserved on bdw+ */ 1091 #define DERRMR_PIPEA_SCANLINE (1<<0) 1092 #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 1093 #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 1094 #define DERRMR_PIPEA_VBLANK (1<<3) 1095 #define DERRMR_PIPEA_HBLANK (1<<5) 1096 #define DERRMR_PIPEB_SCANLINE (1<<8) 1097 #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 1098 #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 1099 #define DERRMR_PIPEB_VBLANK (1<<11) 1100 #define DERRMR_PIPEB_HBLANK (1<<13) 1101 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1102 #define DERRMR_PIPEC_SCANLINE (1<<14) 1103 #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 1104 #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 1105 #define DERRMR_PIPEC_VBLANK (1<<21) 1106 #define DERRMR_PIPEC_HBLANK (1<<22) 1107 1108 1109 /* GM45+ chicken bits -- debug workaround bits that may be required 1110 * for various sorts of correct behavior. The top 16 bits of each are 1111 * the enables for writing to the corresponding low bit. 1112 */ 1113 #define _3D_CHICKEN 0x02084 1114 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 1115 #define _3D_CHICKEN2 0x0208c 1116 /* Disables pipelining of read flushes past the SF-WIZ interface. 1117 * Required on all Ironlake steppings according to the B-Spec, but the 1118 * particular danger of not doing so is not specified. 1119 */ 1120 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 1121 #define _3D_CHICKEN3 0x02090 1122 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 1123 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 1124 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 1125 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 1126 1127 #define MI_MODE 0x0209c 1128 # define VS_TIMER_DISPATCH (1 << 6) 1129 # define MI_FLUSH_ENABLE (1 << 12) 1130 # define ASYNC_FLIP_PERF_DISABLE (1 << 14) 1131 # define MODE_IDLE (1 << 9) 1132 # define STOP_RING (1 << 8) 1133 1134 #define GEN6_GT_MODE 0x20d0 1135 #define GEN7_GT_MODE 0x7008 1136 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 1137 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 1138 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 1139 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 1140 #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) 1141 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 1142 1143 #define GFX_MODE 0x02520 1144 #define GFX_MODE_GEN7 0x0229c 1145 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 1146 #define GFX_RUN_LIST_ENABLE (1<<15) 1147 #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 1148 #define GFX_SURFACE_FAULT_ENABLE (1<<12) 1149 #define GFX_REPLAY_MODE (1<<11) 1150 #define GFX_PSMI_GRANULARITY (1<<10) 1151 #define GFX_PPGTT_ENABLE (1<<9) 1152 1153 #define VLV_DISPLAY_BASE 0x180000 1154 #define VLV_MIPI_BASE VLV_DISPLAY_BASE 1155 1156 #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) 1157 #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) 1158 #define SCPD0 0x0209c /* 915+ only */ 1159 #define IER 0x020a0 1160 #define IIR 0x020a4 1161 #define IMR 0x020a8 1162 #define ISR 0x020ac 1163 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) 1164 #define GINT_DIS (1<<22) 1165 #define GCFG_DIS (1<<8) 1166 #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) 1167 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) 1168 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) 1169 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) 1170 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) 1171 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) 1172 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) 1173 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 1174 #define EIR 0x020b0 1175 #define EMR 0x020b4 1176 #define ESR 0x020b8 1177 #define GM45_ERROR_PAGE_TABLE (1<<5) 1178 #define GM45_ERROR_MEM_PRIV (1<<4) 1179 #define I915_ERROR_PAGE_TABLE (1<<4) 1180 #define GM45_ERROR_CP_PRIV (1<<3) 1181 #define I915_ERROR_MEMORY_REFRESH (1<<1) 1182 #define I915_ERROR_INSTRUCTION (1<<0) 1183 #define INSTPM 0x020c0 1184 #define INSTPM_SELF_EN (1<<12) /* 915GM only */ 1185 #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 1186 will not assert AGPBUSY# and will only 1187 be delivered when out of C3. */ 1188 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 1189 #define INSTPM_TLB_INVALIDATE (1<<9) 1190 #define INSTPM_SYNC_FLUSH (1<<5) 1191 #define ACTHD 0x020c8 1192 #define FW_BLC 0x020d8 1193 #define FW_BLC2 0x020dc 1194 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 1195 #define FW_BLC_SELF_EN_MASK (1<<31) 1196 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 1197 #define FW_BLC_SELF_EN (1<<15) /* 945 only */ 1198 #define MM_BURST_LENGTH 0x00700000 1199 #define MM_FIFO_WATERMARK 0x0001F000 1200 #define LM_BURST_LENGTH 0x00000700 1201 #define LM_FIFO_WATERMARK 0x0000001F 1202 #define MI_ARB_STATE 0x020e4 /* 915+ only */ 1203 1204 /* Make render/texture TLB fetches lower priorty than associated data 1205 * fetches. This is not turned on by default 1206 */ 1207 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1208 1209 /* Isoch request wait on GTT enable (Display A/B/C streams). 1210 * Make isoch requests stall on the TLB update. May cause 1211 * display underruns (test mode only) 1212 */ 1213 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1214 1215 /* Block grant count for isoch requests when block count is 1216 * set to a finite value. 1217 */ 1218 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1219 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1220 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1221 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1222 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1223 1224 /* Enable render writes to complete in C2/C3/C4 power states. 1225 * If this isn't enabled, render writes are prevented in low 1226 * power states. That seems bad to me. 1227 */ 1228 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1229 1230 /* This acknowledges an async flip immediately instead 1231 * of waiting for 2TLB fetches. 1232 */ 1233 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1234 1235 /* Enables non-sequential data reads through arbiter 1236 */ 1237 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1238 1239 /* Disable FSB snooping of cacheable write cycles from binner/render 1240 * command stream 1241 */ 1242 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1243 1244 /* Arbiter time slice for non-isoch streams */ 1245 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1246 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1247 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1248 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1249 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1250 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1251 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1252 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1253 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1254 1255 /* Low priority grace period page size */ 1256 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1257 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1258 1259 /* Disable display A/B trickle feed */ 1260 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1261 1262 /* Set display plane priority */ 1263 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1264 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1265 1266 #define MI_STATE 0x020e4 /* gen2 only */ 1267 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1268 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1269 1270 #define CACHE_MODE_0 0x02120 /* 915+ only */ 1271 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 1272 #define CM0_IZ_OPT_DISABLE (1<<6) 1273 #define CM0_ZR_OPT_DISABLE (1<<5) 1274 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 1275 #define CM0_DEPTH_EVICT_DISABLE (1<<4) 1276 #define CM0_COLOR_EVICT_DISABLE (1<<3) 1277 #define CM0_DEPTH_WRITE_DISABLE (1<<1) 1278 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 1279 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 1280 #define GFX_FLSH_CNTL_GEN6 0x101008 1281 #define GFX_FLSH_CNTL_EN (1<<0) 1282 #define ECOSKPD 0x021d0 1283 #define ECO_GATING_CX_ONLY (1<<3) 1284 #define ECO_FLIP_DONE (1<<0) 1285 1286 #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ 1287 #define RC_OP_FLUSH_ENABLE (1<<0) 1288 #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 1289 #define CACHE_MODE_1 0x7004 /* IVB+ */ 1290 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 1291 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 1292 1293 #define GEN6_BLITTER_ECOSKPD 0x221d0 1294 #define GEN6_BLITTER_LOCK_SHIFT 16 1295 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) 1296 1297 #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 1298 #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 1299 #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 1300 1301 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 1302 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 1303 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 1304 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 1305 #define GEN6_BSD_GO_INDICATOR (1 << 4) 1306 1307 /* On modern GEN architectures interrupt control consists of two sets 1308 * of registers. The first set pertains to the ring generating the 1309 * interrupt. The second control is for the functional block generating the 1310 * interrupt. These are PM, GT, DE, etc. 1311 * 1312 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1313 * GT interrupt bits, so we don't need to duplicate the defines. 1314 * 1315 * These defines should cover us well from SNB->HSW with minor exceptions 1316 * it can also work on ILK. 1317 */ 1318 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1319 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1320 #define GT_BLT_USER_INTERRUPT (1 << 22) 1321 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1322 #define GT_BSD_USER_INTERRUPT (1 << 12) 1323 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1324 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1325 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1326 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 1327 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1328 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1329 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1330 1331 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1332 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1333 1334 #define GT_PARITY_ERROR(dev) \ 1335 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1336 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1337 1338 /* These are all the "old" interrupts */ 1339 #define ILK_BSD_USER_INTERRUPT (1<<5) 1340 1341 #define I915_PM_INTERRUPT (1<<31) 1342 #define I915_ISP_INTERRUPT (1<<22) 1343 #define I915_LPE_PIPE_B_INTERRUPT (1<<21) 1344 #define I915_LPE_PIPE_A_INTERRUPT (1<<20) 1345 #define I915_MIPIB_INTERRUPT (1<<19) 1346 #define I915_MIPIA_INTERRUPT (1<<18) 1347 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 1348 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 1349 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 1350 #define I915_MASTER_ERROR_INTERRUPT (1<<15) 1351 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 1352 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 1353 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 1354 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 1355 #define I915_HWB_OOM_INTERRUPT (1<<13) 1356 #define I915_LPE_PIPE_C_INTERRUPT (1<<12) 1357 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 1358 #define I915_MISC_INTERRUPT (1<<11) 1359 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 1360 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 1361 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 1362 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 1363 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 1364 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 1365 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 1366 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 1367 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 1368 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 1369 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 1370 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 1371 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 1372 #define I915_DEBUG_INTERRUPT (1<<2) 1373 #define I915_WINVALID_INTERRUPT (1<<1) 1374 #define I915_USER_INTERRUPT (1<<1) 1375 #define I915_ASLE_INTERRUPT (1<<0) 1376 #define I915_BSD_USER_INTERRUPT (1<<25) 1377 1378 #define GEN6_BSD_RNCID 0x12198 1379 1380 #define GEN7_FF_THREAD_MODE 0x20a0 1381 #define GEN7_FF_SCHED_MASK 0x0077070 1382 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1383 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 1384 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 1385 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 1386 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 1387 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1388 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 1389 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 1390 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 1391 #define GEN7_FF_VS_SCHED_HW (0x0<<12) 1392 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 1393 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 1394 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 1395 #define GEN7_FF_DS_SCHED_HW (0x0<<4) 1396 1397 /* 1398 * Framebuffer compression (915+ only) 1399 */ 1400 1401 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1402 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1403 #define FBC_CONTROL 0x03208 1404 #define FBC_CTL_EN (1<<31) 1405 #define FBC_CTL_PERIODIC (1<<30) 1406 #define FBC_CTL_INTERVAL_SHIFT (16) 1407 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 1408 #define FBC_CTL_C3_IDLE (1<<13) 1409 #define FBC_CTL_STRIDE_SHIFT (5) 1410 #define FBC_CTL_FENCENO_SHIFT (0) 1411 #define FBC_COMMAND 0x0320c 1412 #define FBC_CMD_COMPRESS (1<<0) 1413 #define FBC_STATUS 0x03210 1414 #define FBC_STAT_COMPRESSING (1<<31) 1415 #define FBC_STAT_COMPRESSED (1<<30) 1416 #define FBC_STAT_MODIFIED (1<<29) 1417 #define FBC_STAT_CURRENT_LINE_SHIFT (0) 1418 #define FBC_CONTROL2 0x03214 1419 #define FBC_CTL_FENCE_DBL (0<<4) 1420 #define FBC_CTL_IDLE_IMM (0<<2) 1421 #define FBC_CTL_IDLE_FULL (1<<2) 1422 #define FBC_CTL_IDLE_LINE (2<<2) 1423 #define FBC_CTL_IDLE_DEBUG (3<<2) 1424 #define FBC_CTL_CPU_FENCE (1<<1) 1425 #define FBC_CTL_PLANE(plane) ((plane)<<0) 1426 #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ 1427 #define FBC_TAG 0x03300 1428 1429 #define FBC_LL_SIZE (1536) 1430 1431 /* Framebuffer compression for GM45+ */ 1432 #define DPFC_CB_BASE 0x3200 1433 #define DPFC_CONTROL 0x3208 1434 #define DPFC_CTL_EN (1<<31) 1435 #define DPFC_CTL_PLANE(plane) ((plane)<<30) 1436 #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 1437 #define DPFC_CTL_FENCE_EN (1<<29) 1438 #define IVB_DPFC_CTL_FENCE_EN (1<<28) 1439 #define DPFC_CTL_PERSISTENT_MODE (1<<25) 1440 #define DPFC_SR_EN (1<<10) 1441 #define DPFC_CTL_LIMIT_1X (0<<6) 1442 #define DPFC_CTL_LIMIT_2X (1<<6) 1443 #define DPFC_CTL_LIMIT_4X (2<<6) 1444 #define DPFC_RECOMP_CTL 0x320c 1445 #define DPFC_RECOMP_STALL_EN (1<<27) 1446 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 1447 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 1448 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 1449 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 1450 #define DPFC_STATUS 0x3210 1451 #define DPFC_INVAL_SEG_SHIFT (16) 1452 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 1453 #define DPFC_COMP_SEG_SHIFT (0) 1454 #define DPFC_COMP_SEG_MASK (0x000003ff) 1455 #define DPFC_STATUS2 0x3214 1456 #define DPFC_FENCE_YOFF 0x3218 1457 #define DPFC_CHICKEN 0x3224 1458 #define DPFC_HT_MODIFY (1<<31) 1459 1460 /* Framebuffer compression for Ironlake */ 1461 #define ILK_DPFC_CB_BASE 0x43200 1462 #define ILK_DPFC_CONTROL 0x43208 1463 /* The bit 28-8 is reserved */ 1464 #define DPFC_RESERVED (0x1FFFFF00) 1465 #define ILK_DPFC_RECOMP_CTL 0x4320c 1466 #define ILK_DPFC_STATUS 0x43210 1467 #define ILK_DPFC_FENCE_YOFF 0x43218 1468 #define ILK_DPFC_CHICKEN 0x43224 1469 #define ILK_FBC_RT_BASE 0x2128 1470 #define ILK_FBC_RT_VALID (1<<0) 1471 #define SNB_FBC_FRONT_BUFFER (1<<1) 1472 1473 #define ILK_DISPLAY_CHICKEN1 0x42000 1474 #define ILK_FBCQ_DIS (1<<22) 1475 #define ILK_PABSTRETCH_DIS (1<<21) 1476 1477 1478 /* 1479 * Framebuffer compression for Sandybridge 1480 * 1481 * The following two registers are of type GTTMMADR 1482 */ 1483 #define SNB_DPFC_CTL_SA 0x100100 1484 #define SNB_CPU_FENCE_ENABLE (1<<29) 1485 #define DPFC_CPU_FENCE_OFFSET 0x100104 1486 1487 /* Framebuffer compression for Ivybridge */ 1488 #define IVB_FBC_RT_BASE 0x7020 1489 1490 #define IPS_CTL 0x43408 1491 #define IPS_ENABLE (1 << 31) 1492 1493 #define MSG_FBC_REND_STATE 0x50380 1494 #define FBC_REND_NUKE (1<<2) 1495 #define FBC_REND_CACHE_CLEAN (1<<1) 1496 1497 /* 1498 * GPIO regs 1499 */ 1500 #define GPIOA 0x5010 1501 #define GPIOB 0x5014 1502 #define GPIOC 0x5018 1503 #define GPIOD 0x501c 1504 #define GPIOE 0x5020 1505 #define GPIOF 0x5024 1506 #define GPIOG 0x5028 1507 #define GPIOH 0x502c 1508 # define GPIO_CLOCK_DIR_MASK (1 << 0) 1509 # define GPIO_CLOCK_DIR_IN (0 << 1) 1510 # define GPIO_CLOCK_DIR_OUT (1 << 1) 1511 # define GPIO_CLOCK_VAL_MASK (1 << 2) 1512 # define GPIO_CLOCK_VAL_OUT (1 << 3) 1513 # define GPIO_CLOCK_VAL_IN (1 << 4) 1514 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1515 # define GPIO_DATA_DIR_MASK (1 << 8) 1516 # define GPIO_DATA_DIR_IN (0 << 9) 1517 # define GPIO_DATA_DIR_OUT (1 << 9) 1518 # define GPIO_DATA_VAL_MASK (1 << 10) 1519 # define GPIO_DATA_VAL_OUT (1 << 11) 1520 # define GPIO_DATA_VAL_IN (1 << 12) 1521 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1522 1523 #define GMBUS0 0x5100 /* clock/port select */ 1524 #define GMBUS_RATE_100KHZ (0<<8) 1525 #define GMBUS_RATE_50KHZ (1<<8) 1526 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 1527 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 1528 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 1529 #define GMBUS_PORT_DISABLED 0 1530 #define GMBUS_PORT_SSC 1 1531 #define GMBUS_PORT_VGADDC 2 1532 #define GMBUS_PORT_PANEL 3 1533 #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ 1534 #define GMBUS_PORT_DPC 4 /* HDMIC */ 1535 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 1536 #define GMBUS_PORT_DPD 6 /* HDMID */ 1537 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ 1538 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) 1539 #define GMBUS1 0x5104 /* command/status */ 1540 #define GMBUS_SW_CLR_INT (1<<31) 1541 #define GMBUS_SW_RDY (1<<30) 1542 #define GMBUS_ENT (1<<29) /* enable timeout */ 1543 #define GMBUS_CYCLE_NONE (0<<25) 1544 #define GMBUS_CYCLE_WAIT (1<<25) 1545 #define GMBUS_CYCLE_INDEX (2<<25) 1546 #define GMBUS_CYCLE_STOP (4<<25) 1547 #define GMBUS_BYTE_COUNT_SHIFT 16 1548 #define GMBUS_SLAVE_INDEX_SHIFT 8 1549 #define GMBUS_SLAVE_ADDR_SHIFT 1 1550 #define GMBUS_SLAVE_READ (1<<0) 1551 #define GMBUS_SLAVE_WRITE (0<<0) 1552 #define GMBUS2 0x5108 /* status */ 1553 #define GMBUS_INUSE (1<<15) 1554 #define GMBUS_HW_WAIT_PHASE (1<<14) 1555 #define GMBUS_STALL_TIMEOUT (1<<13) 1556 #define GMBUS_INT (1<<12) 1557 #define GMBUS_HW_RDY (1<<11) 1558 #define GMBUS_SATOER (1<<10) 1559 #define GMBUS_ACTIVE (1<<9) 1560 #define GMBUS3 0x510c /* data buffer bytes 3-0 */ 1561 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 1562 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 1563 #define GMBUS_NAK_EN (1<<3) 1564 #define GMBUS_IDLE_EN (1<<2) 1565 #define GMBUS_HW_WAIT_EN (1<<1) 1566 #define GMBUS_HW_RDY_EN (1<<0) 1567 #define GMBUS5 0x5120 /* byte index */ 1568 #define GMBUS_2BYTE_INDEX_EN (1<<31) 1569 1570 /* 1571 * Clock control & power management 1572 */ 1573 #define DPLL_A_OFFSET 0x6014 1574 #define DPLL_B_OFFSET 0x6018 1575 #define CHV_DPLL_C_OFFSET 0x6030 1576 #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \ 1577 dev_priv->info.display_mmio_offset) 1578 1579 #define VGA0 0x6000 1580 #define VGA1 0x6004 1581 #define VGA_PD 0x6010 1582 #define VGA0_PD_P2_DIV_4 (1 << 7) 1583 #define VGA0_PD_P1_DIV_2 (1 << 5) 1584 #define VGA0_PD_P1_SHIFT 0 1585 #define VGA0_PD_P1_MASK (0x1f << 0) 1586 #define VGA1_PD_P2_DIV_4 (1 << 15) 1587 #define VGA1_PD_P1_DIV_2 (1 << 13) 1588 #define VGA1_PD_P1_SHIFT 8 1589 #define VGA1_PD_P1_MASK (0x1f << 8) 1590 #define DPLL_VCO_ENABLE (1 << 31) 1591 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1592 #define DPLL_DVO_2X_MODE (1 << 30) 1593 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1594 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1595 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 1596 #define DPLL_VGA_MODE_DIS (1 << 28) 1597 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1598 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1599 #define DPLL_MODE_MASK (3 << 26) 1600 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1601 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1602 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1603 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1604 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1605 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1606 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1607 #define DPLL_LOCK_VLV (1<<15) 1608 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 1609 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 1610 #define DPLL_SSC_REF_CLOCK_CHV (1<<13) 1611 #define DPLL_PORTC_READY_MASK (0xf << 4) 1612 #define DPLL_PORTB_READY_MASK (0xf) 1613 1614 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1615 1616 /* Additional CHV pll/phy registers */ 1617 #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) 1618 #define DPLL_PORTD_READY_MASK (0xf) 1619 #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) 1620 #define PHY_COM_LANE_RESET_DEASSERT(phy, val) \ 1621 ((phy == DPIO_PHY0) ? (val | 1) : (val | 2)) 1622 #define PHY_COM_LANE_RESET_ASSERT(phy, val) \ 1623 ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2)) 1624 #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) 1625 #define PHY_POWERGOOD(phy) ((phy == DPIO_PHY0) ? (1<<31) : (1<<30)) 1626 1627 /* 1628 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1629 * this field (only one bit may be set). 1630 */ 1631 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1632 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1633 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1634 /* i830, required in DVO non-gang */ 1635 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1636 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1637 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1638 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1639 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1640 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1641 #define PLL_REF_INPUT_MASK (3 << 13) 1642 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1643 /* Ironlake */ 1644 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1645 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1646 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 1647 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1648 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1649 1650 /* 1651 * Parallel to Serial Load Pulse phase selection. 1652 * Selects the phase for the 10X DPLL clock for the PCIe 1653 * digital display port. The range is 4 to 13; 10 or more 1654 * is just a flip delay. The default is 6 1655 */ 1656 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1657 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1658 /* 1659 * SDVO multiplier for 945G/GM. Not used on 965. 1660 */ 1661 #define SDVO_MULTIPLIER_MASK 0x000000ff 1662 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1663 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1664 1665 #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */ 1666 #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */ 1667 #define CHV_DPLL_C_MD_OFFSET 0x603c 1668 #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \ 1669 dev_priv->info.display_mmio_offset) 1670 1671 /* 1672 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1673 * 1674 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1675 */ 1676 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1677 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1678 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1679 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1680 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1681 /* 1682 * SDVO/UDI pixel multiplier. 1683 * 1684 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1685 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1686 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1687 * dummy bytes in the datastream at an increased clock rate, with both sides of 1688 * the link knowing how many bytes are fill. 1689 * 1690 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1691 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1692 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1693 * through an SDVO command. 1694 * 1695 * This register field has values of multiplication factor minus 1, with 1696 * a maximum multiplier of 5 for SDVO. 1697 */ 1698 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1699 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1700 /* 1701 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1702 * This best be set to the default value (3) or the CRT won't work. No, 1703 * I don't entirely understand what this does... 1704 */ 1705 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1706 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1707 1708 #define _FPA0 0x06040 1709 #define _FPA1 0x06044 1710 #define _FPB0 0x06048 1711 #define _FPB1 0x0604c 1712 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 1713 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 1714 #define FP_N_DIV_MASK 0x003f0000 1715 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1716 #define FP_N_DIV_SHIFT 16 1717 #define FP_M1_DIV_MASK 0x00003f00 1718 #define FP_M1_DIV_SHIFT 8 1719 #define FP_M2_DIV_MASK 0x0000003f 1720 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1721 #define FP_M2_DIV_SHIFT 0 1722 #define DPLL_TEST 0x606c 1723 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1724 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1725 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1726 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1727 #define DPLLB_TEST_N_BYPASS (1 << 19) 1728 #define DPLLB_TEST_M_BYPASS (1 << 18) 1729 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1730 #define DPLLA_TEST_N_BYPASS (1 << 3) 1731 #define DPLLA_TEST_M_BYPASS (1 << 2) 1732 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1733 #define D_STATE 0x6104 1734 #define DSTATE_GFX_RESET_I830 (1<<6) 1735 #define DSTATE_PLL_D3_OFF (1<<3) 1736 #define DSTATE_GFX_CLOCK_GATING (1<<1) 1737 #define DSTATE_DOT_CLOCK_GATING (1<<0) 1738 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) 1739 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1740 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1741 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1742 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1743 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1744 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1745 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1746 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1747 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1748 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1749 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1750 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1751 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1752 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1753 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1754 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1755 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1756 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1757 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1758 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1759 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1760 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1761 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1762 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1763 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1764 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1765 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1766 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1767 /* 1768 * This bit must be set on the 830 to prevent hangs when turning off the 1769 * overlay scaler. 1770 */ 1771 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1772 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1773 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1774 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1775 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1776 1777 #define RENCLK_GATE_D1 0x6204 1778 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1779 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1780 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1781 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1782 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1783 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1784 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1785 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1786 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1787 /* This bit must be unset on 855,865 */ 1788 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1789 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1790 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1791 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1792 /* This bit must be set on 855,865. */ 1793 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1794 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1795 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1796 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1797 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1798 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1799 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1800 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1801 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1802 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1803 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1804 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1805 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1806 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1807 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1808 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1809 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1810 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1811 1812 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1813 /* This bit must always be set on 965G/965GM */ 1814 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1815 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1816 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1817 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1818 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1819 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1820 /* This bit must always be set on 965G */ 1821 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1822 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1823 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1824 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1825 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1826 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1827 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1828 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1829 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1830 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1831 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1832 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1833 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1834 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1835 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1836 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1837 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1838 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1839 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1840 1841 #define RENCLK_GATE_D2 0x6208 1842 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1843 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1844 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1845 1846 #define VDECCLK_GATE_D 0x620C /* g4x only */ 1847 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1848 1849 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 1850 #define DEUC 0x6214 /* CRL only */ 1851 1852 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) 1853 #define FW_CSPWRDWNEN (1<<15) 1854 1855 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) 1856 1857 #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) 1858 #define CDCLK_FREQ_SHIFT 4 1859 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1860 #define CZCLK_FREQ_MASK 0xf 1861 #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) 1862 1863 /* 1864 * Palette regs 1865 */ 1866 #define PALETTE_A_OFFSET 0xa000 1867 #define PALETTE_B_OFFSET 0xa800 1868 #define CHV_PALETTE_C_OFFSET 0xc000 1869 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ 1870 dev_priv->info.display_mmio_offset) 1871 1872 /* MCH MMIO space */ 1873 1874 /* 1875 * MCHBAR mirror. 1876 * 1877 * This mirrors the MCHBAR MMIO space whose location is determined by 1878 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1879 * every way. It is not accessible from the CP register read instructions. 1880 * 1881 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 1882 * just read. 1883 */ 1884 #define MCHBAR_MIRROR_BASE 0x10000 1885 1886 #define MCHBAR_MIRROR_BASE_SNB 0x140000 1887 1888 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 1889 #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) 1890 1891 /* 915-945 and GM965 MCH register controlling DRAM channel access */ 1892 #define DCC 0x10200 1893 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1894 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1895 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1896 #define DCC_ADDRESSING_MODE_MASK (3 << 0) 1897 #define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1898 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1899 1900 /* Pineview MCH register contains DDR3 setting */ 1901 #define CSHRDDR3CTL 0x101a8 1902 #define CSHRDDR3CTL_DDR3 (1 << 2) 1903 1904 /* 965 MCH register controlling DRAM channel configuration */ 1905 #define C0DRB3 0x10206 1906 #define C1DRB3 0x10606 1907 1908 /* snb MCH registers for reading the DRAM channel configuration */ 1909 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 1910 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 1911 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 1912 #define MAD_DIMM_ECC_MASK (0x3 << 24) 1913 #define MAD_DIMM_ECC_OFF (0x0 << 24) 1914 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 1915 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 1916 #define MAD_DIMM_ECC_ON (0x3 << 24) 1917 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 1918 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 1919 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 1920 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 1921 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 1922 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 1923 #define MAD_DIMM_A_SELECT (0x1 << 16) 1924 /* DIMM sizes are in multiples of 256mb. */ 1925 #define MAD_DIMM_B_SIZE_SHIFT 8 1926 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 1927 #define MAD_DIMM_A_SIZE_SHIFT 0 1928 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 1929 1930 /* snb MCH registers for priority tuning */ 1931 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) 1932 #define MCH_SSKPD_WM0_MASK 0x3f 1933 #define MCH_SSKPD_WM0_VAL 0xc 1934 1935 #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) 1936 1937 /* Clocking configuration register */ 1938 #define CLKCFG 0x10c00 1939 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1940 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 1941 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 1942 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 1943 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 1944 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 1945 /* Note, below two are guess */ 1946 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 1947 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 1948 #define CLKCFG_FSB_MASK (7 << 0) 1949 #define CLKCFG_MEM_533 (1 << 4) 1950 #define CLKCFG_MEM_667 (2 << 4) 1951 #define CLKCFG_MEM_800 (3 << 4) 1952 #define CLKCFG_MEM_MASK (7 << 4) 1953 1954 #define TSC1 0x11001 1955 #define TSE (1<<0) 1956 #define TR1 0x11006 1957 #define TSFS 0x11020 1958 #define TSFS_SLOPE_MASK 0x0000ff00 1959 #define TSFS_SLOPE_SHIFT 8 1960 #define TSFS_INTR_MASK 0x000000ff 1961 1962 #define CRSTANDVID 0x11100 1963 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1964 #define PXVFREQ_PX_MASK 0x7f000000 1965 #define PXVFREQ_PX_SHIFT 24 1966 #define VIDFREQ_BASE 0x11110 1967 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1968 #define VIDFREQ2 0x11114 1969 #define VIDFREQ3 0x11118 1970 #define VIDFREQ4 0x1111c 1971 #define VIDFREQ_P0_MASK 0x1f000000 1972 #define VIDFREQ_P0_SHIFT 24 1973 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1974 #define VIDFREQ_P0_CSCLK_SHIFT 20 1975 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1976 #define VIDFREQ_P0_CRCLK_SHIFT 16 1977 #define VIDFREQ_P1_MASK 0x00001f00 1978 #define VIDFREQ_P1_SHIFT 8 1979 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1980 #define VIDFREQ_P1_CSCLK_SHIFT 4 1981 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1982 #define INTTOEXT_BASE_ILK 0x11300 1983 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 1984 #define INTTOEXT_MAP3_SHIFT 24 1985 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1986 #define INTTOEXT_MAP2_SHIFT 16 1987 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1988 #define INTTOEXT_MAP1_SHIFT 8 1989 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1990 #define INTTOEXT_MAP0_SHIFT 0 1991 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1992 #define MEMSWCTL 0x11170 /* Ironlake only */ 1993 #define MEMCTL_CMD_MASK 0xe000 1994 #define MEMCTL_CMD_SHIFT 13 1995 #define MEMCTL_CMD_RCLK_OFF 0 1996 #define MEMCTL_CMD_RCLK_ON 1 1997 #define MEMCTL_CMD_CHFREQ 2 1998 #define MEMCTL_CMD_CHVID 3 1999 #define MEMCTL_CMD_VMMOFF 4 2000 #define MEMCTL_CMD_VMMON 5 2001 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 2002 when command complete */ 2003 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 2004 #define MEMCTL_FREQ_SHIFT 8 2005 #define MEMCTL_SFCAVM (1<<7) 2006 #define MEMCTL_TGT_VID_MASK 0x007f 2007 #define MEMIHYST 0x1117c 2008 #define MEMINTREN 0x11180 /* 16 bits */ 2009 #define MEMINT_RSEXIT_EN (1<<8) 2010 #define MEMINT_CX_SUPR_EN (1<<7) 2011 #define MEMINT_CONT_BUSY_EN (1<<6) 2012 #define MEMINT_AVG_BUSY_EN (1<<5) 2013 #define MEMINT_EVAL_CHG_EN (1<<4) 2014 #define MEMINT_MON_IDLE_EN (1<<3) 2015 #define MEMINT_UP_EVAL_EN (1<<2) 2016 #define MEMINT_DOWN_EVAL_EN (1<<1) 2017 #define MEMINT_SW_CMD_EN (1<<0) 2018 #define MEMINTRSTR 0x11182 /* 16 bits */ 2019 #define MEM_RSEXIT_MASK 0xc000 2020 #define MEM_RSEXIT_SHIFT 14 2021 #define MEM_CONT_BUSY_MASK 0x3000 2022 #define MEM_CONT_BUSY_SHIFT 12 2023 #define MEM_AVG_BUSY_MASK 0x0c00 2024 #define MEM_AVG_BUSY_SHIFT 10 2025 #define MEM_EVAL_CHG_MASK 0x0300 2026 #define MEM_EVAL_BUSY_SHIFT 8 2027 #define MEM_MON_IDLE_MASK 0x00c0 2028 #define MEM_MON_IDLE_SHIFT 6 2029 #define MEM_UP_EVAL_MASK 0x0030 2030 #define MEM_UP_EVAL_SHIFT 4 2031 #define MEM_DOWN_EVAL_MASK 0x000c 2032 #define MEM_DOWN_EVAL_SHIFT 2 2033 #define MEM_SW_CMD_MASK 0x0003 2034 #define MEM_INT_STEER_GFX 0 2035 #define MEM_INT_STEER_CMR 1 2036 #define MEM_INT_STEER_SMI 2 2037 #define MEM_INT_STEER_SCI 3 2038 #define MEMINTRSTS 0x11184 2039 #define MEMINT_RSEXIT (1<<7) 2040 #define MEMINT_CONT_BUSY (1<<6) 2041 #define MEMINT_AVG_BUSY (1<<5) 2042 #define MEMINT_EVAL_CHG (1<<4) 2043 #define MEMINT_MON_IDLE (1<<3) 2044 #define MEMINT_UP_EVAL (1<<2) 2045 #define MEMINT_DOWN_EVAL (1<<1) 2046 #define MEMINT_SW_CMD (1<<0) 2047 #define MEMMODECTL 0x11190 2048 #define MEMMODE_BOOST_EN (1<<31) 2049 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 2050 #define MEMMODE_BOOST_FREQ_SHIFT 24 2051 #define MEMMODE_IDLE_MODE_MASK 0x00030000 2052 #define MEMMODE_IDLE_MODE_SHIFT 16 2053 #define MEMMODE_IDLE_MODE_EVAL 0 2054 #define MEMMODE_IDLE_MODE_CONT 1 2055 #define MEMMODE_HWIDLE_EN (1<<15) 2056 #define MEMMODE_SWMODE_EN (1<<14) 2057 #define MEMMODE_RCLK_GATE (1<<13) 2058 #define MEMMODE_HW_UPDATE (1<<12) 2059 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 2060 #define MEMMODE_FSTART_SHIFT 8 2061 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 2062 #define MEMMODE_FMAX_SHIFT 4 2063 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 2064 #define RCBMAXAVG 0x1119c 2065 #define MEMSWCTL2 0x1119e /* Cantiga only */ 2066 #define SWMEMCMD_RENDER_OFF (0 << 13) 2067 #define SWMEMCMD_RENDER_ON (1 << 13) 2068 #define SWMEMCMD_SWFREQ (2 << 13) 2069 #define SWMEMCMD_TARVID (3 << 13) 2070 #define SWMEMCMD_VRM_OFF (4 << 13) 2071 #define SWMEMCMD_VRM_ON (5 << 13) 2072 #define CMDSTS (1<<12) 2073 #define SFCAVM (1<<11) 2074 #define SWFREQ_MASK 0x0380 /* P0-7 */ 2075 #define SWFREQ_SHIFT 7 2076 #define TARVID_MASK 0x001f 2077 #define MEMSTAT_CTG 0x111a0 2078 #define RCBMINAVG 0x111a0 2079 #define RCUPEI 0x111b0 2080 #define RCDNEI 0x111b4 2081 #define RSTDBYCTL 0x111b8 2082 #define RS1EN (1<<31) 2083 #define RS2EN (1<<30) 2084 #define RS3EN (1<<29) 2085 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 2086 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 2087 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 2088 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 2089 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 2090 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 2091 #define RSX_STATUS_MASK (7<<20) 2092 #define RSX_STATUS_ON (0<<20) 2093 #define RSX_STATUS_RC1 (1<<20) 2094 #define RSX_STATUS_RC1E (2<<20) 2095 #define RSX_STATUS_RS1 (3<<20) 2096 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 2097 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 2098 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 2099 #define RSX_STATUS_RSVD2 (7<<20) 2100 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 2101 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 2102 #define JRSC (1<<17) /* rsx coupled to cpu c-state */ 2103 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 2104 #define RS1CONTSAV_MASK (3<<14) 2105 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 2106 #define RS1CONTSAV_RSVD (1<<14) 2107 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 2108 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 2109 #define NORMSLEXLAT_MASK (3<<12) 2110 #define SLOW_RS123 (0<<12) 2111 #define SLOW_RS23 (1<<12) 2112 #define SLOW_RS3 (2<<12) 2113 #define NORMAL_RS123 (3<<12) 2114 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 2115 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 2116 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 2117 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 2118 #define RS_CSTATE_MASK (3<<4) 2119 #define RS_CSTATE_C367_RS1 (0<<4) 2120 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 2121 #define RS_CSTATE_RSVD (2<<4) 2122 #define RS_CSTATE_C367_RS2 (3<<4) 2123 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 2124 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 2125 #define VIDCTL 0x111c0 2126 #define VIDSTS 0x111c8 2127 #define VIDSTART 0x111cc /* 8 bits */ 2128 #define MEMSTAT_ILK 0x111f8 2129 #define MEMSTAT_VID_MASK 0x7f00 2130 #define MEMSTAT_VID_SHIFT 8 2131 #define MEMSTAT_PSTATE_MASK 0x00f8 2132 #define MEMSTAT_PSTATE_SHIFT 3 2133 #define MEMSTAT_MON_ACTV (1<<2) 2134 #define MEMSTAT_SRC_CTL_MASK 0x0003 2135 #define MEMSTAT_SRC_CTL_CORE 0 2136 #define MEMSTAT_SRC_CTL_TRB 1 2137 #define MEMSTAT_SRC_CTL_THM 2 2138 #define MEMSTAT_SRC_CTL_STDBY 3 2139 #define RCPREVBSYTUPAVG 0x113b8 2140 #define RCPREVBSYTDNAVG 0x113bc 2141 #define PMMISC 0x11214 2142 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 2143 #define SDEW 0x1124c 2144 #define CSIEW0 0x11250 2145 #define CSIEW1 0x11254 2146 #define CSIEW2 0x11258 2147 #define PEW 0x1125c 2148 #define DEW 0x11270 2149 #define MCHAFE 0x112c0 2150 #define CSIEC 0x112e0 2151 #define DMIEC 0x112e4 2152 #define DDREC 0x112e8 2153 #define PEG0EC 0x112ec 2154 #define PEG1EC 0x112f0 2155 #define GFXEC 0x112f4 2156 #define RPPREVBSYTUPAVG 0x113b8 2157 #define RPPREVBSYTDNAVG 0x113bc 2158 #define ECR 0x11600 2159 #define ECR_GPFE (1<<31) 2160 #define ECR_IMONE (1<<30) 2161 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 2162 #define OGW0 0x11608 2163 #define OGW1 0x1160c 2164 #define EG0 0x11610 2165 #define EG1 0x11614 2166 #define EG2 0x11618 2167 #define EG3 0x1161c 2168 #define EG4 0x11620 2169 #define EG5 0x11624 2170 #define EG6 0x11628 2171 #define EG7 0x1162c 2172 #define PXW 0x11664 2173 #define PXWL 0x11680 2174 #define LCFUSE02 0x116c0 2175 #define LCFUSE_HIV_MASK 0x000000ff 2176 #define CSIPLL0 0x12c10 2177 #define DDRMPLL1 0X12c20 2178 #define PEG_BAND_GAP_DATA 0x14d68 2179 2180 #define GEN6_GT_THREAD_STATUS_REG 0x13805c 2181 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 2182 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) 2183 2184 #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) 2185 #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) 2186 #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) 2187 2188 /* 2189 * Logical Context regs 2190 */ 2191 #define CCID 0x2180 2192 #define CCID_EN (1<<0) 2193 /* 2194 * Notes on SNB/IVB/VLV context size: 2195 * - Power context is saved elsewhere (LLC or stolen) 2196 * - Ring/execlist context is saved on SNB, not on IVB 2197 * - Extended context size already includes render context size 2198 * - We always need to follow the extended context size. 2199 * SNB BSpec has comments indicating that we should use the 2200 * render context size instead if execlists are disabled, but 2201 * based on empirical testing that's just nonsense. 2202 * - Pipelined/VF state is saved on SNB/IVB respectively 2203 * - GT1 size just indicates how much of render context 2204 * doesn't need saving on GT1 2205 */ 2206 #define CXT_SIZE 0x21a0 2207 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) 2208 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) 2209 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) 2210 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) 2211 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) 2212 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 2213 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 2214 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 2215 #define GEN7_CXT_SIZE 0x21a8 2216 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) 2217 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) 2218 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) 2219 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) 2220 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) 2221 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) 2222 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 2223 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 2224 /* Haswell does have the CXT_SIZE register however it does not appear to be 2225 * valid. Now, docs explain in dwords what is in the context object. The full 2226 * size is 70720 bytes, however, the power context and execlist context will 2227 * never be saved (power context is stored elsewhere, and execlists don't work 2228 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. 2229 */ 2230 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 2231 /* Same as Haswell, but 72064 bytes now. */ 2232 #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) 2233 2234 2235 #define VLV_CLK_CTL2 0x101104 2236 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 2237 2238 /* 2239 * Overlay regs 2240 */ 2241 2242 #define OVADD 0x30000 2243 #define DOVSTA 0x30008 2244 #define OC_BUF (0x3<<20) 2245 #define OGAMC5 0x30010 2246 #define OGAMC4 0x30014 2247 #define OGAMC3 0x30018 2248 #define OGAMC2 0x3001c 2249 #define OGAMC1 0x30020 2250 #define OGAMC0 0x30024 2251 2252 /* 2253 * Display engine regs 2254 */ 2255 2256 /* Pipe A CRC regs */ 2257 #define _PIPE_CRC_CTL_A 0x60050 2258 #define PIPE_CRC_ENABLE (1 << 31) 2259 /* ivb+ source selection */ 2260 #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 2261 #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 2262 #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 2263 /* ilk+ source selection */ 2264 #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 2265 #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 2266 #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 2267 /* embedded DP port on the north display block, reserved on ivb */ 2268 #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 2269 #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 2270 /* vlv source selection */ 2271 #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 2272 #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 2273 #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 2274 /* with DP port the pipe source is invalid */ 2275 #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 2276 #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 2277 #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 2278 /* gen3+ source selection */ 2279 #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 2280 #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 2281 #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 2282 /* with DP/TV port the pipe source is invalid */ 2283 #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 2284 #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 2285 #define PIPE_CRC_SOURCE_TV_POST (5 << 28) 2286 #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 2287 #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 2288 /* gen2 doesn't have source selection bits */ 2289 #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 2290 2291 #define _PIPE_CRC_RES_1_A_IVB 0x60064 2292 #define _PIPE_CRC_RES_2_A_IVB 0x60068 2293 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 2294 #define _PIPE_CRC_RES_4_A_IVB 0x60070 2295 #define _PIPE_CRC_RES_5_A_IVB 0x60074 2296 2297 #define _PIPE_CRC_RES_RED_A 0x60060 2298 #define _PIPE_CRC_RES_GREEN_A 0x60064 2299 #define _PIPE_CRC_RES_BLUE_A 0x60068 2300 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 2301 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 2302 2303 /* Pipe B CRC regs */ 2304 #define _PIPE_CRC_RES_1_B_IVB 0x61064 2305 #define _PIPE_CRC_RES_2_B_IVB 0x61068 2306 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 2307 #define _PIPE_CRC_RES_4_B_IVB 0x61070 2308 #define _PIPE_CRC_RES_5_B_IVB 0x61074 2309 2310 #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) 2311 #define PIPE_CRC_RES_1_IVB(pipe) \ 2312 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) 2313 #define PIPE_CRC_RES_2_IVB(pipe) \ 2314 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) 2315 #define PIPE_CRC_RES_3_IVB(pipe) \ 2316 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) 2317 #define PIPE_CRC_RES_4_IVB(pipe) \ 2318 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) 2319 #define PIPE_CRC_RES_5_IVB(pipe) \ 2320 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) 2321 2322 #define PIPE_CRC_RES_RED(pipe) \ 2323 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) 2324 #define PIPE_CRC_RES_GREEN(pipe) \ 2325 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) 2326 #define PIPE_CRC_RES_BLUE(pipe) \ 2327 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) 2328 #define PIPE_CRC_RES_RES1_I915(pipe) \ 2329 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) 2330 #define PIPE_CRC_RES_RES2_G4X(pipe) \ 2331 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 2332 2333 /* Pipe A timing regs */ 2334 #define _HTOTAL_A 0x60000 2335 #define _HBLANK_A 0x60004 2336 #define _HSYNC_A 0x60008 2337 #define _VTOTAL_A 0x6000c 2338 #define _VBLANK_A 0x60010 2339 #define _VSYNC_A 0x60014 2340 #define _PIPEASRC 0x6001c 2341 #define _BCLRPAT_A 0x60020 2342 #define _VSYNCSHIFT_A 0x60028 2343 2344 /* Pipe B timing regs */ 2345 #define _HTOTAL_B 0x61000 2346 #define _HBLANK_B 0x61004 2347 #define _HSYNC_B 0x61008 2348 #define _VTOTAL_B 0x6100c 2349 #define _VBLANK_B 0x61010 2350 #define _VSYNC_B 0x61014 2351 #define _PIPEBSRC 0x6101c 2352 #define _BCLRPAT_B 0x61020 2353 #define _VSYNCSHIFT_B 0x61028 2354 2355 #define TRANSCODER_A_OFFSET 0x60000 2356 #define TRANSCODER_B_OFFSET 0x61000 2357 #define TRANSCODER_C_OFFSET 0x62000 2358 #define CHV_TRANSCODER_C_OFFSET 0x63000 2359 #define TRANSCODER_EDP_OFFSET 0x6f000 2360 2361 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ 2362 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 2363 dev_priv->info.display_mmio_offset) 2364 2365 #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) 2366 #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) 2367 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) 2368 #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) 2369 #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) 2370 #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) 2371 #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) 2372 #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) 2373 #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) 2374 2375 /* HSW+ eDP PSR registers */ 2376 #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) 2377 #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) 2378 #define EDP_PSR_ENABLE (1<<31) 2379 #define EDP_PSR_LINK_DISABLE (0<<27) 2380 #define EDP_PSR_LINK_STANDBY (1<<27) 2381 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 2382 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 2383 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 2384 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 2385 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 2386 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2387 #define EDP_PSR_SKIP_AUX_EXIT (1<<12) 2388 #define EDP_PSR_TP1_TP2_SEL (0<<11) 2389 #define EDP_PSR_TP1_TP3_SEL (1<<11) 2390 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 2391 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 2392 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 2393 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 2394 #define EDP_PSR_TP1_TIME_500us (0<<4) 2395 #define EDP_PSR_TP1_TIME_100us (1<<4) 2396 #define EDP_PSR_TP1_TIME_2500us (2<<4) 2397 #define EDP_PSR_TP1_TIME_0us (3<<4) 2398 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2399 2400 #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) 2401 #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) 2402 #define EDP_PSR_DPCD_COMMAND 0x80060000 2403 #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) 2404 #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24) 2405 #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) 2406 #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) 2407 #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) 2408 2409 #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) 2410 #define EDP_PSR_STATUS_STATE_MASK (7<<29) 2411 #define EDP_PSR_STATUS_STATE_IDLE (0<<29) 2412 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 2413 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 2414 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 2415 #define EDP_PSR_STATUS_STATE_BUFON (4<<29) 2416 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 2417 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 2418 #define EDP_PSR_STATUS_LINK_MASK (3<<26) 2419 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 2420 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 2421 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 2422 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2423 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2424 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2425 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2426 #define EDP_PSR_STATUS_AUX_ERROR (1<<15) 2427 #define EDP_PSR_STATUS_AUX_SENDING (1<<12) 2428 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 2429 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 2430 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 2431 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2432 2433 #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) 2434 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2435 2436 #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) 2437 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 2438 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 2439 #define EDP_PSR_DEBUG_MASK_HPD (1<<25) 2440 2441 /* VGA port control */ 2442 #define ADPA 0x61100 2443 #define PCH_ADPA 0xe1100 2444 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) 2445 2446 #define ADPA_DAC_ENABLE (1<<31) 2447 #define ADPA_DAC_DISABLE 0 2448 #define ADPA_PIPE_SELECT_MASK (1<<30) 2449 #define ADPA_PIPE_A_SELECT 0 2450 #define ADPA_PIPE_B_SELECT (1<<30) 2451 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 2452 /* CPT uses bits 29:30 for pch transcoder select */ 2453 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2454 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 2455 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 2456 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 2457 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 2458 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 2459 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 2460 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 2461 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 2462 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 2463 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 2464 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 2465 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 2466 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 2467 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 2468 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 2469 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 2470 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 2471 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 2472 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 2473 #define ADPA_SETS_HVPOLARITY 0 2474 #define ADPA_VSYNC_CNTL_DISABLE (1<<10) 2475 #define ADPA_VSYNC_CNTL_ENABLE 0 2476 #define ADPA_HSYNC_CNTL_DISABLE (1<<11) 2477 #define ADPA_HSYNC_CNTL_ENABLE 0 2478 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 2479 #define ADPA_VSYNC_ACTIVE_LOW 0 2480 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 2481 #define ADPA_HSYNC_ACTIVE_LOW 0 2482 #define ADPA_DPMS_MASK (~(3<<10)) 2483 #define ADPA_DPMS_ON (0<<10) 2484 #define ADPA_DPMS_SUSPEND (1<<10) 2485 #define ADPA_DPMS_STANDBY (2<<10) 2486 #define ADPA_DPMS_OFF (3<<10) 2487 2488 2489 /* Hotplug control (945+ only) */ 2490 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) 2491 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2492 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2493 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2494 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2495 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2496 #define TV_HOTPLUG_INT_EN (1 << 18) 2497 #define CRT_HOTPLUG_INT_EN (1 << 9) 2498 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2499 PORTC_HOTPLUG_INT_EN | \ 2500 PORTD_HOTPLUG_INT_EN | \ 2501 SDVOC_HOTPLUG_INT_EN | \ 2502 SDVOB_HOTPLUG_INT_EN | \ 2503 CRT_HOTPLUG_INT_EN) 2504 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2505 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2506 /* must use period 64 on GM45 according to docs */ 2507 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2508 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2509 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2510 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2511 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2512 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2513 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2514 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2515 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2516 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2517 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2518 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2519 2520 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) 2521 /* 2522 * HDMI/DP bits are gen4+ 2523 * 2524 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2525 * Please check the detailed lore in the commit message for for experimental 2526 * evidence. 2527 */ 2528 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2529 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2530 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2531 /* VLV DP/HDMI bits again match Bspec */ 2532 #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) 2533 #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) 2534 #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) 2535 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2536 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2537 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2538 /* CRT/TV common between gen3+ */ 2539 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2540 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2541 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2542 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2543 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2544 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2545 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2546 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2547 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2548 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2549 2550 /* SDVO is different across gen3/4 */ 2551 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2552 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2553 /* 2554 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2555 * since reality corrobates that they're the same as on gen3. But keep these 2556 * bits here (and the comment!) to help any other lost wanderers back onto the 2557 * right tracks. 2558 */ 2559 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2560 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2561 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2562 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2563 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2564 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2565 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2566 PORTB_HOTPLUG_INT_STATUS | \ 2567 PORTC_HOTPLUG_INT_STATUS | \ 2568 PORTD_HOTPLUG_INT_STATUS) 2569 2570 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2571 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2572 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2573 PORTB_HOTPLUG_INT_STATUS | \ 2574 PORTC_HOTPLUG_INT_STATUS | \ 2575 PORTD_HOTPLUG_INT_STATUS) 2576 2577 /* SDVO and HDMI port control. 2578 * The same register may be used for SDVO or HDMI */ 2579 #define GEN3_SDVOB 0x61140 2580 #define GEN3_SDVOC 0x61160 2581 #define GEN4_HDMIB GEN3_SDVOB 2582 #define GEN4_HDMIC GEN3_SDVOC 2583 #define CHV_HDMID 0x6116C 2584 #define PCH_SDVOB 0xe1140 2585 #define PCH_HDMIB PCH_SDVOB 2586 #define PCH_HDMIC 0xe1150 2587 #define PCH_HDMID 0xe1160 2588 2589 #define PORT_DFT_I9XX 0x61150 2590 #define DC_BALANCE_RESET (1 << 25) 2591 #define PORT_DFT2_G4X 0x61154 2592 #define DC_BALANCE_RESET_VLV (1 << 31) 2593 #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) 2594 #define PIPE_B_SCRAMBLE_RESET (1 << 1) 2595 #define PIPE_A_SCRAMBLE_RESET (1 << 0) 2596 2597 /* Gen 3 SDVO bits: */ 2598 #define SDVO_ENABLE (1 << 31) 2599 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2600 #define SDVO_PIPE_SEL_MASK (1 << 30) 2601 #define SDVO_PIPE_B_SELECT (1 << 30) 2602 #define SDVO_STALL_SELECT (1 << 29) 2603 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2604 /* 2605 * 915G/GM SDVO pixel multiplier. 2606 * Programmed value is multiplier - 1, up to 5x. 2607 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2608 */ 2609 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2610 #define SDVO_PORT_MULTIPLY_SHIFT 23 2611 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2612 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2613 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2614 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2615 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2616 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2617 #define SDVO_DETECTED (1 << 2) 2618 /* Bits to be preserved when writing */ 2619 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2620 SDVO_INTERRUPT_ENABLE) 2621 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2622 2623 /* Gen 4 SDVO/HDMI bits: */ 2624 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2625 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2626 #define SDVO_ENCODING_SDVO (0 << 10) 2627 #define SDVO_ENCODING_HDMI (2 << 10) 2628 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2629 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2630 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2631 #define SDVO_AUDIO_ENABLE (1 << 6) 2632 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2633 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2634 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2635 2636 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2637 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2638 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2639 2640 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2641 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2642 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2643 2644 /* CHV SDVO/HDMI bits: */ 2645 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2646 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2647 2648 2649 /* DVO port control */ 2650 #define DVOA 0x61120 2651 #define DVOB 0x61140 2652 #define DVOC 0x61160 2653 #define DVO_ENABLE (1 << 31) 2654 #define DVO_PIPE_B_SELECT (1 << 30) 2655 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2656 #define DVO_PIPE_STALL (1 << 28) 2657 #define DVO_PIPE_STALL_TV (2 << 28) 2658 #define DVO_PIPE_STALL_MASK (3 << 28) 2659 #define DVO_USE_VGA_SYNC (1 << 15) 2660 #define DVO_DATA_ORDER_I740 (0 << 14) 2661 #define DVO_DATA_ORDER_FP (1 << 14) 2662 #define DVO_VSYNC_DISABLE (1 << 11) 2663 #define DVO_HSYNC_DISABLE (1 << 10) 2664 #define DVO_VSYNC_TRISTATE (1 << 9) 2665 #define DVO_HSYNC_TRISTATE (1 << 8) 2666 #define DVO_BORDER_ENABLE (1 << 7) 2667 #define DVO_DATA_ORDER_GBRG (1 << 6) 2668 #define DVO_DATA_ORDER_RGGB (0 << 6) 2669 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2670 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2671 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2672 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2673 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2674 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2675 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2676 #define DVO_PRESERVE_MASK (0x7<<24) 2677 #define DVOA_SRCDIM 0x61124 2678 #define DVOB_SRCDIM 0x61144 2679 #define DVOC_SRCDIM 0x61164 2680 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2681 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2682 2683 /* LVDS port control */ 2684 #define LVDS 0x61180 2685 /* 2686 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2687 * the DPLL semantics change when the LVDS is assigned to that pipe. 2688 */ 2689 #define LVDS_PORT_EN (1 << 31) 2690 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2691 #define LVDS_PIPEB_SELECT (1 << 30) 2692 #define LVDS_PIPE_MASK (1 << 30) 2693 #define LVDS_PIPE(pipe) ((pipe) << 30) 2694 /* LVDS dithering flag on 965/g4x platform */ 2695 #define LVDS_ENABLE_DITHER (1 << 25) 2696 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2697 #define LVDS_VSYNC_POLARITY (1 << 21) 2698 #define LVDS_HSYNC_POLARITY (1 << 20) 2699 2700 /* Enable border for unscaled (or aspect-scaled) display */ 2701 #define LVDS_BORDER_ENABLE (1 << 15) 2702 /* 2703 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2704 * pixel. 2705 */ 2706 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2707 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2708 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2709 /* 2710 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2711 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2712 * on. 2713 */ 2714 #define LVDS_A3_POWER_MASK (3 << 6) 2715 #define LVDS_A3_POWER_DOWN (0 << 6) 2716 #define LVDS_A3_POWER_UP (3 << 6) 2717 /* 2718 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2719 * is set. 2720 */ 2721 #define LVDS_CLKB_POWER_MASK (3 << 4) 2722 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2723 #define LVDS_CLKB_POWER_UP (3 << 4) 2724 /* 2725 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2726 * setting for whether we are in dual-channel mode. The B3 pair will 2727 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2728 */ 2729 #define LVDS_B0B3_POWER_MASK (3 << 2) 2730 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2731 #define LVDS_B0B3_POWER_UP (3 << 2) 2732 2733 /* Video Data Island Packet control */ 2734 #define VIDEO_DIP_DATA 0x61178 2735 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC 2736 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2737 * of the infoframe structure specified by CEA-861. */ 2738 #define VIDEO_DIP_DATA_SIZE 32 2739 #define VIDEO_DIP_VSC_DATA_SIZE 36 2740 #define VIDEO_DIP_CTL 0x61170 2741 /* Pre HSW: */ 2742 #define VIDEO_DIP_ENABLE (1 << 31) 2743 #define VIDEO_DIP_PORT(port) ((port) << 29) 2744 #define VIDEO_DIP_PORT_MASK (3 << 29) 2745 #define VIDEO_DIP_ENABLE_GCP (1 << 25) 2746 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2747 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2748 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 2749 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2750 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2751 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2752 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2753 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2754 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2755 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2756 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2757 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2758 /* HSW and later: */ 2759 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2760 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2761 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2762 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2763 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2764 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2765 2766 /* Panel power sequencing */ 2767 #define PP_STATUS 0x61200 2768 #define PP_ON (1 << 31) 2769 /* 2770 * Indicates that all dependencies of the panel are on: 2771 * 2772 * - PLL enabled 2773 * - pipe enabled 2774 * - LVDS/DVOB/DVOC on 2775 */ 2776 #define PP_READY (1 << 30) 2777 #define PP_SEQUENCE_NONE (0 << 28) 2778 #define PP_SEQUENCE_POWER_UP (1 << 28) 2779 #define PP_SEQUENCE_POWER_DOWN (2 << 28) 2780 #define PP_SEQUENCE_MASK (3 << 28) 2781 #define PP_SEQUENCE_SHIFT 28 2782 #define PP_CYCLE_DELAY_ACTIVE (1 << 27) 2783 #define PP_SEQUENCE_STATE_MASK 0x0000000f 2784 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 2785 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 2786 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 2787 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 2788 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 2789 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 2790 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 2791 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 2792 #define PP_SEQUENCE_STATE_RESET (0xf << 0) 2793 #define PP_CONTROL 0x61204 2794 #define POWER_TARGET_ON (1 << 0) 2795 #define PP_ON_DELAYS 0x61208 2796 #define PP_OFF_DELAYS 0x6120c 2797 #define PP_DIVISOR 0x61210 2798 2799 /* Panel fitting */ 2800 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) 2801 #define PFIT_ENABLE (1 << 31) 2802 #define PFIT_PIPE_MASK (3 << 29) 2803 #define PFIT_PIPE_SHIFT 29 2804 #define VERT_INTERP_DISABLE (0 << 10) 2805 #define VERT_INTERP_BILINEAR (1 << 10) 2806 #define VERT_INTERP_MASK (3 << 10) 2807 #define VERT_AUTO_SCALE (1 << 9) 2808 #define HORIZ_INTERP_DISABLE (0 << 6) 2809 #define HORIZ_INTERP_BILINEAR (1 << 6) 2810 #define HORIZ_INTERP_MASK (3 << 6) 2811 #define HORIZ_AUTO_SCALE (1 << 5) 2812 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2813 #define PFIT_FILTER_FUZZY (0 << 24) 2814 #define PFIT_SCALING_AUTO (0 << 26) 2815 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2816 #define PFIT_SCALING_PILLAR (2 << 26) 2817 #define PFIT_SCALING_LETTER (3 << 26) 2818 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) 2819 /* Pre-965 */ 2820 #define PFIT_VERT_SCALE_SHIFT 20 2821 #define PFIT_VERT_SCALE_MASK 0xfff00000 2822 #define PFIT_HORIZ_SCALE_SHIFT 4 2823 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2824 /* 965+ */ 2825 #define PFIT_VERT_SCALE_SHIFT_965 16 2826 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2827 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2828 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2829 2830 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) 2831 2832 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 2833 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 2834 #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 2835 _VLV_BLC_PWM_CTL2_B) 2836 2837 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 2838 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 2839 #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 2840 _VLV_BLC_PWM_CTL_B) 2841 2842 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 2843 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 2844 #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 2845 _VLV_BLC_HIST_CTL_B) 2846 2847 /* Backlight control */ 2848 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 2849 #define BLM_PWM_ENABLE (1 << 31) 2850 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 2851 #define BLM_PIPE_SELECT (1 << 29) 2852 #define BLM_PIPE_SELECT_IVB (3 << 29) 2853 #define BLM_PIPE_A (0 << 29) 2854 #define BLM_PIPE_B (1 << 29) 2855 #define BLM_PIPE_C (2 << 29) /* ivb + */ 2856 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 2857 #define BLM_TRANSCODER_B BLM_PIPE_B 2858 #define BLM_TRANSCODER_C BLM_PIPE_C 2859 #define BLM_TRANSCODER_EDP (3 << 29) 2860 #define BLM_PIPE(pipe) ((pipe) << 29) 2861 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 2862 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 2863 #define BLM_PHASE_IN_ENABLE (1 << 25) 2864 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 2865 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 2866 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 2867 #define BLM_PHASE_IN_COUNT_SHIFT (8) 2868 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 2869 #define BLM_PHASE_IN_INCR_SHIFT (0) 2870 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 2871 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) 2872 /* 2873 * This is the most significant 15 bits of the number of backlight cycles in a 2874 * complete cycle of the modulated backlight control. 2875 * 2876 * The actual value is this field multiplied by two. 2877 */ 2878 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 2879 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 2880 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 2881 /* 2882 * This is the number of cycles out of the backlight modulation cycle for which 2883 * the backlight is on. 2884 * 2885 * This field must be no greater than the number of cycles in the complete 2886 * backlight modulation cycle. 2887 */ 2888 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 2889 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 2890 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 2891 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 2892 2893 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) 2894 2895 /* New registers for PCH-split platforms. Safe where new bits show up, the 2896 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 2897 #define BLC_PWM_CPU_CTL2 0x48250 2898 #define BLC_PWM_CPU_CTL 0x48254 2899 2900 #define HSW_BLC_PWM2_CTL 0x48350 2901 2902 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 2903 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 2904 #define BLC_PWM_PCH_CTL1 0xc8250 2905 #define BLM_PCH_PWM_ENABLE (1 << 31) 2906 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 2907 #define BLM_PCH_POLARITY (1 << 29) 2908 #define BLC_PWM_PCH_CTL2 0xc8254 2909 2910 #define UTIL_PIN_CTL 0x48400 2911 #define UTIL_PIN_ENABLE (1 << 31) 2912 2913 #define PCH_GTC_CTL 0xe7000 2914 #define PCH_GTC_ENABLE (1 << 31) 2915 2916 /* TV port control */ 2917 #define TV_CTL 0x68000 2918 /* Enables the TV encoder */ 2919 # define TV_ENC_ENABLE (1 << 31) 2920 /* Sources the TV encoder input from pipe B instead of A. */ 2921 # define TV_ENC_PIPEB_SELECT (1 << 30) 2922 /* Outputs composite video (DAC A only) */ 2923 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 2924 /* Outputs SVideo video (DAC B/C) */ 2925 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 2926 /* Outputs Component video (DAC A/B/C) */ 2927 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 2928 /* Outputs Composite and SVideo (DAC A/B/C) */ 2929 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 2930 # define TV_TRILEVEL_SYNC (1 << 21) 2931 /* Enables slow sync generation (945GM only) */ 2932 # define TV_SLOW_SYNC (1 << 20) 2933 /* Selects 4x oversampling for 480i and 576p */ 2934 # define TV_OVERSAMPLE_4X (0 << 18) 2935 /* Selects 2x oversampling for 720p and 1080i */ 2936 # define TV_OVERSAMPLE_2X (1 << 18) 2937 /* Selects no oversampling for 1080p */ 2938 # define TV_OVERSAMPLE_NONE (2 << 18) 2939 /* Selects 8x oversampling */ 2940 # define TV_OVERSAMPLE_8X (3 << 18) 2941 /* Selects progressive mode rather than interlaced */ 2942 # define TV_PROGRESSIVE (1 << 17) 2943 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 2944 # define TV_PAL_BURST (1 << 16) 2945 /* Field for setting delay of Y compared to C */ 2946 # define TV_YC_SKEW_MASK (7 << 12) 2947 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 2948 # define TV_ENC_SDP_FIX (1 << 11) 2949 /* 2950 * Enables a fix for the 915GM only. 2951 * 2952 * Not sure what it does. 2953 */ 2954 # define TV_ENC_C0_FIX (1 << 10) 2955 /* Bits that must be preserved by software */ 2956 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 2957 # define TV_FUSE_STATE_MASK (3 << 4) 2958 /* Read-only state that reports all features enabled */ 2959 # define TV_FUSE_STATE_ENABLED (0 << 4) 2960 /* Read-only state that reports that Macrovision is disabled in hardware*/ 2961 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 2962 /* Read-only state that reports that TV-out is disabled in hardware. */ 2963 # define TV_FUSE_STATE_DISABLED (2 << 4) 2964 /* Normal operation */ 2965 # define TV_TEST_MODE_NORMAL (0 << 0) 2966 /* Encoder test pattern 1 - combo pattern */ 2967 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 2968 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 2969 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 2970 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 2971 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 2972 /* Encoder test pattern 4 - random noise */ 2973 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 2974 /* Encoder test pattern 5 - linear color ramps */ 2975 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 2976 /* 2977 * This test mode forces the DACs to 50% of full output. 2978 * 2979 * This is used for load detection in combination with TVDAC_SENSE_MASK 2980 */ 2981 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 2982 # define TV_TEST_MODE_MASK (7 << 0) 2983 2984 #define TV_DAC 0x68004 2985 # define TV_DAC_SAVE 0x00ffff00 2986 /* 2987 * Reports that DAC state change logic has reported change (RO). 2988 * 2989 * This gets cleared when TV_DAC_STATE_EN is cleared 2990 */ 2991 # define TVDAC_STATE_CHG (1 << 31) 2992 # define TVDAC_SENSE_MASK (7 << 28) 2993 /* Reports that DAC A voltage is above the detect threshold */ 2994 # define TVDAC_A_SENSE (1 << 30) 2995 /* Reports that DAC B voltage is above the detect threshold */ 2996 # define TVDAC_B_SENSE (1 << 29) 2997 /* Reports that DAC C voltage is above the detect threshold */ 2998 # define TVDAC_C_SENSE (1 << 28) 2999 /* 3000 * Enables DAC state detection logic, for load-based TV detection. 3001 * 3002 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3003 * to off, for load detection to work. 3004 */ 3005 # define TVDAC_STATE_CHG_EN (1 << 27) 3006 /* Sets the DAC A sense value to high */ 3007 # define TVDAC_A_SENSE_CTL (1 << 26) 3008 /* Sets the DAC B sense value to high */ 3009 # define TVDAC_B_SENSE_CTL (1 << 25) 3010 /* Sets the DAC C sense value to high */ 3011 # define TVDAC_C_SENSE_CTL (1 << 24) 3012 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3013 # define DAC_CTL_OVERRIDE (1 << 7) 3014 /* Sets the slew rate. Must be preserved in software */ 3015 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3016 # define DAC_A_1_3_V (0 << 4) 3017 # define DAC_A_1_1_V (1 << 4) 3018 # define DAC_A_0_7_V (2 << 4) 3019 # define DAC_A_MASK (3 << 4) 3020 # define DAC_B_1_3_V (0 << 2) 3021 # define DAC_B_1_1_V (1 << 2) 3022 # define DAC_B_0_7_V (2 << 2) 3023 # define DAC_B_MASK (3 << 2) 3024 # define DAC_C_1_3_V (0 << 0) 3025 # define DAC_C_1_1_V (1 << 0) 3026 # define DAC_C_0_7_V (2 << 0) 3027 # define DAC_C_MASK (3 << 0) 3028 3029 /* 3030 * CSC coefficients are stored in a floating point format with 9 bits of 3031 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3032 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3033 * -1 (0x3) being the only legal negative value. 3034 */ 3035 #define TV_CSC_Y 0x68010 3036 # define TV_RY_MASK 0x07ff0000 3037 # define TV_RY_SHIFT 16 3038 # define TV_GY_MASK 0x00000fff 3039 # define TV_GY_SHIFT 0 3040 3041 #define TV_CSC_Y2 0x68014 3042 # define TV_BY_MASK 0x07ff0000 3043 # define TV_BY_SHIFT 16 3044 /* 3045 * Y attenuation for component video. 3046 * 3047 * Stored in 1.9 fixed point. 3048 */ 3049 # define TV_AY_MASK 0x000003ff 3050 # define TV_AY_SHIFT 0 3051 3052 #define TV_CSC_U 0x68018 3053 # define TV_RU_MASK 0x07ff0000 3054 # define TV_RU_SHIFT 16 3055 # define TV_GU_MASK 0x000007ff 3056 # define TV_GU_SHIFT 0 3057 3058 #define TV_CSC_U2 0x6801c 3059 # define TV_BU_MASK 0x07ff0000 3060 # define TV_BU_SHIFT 16 3061 /* 3062 * U attenuation for component video. 3063 * 3064 * Stored in 1.9 fixed point. 3065 */ 3066 # define TV_AU_MASK 0x000003ff 3067 # define TV_AU_SHIFT 0 3068 3069 #define TV_CSC_V 0x68020 3070 # define TV_RV_MASK 0x0fff0000 3071 # define TV_RV_SHIFT 16 3072 # define TV_GV_MASK 0x000007ff 3073 # define TV_GV_SHIFT 0 3074 3075 #define TV_CSC_V2 0x68024 3076 # define TV_BV_MASK 0x07ff0000 3077 # define TV_BV_SHIFT 16 3078 /* 3079 * V attenuation for component video. 3080 * 3081 * Stored in 1.9 fixed point. 3082 */ 3083 # define TV_AV_MASK 0x000007ff 3084 # define TV_AV_SHIFT 0 3085 3086 #define TV_CLR_KNOBS 0x68028 3087 /* 2s-complement brightness adjustment */ 3088 # define TV_BRIGHTNESS_MASK 0xff000000 3089 # define TV_BRIGHTNESS_SHIFT 24 3090 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3091 # define TV_CONTRAST_MASK 0x00ff0000 3092 # define TV_CONTRAST_SHIFT 16 3093 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3094 # define TV_SATURATION_MASK 0x0000ff00 3095 # define TV_SATURATION_SHIFT 8 3096 /* Hue adjustment, as an integer phase angle in degrees */ 3097 # define TV_HUE_MASK 0x000000ff 3098 # define TV_HUE_SHIFT 0 3099 3100 #define TV_CLR_LEVEL 0x6802c 3101 /* Controls the DAC level for black */ 3102 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3103 # define TV_BLACK_LEVEL_SHIFT 16 3104 /* Controls the DAC level for blanking */ 3105 # define TV_BLANK_LEVEL_MASK 0x000001ff 3106 # define TV_BLANK_LEVEL_SHIFT 0 3107 3108 #define TV_H_CTL_1 0x68030 3109 /* Number of pixels in the hsync. */ 3110 # define TV_HSYNC_END_MASK 0x1fff0000 3111 # define TV_HSYNC_END_SHIFT 16 3112 /* Total number of pixels minus one in the line (display and blanking). */ 3113 # define TV_HTOTAL_MASK 0x00001fff 3114 # define TV_HTOTAL_SHIFT 0 3115 3116 #define TV_H_CTL_2 0x68034 3117 /* Enables the colorburst (needed for non-component color) */ 3118 # define TV_BURST_ENA (1 << 31) 3119 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3120 # define TV_HBURST_START_SHIFT 16 3121 # define TV_HBURST_START_MASK 0x1fff0000 3122 /* Length of the colorburst */ 3123 # define TV_HBURST_LEN_SHIFT 0 3124 # define TV_HBURST_LEN_MASK 0x0001fff 3125 3126 #define TV_H_CTL_3 0x68038 3127 /* End of hblank, measured in pixels minus one from start of hsync */ 3128 # define TV_HBLANK_END_SHIFT 16 3129 # define TV_HBLANK_END_MASK 0x1fff0000 3130 /* Start of hblank, measured in pixels minus one from start of hsync */ 3131 # define TV_HBLANK_START_SHIFT 0 3132 # define TV_HBLANK_START_MASK 0x0001fff 3133 3134 #define TV_V_CTL_1 0x6803c 3135 /* XXX */ 3136 # define TV_NBR_END_SHIFT 16 3137 # define TV_NBR_END_MASK 0x07ff0000 3138 /* XXX */ 3139 # define TV_VI_END_F1_SHIFT 8 3140 # define TV_VI_END_F1_MASK 0x00003f00 3141 /* XXX */ 3142 # define TV_VI_END_F2_SHIFT 0 3143 # define TV_VI_END_F2_MASK 0x0000003f 3144 3145 #define TV_V_CTL_2 0x68040 3146 /* Length of vsync, in half lines */ 3147 # define TV_VSYNC_LEN_MASK 0x07ff0000 3148 # define TV_VSYNC_LEN_SHIFT 16 3149 /* Offset of the start of vsync in field 1, measured in one less than the 3150 * number of half lines. 3151 */ 3152 # define TV_VSYNC_START_F1_MASK 0x00007f00 3153 # define TV_VSYNC_START_F1_SHIFT 8 3154 /* 3155 * Offset of the start of vsync in field 2, measured in one less than the 3156 * number of half lines. 3157 */ 3158 # define TV_VSYNC_START_F2_MASK 0x0000007f 3159 # define TV_VSYNC_START_F2_SHIFT 0 3160 3161 #define TV_V_CTL_3 0x68044 3162 /* Enables generation of the equalization signal */ 3163 # define TV_EQUAL_ENA (1 << 31) 3164 /* Length of vsync, in half lines */ 3165 # define TV_VEQ_LEN_MASK 0x007f0000 3166 # define TV_VEQ_LEN_SHIFT 16 3167 /* Offset of the start of equalization in field 1, measured in one less than 3168 * the number of half lines. 3169 */ 3170 # define TV_VEQ_START_F1_MASK 0x0007f00 3171 # define TV_VEQ_START_F1_SHIFT 8 3172 /* 3173 * Offset of the start of equalization in field 2, measured in one less than 3174 * the number of half lines. 3175 */ 3176 # define TV_VEQ_START_F2_MASK 0x000007f 3177 # define TV_VEQ_START_F2_SHIFT 0 3178 3179 #define TV_V_CTL_4 0x68048 3180 /* 3181 * Offset to start of vertical colorburst, measured in one less than the 3182 * number of lines from vertical start. 3183 */ 3184 # define TV_VBURST_START_F1_MASK 0x003f0000 3185 # define TV_VBURST_START_F1_SHIFT 16 3186 /* 3187 * Offset to the end of vertical colorburst, measured in one less than the 3188 * number of lines from the start of NBR. 3189 */ 3190 # define TV_VBURST_END_F1_MASK 0x000000ff 3191 # define TV_VBURST_END_F1_SHIFT 0 3192 3193 #define TV_V_CTL_5 0x6804c 3194 /* 3195 * Offset to start of vertical colorburst, measured in one less than the 3196 * number of lines from vertical start. 3197 */ 3198 # define TV_VBURST_START_F2_MASK 0x003f0000 3199 # define TV_VBURST_START_F2_SHIFT 16 3200 /* 3201 * Offset to the end of vertical colorburst, measured in one less than the 3202 * number of lines from the start of NBR. 3203 */ 3204 # define TV_VBURST_END_F2_MASK 0x000000ff 3205 # define TV_VBURST_END_F2_SHIFT 0 3206 3207 #define TV_V_CTL_6 0x68050 3208 /* 3209 * Offset to start of vertical colorburst, measured in one less than the 3210 * number of lines from vertical start. 3211 */ 3212 # define TV_VBURST_START_F3_MASK 0x003f0000 3213 # define TV_VBURST_START_F3_SHIFT 16 3214 /* 3215 * Offset to the end of vertical colorburst, measured in one less than the 3216 * number of lines from the start of NBR. 3217 */ 3218 # define TV_VBURST_END_F3_MASK 0x000000ff 3219 # define TV_VBURST_END_F3_SHIFT 0 3220 3221 #define TV_V_CTL_7 0x68054 3222 /* 3223 * Offset to start of vertical colorburst, measured in one less than the 3224 * number of lines from vertical start. 3225 */ 3226 # define TV_VBURST_START_F4_MASK 0x003f0000 3227 # define TV_VBURST_START_F4_SHIFT 16 3228 /* 3229 * Offset to the end of vertical colorburst, measured in one less than the 3230 * number of lines from the start of NBR. 3231 */ 3232 # define TV_VBURST_END_F4_MASK 0x000000ff 3233 # define TV_VBURST_END_F4_SHIFT 0 3234 3235 #define TV_SC_CTL_1 0x68060 3236 /* Turns on the first subcarrier phase generation DDA */ 3237 # define TV_SC_DDA1_EN (1 << 31) 3238 /* Turns on the first subcarrier phase generation DDA */ 3239 # define TV_SC_DDA2_EN (1 << 30) 3240 /* Turns on the first subcarrier phase generation DDA */ 3241 # define TV_SC_DDA3_EN (1 << 29) 3242 /* Sets the subcarrier DDA to reset frequency every other field */ 3243 # define TV_SC_RESET_EVERY_2 (0 << 24) 3244 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3245 # define TV_SC_RESET_EVERY_4 (1 << 24) 3246 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3247 # define TV_SC_RESET_EVERY_8 (2 << 24) 3248 /* Sets the subcarrier DDA to never reset the frequency */ 3249 # define TV_SC_RESET_NEVER (3 << 24) 3250 /* Sets the peak amplitude of the colorburst.*/ 3251 # define TV_BURST_LEVEL_MASK 0x00ff0000 3252 # define TV_BURST_LEVEL_SHIFT 16 3253 /* Sets the increment of the first subcarrier phase generation DDA */ 3254 # define TV_SCDDA1_INC_MASK 0x00000fff 3255 # define TV_SCDDA1_INC_SHIFT 0 3256 3257 #define TV_SC_CTL_2 0x68064 3258 /* Sets the rollover for the second subcarrier phase generation DDA */ 3259 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3260 # define TV_SCDDA2_SIZE_SHIFT 16 3261 /* Sets the increent of the second subcarrier phase generation DDA */ 3262 # define TV_SCDDA2_INC_MASK 0x00007fff 3263 # define TV_SCDDA2_INC_SHIFT 0 3264 3265 #define TV_SC_CTL_3 0x68068 3266 /* Sets the rollover for the third subcarrier phase generation DDA */ 3267 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3268 # define TV_SCDDA3_SIZE_SHIFT 16 3269 /* Sets the increent of the third subcarrier phase generation DDA */ 3270 # define TV_SCDDA3_INC_MASK 0x00007fff 3271 # define TV_SCDDA3_INC_SHIFT 0 3272 3273 #define TV_WIN_POS 0x68070 3274 /* X coordinate of the display from the start of horizontal active */ 3275 # define TV_XPOS_MASK 0x1fff0000 3276 # define TV_XPOS_SHIFT 16 3277 /* Y coordinate of the display from the start of vertical active (NBR) */ 3278 # define TV_YPOS_MASK 0x00000fff 3279 # define TV_YPOS_SHIFT 0 3280 3281 #define TV_WIN_SIZE 0x68074 3282 /* Horizontal size of the display window, measured in pixels*/ 3283 # define TV_XSIZE_MASK 0x1fff0000 3284 # define TV_XSIZE_SHIFT 16 3285 /* 3286 * Vertical size of the display window, measured in pixels. 3287 * 3288 * Must be even for interlaced modes. 3289 */ 3290 # define TV_YSIZE_MASK 0x00000fff 3291 # define TV_YSIZE_SHIFT 0 3292 3293 #define TV_FILTER_CTL_1 0x68080 3294 /* 3295 * Enables automatic scaling calculation. 3296 * 3297 * If set, the rest of the registers are ignored, and the calculated values can 3298 * be read back from the register. 3299 */ 3300 # define TV_AUTO_SCALE (1 << 31) 3301 /* 3302 * Disables the vertical filter. 3303 * 3304 * This is required on modes more than 1024 pixels wide */ 3305 # define TV_V_FILTER_BYPASS (1 << 29) 3306 /* Enables adaptive vertical filtering */ 3307 # define TV_VADAPT (1 << 28) 3308 # define TV_VADAPT_MODE_MASK (3 << 26) 3309 /* Selects the least adaptive vertical filtering mode */ 3310 # define TV_VADAPT_MODE_LEAST (0 << 26) 3311 /* Selects the moderately adaptive vertical filtering mode */ 3312 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3313 /* Selects the most adaptive vertical filtering mode */ 3314 # define TV_VADAPT_MODE_MOST (3 << 26) 3315 /* 3316 * Sets the horizontal scaling factor. 3317 * 3318 * This should be the fractional part of the horizontal scaling factor divided 3319 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3320 * 3321 * (src width - 1) / ((oversample * dest width) - 1) 3322 */ 3323 # define TV_HSCALE_FRAC_MASK 0x00003fff 3324 # define TV_HSCALE_FRAC_SHIFT 0 3325 3326 #define TV_FILTER_CTL_2 0x68084 3327 /* 3328 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3329 * 3330 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3331 */ 3332 # define TV_VSCALE_INT_MASK 0x00038000 3333 # define TV_VSCALE_INT_SHIFT 15 3334 /* 3335 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3336 * 3337 * \sa TV_VSCALE_INT_MASK 3338 */ 3339 # define TV_VSCALE_FRAC_MASK 0x00007fff 3340 # define TV_VSCALE_FRAC_SHIFT 0 3341 3342 #define TV_FILTER_CTL_3 0x68088 3343 /* 3344 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3345 * 3346 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3347 * 3348 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3349 */ 3350 # define TV_VSCALE_IP_INT_MASK 0x00038000 3351 # define TV_VSCALE_IP_INT_SHIFT 15 3352 /* 3353 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3354 * 3355 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3356 * 3357 * \sa TV_VSCALE_IP_INT_MASK 3358 */ 3359 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3360 # define TV_VSCALE_IP_FRAC_SHIFT 0 3361 3362 #define TV_CC_CONTROL 0x68090 3363 # define TV_CC_ENABLE (1 << 31) 3364 /* 3365 * Specifies which field to send the CC data in. 3366 * 3367 * CC data is usually sent in field 0. 3368 */ 3369 # define TV_CC_FID_MASK (1 << 27) 3370 # define TV_CC_FID_SHIFT 27 3371 /* Sets the horizontal position of the CC data. Usually 135. */ 3372 # define TV_CC_HOFF_MASK 0x03ff0000 3373 # define TV_CC_HOFF_SHIFT 16 3374 /* Sets the vertical position of the CC data. Usually 21 */ 3375 # define TV_CC_LINE_MASK 0x0000003f 3376 # define TV_CC_LINE_SHIFT 0 3377 3378 #define TV_CC_DATA 0x68094 3379 # define TV_CC_RDY (1 << 31) 3380 /* Second word of CC data to be transmitted. */ 3381 # define TV_CC_DATA_2_MASK 0x007f0000 3382 # define TV_CC_DATA_2_SHIFT 16 3383 /* First word of CC data to be transmitted. */ 3384 # define TV_CC_DATA_1_MASK 0x0000007f 3385 # define TV_CC_DATA_1_SHIFT 0 3386 3387 #define TV_H_LUMA_0 0x68100 3388 #define TV_H_LUMA_59 0x681ec 3389 #define TV_H_CHROMA_0 0x68200 3390 #define TV_H_CHROMA_59 0x682ec 3391 #define TV_V_LUMA_0 0x68300 3392 #define TV_V_LUMA_42 0x683a8 3393 #define TV_V_CHROMA_0 0x68400 3394 #define TV_V_CHROMA_42 0x684a8 3395 3396 /* Display Port */ 3397 #define DP_A 0x64000 /* eDP */ 3398 #define DP_B 0x64100 3399 #define DP_C 0x64200 3400 #define DP_D 0x64300 3401 3402 #define DP_PORT_EN (1 << 31) 3403 #define DP_PIPEB_SELECT (1 << 30) 3404 #define DP_PIPE_MASK (1 << 30) 3405 #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 3406 #define DP_PIPE_MASK_CHV (3 << 16) 3407 3408 /* Link training mode - select a suitable mode for each stage */ 3409 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3410 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3411 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3412 #define DP_LINK_TRAIN_OFF (3 << 28) 3413 #define DP_LINK_TRAIN_MASK (3 << 28) 3414 #define DP_LINK_TRAIN_SHIFT 28 3415 3416 /* CPT Link training mode */ 3417 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3418 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3419 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3420 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3421 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3422 #define DP_LINK_TRAIN_SHIFT_CPT 8 3423 3424 /* Signal voltages. These are mostly controlled by the other end */ 3425 #define DP_VOLTAGE_0_4 (0 << 25) 3426 #define DP_VOLTAGE_0_6 (1 << 25) 3427 #define DP_VOLTAGE_0_8 (2 << 25) 3428 #define DP_VOLTAGE_1_2 (3 << 25) 3429 #define DP_VOLTAGE_MASK (7 << 25) 3430 #define DP_VOLTAGE_SHIFT 25 3431 3432 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3433 * they want 3434 */ 3435 #define DP_PRE_EMPHASIS_0 (0 << 22) 3436 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3437 #define DP_PRE_EMPHASIS_6 (2 << 22) 3438 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3439 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3440 #define DP_PRE_EMPHASIS_SHIFT 22 3441 3442 /* How many wires to use. I guess 3 was too hard */ 3443 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3444 #define DP_PORT_WIDTH_MASK (7 << 19) 3445 3446 /* Mystic DPCD version 1.1 special mode */ 3447 #define DP_ENHANCED_FRAMING (1 << 18) 3448 3449 /* eDP */ 3450 #define DP_PLL_FREQ_270MHZ (0 << 16) 3451 #define DP_PLL_FREQ_160MHZ (1 << 16) 3452 #define DP_PLL_FREQ_MASK (3 << 16) 3453 3454 /* locked once port is enabled */ 3455 #define DP_PORT_REVERSAL (1 << 15) 3456 3457 /* eDP */ 3458 #define DP_PLL_ENABLE (1 << 14) 3459 3460 /* sends the clock on lane 15 of the PEG for debug */ 3461 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3462 3463 #define DP_SCRAMBLING_DISABLE (1 << 12) 3464 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3465 3466 /* limit RGB values to avoid confusing TVs */ 3467 #define DP_COLOR_RANGE_16_235 (1 << 8) 3468 3469 /* Turn on the audio link */ 3470 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3471 3472 /* vs and hs sync polarity */ 3473 #define DP_SYNC_VS_HIGH (1 << 4) 3474 #define DP_SYNC_HS_HIGH (1 << 3) 3475 3476 /* A fantasy */ 3477 #define DP_DETECTED (1 << 2) 3478 3479 /* The aux channel provides a way to talk to the 3480 * signal sink for DDC etc. Max packet size supported 3481 * is 20 bytes in each direction, hence the 5 fixed 3482 * data registers 3483 */ 3484 #define DPA_AUX_CH_CTL 0x64010 3485 #define DPA_AUX_CH_DATA1 0x64014 3486 #define DPA_AUX_CH_DATA2 0x64018 3487 #define DPA_AUX_CH_DATA3 0x6401c 3488 #define DPA_AUX_CH_DATA4 0x64020 3489 #define DPA_AUX_CH_DATA5 0x64024 3490 3491 #define DPB_AUX_CH_CTL 0x64110 3492 #define DPB_AUX_CH_DATA1 0x64114 3493 #define DPB_AUX_CH_DATA2 0x64118 3494 #define DPB_AUX_CH_DATA3 0x6411c 3495 #define DPB_AUX_CH_DATA4 0x64120 3496 #define DPB_AUX_CH_DATA5 0x64124 3497 3498 #define DPC_AUX_CH_CTL 0x64210 3499 #define DPC_AUX_CH_DATA1 0x64214 3500 #define DPC_AUX_CH_DATA2 0x64218 3501 #define DPC_AUX_CH_DATA3 0x6421c 3502 #define DPC_AUX_CH_DATA4 0x64220 3503 #define DPC_AUX_CH_DATA5 0x64224 3504 3505 #define DPD_AUX_CH_CTL 0x64310 3506 #define DPD_AUX_CH_DATA1 0x64314 3507 #define DPD_AUX_CH_DATA2 0x64318 3508 #define DPD_AUX_CH_DATA3 0x6431c 3509 #define DPD_AUX_CH_DATA4 0x64320 3510 #define DPD_AUX_CH_DATA5 0x64324 3511 3512 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3513 #define DP_AUX_CH_CTL_DONE (1 << 30) 3514 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3515 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3516 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3517 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3518 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3519 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 3520 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3521 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3522 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3523 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3524 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3525 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3526 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3527 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3528 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3529 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3530 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3531 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3532 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3533 3534 /* 3535 * Computing GMCH M and N values for the Display Port link 3536 * 3537 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3538 * 3539 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3540 * 3541 * The GMCH value is used internally 3542 * 3543 * bytes_per_pixel is the number of bytes coming out of the plane, 3544 * which is after the LUTs, so we want the bytes for our color format. 3545 * For our current usage, this is always 3, one byte for R, G and B. 3546 */ 3547 #define _PIPEA_DATA_M_G4X 0x70050 3548 #define _PIPEB_DATA_M_G4X 0x71050 3549 3550 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3551 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 3552 #define TU_SIZE_SHIFT 25 3553 #define TU_SIZE_MASK (0x3f << 25) 3554 3555 #define DATA_LINK_M_N_MASK (0xffffff) 3556 #define DATA_LINK_N_MAX (0x800000) 3557 3558 #define _PIPEA_DATA_N_G4X 0x70054 3559 #define _PIPEB_DATA_N_G4X 0x71054 3560 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 3561 3562 /* 3563 * Computing Link M and N values for the Display Port link 3564 * 3565 * Link M / N = pixel_clock / ls_clk 3566 * 3567 * (the DP spec calls pixel_clock the 'strm_clk') 3568 * 3569 * The Link value is transmitted in the Main Stream 3570 * Attributes and VB-ID. 3571 */ 3572 3573 #define _PIPEA_LINK_M_G4X 0x70060 3574 #define _PIPEB_LINK_M_G4X 0x71060 3575 #define PIPEA_DP_LINK_M_MASK (0xffffff) 3576 3577 #define _PIPEA_LINK_N_G4X 0x70064 3578 #define _PIPEB_LINK_N_G4X 0x71064 3579 #define PIPEA_DP_LINK_N_MASK (0xffffff) 3580 3581 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3582 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3583 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3584 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3585 3586 /* Display & cursor control */ 3587 3588 /* Pipe A */ 3589 #define _PIPEADSL 0x70000 3590 #define DSL_LINEMASK_GEN2 0x00000fff 3591 #define DSL_LINEMASK_GEN3 0x00001fff 3592 #define _PIPEACONF 0x70008 3593 #define PIPECONF_ENABLE (1<<31) 3594 #define PIPECONF_DISABLE 0 3595 #define PIPECONF_DOUBLE_WIDE (1<<30) 3596 #define I965_PIPECONF_ACTIVE (1<<30) 3597 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 3598 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 3599 #define PIPECONF_SINGLE_WIDE 0 3600 #define PIPECONF_PIPE_UNLOCKED 0 3601 #define PIPECONF_PIPE_LOCKED (1<<25) 3602 #define PIPECONF_PALETTE 0 3603 #define PIPECONF_GAMMA (1<<24) 3604 #define PIPECONF_FORCE_BORDER (1<<25) 3605 #define PIPECONF_INTERLACE_MASK (7 << 21) 3606 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 3607 /* Note that pre-gen3 does not support interlaced display directly. Panel 3608 * fitting must be disabled on pre-ilk for interlaced. */ 3609 #define PIPECONF_PROGRESSIVE (0 << 21) 3610 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 3611 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 3612 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 3613 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 3614 /* Ironlake and later have a complete new set of values for interlaced. PFIT 3615 * means panel fitter required, PF means progressive fetch, DBL means power 3616 * saving pixel doubling. */ 3617 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 3618 #define PIPECONF_INTERLACED_ILK (3 << 21) 3619 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 3620 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 3621 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 3622 #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 3623 #define PIPECONF_CXSR_DOWNCLOCK (1<<16) 3624 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 3625 #define PIPECONF_BPC_MASK (0x7 << 5) 3626 #define PIPECONF_8BPC (0<<5) 3627 #define PIPECONF_10BPC (1<<5) 3628 #define PIPECONF_6BPC (2<<5) 3629 #define PIPECONF_12BPC (3<<5) 3630 #define PIPECONF_DITHER_EN (1<<4) 3631 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 3632 #define PIPECONF_DITHER_TYPE_SP (0<<2) 3633 #define PIPECONF_DITHER_TYPE_ST1 (1<<2) 3634 #define PIPECONF_DITHER_TYPE_ST2 (2<<2) 3635 #define PIPECONF_DITHER_TYPE_TEMP (3<<2) 3636 #define _PIPEASTAT 0x70024 3637 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 3638 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 3639 #define PIPE_CRC_ERROR_ENABLE (1UL<<29) 3640 #define PIPE_CRC_DONE_ENABLE (1UL<<28) 3641 #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 3642 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 3643 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 3644 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 3645 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 3646 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 3647 #define PIPE_DPST_EVENT_ENABLE (1UL<<23) 3648 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 3649 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 3650 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 3651 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 3652 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 3653 #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 3654 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 3655 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 3656 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 3657 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 3658 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 3659 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 3660 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 3661 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 3662 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 3663 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 3664 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 3665 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 3666 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 3667 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 3668 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 3669 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 3670 #define PIPE_DPST_EVENT_STATUS (1UL<<7) 3671 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 3672 #define PIPE_A_PSR_STATUS_VLV (1UL<<6) 3673 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 3674 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 3675 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 3676 #define PIPE_B_PSR_STATUS_VLV (1UL<<3) 3677 #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 3678 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 3679 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 3680 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 3681 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 3682 #define PIPE_HBLANK_INT_STATUS (1UL<<0) 3683 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 3684 3685 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3686 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3687 3688 #define PIPE_A_OFFSET 0x70000 3689 #define PIPE_B_OFFSET 0x71000 3690 #define PIPE_C_OFFSET 0x72000 3691 #define CHV_PIPE_C_OFFSET 0x74000 3692 /* 3693 * There's actually no pipe EDP. Some pipe registers have 3694 * simply shifted from the pipe to the transcoder, while 3695 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3696 * to access such registers in transcoder EDP. 3697 */ 3698 #define PIPE_EDP_OFFSET 0x7f000 3699 3700 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ 3701 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 3702 dev_priv->info.display_mmio_offset) 3703 3704 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) 3705 #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) 3706 #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) 3707 #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) 3708 #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) 3709 3710 #define _PIPE_MISC_A 0x70030 3711 #define _PIPE_MISC_B 0x71030 3712 #define PIPEMISC_DITHER_BPC_MASK (7<<5) 3713 #define PIPEMISC_DITHER_8_BPC (0<<5) 3714 #define PIPEMISC_DITHER_10_BPC (1<<5) 3715 #define PIPEMISC_DITHER_6_BPC (2<<5) 3716 #define PIPEMISC_DITHER_12_BPC (3<<5) 3717 #define PIPEMISC_DITHER_ENABLE (1<<4) 3718 #define PIPEMISC_DITHER_TYPE_MASK (3<<2) 3719 #define PIPEMISC_DITHER_TYPE_SP (0<<2) 3720 #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) 3721 3722 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) 3723 #define PIPEB_LINE_COMPARE_INT_EN (1<<29) 3724 #define PIPEB_HLINE_INT_EN (1<<28) 3725 #define PIPEB_VBLANK_INT_EN (1<<27) 3726 #define SPRITED_FLIP_DONE_INT_EN (1<<26) 3727 #define SPRITEC_FLIP_DONE_INT_EN (1<<25) 3728 #define PLANEB_FLIP_DONE_INT_EN (1<<24) 3729 #define PIPE_PSR_INT_EN (1<<22) 3730 #define PIPEA_LINE_COMPARE_INT_EN (1<<21) 3731 #define PIPEA_HLINE_INT_EN (1<<20) 3732 #define PIPEA_VBLANK_INT_EN (1<<19) 3733 #define SPRITEB_FLIP_DONE_INT_EN (1<<18) 3734 #define SPRITEA_FLIP_DONE_INT_EN (1<<17) 3735 #define PLANEA_FLIPDONE_INT_EN (1<<16) 3736 #define PIPEC_LINE_COMPARE_INT_EN (1<<13) 3737 #define PIPEC_HLINE_INT_EN (1<<12) 3738 #define PIPEC_VBLANK_INT_EN (1<<11) 3739 #define SPRITEF_FLIPDONE_INT_EN (1<<10) 3740 #define SPRITEE_FLIPDONE_INT_EN (1<<9) 3741 #define PLANEC_FLIPDONE_INT_EN (1<<8) 3742 3743 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3744 #define SPRITEF_INVALID_GTT_INT_EN (1<<27) 3745 #define SPRITEE_INVALID_GTT_INT_EN (1<<26) 3746 #define PLANEC_INVALID_GTT_INT_EN (1<<25) 3747 #define CURSORC_INVALID_GTT_INT_EN (1<<24) 3748 #define CURSORB_INVALID_GTT_INT_EN (1<<23) 3749 #define CURSORA_INVALID_GTT_INT_EN (1<<22) 3750 #define SPRITED_INVALID_GTT_INT_EN (1<<21) 3751 #define SPRITEC_INVALID_GTT_INT_EN (1<<20) 3752 #define PLANEB_INVALID_GTT_INT_EN (1<<19) 3753 #define SPRITEB_INVALID_GTT_INT_EN (1<<18) 3754 #define SPRITEA_INVALID_GTT_INT_EN (1<<17) 3755 #define PLANEA_INVALID_GTT_INT_EN (1<<16) 3756 #define DPINVGTT_EN_MASK 0xff0000 3757 #define DPINVGTT_EN_MASK_CHV 0xfff0000 3758 #define SPRITEF_INVALID_GTT_STATUS (1<<11) 3759 #define SPRITEE_INVALID_GTT_STATUS (1<<10) 3760 #define PLANEC_INVALID_GTT_STATUS (1<<9) 3761 #define CURSORC_INVALID_GTT_STATUS (1<<8) 3762 #define CURSORB_INVALID_GTT_STATUS (1<<7) 3763 #define CURSORA_INVALID_GTT_STATUS (1<<6) 3764 #define SPRITED_INVALID_GTT_STATUS (1<<5) 3765 #define SPRITEC_INVALID_GTT_STATUS (1<<4) 3766 #define PLANEB_INVALID_GTT_STATUS (1<<3) 3767 #define SPRITEB_INVALID_GTT_STATUS (1<<2) 3768 #define SPRITEA_INVALID_GTT_STATUS (1<<1) 3769 #define PLANEA_INVALID_GTT_STATUS (1<<0) 3770 #define DPINVGTT_STATUS_MASK 0xff 3771 #define DPINVGTT_STATUS_MASK_CHV 0xfff 3772 3773 #define DSPARB 0x70030 3774 #define DSPARB_CSTART_MASK (0x7f << 7) 3775 #define DSPARB_CSTART_SHIFT 7 3776 #define DSPARB_BSTART_MASK (0x7f) 3777 #define DSPARB_BSTART_SHIFT 0 3778 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3779 #define DSPARB_AEND_SHIFT 0 3780 3781 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) 3782 #define DSPFW_SR_SHIFT 23 3783 #define DSPFW_SR_MASK (0x1ff<<23) 3784 #define DSPFW_CURSORB_SHIFT 16 3785 #define DSPFW_CURSORB_MASK (0x3f<<16) 3786 #define DSPFW_PLANEB_SHIFT 8 3787 #define DSPFW_PLANEB_MASK (0x7f<<8) 3788 #define DSPFW_PLANEA_MASK (0x7f) 3789 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) 3790 #define DSPFW_CURSORA_MASK 0x00003f00 3791 #define DSPFW_CURSORA_SHIFT 8 3792 #define DSPFW_PLANEC_MASK (0x7f) 3793 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) 3794 #define DSPFW_HPLL_SR_EN (1<<31) 3795 #define DSPFW_CURSOR_SR_SHIFT 24 3796 #define PINEVIEW_SELF_REFRESH_EN (1<<30) 3797 #define DSPFW_CURSOR_SR_MASK (0x3f<<24) 3798 #define DSPFW_HPLL_CURSOR_SHIFT 16 3799 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 3800 #define DSPFW_HPLL_SR_MASK (0x1ff) 3801 #define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070) 3802 #define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c) 3803 3804 /* drain latency register values*/ 3805 #define DRAIN_LATENCY_PRECISION_32 32 3806 #define DRAIN_LATENCY_PRECISION_16 16 3807 #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) 3808 #define DDL_CURSORA_PRECISION_32 (1<<31) 3809 #define DDL_CURSORA_PRECISION_16 (0<<31) 3810 #define DDL_CURSORA_SHIFT 24 3811 #define DDL_SPRITEB_PRECISION_32 (1<<23) 3812 #define DDL_SPRITEB_PRECISION_16 (0<<23) 3813 #define DDL_SPRITEB_SHIFT 16 3814 #define DDL_SPRITEA_PRECISION_32 (1<<15) 3815 #define DDL_SPRITEA_PRECISION_16 (0<<15) 3816 #define DDL_SPRITEA_SHIFT 8 3817 #define DDL_PLANEA_PRECISION_32 (1<<7) 3818 #define DDL_PLANEA_PRECISION_16 (0<<7) 3819 #define DDL_PLANEA_SHIFT 0 3820 3821 #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) 3822 #define DDL_CURSORB_PRECISION_32 (1<<31) 3823 #define DDL_CURSORB_PRECISION_16 (0<<31) 3824 #define DDL_CURSORB_SHIFT 24 3825 #define DDL_SPRITED_PRECISION_32 (1<<23) 3826 #define DDL_SPRITED_PRECISION_16 (0<<23) 3827 #define DDL_SPRITED_SHIFT 16 3828 #define DDL_SPRITEC_PRECISION_32 (1<<15) 3829 #define DDL_SPRITEC_PRECISION_16 (0<<15) 3830 #define DDL_SPRITEC_SHIFT 8 3831 #define DDL_PLANEB_PRECISION_32 (1<<7) 3832 #define DDL_PLANEB_PRECISION_16 (0<<7) 3833 #define DDL_PLANEB_SHIFT 0 3834 3835 #define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058) 3836 #define DDL_CURSORC_PRECISION_32 (1<<31) 3837 #define DDL_CURSORC_PRECISION_16 (0<<31) 3838 #define DDL_CURSORC_SHIFT 24 3839 #define DDL_SPRITEF_PRECISION_32 (1<<23) 3840 #define DDL_SPRITEF_PRECISION_16 (0<<23) 3841 #define DDL_SPRITEF_SHIFT 16 3842 #define DDL_SPRITEE_PRECISION_32 (1<<15) 3843 #define DDL_SPRITEE_PRECISION_16 (0<<15) 3844 #define DDL_SPRITEE_SHIFT 8 3845 #define DDL_PLANEC_PRECISION_32 (1<<7) 3846 #define DDL_PLANEC_PRECISION_16 (0<<7) 3847 #define DDL_PLANEC_SHIFT 0 3848 3849 /* FIFO watermark sizes etc */ 3850 #define G4X_FIFO_LINE_SIZE 64 3851 #define I915_FIFO_LINE_SIZE 64 3852 #define I830_FIFO_LINE_SIZE 32 3853 3854 #define VALLEYVIEW_FIFO_SIZE 255 3855 #define G4X_FIFO_SIZE 127 3856 #define I965_FIFO_SIZE 512 3857 #define I945_FIFO_SIZE 127 3858 #define I915_FIFO_SIZE 95 3859 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 3860 #define I830_FIFO_SIZE 95 3861 3862 #define VALLEYVIEW_MAX_WM 0xff 3863 #define G4X_MAX_WM 0x3f 3864 #define I915_MAX_WM 0x3f 3865 3866 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 3867 #define PINEVIEW_FIFO_LINE_SIZE 64 3868 #define PINEVIEW_MAX_WM 0x1ff 3869 #define PINEVIEW_DFT_WM 0x3f 3870 #define PINEVIEW_DFT_HPLLOFF_WM 0 3871 #define PINEVIEW_GUARD_WM 10 3872 #define PINEVIEW_CURSOR_FIFO 64 3873 #define PINEVIEW_CURSOR_MAX_WM 0x3f 3874 #define PINEVIEW_CURSOR_DFT_WM 0 3875 #define PINEVIEW_CURSOR_GUARD_WM 5 3876 3877 #define VALLEYVIEW_CURSOR_MAX_WM 64 3878 #define I965_CURSOR_FIFO 64 3879 #define I965_CURSOR_MAX_WM 32 3880 #define I965_CURSOR_DFT_WM 8 3881 3882 /* define the Watermark register on Ironlake */ 3883 #define WM0_PIPEA_ILK 0x45100 3884 #define WM0_PIPE_PLANE_MASK (0xffff<<16) 3885 #define WM0_PIPE_PLANE_SHIFT 16 3886 #define WM0_PIPE_SPRITE_MASK (0xff<<8) 3887 #define WM0_PIPE_SPRITE_SHIFT 8 3888 #define WM0_PIPE_CURSOR_MASK (0xff) 3889 3890 #define WM0_PIPEB_ILK 0x45104 3891 #define WM0_PIPEC_IVB 0x45200 3892 #define WM1_LP_ILK 0x45108 3893 #define WM1_LP_SR_EN (1<<31) 3894 #define WM1_LP_LATENCY_SHIFT 24 3895 #define WM1_LP_LATENCY_MASK (0x7f<<24) 3896 #define WM1_LP_FBC_MASK (0xf<<20) 3897 #define WM1_LP_FBC_SHIFT 20 3898 #define WM1_LP_FBC_SHIFT_BDW 19 3899 #define WM1_LP_SR_MASK (0x7ff<<8) 3900 #define WM1_LP_SR_SHIFT 8 3901 #define WM1_LP_CURSOR_MASK (0xff) 3902 #define WM2_LP_ILK 0x4510c 3903 #define WM2_LP_EN (1<<31) 3904 #define WM3_LP_ILK 0x45110 3905 #define WM3_LP_EN (1<<31) 3906 #define WM1S_LP_ILK 0x45120 3907 #define WM2S_LP_IVB 0x45124 3908 #define WM3S_LP_IVB 0x45128 3909 #define WM1S_LP_EN (1<<31) 3910 3911 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 3912 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 3913 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 3914 3915 /* Memory latency timer register */ 3916 #define MLTR_ILK 0x11222 3917 #define MLTR_WM1_SHIFT 0 3918 #define MLTR_WM2_SHIFT 8 3919 /* the unit of memory self-refresh latency time is 0.5us */ 3920 #define ILK_SRLT_MASK 0x3f 3921 3922 3923 /* the address where we get all kinds of latency value */ 3924 #define SSKPD 0x5d10 3925 #define SSKPD_WM_MASK 0x3f 3926 #define SSKPD_WM0_SHIFT 0 3927 #define SSKPD_WM1_SHIFT 8 3928 #define SSKPD_WM2_SHIFT 16 3929 #define SSKPD_WM3_SHIFT 24 3930 3931 /* 3932 * The two pipe frame counter registers are not synchronized, so 3933 * reading a stable value is somewhat tricky. The following code 3934 * should work: 3935 * 3936 * do { 3937 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 3938 * PIPE_FRAME_HIGH_SHIFT; 3939 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 3940 * PIPE_FRAME_LOW_SHIFT); 3941 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 3942 * PIPE_FRAME_HIGH_SHIFT); 3943 * } while (high1 != high2); 3944 * frame = (high1 << 8) | low1; 3945 */ 3946 #define _PIPEAFRAMEHIGH 0x70040 3947 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 3948 #define PIPE_FRAME_HIGH_SHIFT 0 3949 #define _PIPEAFRAMEPIXEL 0x70044 3950 #define PIPE_FRAME_LOW_MASK 0xff000000 3951 #define PIPE_FRAME_LOW_SHIFT 24 3952 #define PIPE_PIXEL_MASK 0x00ffffff 3953 #define PIPE_PIXEL_SHIFT 0 3954 /* GM45+ just has to be different */ 3955 #define _PIPEA_FRMCOUNT_GM45 0x70040 3956 #define _PIPEA_FLIPCOUNT_GM45 0x70044 3957 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) 3958 #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) 3959 3960 /* Cursor A & B regs */ 3961 #define _CURACNTR 0x70080 3962 /* Old style CUR*CNTR flags (desktop 8xx) */ 3963 #define CURSOR_ENABLE 0x80000000 3964 #define CURSOR_GAMMA_ENABLE 0x40000000 3965 #define CURSOR_STRIDE_MASK 0x30000000 3966 #define CURSOR_PIPE_CSC_ENABLE (1<<24) 3967 #define CURSOR_FORMAT_SHIFT 24 3968 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 3969 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 3970 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 3971 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 3972 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 3973 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 3974 /* New style CUR*CNTR flags */ 3975 #define CURSOR_MODE 0x27 3976 #define CURSOR_MODE_DISABLE 0x00 3977 #define CURSOR_MODE_128_32B_AX 0x02 3978 #define CURSOR_MODE_256_32B_AX 0x03 3979 #define CURSOR_MODE_64_32B_AX 0x07 3980 #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 3981 #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 3982 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 3983 #define MCURSOR_PIPE_SELECT (1 << 28) 3984 #define MCURSOR_PIPE_A 0x00 3985 #define MCURSOR_PIPE_B (1 << 28) 3986 #define MCURSOR_GAMMA_ENABLE (1 << 26) 3987 #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 3988 #define _CURABASE 0x70084 3989 #define _CURAPOS 0x70088 3990 #define CURSOR_POS_MASK 0x007FF 3991 #define CURSOR_POS_SIGN 0x8000 3992 #define CURSOR_X_SHIFT 0 3993 #define CURSOR_Y_SHIFT 16 3994 #define CURSIZE 0x700a0 3995 #define _CURBCNTR 0x700c0 3996 #define _CURBBASE 0x700c4 3997 #define _CURBPOS 0x700c8 3998 3999 #define _CURBCNTR_IVB 0x71080 4000 #define _CURBBASE_IVB 0x71084 4001 #define _CURBPOS_IVB 0x71088 4002 4003 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ 4004 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 4005 dev_priv->info.display_mmio_offset) 4006 4007 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 4008 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 4009 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 4010 4011 #define CURSOR_A_OFFSET 0x70080 4012 #define CURSOR_B_OFFSET 0x700c0 4013 #define CHV_CURSOR_C_OFFSET 0x700e0 4014 #define IVB_CURSOR_B_OFFSET 0x71080 4015 #define IVB_CURSOR_C_OFFSET 0x72080 4016 4017 /* Display A control */ 4018 #define _DSPACNTR 0x70180 4019 #define DISPLAY_PLANE_ENABLE (1<<31) 4020 #define DISPLAY_PLANE_DISABLE 0 4021 #define DISPPLANE_GAMMA_ENABLE (1<<30) 4022 #define DISPPLANE_GAMMA_DISABLE 0 4023 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 4024 #define DISPPLANE_YUV422 (0x0<<26) 4025 #define DISPPLANE_8BPP (0x2<<26) 4026 #define DISPPLANE_BGRA555 (0x3<<26) 4027 #define DISPPLANE_BGRX555 (0x4<<26) 4028 #define DISPPLANE_BGRX565 (0x5<<26) 4029 #define DISPPLANE_BGRX888 (0x6<<26) 4030 #define DISPPLANE_BGRA888 (0x7<<26) 4031 #define DISPPLANE_RGBX101010 (0x8<<26) 4032 #define DISPPLANE_RGBA101010 (0x9<<26) 4033 #define DISPPLANE_BGRX101010 (0xa<<26) 4034 #define DISPPLANE_RGBX161616 (0xc<<26) 4035 #define DISPPLANE_RGBX888 (0xe<<26) 4036 #define DISPPLANE_RGBA888 (0xf<<26) 4037 #define DISPPLANE_STEREO_ENABLE (1<<25) 4038 #define DISPPLANE_STEREO_DISABLE 0 4039 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 4040 #define DISPPLANE_SEL_PIPE_SHIFT 24 4041 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 4042 #define DISPPLANE_SEL_PIPE_A 0 4043 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 4044 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 4045 #define DISPPLANE_SRC_KEY_DISABLE 0 4046 #define DISPPLANE_LINE_DOUBLE (1<<20) 4047 #define DISPPLANE_NO_LINE_DOUBLE 0 4048 #define DISPPLANE_STEREO_POLARITY_FIRST 0 4049 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 4050 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 4051 #define DISPPLANE_TILED (1<<10) 4052 #define _DSPAADDR 0x70184 4053 #define _DSPASTRIDE 0x70188 4054 #define _DSPAPOS 0x7018C /* reserved */ 4055 #define _DSPASIZE 0x70190 4056 #define _DSPASURF 0x7019C /* 965+ only */ 4057 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4058 #define _DSPAOFFSET 0x701A4 /* HSW */ 4059 #define _DSPASURFLIVE 0x701AC 4060 4061 #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) 4062 #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) 4063 #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) 4064 #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) 4065 #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) 4066 #define DSPSURF(plane) _PIPE2(plane, _DSPASURF) 4067 #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) 4068 #define DSPLINOFF(plane) DSPADDR(plane) 4069 #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) 4070 #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) 4071 4072 /* Display/Sprite base address macros */ 4073 #define DISP_BASEADDR_MASK (0xfffff000) 4074 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 4075 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 4076 4077 /* VBIOS flags */ 4078 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) 4079 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) 4080 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) 4081 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) 4082 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) 4083 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) 4084 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) 4085 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) 4086 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) 4087 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) 4088 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) 4089 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) 4090 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) 4091 4092 /* Pipe B */ 4093 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 4094 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 4095 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 4096 #define _PIPEBFRAMEHIGH 0x71040 4097 #define _PIPEBFRAMEPIXEL 0x71044 4098 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) 4099 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) 4100 4101 4102 /* Display B control */ 4103 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 4104 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 4105 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 4106 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 4107 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 4108 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 4109 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 4110 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 4111 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 4112 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 4113 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 4114 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 4115 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 4116 4117 /* Sprite A control */ 4118 #define _DVSACNTR 0x72180 4119 #define DVS_ENABLE (1<<31) 4120 #define DVS_GAMMA_ENABLE (1<<30) 4121 #define DVS_PIXFORMAT_MASK (3<<25) 4122 #define DVS_FORMAT_YUV422 (0<<25) 4123 #define DVS_FORMAT_RGBX101010 (1<<25) 4124 #define DVS_FORMAT_RGBX888 (2<<25) 4125 #define DVS_FORMAT_RGBX161616 (3<<25) 4126 #define DVS_PIPE_CSC_ENABLE (1<<24) 4127 #define DVS_SOURCE_KEY (1<<22) 4128 #define DVS_RGB_ORDER_XBGR (1<<20) 4129 #define DVS_YUV_BYTE_ORDER_MASK (3<<16) 4130 #define DVS_YUV_ORDER_YUYV (0<<16) 4131 #define DVS_YUV_ORDER_UYVY (1<<16) 4132 #define DVS_YUV_ORDER_YVYU (2<<16) 4133 #define DVS_YUV_ORDER_VYUY (3<<16) 4134 #define DVS_DEST_KEY (1<<2) 4135 #define DVS_TRICKLE_FEED_DISABLE (1<<14) 4136 #define DVS_TILED (1<<10) 4137 #define _DVSALINOFF 0x72184 4138 #define _DVSASTRIDE 0x72188 4139 #define _DVSAPOS 0x7218c 4140 #define _DVSASIZE 0x72190 4141 #define _DVSAKEYVAL 0x72194 4142 #define _DVSAKEYMSK 0x72198 4143 #define _DVSASURF 0x7219c 4144 #define _DVSAKEYMAXVAL 0x721a0 4145 #define _DVSATILEOFF 0x721a4 4146 #define _DVSASURFLIVE 0x721ac 4147 #define _DVSASCALE 0x72204 4148 #define DVS_SCALE_ENABLE (1<<31) 4149 #define DVS_FILTER_MASK (3<<29) 4150 #define DVS_FILTER_MEDIUM (0<<29) 4151 #define DVS_FILTER_ENHANCING (1<<29) 4152 #define DVS_FILTER_SOFTENING (2<<29) 4153 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4154 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 4155 #define _DVSAGAMC 0x72300 4156 4157 #define _DVSBCNTR 0x73180 4158 #define _DVSBLINOFF 0x73184 4159 #define _DVSBSTRIDE 0x73188 4160 #define _DVSBPOS 0x7318c 4161 #define _DVSBSIZE 0x73190 4162 #define _DVSBKEYVAL 0x73194 4163 #define _DVSBKEYMSK 0x73198 4164 #define _DVSBSURF 0x7319c 4165 #define _DVSBKEYMAXVAL 0x731a0 4166 #define _DVSBTILEOFF 0x731a4 4167 #define _DVSBSURFLIVE 0x731ac 4168 #define _DVSBSCALE 0x73204 4169 #define _DVSBGAMC 0x73300 4170 4171 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4172 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4173 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4174 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 4175 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 4176 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4177 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4178 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4179 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4180 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4181 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4182 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4183 4184 #define _SPRA_CTL 0x70280 4185 #define SPRITE_ENABLE (1<<31) 4186 #define SPRITE_GAMMA_ENABLE (1<<30) 4187 #define SPRITE_PIXFORMAT_MASK (7<<25) 4188 #define SPRITE_FORMAT_YUV422 (0<<25) 4189 #define SPRITE_FORMAT_RGBX101010 (1<<25) 4190 #define SPRITE_FORMAT_RGBX888 (2<<25) 4191 #define SPRITE_FORMAT_RGBX161616 (3<<25) 4192 #define SPRITE_FORMAT_YUV444 (4<<25) 4193 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 4194 #define SPRITE_PIPE_CSC_ENABLE (1<<24) 4195 #define SPRITE_SOURCE_KEY (1<<22) 4196 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 4197 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 4198 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 4199 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 4200 #define SPRITE_YUV_ORDER_YUYV (0<<16) 4201 #define SPRITE_YUV_ORDER_UYVY (1<<16) 4202 #define SPRITE_YUV_ORDER_YVYU (2<<16) 4203 #define SPRITE_YUV_ORDER_VYUY (3<<16) 4204 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 4205 #define SPRITE_INT_GAMMA_ENABLE (1<<13) 4206 #define SPRITE_TILED (1<<10) 4207 #define SPRITE_DEST_KEY (1<<2) 4208 #define _SPRA_LINOFF 0x70284 4209 #define _SPRA_STRIDE 0x70288 4210 #define _SPRA_POS 0x7028c 4211 #define _SPRA_SIZE 0x70290 4212 #define _SPRA_KEYVAL 0x70294 4213 #define _SPRA_KEYMSK 0x70298 4214 #define _SPRA_SURF 0x7029c 4215 #define _SPRA_KEYMAX 0x702a0 4216 #define _SPRA_TILEOFF 0x702a4 4217 #define _SPRA_OFFSET 0x702a4 4218 #define _SPRA_SURFLIVE 0x702ac 4219 #define _SPRA_SCALE 0x70304 4220 #define SPRITE_SCALE_ENABLE (1<<31) 4221 #define SPRITE_FILTER_MASK (3<<29) 4222 #define SPRITE_FILTER_MEDIUM (0<<29) 4223 #define SPRITE_FILTER_ENHANCING (1<<29) 4224 #define SPRITE_FILTER_SOFTENING (2<<29) 4225 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4226 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 4227 #define _SPRA_GAMC 0x70400 4228 4229 #define _SPRB_CTL 0x71280 4230 #define _SPRB_LINOFF 0x71284 4231 #define _SPRB_STRIDE 0x71288 4232 #define _SPRB_POS 0x7128c 4233 #define _SPRB_SIZE 0x71290 4234 #define _SPRB_KEYVAL 0x71294 4235 #define _SPRB_KEYMSK 0x71298 4236 #define _SPRB_SURF 0x7129c 4237 #define _SPRB_KEYMAX 0x712a0 4238 #define _SPRB_TILEOFF 0x712a4 4239 #define _SPRB_OFFSET 0x712a4 4240 #define _SPRB_SURFLIVE 0x712ac 4241 #define _SPRB_SCALE 0x71304 4242 #define _SPRB_GAMC 0x71400 4243 4244 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4245 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4246 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4247 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 4248 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4249 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4250 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4251 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4252 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4253 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4254 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4255 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4256 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 4257 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4258 4259 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4260 #define SP_ENABLE (1<<31) 4261 #define SP_GAMMA_ENABLE (1<<30) 4262 #define SP_PIXFORMAT_MASK (0xf<<26) 4263 #define SP_FORMAT_YUV422 (0<<26) 4264 #define SP_FORMAT_BGR565 (5<<26) 4265 #define SP_FORMAT_BGRX8888 (6<<26) 4266 #define SP_FORMAT_BGRA8888 (7<<26) 4267 #define SP_FORMAT_RGBX1010102 (8<<26) 4268 #define SP_FORMAT_RGBA1010102 (9<<26) 4269 #define SP_FORMAT_RGBX8888 (0xe<<26) 4270 #define SP_FORMAT_RGBA8888 (0xf<<26) 4271 #define SP_SOURCE_KEY (1<<22) 4272 #define SP_YUV_BYTE_ORDER_MASK (3<<16) 4273 #define SP_YUV_ORDER_YUYV (0<<16) 4274 #define SP_YUV_ORDER_UYVY (1<<16) 4275 #define SP_YUV_ORDER_YVYU (2<<16) 4276 #define SP_YUV_ORDER_VYUY (3<<16) 4277 #define SP_TILED (1<<10) 4278 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4279 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4280 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4281 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4282 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4283 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4284 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4285 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4286 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4287 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4288 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 4289 4290 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4291 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4292 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4293 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4294 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4295 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4296 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4297 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4298 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4299 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4300 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4301 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 4302 4303 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) 4304 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) 4305 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) 4306 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) 4307 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) 4308 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) 4309 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) 4310 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) 4311 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4312 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) 4313 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) 4314 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) 4315 4316 /* VBIOS regs */ 4317 #define VGACNTRL 0x71400 4318 # define VGA_DISP_DISABLE (1 << 31) 4319 # define VGA_2X_MODE (1 << 30) 4320 # define VGA_PIPE_B_SELECT (1 << 29) 4321 4322 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) 4323 4324 /* Ironlake */ 4325 4326 #define CPU_VGACNTRL 0x41000 4327 4328 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 4329 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 4330 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 4331 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 4332 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 4333 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 4334 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 4335 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 4336 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 4337 4338 /* refresh rate hardware control */ 4339 #define RR_HW_CTL 0x45300 4340 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 4341 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 4342 4343 #define FDI_PLL_BIOS_0 0x46000 4344 #define FDI_PLL_FB_CLOCK_MASK 0xff 4345 #define FDI_PLL_BIOS_1 0x46004 4346 #define FDI_PLL_BIOS_2 0x46008 4347 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 4348 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 4349 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 4350 4351 #define PCH_3DCGDIS0 0x46020 4352 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 4353 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 4354 4355 #define PCH_3DCGDIS1 0x46024 4356 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 4357 4358 #define FDI_PLL_FREQ_CTL 0x46030 4359 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 4360 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 4361 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 4362 4363 4364 #define _PIPEA_DATA_M1 0x60030 4365 #define PIPE_DATA_M1_OFFSET 0 4366 #define _PIPEA_DATA_N1 0x60034 4367 #define PIPE_DATA_N1_OFFSET 0 4368 4369 #define _PIPEA_DATA_M2 0x60038 4370 #define PIPE_DATA_M2_OFFSET 0 4371 #define _PIPEA_DATA_N2 0x6003c 4372 #define PIPE_DATA_N2_OFFSET 0 4373 4374 #define _PIPEA_LINK_M1 0x60040 4375 #define PIPE_LINK_M1_OFFSET 0 4376 #define _PIPEA_LINK_N1 0x60044 4377 #define PIPE_LINK_N1_OFFSET 0 4378 4379 #define _PIPEA_LINK_M2 0x60048 4380 #define PIPE_LINK_M2_OFFSET 0 4381 #define _PIPEA_LINK_N2 0x6004c 4382 #define PIPE_LINK_N2_OFFSET 0 4383 4384 /* PIPEB timing regs are same start from 0x61000 */ 4385 4386 #define _PIPEB_DATA_M1 0x61030 4387 #define _PIPEB_DATA_N1 0x61034 4388 #define _PIPEB_DATA_M2 0x61038 4389 #define _PIPEB_DATA_N2 0x6103c 4390 #define _PIPEB_LINK_M1 0x61040 4391 #define _PIPEB_LINK_N1 0x61044 4392 #define _PIPEB_LINK_M2 0x61048 4393 #define _PIPEB_LINK_N2 0x6104c 4394 4395 #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) 4396 #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) 4397 #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) 4398 #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) 4399 #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) 4400 #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) 4401 #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) 4402 #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) 4403 4404 /* CPU panel fitter */ 4405 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 4406 #define _PFA_CTL_1 0x68080 4407 #define _PFB_CTL_1 0x68880 4408 #define PF_ENABLE (1<<31) 4409 #define PF_PIPE_SEL_MASK_IVB (3<<29) 4410 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 4411 #define PF_FILTER_MASK (3<<23) 4412 #define PF_FILTER_PROGRAMMED (0<<23) 4413 #define PF_FILTER_MED_3x3 (1<<23) 4414 #define PF_FILTER_EDGE_ENHANCE (2<<23) 4415 #define PF_FILTER_EDGE_SOFTEN (3<<23) 4416 #define _PFA_WIN_SZ 0x68074 4417 #define _PFB_WIN_SZ 0x68874 4418 #define _PFA_WIN_POS 0x68070 4419 #define _PFB_WIN_POS 0x68870 4420 #define _PFA_VSCALE 0x68084 4421 #define _PFB_VSCALE 0x68884 4422 #define _PFA_HSCALE 0x68090 4423 #define _PFB_HSCALE 0x68890 4424 4425 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 4426 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 4427 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 4428 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 4429 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 4430 4431 /* legacy palette */ 4432 #define _LGC_PALETTE_A 0x4a000 4433 #define _LGC_PALETTE_B 0x4a800 4434 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 4435 4436 #define _GAMMA_MODE_A 0x4a480 4437 #define _GAMMA_MODE_B 0x4ac80 4438 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 4439 #define GAMMA_MODE_MODE_MASK (3 << 0) 4440 #define GAMMA_MODE_MODE_8BIT (0 << 0) 4441 #define GAMMA_MODE_MODE_10BIT (1 << 0) 4442 #define GAMMA_MODE_MODE_12BIT (2 << 0) 4443 #define GAMMA_MODE_MODE_SPLIT (3 << 0) 4444 4445 /* interrupts */ 4446 #define DE_MASTER_IRQ_CONTROL (1 << 31) 4447 #define DE_SPRITEB_FLIP_DONE (1 << 29) 4448 #define DE_SPRITEA_FLIP_DONE (1 << 28) 4449 #define DE_PLANEB_FLIP_DONE (1 << 27) 4450 #define DE_PLANEA_FLIP_DONE (1 << 26) 4451 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 4452 #define DE_PCU_EVENT (1 << 25) 4453 #define DE_GTT_FAULT (1 << 24) 4454 #define DE_POISON (1 << 23) 4455 #define DE_PERFORM_COUNTER (1 << 22) 4456 #define DE_PCH_EVENT (1 << 21) 4457 #define DE_AUX_CHANNEL_A (1 << 20) 4458 #define DE_DP_A_HOTPLUG (1 << 19) 4459 #define DE_GSE (1 << 18) 4460 #define DE_PIPEB_VBLANK (1 << 15) 4461 #define DE_PIPEB_EVEN_FIELD (1 << 14) 4462 #define DE_PIPEB_ODD_FIELD (1 << 13) 4463 #define DE_PIPEB_LINE_COMPARE (1 << 12) 4464 #define DE_PIPEB_VSYNC (1 << 11) 4465 #define DE_PIPEB_CRC_DONE (1 << 10) 4466 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 4467 #define DE_PIPEA_VBLANK (1 << 7) 4468 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 4469 #define DE_PIPEA_EVEN_FIELD (1 << 6) 4470 #define DE_PIPEA_ODD_FIELD (1 << 5) 4471 #define DE_PIPEA_LINE_COMPARE (1 << 4) 4472 #define DE_PIPEA_VSYNC (1 << 3) 4473 #define DE_PIPEA_CRC_DONE (1 << 2) 4474 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 4475 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 4476 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 4477 4478 /* More Ivybridge lolz */ 4479 #define DE_ERR_INT_IVB (1<<30) 4480 #define DE_GSE_IVB (1<<29) 4481 #define DE_PCH_EVENT_IVB (1<<28) 4482 #define DE_DP_A_HOTPLUG_IVB (1<<27) 4483 #define DE_AUX_CHANNEL_A_IVB (1<<26) 4484 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 4485 #define DE_PLANEC_FLIP_DONE_IVB (1<<13) 4486 #define DE_PIPEC_VBLANK_IVB (1<<10) 4487 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 4488 #define DE_PLANEB_FLIP_DONE_IVB (1<<8) 4489 #define DE_PIPEB_VBLANK_IVB (1<<5) 4490 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 4491 #define DE_PLANEA_FLIP_DONE_IVB (1<<3) 4492 #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 4493 #define DE_PIPEA_VBLANK_IVB (1<<0) 4494 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) 4495 4496 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 4497 #define MASTER_INTERRUPT_ENABLE (1<<31) 4498 4499 #define DEISR 0x44000 4500 #define DEIMR 0x44004 4501 #define DEIIR 0x44008 4502 #define DEIER 0x4400c 4503 4504 #define GTISR 0x44010 4505 #define GTIMR 0x44014 4506 #define GTIIR 0x44018 4507 #define GTIER 0x4401c 4508 4509 #define GEN8_MASTER_IRQ 0x44200 4510 #define GEN8_MASTER_IRQ_CONTROL (1<<31) 4511 #define GEN8_PCU_IRQ (1<<30) 4512 #define GEN8_DE_PCH_IRQ (1<<23) 4513 #define GEN8_DE_MISC_IRQ (1<<22) 4514 #define GEN8_DE_PORT_IRQ (1<<20) 4515 #define GEN8_DE_PIPE_C_IRQ (1<<18) 4516 #define GEN8_DE_PIPE_B_IRQ (1<<17) 4517 #define GEN8_DE_PIPE_A_IRQ (1<<16) 4518 #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) 4519 #define GEN8_GT_VECS_IRQ (1<<6) 4520 #define GEN8_GT_PM_IRQ (1<<4) 4521 #define GEN8_GT_VCS2_IRQ (1<<3) 4522 #define GEN8_GT_VCS1_IRQ (1<<2) 4523 #define GEN8_GT_BCS_IRQ (1<<1) 4524 #define GEN8_GT_RCS_IRQ (1<<0) 4525 4526 #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) 4527 #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) 4528 #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) 4529 #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) 4530 4531 #define GEN8_BCS_IRQ_SHIFT 16 4532 #define GEN8_RCS_IRQ_SHIFT 0 4533 #define GEN8_VCS2_IRQ_SHIFT 16 4534 #define GEN8_VCS1_IRQ_SHIFT 0 4535 #define GEN8_VECS_IRQ_SHIFT 0 4536 4537 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) 4538 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) 4539 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) 4540 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) 4541 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 4542 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 4543 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 4544 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 4545 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 4546 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 4547 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 4548 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 4549 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 4550 #define GEN8_PIPE_VSYNC (1 << 1) 4551 #define GEN8_PIPE_VBLANK (1 << 0) 4552 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 4553 (GEN8_PIPE_CURSOR_FAULT | \ 4554 GEN8_PIPE_SPRITE_FAULT | \ 4555 GEN8_PIPE_PRIMARY_FAULT) 4556 4557 #define GEN8_DE_PORT_ISR 0x44440 4558 #define GEN8_DE_PORT_IMR 0x44444 4559 #define GEN8_DE_PORT_IIR 0x44448 4560 #define GEN8_DE_PORT_IER 0x4444c 4561 #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 4562 #define GEN8_AUX_CHANNEL_A (1 << 0) 4563 4564 #define GEN8_DE_MISC_ISR 0x44460 4565 #define GEN8_DE_MISC_IMR 0x44464 4566 #define GEN8_DE_MISC_IIR 0x44468 4567 #define GEN8_DE_MISC_IER 0x4446c 4568 #define GEN8_DE_MISC_GSE (1 << 27) 4569 4570 #define GEN8_PCU_ISR 0x444e0 4571 #define GEN8_PCU_IMR 0x444e4 4572 #define GEN8_PCU_IIR 0x444e8 4573 #define GEN8_PCU_IER 0x444ec 4574 4575 #define ILK_DISPLAY_CHICKEN2 0x42004 4576 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 4577 #define ILK_ELPIN_409_SELECT (1 << 25) 4578 #define ILK_DPARB_GATE (1<<22) 4579 #define ILK_VSDPFD_FULL (1<<21) 4580 #define FUSE_STRAP 0x42014 4581 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 4582 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 4583 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 4584 #define ILK_HDCP_DISABLE (1 << 25) 4585 #define ILK_eDP_A_DISABLE (1 << 24) 4586 #define HSW_CDCLK_LIMIT (1 << 24) 4587 #define ILK_DESKTOP (1 << 23) 4588 4589 #define ILK_DSPCLK_GATE_D 0x42020 4590 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 4591 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 4592 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 4593 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 4594 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 4595 4596 #define IVB_CHICKEN3 0x4200c 4597 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 4598 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 4599 4600 #define CHICKEN_PAR1_1 0x42080 4601 #define DPA_MASK_VBLANK_SRD (1 << 15) 4602 #define FORCE_ARB_IDLE_PLANES (1 << 14) 4603 4604 #define _CHICKEN_PIPESL_1_A 0x420b0 4605 #define _CHICKEN_PIPESL_1_B 0x420b4 4606 #define HSW_FBCQ_DIS (1 << 22) 4607 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 4608 #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 4609 4610 #define DISP_ARB_CTL 0x45000 4611 #define DISP_TILE_SURFACE_SWIZZLING (1<<13) 4612 #define DISP_FBC_WM_DIS (1<<15) 4613 #define DISP_ARB_CTL2 0x45004 4614 #define DISP_DATA_PARTITION_5_6 (1<<6) 4615 #define GEN7_MSG_CTL 0x45010 4616 #define WAIT_FOR_PCH_RESET_ACK (1<<1) 4617 #define WAIT_FOR_PCH_FLR_ACK (1<<0) 4618 #define HSW_NDE_RSTWRN_OPT 0x46408 4619 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 4620 4621 /* GEN7 chicken */ 4622 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 4623 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 4624 #define COMMON_SLICE_CHICKEN2 0x7014 4625 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 4626 4627 #define GEN7_L3SQCREG1 0xB010 4628 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 4629 4630 #define GEN7_L3CNTLREG1 0xB01C 4631 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 4632 #define GEN7_L3AGDIS (1<<19) 4633 4634 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 4635 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 4636 4637 #define GEN7_L3SQCREG4 0xb034 4638 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 4639 4640 /* GEN8 chicken */ 4641 #define HDC_CHICKEN0 0x7300 4642 #define HDC_FORCE_NON_COHERENT (1<<4) 4643 4644 /* WaCatErrorRejectionIssue */ 4645 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 4646 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 4647 4648 #define HSW_SCRATCH1 0xb038 4649 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 4650 4651 /* PCH */ 4652 4653 /* south display engine interrupt: IBX */ 4654 #define SDE_AUDIO_POWER_D (1 << 27) 4655 #define SDE_AUDIO_POWER_C (1 << 26) 4656 #define SDE_AUDIO_POWER_B (1 << 25) 4657 #define SDE_AUDIO_POWER_SHIFT (25) 4658 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 4659 #define SDE_GMBUS (1 << 24) 4660 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 4661 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 4662 #define SDE_AUDIO_HDCP_MASK (3 << 22) 4663 #define SDE_AUDIO_TRANSB (1 << 21) 4664 #define SDE_AUDIO_TRANSA (1 << 20) 4665 #define SDE_AUDIO_TRANS_MASK (3 << 20) 4666 #define SDE_POISON (1 << 19) 4667 /* 18 reserved */ 4668 #define SDE_FDI_RXB (1 << 17) 4669 #define SDE_FDI_RXA (1 << 16) 4670 #define SDE_FDI_MASK (3 << 16) 4671 #define SDE_AUXD (1 << 15) 4672 #define SDE_AUXC (1 << 14) 4673 #define SDE_AUXB (1 << 13) 4674 #define SDE_AUX_MASK (7 << 13) 4675 /* 12 reserved */ 4676 #define SDE_CRT_HOTPLUG (1 << 11) 4677 #define SDE_PORTD_HOTPLUG (1 << 10) 4678 #define SDE_PORTC_HOTPLUG (1 << 9) 4679 #define SDE_PORTB_HOTPLUG (1 << 8) 4680 #define SDE_SDVOB_HOTPLUG (1 << 6) 4681 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 4682 SDE_SDVOB_HOTPLUG | \ 4683 SDE_PORTB_HOTPLUG | \ 4684 SDE_PORTC_HOTPLUG | \ 4685 SDE_PORTD_HOTPLUG) 4686 #define SDE_TRANSB_CRC_DONE (1 << 5) 4687 #define SDE_TRANSB_CRC_ERR (1 << 4) 4688 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 4689 #define SDE_TRANSA_CRC_DONE (1 << 2) 4690 #define SDE_TRANSA_CRC_ERR (1 << 1) 4691 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 4692 #define SDE_TRANS_MASK (0x3f) 4693 4694 /* south display engine interrupt: CPT/PPT */ 4695 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 4696 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 4697 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 4698 #define SDE_AUDIO_POWER_SHIFT_CPT 29 4699 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 4700 #define SDE_AUXD_CPT (1 << 27) 4701 #define SDE_AUXC_CPT (1 << 26) 4702 #define SDE_AUXB_CPT (1 << 25) 4703 #define SDE_AUX_MASK_CPT (7 << 25) 4704 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 4705 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 4706 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 4707 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 4708 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 4709 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 4710 SDE_SDVOB_HOTPLUG_CPT | \ 4711 SDE_PORTD_HOTPLUG_CPT | \ 4712 SDE_PORTC_HOTPLUG_CPT | \ 4713 SDE_PORTB_HOTPLUG_CPT) 4714 #define SDE_GMBUS_CPT (1 << 17) 4715 #define SDE_ERROR_CPT (1 << 16) 4716 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 4717 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 4718 #define SDE_FDI_RXC_CPT (1 << 8) 4719 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 4720 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 4721 #define SDE_FDI_RXB_CPT (1 << 4) 4722 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 4723 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 4724 #define SDE_FDI_RXA_CPT (1 << 0) 4725 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 4726 SDE_AUDIO_CP_REQ_B_CPT | \ 4727 SDE_AUDIO_CP_REQ_A_CPT) 4728 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 4729 SDE_AUDIO_CP_CHG_B_CPT | \ 4730 SDE_AUDIO_CP_CHG_A_CPT) 4731 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 4732 SDE_FDI_RXB_CPT | \ 4733 SDE_FDI_RXA_CPT) 4734 4735 #define SDEISR 0xc4000 4736 #define SDEIMR 0xc4004 4737 #define SDEIIR 0xc4008 4738 #define SDEIER 0xc400c 4739 4740 #define SERR_INT 0xc4040 4741 #define SERR_INT_POISON (1<<31) 4742 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 4743 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 4744 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 4745 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 4746 4747 /* digital port hotplug */ 4748 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 4749 #define PORTD_HOTPLUG_ENABLE (1 << 20) 4750 #define PORTD_PULSE_DURATION_2ms (0) 4751 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 4752 #define PORTD_PULSE_DURATION_6ms (2 << 18) 4753 #define PORTD_PULSE_DURATION_100ms (3 << 18) 4754 #define PORTD_PULSE_DURATION_MASK (3 << 18) 4755 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) 4756 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 4757 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 4758 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 4759 #define PORTC_HOTPLUG_ENABLE (1 << 12) 4760 #define PORTC_PULSE_DURATION_2ms (0) 4761 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 4762 #define PORTC_PULSE_DURATION_6ms (2 << 10) 4763 #define PORTC_PULSE_DURATION_100ms (3 << 10) 4764 #define PORTC_PULSE_DURATION_MASK (3 << 10) 4765 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) 4766 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 4767 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 4768 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 4769 #define PORTB_HOTPLUG_ENABLE (1 << 4) 4770 #define PORTB_PULSE_DURATION_2ms (0) 4771 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 4772 #define PORTB_PULSE_DURATION_6ms (2 << 2) 4773 #define PORTB_PULSE_DURATION_100ms (3 << 2) 4774 #define PORTB_PULSE_DURATION_MASK (3 << 2) 4775 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) 4776 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 4777 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 4778 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 4779 4780 #define PCH_GPIOA 0xc5010 4781 #define PCH_GPIOB 0xc5014 4782 #define PCH_GPIOC 0xc5018 4783 #define PCH_GPIOD 0xc501c 4784 #define PCH_GPIOE 0xc5020 4785 #define PCH_GPIOF 0xc5024 4786 4787 #define PCH_GMBUS0 0xc5100 4788 #define PCH_GMBUS1 0xc5104 4789 #define PCH_GMBUS2 0xc5108 4790 #define PCH_GMBUS3 0xc510c 4791 #define PCH_GMBUS4 0xc5110 4792 #define PCH_GMBUS5 0xc5120 4793 4794 #define _PCH_DPLL_A 0xc6014 4795 #define _PCH_DPLL_B 0xc6018 4796 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 4797 4798 #define _PCH_FPA0 0xc6040 4799 #define FP_CB_TUNE (0x3<<22) 4800 #define _PCH_FPA1 0xc6044 4801 #define _PCH_FPB0 0xc6048 4802 #define _PCH_FPB1 0xc604c 4803 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 4804 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 4805 4806 #define PCH_DPLL_TEST 0xc606c 4807 4808 #define PCH_DREF_CONTROL 0xC6200 4809 #define DREF_CONTROL_MASK 0x7fc3 4810 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 4811 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 4812 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 4813 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 4814 #define DREF_SSC_SOURCE_DISABLE (0<<11) 4815 #define DREF_SSC_SOURCE_ENABLE (2<<11) 4816 #define DREF_SSC_SOURCE_MASK (3<<11) 4817 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 4818 #define DREF_NONSPREAD_CK505_ENABLE (1<<9) 4819 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 4820 #define DREF_NONSPREAD_SOURCE_MASK (3<<9) 4821 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 4822 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 4823 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 4824 #define DREF_SSC4_DOWNSPREAD (0<<6) 4825 #define DREF_SSC4_CENTERSPREAD (1<<6) 4826 #define DREF_SSC1_DISABLE (0<<1) 4827 #define DREF_SSC1_ENABLE (1<<1) 4828 #define DREF_SSC4_DISABLE (0) 4829 #define DREF_SSC4_ENABLE (1) 4830 4831 #define PCH_RAWCLK_FREQ 0xc6204 4832 #define FDL_TP1_TIMER_SHIFT 12 4833 #define FDL_TP1_TIMER_MASK (3<<12) 4834 #define FDL_TP2_TIMER_SHIFT 10 4835 #define FDL_TP2_TIMER_MASK (3<<10) 4836 #define RAWCLK_FREQ_MASK 0x3ff 4837 4838 #define PCH_DPLL_TMR_CFG 0xc6208 4839 4840 #define PCH_SSC4_PARMS 0xc6210 4841 #define PCH_SSC4_AUX_PARMS 0xc6214 4842 4843 #define PCH_DPLL_SEL 0xc7000 4844 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) 4845 #define TRANS_DPLLA_SEL(pipe) 0 4846 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) 4847 4848 /* transcoder */ 4849 4850 #define _PCH_TRANS_HTOTAL_A 0xe0000 4851 #define TRANS_HTOTAL_SHIFT 16 4852 #define TRANS_HACTIVE_SHIFT 0 4853 #define _PCH_TRANS_HBLANK_A 0xe0004 4854 #define TRANS_HBLANK_END_SHIFT 16 4855 #define TRANS_HBLANK_START_SHIFT 0 4856 #define _PCH_TRANS_HSYNC_A 0xe0008 4857 #define TRANS_HSYNC_END_SHIFT 16 4858 #define TRANS_HSYNC_START_SHIFT 0 4859 #define _PCH_TRANS_VTOTAL_A 0xe000c 4860 #define TRANS_VTOTAL_SHIFT 16 4861 #define TRANS_VACTIVE_SHIFT 0 4862 #define _PCH_TRANS_VBLANK_A 0xe0010 4863 #define TRANS_VBLANK_END_SHIFT 16 4864 #define TRANS_VBLANK_START_SHIFT 0 4865 #define _PCH_TRANS_VSYNC_A 0xe0014 4866 #define TRANS_VSYNC_END_SHIFT 16 4867 #define TRANS_VSYNC_START_SHIFT 0 4868 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 4869 4870 #define _PCH_TRANSA_DATA_M1 0xe0030 4871 #define _PCH_TRANSA_DATA_N1 0xe0034 4872 #define _PCH_TRANSA_DATA_M2 0xe0038 4873 #define _PCH_TRANSA_DATA_N2 0xe003c 4874 #define _PCH_TRANSA_LINK_M1 0xe0040 4875 #define _PCH_TRANSA_LINK_N1 0xe0044 4876 #define _PCH_TRANSA_LINK_M2 0xe0048 4877 #define _PCH_TRANSA_LINK_N2 0xe004c 4878 4879 /* Per-transcoder DIP controls */ 4880 4881 #define _VIDEO_DIP_CTL_A 0xe0200 4882 #define _VIDEO_DIP_DATA_A 0xe0208 4883 #define _VIDEO_DIP_GCP_A 0xe0210 4884 4885 #define _VIDEO_DIP_CTL_B 0xe1200 4886 #define _VIDEO_DIP_DATA_B 0xe1208 4887 #define _VIDEO_DIP_GCP_B 0xe1210 4888 4889 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 4890 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 4891 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 4892 4893 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 4894 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 4895 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 4896 4897 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 4898 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 4899 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 4900 4901 #define VLV_TVIDEO_DIP_CTL(pipe) \ 4902 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B) 4903 #define VLV_TVIDEO_DIP_DATA(pipe) \ 4904 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B) 4905 #define VLV_TVIDEO_DIP_GCP(pipe) \ 4906 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) 4907 4908 /* Haswell DIP controls */ 4909 #define HSW_VIDEO_DIP_CTL_A 0x60200 4910 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 4911 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 4912 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 4913 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 4914 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 4915 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 4916 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 4917 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 4918 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 4919 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 4920 #define HSW_VIDEO_DIP_GCP_A 0x60210 4921 4922 #define HSW_VIDEO_DIP_CTL_B 0x61200 4923 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 4924 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 4925 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 4926 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 4927 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 4928 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 4929 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 4930 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 4931 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 4932 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 4933 #define HSW_VIDEO_DIP_GCP_B 0x61210 4934 4935 #define HSW_TVIDEO_DIP_CTL(trans) \ 4936 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) 4937 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ 4938 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) 4939 #define HSW_TVIDEO_DIP_VS_DATA(trans) \ 4940 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) 4941 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ 4942 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) 4943 #define HSW_TVIDEO_DIP_GCP(trans) \ 4944 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) 4945 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ 4946 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) 4947 4948 #define HSW_STEREO_3D_CTL_A 0x70020 4949 #define S3D_ENABLE (1<<31) 4950 #define HSW_STEREO_3D_CTL_B 0x71020 4951 4952 #define HSW_STEREO_3D_CTL(trans) \ 4953 _PIPE2(trans, HSW_STEREO_3D_CTL_A) 4954 4955 #define _PCH_TRANS_HTOTAL_B 0xe1000 4956 #define _PCH_TRANS_HBLANK_B 0xe1004 4957 #define _PCH_TRANS_HSYNC_B 0xe1008 4958 #define _PCH_TRANS_VTOTAL_B 0xe100c 4959 #define _PCH_TRANS_VBLANK_B 0xe1010 4960 #define _PCH_TRANS_VSYNC_B 0xe1014 4961 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 4962 4963 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 4964 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 4965 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 4966 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 4967 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 4968 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 4969 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ 4970 _PCH_TRANS_VSYNCSHIFT_B) 4971 4972 #define _PCH_TRANSB_DATA_M1 0xe1030 4973 #define _PCH_TRANSB_DATA_N1 0xe1034 4974 #define _PCH_TRANSB_DATA_M2 0xe1038 4975 #define _PCH_TRANSB_DATA_N2 0xe103c 4976 #define _PCH_TRANSB_LINK_M1 0xe1040 4977 #define _PCH_TRANSB_LINK_N1 0xe1044 4978 #define _PCH_TRANSB_LINK_M2 0xe1048 4979 #define _PCH_TRANSB_LINK_N2 0xe104c 4980 4981 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 4982 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 4983 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 4984 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 4985 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 4986 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 4987 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 4988 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 4989 4990 #define _PCH_TRANSACONF 0xf0008 4991 #define _PCH_TRANSBCONF 0xf1008 4992 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 4993 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ 4994 #define TRANS_DISABLE (0<<31) 4995 #define TRANS_ENABLE (1<<31) 4996 #define TRANS_STATE_MASK (1<<30) 4997 #define TRANS_STATE_DISABLE (0<<30) 4998 #define TRANS_STATE_ENABLE (1<<30) 4999 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 5000 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 5001 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 5002 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 5003 #define TRANS_INTERLACE_MASK (7<<21) 5004 #define TRANS_PROGRESSIVE (0<<21) 5005 #define TRANS_INTERLACED (3<<21) 5006 #define TRANS_LEGACY_INTERLACED_ILK (2<<21) 5007 #define TRANS_8BPC (0<<5) 5008 #define TRANS_10BPC (1<<5) 5009 #define TRANS_6BPC (2<<5) 5010 #define TRANS_12BPC (3<<5) 5011 5012 #define _TRANSA_CHICKEN1 0xf0060 5013 #define _TRANSB_CHICKEN1 0xf1060 5014 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 5015 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 5016 #define _TRANSA_CHICKEN2 0xf0064 5017 #define _TRANSB_CHICKEN2 0xf1064 5018 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 5019 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 5020 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 5021 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 5022 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 5023 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 5024 5025 #define SOUTH_CHICKEN1 0xc2000 5026 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 5027 #define FDIA_PHASE_SYNC_SHIFT_EN 18 5028 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 5029 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 5030 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 5031 #define SOUTH_CHICKEN2 0xc2004 5032 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 5033 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 5034 #define DPLS_EDP_PPS_FIX_DIS (1<<0) 5035 5036 #define _FDI_RXA_CHICKEN 0xc200c 5037 #define _FDI_RXB_CHICKEN 0xc2010 5038 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 5039 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 5040 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 5041 5042 #define SOUTH_DSPCLK_GATE_D 0xc2020 5043 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 5044 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 5045 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 5046 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 5047 5048 /* CPU: FDI_TX */ 5049 #define _FDI_TXA_CTL 0x60100 5050 #define _FDI_TXB_CTL 0x61100 5051 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 5052 #define FDI_TX_DISABLE (0<<31) 5053 #define FDI_TX_ENABLE (1<<31) 5054 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 5055 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 5056 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 5057 #define FDI_LINK_TRAIN_NONE (3<<28) 5058 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 5059 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 5060 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 5061 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 5062 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 5063 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 5064 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 5065 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 5066 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 5067 SNB has different settings. */ 5068 /* SNB A-stepping */ 5069 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 5070 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 5071 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 5072 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 5073 /* SNB B-stepping */ 5074 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 5075 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 5076 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 5077 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 5078 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 5079 #define FDI_DP_PORT_WIDTH_SHIFT 19 5080 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 5081 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 5082 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 5083 /* Ironlake: hardwired to 1 */ 5084 #define FDI_TX_PLL_ENABLE (1<<14) 5085 5086 /* Ivybridge has different bits for lolz */ 5087 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 5088 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 5089 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 5090 #define FDI_LINK_TRAIN_NONE_IVB (3<<8) 5091 5092 /* both Tx and Rx */ 5093 #define FDI_COMPOSITE_SYNC (1<<11) 5094 #define FDI_LINK_TRAIN_AUTO (1<<10) 5095 #define FDI_SCRAMBLING_ENABLE (0<<7) 5096 #define FDI_SCRAMBLING_DISABLE (1<<7) 5097 5098 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 5099 #define _FDI_RXA_CTL 0xf000c 5100 #define _FDI_RXB_CTL 0xf100c 5101 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 5102 #define FDI_RX_ENABLE (1<<31) 5103 /* train, dp width same as FDI_TX */ 5104 #define FDI_FS_ERRC_ENABLE (1<<27) 5105 #define FDI_FE_ERRC_ENABLE (1<<26) 5106 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 5107 #define FDI_8BPC (0<<16) 5108 #define FDI_10BPC (1<<16) 5109 #define FDI_6BPC (2<<16) 5110 #define FDI_12BPC (3<<16) 5111 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 5112 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 5113 #define FDI_RX_PLL_ENABLE (1<<13) 5114 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 5115 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 5116 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 5117 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 5118 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 5119 #define FDI_PCDCLK (1<<4) 5120 /* CPT */ 5121 #define FDI_AUTO_TRAINING (1<<10) 5122 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 5123 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 5124 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 5125 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 5126 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 5127 5128 #define _FDI_RXA_MISC 0xf0010 5129 #define _FDI_RXB_MISC 0xf1010 5130 #define FDI_RX_PWRDN_LANE1_MASK (3<<26) 5131 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 5132 #define FDI_RX_PWRDN_LANE0_MASK (3<<24) 5133 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 5134 #define FDI_RX_TP1_TO_TP2_48 (2<<20) 5135 #define FDI_RX_TP1_TO_TP2_64 (3<<20) 5136 #define FDI_RX_FDI_DELAY_90 (0x90<<0) 5137 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 5138 5139 #define _FDI_RXA_TUSIZE1 0xf0030 5140 #define _FDI_RXA_TUSIZE2 0xf0038 5141 #define _FDI_RXB_TUSIZE1 0xf1030 5142 #define _FDI_RXB_TUSIZE2 0xf1038 5143 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 5144 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 5145 5146 /* FDI_RX interrupt register format */ 5147 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 5148 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 5149 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 5150 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 5151 #define FDI_RX_FS_CODE_ERR (1<<6) 5152 #define FDI_RX_FE_CODE_ERR (1<<5) 5153 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 5154 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 5155 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 5156 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 5157 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 5158 5159 #define _FDI_RXA_IIR 0xf0014 5160 #define _FDI_RXA_IMR 0xf0018 5161 #define _FDI_RXB_IIR 0xf1014 5162 #define _FDI_RXB_IMR 0xf1018 5163 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 5164 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 5165 5166 #define FDI_PLL_CTL_1 0xfe000 5167 #define FDI_PLL_CTL_2 0xfe004 5168 5169 #define PCH_LVDS 0xe1180 5170 #define LVDS_DETECTED (1 << 1) 5171 5172 /* vlv has 2 sets of panel control regs. */ 5173 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 5174 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 5175 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 5176 #define PANEL_PORT_SELECT_DPB_VLV (1 << 30) 5177 #define PANEL_PORT_SELECT_DPC_VLV (2 << 30) 5178 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 5179 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 5180 5181 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) 5182 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) 5183 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) 5184 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 5185 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 5186 5187 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) 5188 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) 5189 #define VLV_PIPE_PP_ON_DELAYS(pipe) \ 5190 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) 5191 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ 5192 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) 5193 #define VLV_PIPE_PP_DIVISOR(pipe) \ 5194 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) 5195 5196 #define PCH_PP_STATUS 0xc7200 5197 #define PCH_PP_CONTROL 0xc7204 5198 #define PANEL_UNLOCK_REGS (0xabcd << 16) 5199 #define PANEL_UNLOCK_MASK (0xffff << 16) 5200 #define EDP_FORCE_VDD (1 << 3) 5201 #define EDP_BLC_ENABLE (1 << 2) 5202 #define PANEL_POWER_RESET (1 << 1) 5203 #define PANEL_POWER_OFF (0 << 0) 5204 #define PANEL_POWER_ON (1 << 0) 5205 #define PCH_PP_ON_DELAYS 0xc7208 5206 #define PANEL_PORT_SELECT_MASK (3 << 30) 5207 #define PANEL_PORT_SELECT_LVDS (0 << 30) 5208 #define PANEL_PORT_SELECT_DPA (1 << 30) 5209 #define PANEL_PORT_SELECT_DPC (2 << 30) 5210 #define PANEL_PORT_SELECT_DPD (3 << 30) 5211 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 5212 #define PANEL_POWER_UP_DELAY_SHIFT 16 5213 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 5214 #define PANEL_LIGHT_ON_DELAY_SHIFT 0 5215 5216 #define PCH_PP_OFF_DELAYS 0xc720c 5217 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 5218 #define PANEL_POWER_DOWN_DELAY_SHIFT 16 5219 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 5220 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 5221 5222 #define PCH_PP_DIVISOR 0xc7210 5223 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 5224 #define PP_REFERENCE_DIVIDER_SHIFT 8 5225 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 5226 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 5227 5228 #define PCH_DP_B 0xe4100 5229 #define PCH_DPB_AUX_CH_CTL 0xe4110 5230 #define PCH_DPB_AUX_CH_DATA1 0xe4114 5231 #define PCH_DPB_AUX_CH_DATA2 0xe4118 5232 #define PCH_DPB_AUX_CH_DATA3 0xe411c 5233 #define PCH_DPB_AUX_CH_DATA4 0xe4120 5234 #define PCH_DPB_AUX_CH_DATA5 0xe4124 5235 5236 #define PCH_DP_C 0xe4200 5237 #define PCH_DPC_AUX_CH_CTL 0xe4210 5238 #define PCH_DPC_AUX_CH_DATA1 0xe4214 5239 #define PCH_DPC_AUX_CH_DATA2 0xe4218 5240 #define PCH_DPC_AUX_CH_DATA3 0xe421c 5241 #define PCH_DPC_AUX_CH_DATA4 0xe4220 5242 #define PCH_DPC_AUX_CH_DATA5 0xe4224 5243 5244 #define PCH_DP_D 0xe4300 5245 #define PCH_DPD_AUX_CH_CTL 0xe4310 5246 #define PCH_DPD_AUX_CH_DATA1 0xe4314 5247 #define PCH_DPD_AUX_CH_DATA2 0xe4318 5248 #define PCH_DPD_AUX_CH_DATA3 0xe431c 5249 #define PCH_DPD_AUX_CH_DATA4 0xe4320 5250 #define PCH_DPD_AUX_CH_DATA5 0xe4324 5251 5252 /* CPT */ 5253 #define PORT_TRANS_A_SEL_CPT 0 5254 #define PORT_TRANS_B_SEL_CPT (1<<29) 5255 #define PORT_TRANS_C_SEL_CPT (2<<29) 5256 #define PORT_TRANS_SEL_MASK (3<<29) 5257 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 5258 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 5259 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 5260 #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 5261 #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 5262 5263 #define TRANS_DP_CTL_A 0xe0300 5264 #define TRANS_DP_CTL_B 0xe1300 5265 #define TRANS_DP_CTL_C 0xe2300 5266 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) 5267 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 5268 #define TRANS_DP_PORT_SEL_B (0<<29) 5269 #define TRANS_DP_PORT_SEL_C (1<<29) 5270 #define TRANS_DP_PORT_SEL_D (2<<29) 5271 #define TRANS_DP_PORT_SEL_NONE (3<<29) 5272 #define TRANS_DP_PORT_SEL_MASK (3<<29) 5273 #define TRANS_DP_AUDIO_ONLY (1<<26) 5274 #define TRANS_DP_ENH_FRAMING (1<<18) 5275 #define TRANS_DP_8BPC (0<<9) 5276 #define TRANS_DP_10BPC (1<<9) 5277 #define TRANS_DP_6BPC (2<<9) 5278 #define TRANS_DP_12BPC (3<<9) 5279 #define TRANS_DP_BPC_MASK (3<<9) 5280 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 5281 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 5282 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 5283 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 5284 #define TRANS_DP_SYNC_MASK (3<<3) 5285 5286 /* SNB eDP training params */ 5287 /* SNB A-stepping */ 5288 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 5289 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 5290 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 5291 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 5292 /* SNB B-stepping */ 5293 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 5294 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 5295 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 5296 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 5297 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 5298 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 5299 5300 /* IVB */ 5301 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 5302 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 5303 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 5304 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 5305 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 5306 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 5307 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 5308 5309 /* legacy values */ 5310 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 5311 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 5312 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 5313 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 5314 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 5315 5316 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 5317 5318 #define VLV_PMWGICZ 0x1300a4 5319 5320 #define FORCEWAKE 0xA18C 5321 #define FORCEWAKE_VLV 0x1300b0 5322 #define FORCEWAKE_ACK_VLV 0x1300b4 5323 #define FORCEWAKE_MEDIA_VLV 0x1300b8 5324 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc 5325 #define FORCEWAKE_ACK_HSW 0x130044 5326 #define FORCEWAKE_ACK 0x130090 5327 #define VLV_GTLC_WAKE_CTRL 0x130090 5328 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 5329 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 5330 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 5331 5332 #define VLV_GTLC_PW_STATUS 0x130094 5333 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 5334 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 5335 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 5336 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 5337 #define FORCEWAKE_MT 0xa188 /* multi-threaded */ 5338 #define FORCEWAKE_KERNEL 0x1 5339 #define FORCEWAKE_USER 0x2 5340 #define FORCEWAKE_MT_ACK 0x130040 5341 #define ECOBUS 0xa180 5342 #define FORCEWAKE_MT_ENABLE (1<<5) 5343 #define VLV_SPAREG2H 0xA194 5344 5345 #define GTFIFODBG 0x120000 5346 #define GT_FIFO_SBDROPERR (1<<6) 5347 #define GT_FIFO_BLOBDROPERR (1<<5) 5348 #define GT_FIFO_SB_READ_ABORTERR (1<<4) 5349 #define GT_FIFO_DROPERR (1<<3) 5350 #define GT_FIFO_OVFERR (1<<2) 5351 #define GT_FIFO_IAWRERR (1<<1) 5352 #define GT_FIFO_IARDERR (1<<0) 5353 5354 #define GTFIFOCTL 0x120008 5355 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 5356 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 5357 5358 #define HSW_IDICR 0x9008 5359 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 5360 #define HSW_EDRAM_PRESENT 0x120010 5361 5362 #define GEN6_UCGCTL1 0x9400 5363 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 5364 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 5365 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 5366 5367 #define GEN6_UCGCTL2 0x9404 5368 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 5369 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 5370 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 5371 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 5372 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 5373 5374 #define GEN6_UCGCTL3 0x9408 5375 5376 #define GEN7_UCGCTL4 0x940c 5377 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 5378 5379 #define GEN6_RCGCTL1 0x9410 5380 #define GEN6_RCGCTL2 0x9414 5381 #define GEN6_RSTCTL 0x9420 5382 5383 #define GEN8_UCGCTL6 0x9430 5384 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 5385 5386 #define GEN6_GFXPAUSE 0xA000 5387 #define GEN6_RPNSWREQ 0xA008 5388 #define GEN6_TURBO_DISABLE (1<<31) 5389 #define GEN6_FREQUENCY(x) ((x)<<25) 5390 #define HSW_FREQUENCY(x) ((x)<<24) 5391 #define GEN6_OFFSET(x) ((x)<<19) 5392 #define GEN6_AGGRESSIVE_TURBO (0<<15) 5393 #define GEN6_RC_VIDEO_FREQ 0xA00C 5394 #define GEN6_RC_CONTROL 0xA090 5395 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 5396 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 5397 #define GEN6_RC_CTL_RC6_ENABLE (1<<18) 5398 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 5399 #define GEN6_RC_CTL_RC7_ENABLE (1<<22) 5400 #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 5401 #define GEN7_RC_CTL_TO_MODE (1<<28) 5402 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 5403 #define GEN6_RC_CTL_HW_ENABLE (1<<31) 5404 #define GEN6_RP_DOWN_TIMEOUT 0xA010 5405 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 5406 #define GEN6_RPSTAT1 0xA01C 5407 #define GEN6_CAGF_SHIFT 8 5408 #define HSW_CAGF_SHIFT 7 5409 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 5410 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 5411 #define GEN6_RP_CONTROL 0xA024 5412 #define GEN6_RP_MEDIA_TURBO (1<<11) 5413 #define GEN6_RP_MEDIA_MODE_MASK (3<<9) 5414 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 5415 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 5416 #define GEN6_RP_MEDIA_HW_MODE (1<<9) 5417 #define GEN6_RP_MEDIA_SW_MODE (0<<9) 5418 #define GEN6_RP_MEDIA_IS_GFX (1<<8) 5419 #define GEN6_RP_ENABLE (1<<7) 5420 #define GEN6_RP_UP_IDLE_MIN (0x1<<3) 5421 #define GEN6_RP_UP_BUSY_AVG (0x2<<3) 5422 #define GEN6_RP_UP_BUSY_CONT (0x4<<3) 5423 #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 5424 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 5425 #define GEN6_RP_UP_THRESHOLD 0xA02C 5426 #define GEN6_RP_DOWN_THRESHOLD 0xA030 5427 #define GEN6_RP_CUR_UP_EI 0xA050 5428 #define GEN6_CURICONT_MASK 0xffffff 5429 #define GEN6_RP_CUR_UP 0xA054 5430 #define GEN6_CURBSYTAVG_MASK 0xffffff 5431 #define GEN6_RP_PREV_UP 0xA058 5432 #define GEN6_RP_CUR_DOWN_EI 0xA05C 5433 #define GEN6_CURIAVG_MASK 0xffffff 5434 #define GEN6_RP_CUR_DOWN 0xA060 5435 #define GEN6_RP_PREV_DOWN 0xA064 5436 #define GEN6_RP_UP_EI 0xA068 5437 #define GEN6_RP_DOWN_EI 0xA06C 5438 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 5439 #define GEN6_RPDEUHWTC 0xA080 5440 #define GEN6_RPDEUC 0xA084 5441 #define GEN6_RPDEUCSW 0xA088 5442 #define GEN6_RC_STATE 0xA094 5443 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 5444 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 5445 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 5446 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 5447 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 5448 #define GEN6_RC_SLEEP 0xA0B0 5449 #define GEN6_RCUBMABDTMR 0xA0B0 5450 #define GEN6_RC1e_THRESHOLD 0xA0B4 5451 #define GEN6_RC6_THRESHOLD 0xA0B8 5452 #define GEN6_RC6p_THRESHOLD 0xA0BC 5453 #define VLV_RCEDATA 0xA0BC 5454 #define GEN6_RC6pp_THRESHOLD 0xA0C0 5455 #define GEN6_PMINTRMSK 0xA168 5456 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) 5457 #define VLV_PWRDWNUPCTL 0xA294 5458 5459 #define GEN6_PMISR 0x44020 5460 #define GEN6_PMIMR 0x44024 /* rps_lock */ 5461 #define GEN6_PMIIR 0x44028 5462 #define GEN6_PMIER 0x4402C 5463 #define GEN6_PM_MBOX_EVENT (1<<25) 5464 #define GEN6_PM_THERMAL_EVENT (1<<24) 5465 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 5466 #define GEN6_PM_RP_UP_THRESHOLD (1<<5) 5467 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 5468 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 5469 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 5470 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 5471 GEN6_PM_RP_DOWN_THRESHOLD | \ 5472 GEN6_PM_RP_DOWN_TIMEOUT) 5473 5474 #define GEN7_GT_SCRATCH_BASE 0x4F100 5475 #define GEN7_GT_SCRATCH_REG_NUM 8 5476 5477 #define VLV_GTLC_SURVIVABILITY_REG 0x130098 5478 #define VLV_GFX_CLK_STATUS_BIT (1<<3) 5479 #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 5480 5481 #define GEN6_GT_GFX_RC6_LOCKED 0x138104 5482 #define VLV_COUNTER_CONTROL 0x138104 5483 #define VLV_COUNT_RANGE_HIGH (1<<15) 5484 #define VLV_MEDIA_RC6_COUNT_EN (1<<1) 5485 #define VLV_RENDER_RC6_COUNT_EN (1<<0) 5486 #define GEN6_GT_GFX_RC6 0x138108 5487 #define VLV_GT_RENDER_RC6 0x138108 5488 #define VLV_GT_MEDIA_RC6 0x13810C 5489 5490 #define GEN6_GT_GFX_RC6p 0x13810C 5491 #define GEN6_GT_GFX_RC6pp 0x138110 5492 5493 #define GEN6_PCODE_MAILBOX 0x138124 5494 #define GEN6_PCODE_READY (1<<31) 5495 #define GEN6_READ_OC_PARAMS 0xc 5496 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 5497 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 5498 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 5499 #define GEN6_PCODE_READ_RC6VIDS 0x5 5500 #define GEN6_PCODE_READ_D_COMP 0x10 5501 #define GEN6_PCODE_WRITE_D_COMP 0x11 5502 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 5503 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 5504 #define DISPLAY_IPS_CONTROL 0x19 5505 #define GEN6_PCODE_DATA 0x138128 5506 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 5507 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 5508 5509 #define GEN6_GT_CORE_STATUS 0x138060 5510 #define GEN6_CORE_CPD_STATE_MASK (7<<4) 5511 #define GEN6_RCn_MASK 7 5512 #define GEN6_RC0 0 5513 #define GEN6_RC3 2 5514 #define GEN6_RC6 3 5515 #define GEN6_RC7 4 5516 5517 #define GEN7_MISCCPCTL (0x9424) 5518 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 5519 5520 /* IVYBRIDGE DPF */ 5521 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ 5522 #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ 5523 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 5524 #define GEN7_PARITY_ERROR_VALID (1<<13) 5525 #define GEN7_L3CDERRST1_BANK_MASK (3<<11) 5526 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 5527 #define GEN7_PARITY_ERROR_ROW(reg) \ 5528 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 5529 #define GEN7_PARITY_ERROR_BANK(reg) \ 5530 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 5531 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 5532 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 5533 #define GEN7_L3CDERRST1_ENABLE (1<<7) 5534 5535 #define GEN7_L3LOG_BASE 0xB070 5536 #define HSW_L3LOG_BASE_SLICE1 0xB270 5537 #define GEN7_L3LOG_SIZE 0x80 5538 5539 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ 5540 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 5541 #define GEN7_MAX_PS_THREAD_DEP (8<<12) 5542 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 5543 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 5544 5545 #define GEN8_ROW_CHICKEN 0xe4f0 5546 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 5547 #define STALL_DOP_GATING_DISABLE (1<<5) 5548 5549 #define GEN7_ROW_CHICKEN2 0xe4f4 5550 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 5551 #define DOP_CLOCK_GATING_DISABLE (1<<0) 5552 5553 #define HSW_ROW_CHICKEN3 0xe49c 5554 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 5555 5556 #define HALF_SLICE_CHICKEN3 0xe184 5557 #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 5558 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 5559 5560 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) 5561 #define INTEL_AUDIO_DEVCL 0x808629FB 5562 #define INTEL_AUDIO_DEVBLC 0x80862801 5563 #define INTEL_AUDIO_DEVCTG 0x80862802 5564 5565 #define G4X_AUD_CNTL_ST 0x620B4 5566 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 5567 #define G4X_ELDV_DEVCTG (1 << 14) 5568 #define G4X_ELD_ADDR (0xf << 5) 5569 #define G4X_ELD_ACK (1 << 4) 5570 #define G4X_HDMIW_HDMIEDID 0x6210C 5571 5572 #define IBX_HDMIW_HDMIEDID_A 0xE2050 5573 #define IBX_HDMIW_HDMIEDID_B 0xE2150 5574 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 5575 IBX_HDMIW_HDMIEDID_A, \ 5576 IBX_HDMIW_HDMIEDID_B) 5577 #define IBX_AUD_CNTL_ST_A 0xE20B4 5578 #define IBX_AUD_CNTL_ST_B 0xE21B4 5579 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 5580 IBX_AUD_CNTL_ST_A, \ 5581 IBX_AUD_CNTL_ST_B) 5582 #define IBX_ELD_BUFFER_SIZE (0x1f << 10) 5583 #define IBX_ELD_ADDRESS (0x1f << 5) 5584 #define IBX_ELD_ACK (1 << 4) 5585 #define IBX_AUD_CNTL_ST2 0xE20C0 5586 #define IBX_ELD_VALIDB (1 << 0) 5587 #define IBX_CP_READYB (1 << 1) 5588 5589 #define CPT_HDMIW_HDMIEDID_A 0xE5050 5590 #define CPT_HDMIW_HDMIEDID_B 0xE5150 5591 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 5592 CPT_HDMIW_HDMIEDID_A, \ 5593 CPT_HDMIW_HDMIEDID_B) 5594 #define CPT_AUD_CNTL_ST_A 0xE50B4 5595 #define CPT_AUD_CNTL_ST_B 0xE51B4 5596 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 5597 CPT_AUD_CNTL_ST_A, \ 5598 CPT_AUD_CNTL_ST_B) 5599 #define CPT_AUD_CNTRL_ST2 0xE50C0 5600 5601 #define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 5602 #define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 5603 #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 5604 VLV_HDMIW_HDMIEDID_A, \ 5605 VLV_HDMIW_HDMIEDID_B) 5606 #define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 5607 #define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 5608 #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 5609 VLV_AUD_CNTL_ST_A, \ 5610 VLV_AUD_CNTL_ST_B) 5611 #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) 5612 5613 /* These are the 4 32-bit write offset registers for each stream 5614 * output buffer. It determines the offset from the 5615 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 5616 */ 5617 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 5618 5619 #define IBX_AUD_CONFIG_A 0xe2000 5620 #define IBX_AUD_CONFIG_B 0xe2100 5621 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ 5622 IBX_AUD_CONFIG_A, \ 5623 IBX_AUD_CONFIG_B) 5624 #define CPT_AUD_CONFIG_A 0xe5000 5625 #define CPT_AUD_CONFIG_B 0xe5100 5626 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ 5627 CPT_AUD_CONFIG_A, \ 5628 CPT_AUD_CONFIG_B) 5629 #define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 5630 #define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 5631 #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ 5632 VLV_AUD_CONFIG_A, \ 5633 VLV_AUD_CONFIG_B) 5634 5635 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 5636 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 5637 #define AUD_CONFIG_UPPER_N_SHIFT 20 5638 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) 5639 #define AUD_CONFIG_LOWER_N_SHIFT 4 5640 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) 5641 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 5642 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 5643 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 5644 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 5645 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 5646 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 5647 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 5648 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 5649 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 5650 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 5651 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 5652 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 5653 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 5654 5655 /* HSW Audio */ 5656 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ 5657 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ 5658 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ 5659 HSW_AUD_CONFIG_A, \ 5660 HSW_AUD_CONFIG_B) 5661 5662 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ 5663 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ 5664 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ 5665 HSW_AUD_MISC_CTRL_A, \ 5666 HSW_AUD_MISC_CTRL_B) 5667 5668 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ 5669 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ 5670 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ 5671 HSW_AUD_DIP_ELD_CTRL_ST_A, \ 5672 HSW_AUD_DIP_ELD_CTRL_ST_B) 5673 5674 /* Audio Digital Converter */ 5675 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ 5676 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ 5677 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ 5678 HSW_AUD_DIG_CNVT_1, \ 5679 HSW_AUD_DIG_CNVT_2) 5680 #define DIP_PORT_SEL_MASK 0x3 5681 5682 #define HSW_AUD_EDID_DATA_A 0x65050 5683 #define HSW_AUD_EDID_DATA_B 0x65150 5684 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ 5685 HSW_AUD_EDID_DATA_A, \ 5686 HSW_AUD_EDID_DATA_B) 5687 5688 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ 5689 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ 5690 #define AUDIO_INACTIVE_C (1<<11) 5691 #define AUDIO_INACTIVE_B (1<<7) 5692 #define AUDIO_INACTIVE_A (1<<3) 5693 #define AUDIO_OUTPUT_ENABLE_A (1<<2) 5694 #define AUDIO_OUTPUT_ENABLE_B (1<<6) 5695 #define AUDIO_OUTPUT_ENABLE_C (1<<10) 5696 #define AUDIO_ELD_VALID_A (1<<0) 5697 #define AUDIO_ELD_VALID_B (1<<4) 5698 #define AUDIO_ELD_VALID_C (1<<8) 5699 #define AUDIO_CP_READY_A (1<<1) 5700 #define AUDIO_CP_READY_B (1<<5) 5701 #define AUDIO_CP_READY_C (1<<9) 5702 5703 /* HSW Power Wells */ 5704 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ 5705 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ 5706 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ 5707 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ 5708 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 5709 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 5710 #define HSW_PWR_WELL_CTL5 0x45410 5711 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 5712 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 5713 #define HSW_PWR_WELL_FORCE_ON (1<<19) 5714 #define HSW_PWR_WELL_CTL6 0x45414 5715 5716 /* Per-pipe DDI Function Control */ 5717 #define TRANS_DDI_FUNC_CTL_A 0x60400 5718 #define TRANS_DDI_FUNC_CTL_B 0x61400 5719 #define TRANS_DDI_FUNC_CTL_C 0x62400 5720 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 5721 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) 5722 5723 #define TRANS_DDI_FUNC_ENABLE (1<<31) 5724 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 5725 #define TRANS_DDI_PORT_MASK (7<<28) 5726 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 5727 #define TRANS_DDI_PORT_NONE (0<<28) 5728 #define TRANS_DDI_MODE_SELECT_MASK (7<<24) 5729 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 5730 #define TRANS_DDI_MODE_SELECT_DVI (1<<24) 5731 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 5732 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 5733 #define TRANS_DDI_MODE_SELECT_FDI (4<<24) 5734 #define TRANS_DDI_BPC_MASK (7<<20) 5735 #define TRANS_DDI_BPC_8 (0<<20) 5736 #define TRANS_DDI_BPC_10 (1<<20) 5737 #define TRANS_DDI_BPC_6 (2<<20) 5738 #define TRANS_DDI_BPC_12 (3<<20) 5739 #define TRANS_DDI_PVSYNC (1<<17) 5740 #define TRANS_DDI_PHSYNC (1<<16) 5741 #define TRANS_DDI_EDP_INPUT_MASK (7<<12) 5742 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 5743 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 5744 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 5745 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 5746 #define TRANS_DDI_BFI_ENABLE (1<<4) 5747 5748 /* DisplayPort Transport Control */ 5749 #define DP_TP_CTL_A 0x64040 5750 #define DP_TP_CTL_B 0x64140 5751 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) 5752 #define DP_TP_CTL_ENABLE (1<<31) 5753 #define DP_TP_CTL_MODE_SST (0<<27) 5754 #define DP_TP_CTL_MODE_MST (1<<27) 5755 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 5756 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 5757 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 5758 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 5759 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 5760 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 5761 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 5762 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 5763 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 5764 5765 /* DisplayPort Transport Status */ 5766 #define DP_TP_STATUS_A 0x64044 5767 #define DP_TP_STATUS_B 0x64144 5768 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) 5769 #define DP_TP_STATUS_IDLE_DONE (1<<25) 5770 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 5771 5772 /* DDI Buffer Control */ 5773 #define DDI_BUF_CTL_A 0x64000 5774 #define DDI_BUF_CTL_B 0x64100 5775 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) 5776 #define DDI_BUF_CTL_ENABLE (1<<31) 5777 /* Haswell */ 5778 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ 5779 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ 5780 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ 5781 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ 5782 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ 5783 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ 5784 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ 5785 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ 5786 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ 5787 /* Broadwell */ 5788 #define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */ 5789 #define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */ 5790 #define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */ 5791 #define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */ 5792 #define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */ 5793 #define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */ 5794 #define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */ 5795 #define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */ 5796 #define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */ 5797 #define DDI_BUF_EMP_MASK (0xf<<24) 5798 #define DDI_BUF_PORT_REVERSAL (1<<16) 5799 #define DDI_BUF_IS_IDLE (1<<7) 5800 #define DDI_A_4_LANES (1<<4) 5801 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 5802 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 5803 5804 /* DDI Buffer Translations */ 5805 #define DDI_BUF_TRANS_A 0x64E00 5806 #define DDI_BUF_TRANS_B 0x64E60 5807 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) 5808 5809 /* Sideband Interface (SBI) is programmed indirectly, via 5810 * SBI_ADDR, which contains the register offset; and SBI_DATA, 5811 * which contains the payload */ 5812 #define SBI_ADDR 0xC6000 5813 #define SBI_DATA 0xC6004 5814 #define SBI_CTL_STAT 0xC6008 5815 #define SBI_CTL_DEST_ICLK (0x0<<16) 5816 #define SBI_CTL_DEST_MPHY (0x1<<16) 5817 #define SBI_CTL_OP_IORD (0x2<<8) 5818 #define SBI_CTL_OP_IOWR (0x3<<8) 5819 #define SBI_CTL_OP_CRRD (0x6<<8) 5820 #define SBI_CTL_OP_CRWR (0x7<<8) 5821 #define SBI_RESPONSE_FAIL (0x1<<1) 5822 #define SBI_RESPONSE_SUCCESS (0x0<<1) 5823 #define SBI_BUSY (0x1<<0) 5824 #define SBI_READY (0x0<<0) 5825 5826 /* SBI offsets */ 5827 #define SBI_SSCDIVINTPHASE6 0x0600 5828 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 5829 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 5830 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 5831 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 5832 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 5833 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 5834 #define SBI_SSCCTL 0x020c 5835 #define SBI_SSCCTL6 0x060C 5836 #define SBI_SSCCTL_PATHALT (1<<3) 5837 #define SBI_SSCCTL_DISABLE (1<<0) 5838 #define SBI_SSCAUXDIV6 0x0610 5839 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 5840 #define SBI_DBUFF0 0x2a00 5841 #define SBI_GEN0 0x1f00 5842 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 5843 5844 /* LPT PIXCLK_GATE */ 5845 #define PIXCLK_GATE 0xC6020 5846 #define PIXCLK_GATE_UNGATE (1<<0) 5847 #define PIXCLK_GATE_GATE (0<<0) 5848 5849 /* SPLL */ 5850 #define SPLL_CTL 0x46020 5851 #define SPLL_PLL_ENABLE (1<<31) 5852 #define SPLL_PLL_SSC (1<<28) 5853 #define SPLL_PLL_NON_SSC (2<<28) 5854 #define SPLL_PLL_LCPLL (3<<28) 5855 #define SPLL_PLL_REF_MASK (3<<28) 5856 #define SPLL_PLL_FREQ_810MHz (0<<26) 5857 #define SPLL_PLL_FREQ_1350MHz (1<<26) 5858 #define SPLL_PLL_FREQ_2700MHz (2<<26) 5859 #define SPLL_PLL_FREQ_MASK (3<<26) 5860 5861 /* WRPLL */ 5862 #define WRPLL_CTL1 0x46040 5863 #define WRPLL_CTL2 0x46060 5864 #define WRPLL_PLL_ENABLE (1<<31) 5865 #define WRPLL_PLL_SELECT_SSC (0x01<<28) 5866 #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28) 5867 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) 5868 /* WRPLL divider programming */ 5869 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 5870 #define WRPLL_DIVIDER_REF_MASK (0xff) 5871 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 5872 #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 5873 #define WRPLL_DIVIDER_POST_SHIFT 8 5874 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 5875 #define WRPLL_DIVIDER_FB_SHIFT 16 5876 #define WRPLL_DIVIDER_FB_MASK (0xff<<16) 5877 5878 /* Port clock selection */ 5879 #define PORT_CLK_SEL_A 0x46100 5880 #define PORT_CLK_SEL_B 0x46104 5881 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) 5882 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 5883 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 5884 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 5885 #define PORT_CLK_SEL_SPLL (3<<29) 5886 #define PORT_CLK_SEL_WRPLL1 (4<<29) 5887 #define PORT_CLK_SEL_WRPLL2 (5<<29) 5888 #define PORT_CLK_SEL_NONE (7<<29) 5889 #define PORT_CLK_SEL_MASK (7<<29) 5890 5891 /* Transcoder clock selection */ 5892 #define TRANS_CLK_SEL_A 0x46140 5893 #define TRANS_CLK_SEL_B 0x46144 5894 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) 5895 /* For each transcoder, we need to select the corresponding port clock */ 5896 #define TRANS_CLK_SEL_DISABLED (0x0<<29) 5897 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) 5898 5899 #define TRANSA_MSA_MISC 0x60410 5900 #define TRANSB_MSA_MISC 0x61410 5901 #define TRANSC_MSA_MISC 0x62410 5902 #define TRANS_EDP_MSA_MISC 0x6f410 5903 #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) 5904 5905 #define TRANS_MSA_SYNC_CLK (1<<0) 5906 #define TRANS_MSA_6_BPC (0<<5) 5907 #define TRANS_MSA_8_BPC (1<<5) 5908 #define TRANS_MSA_10_BPC (2<<5) 5909 #define TRANS_MSA_12_BPC (3<<5) 5910 #define TRANS_MSA_16_BPC (4<<5) 5911 5912 /* LCPLL Control */ 5913 #define LCPLL_CTL 0x130040 5914 #define LCPLL_PLL_DISABLE (1<<31) 5915 #define LCPLL_PLL_LOCK (1<<30) 5916 #define LCPLL_CLK_FREQ_MASK (3<<26) 5917 #define LCPLL_CLK_FREQ_450 (0<<26) 5918 #define LCPLL_CLK_FREQ_54O_BDW (1<<26) 5919 #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 5920 #define LCPLL_CLK_FREQ_675_BDW (3<<26) 5921 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 5922 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 5923 #define LCPLL_POWER_DOWN_ALLOW (1<<22) 5924 #define LCPLL_CD_SOURCE_FCLK (1<<21) 5925 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 5926 5927 #define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 5928 #define D_COMP_RCOMP_IN_PROGRESS (1<<9) 5929 #define D_COMP_COMP_FORCE (1<<8) 5930 #define D_COMP_COMP_DISABLE (1<<0) 5931 5932 /* Pipe WM_LINETIME - watermark line time */ 5933 #define PIPE_WM_LINETIME_A 0x45270 5934 #define PIPE_WM_LINETIME_B 0x45274 5935 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ 5936 PIPE_WM_LINETIME_B) 5937 #define PIPE_WM_LINETIME_MASK (0x1ff) 5938 #define PIPE_WM_LINETIME_TIME(x) ((x)) 5939 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 5940 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 5941 5942 /* SFUSE_STRAP */ 5943 #define SFUSE_STRAP 0xc2014 5944 #define SFUSE_STRAP_FUSE_LOCK (1<<13) 5945 #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 5946 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 5947 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 5948 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 5949 5950 #define WM_MISC 0x45260 5951 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 5952 5953 #define WM_DBG 0x45280 5954 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 5955 #define WM_DBG_DISALLOW_MAXFIFO (1<<1) 5956 #define WM_DBG_DISALLOW_SPRITE (1<<2) 5957 5958 /* pipe CSC */ 5959 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 5960 #define _PIPE_A_CSC_COEFF_BY 0x49014 5961 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 5962 #define _PIPE_A_CSC_COEFF_BU 0x4901c 5963 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 5964 #define _PIPE_A_CSC_COEFF_BV 0x49024 5965 #define _PIPE_A_CSC_MODE 0x49028 5966 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) 5967 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) 5968 #define CSC_MODE_YUV_TO_RGB (1 << 0) 5969 #define _PIPE_A_CSC_PREOFF_HI 0x49030 5970 #define _PIPE_A_CSC_PREOFF_ME 0x49034 5971 #define _PIPE_A_CSC_PREOFF_LO 0x49038 5972 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 5973 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 5974 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 5975 5976 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 5977 #define _PIPE_B_CSC_COEFF_BY 0x49114 5978 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 5979 #define _PIPE_B_CSC_COEFF_BU 0x4911c 5980 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 5981 #define _PIPE_B_CSC_COEFF_BV 0x49124 5982 #define _PIPE_B_CSC_MODE 0x49128 5983 #define _PIPE_B_CSC_PREOFF_HI 0x49130 5984 #define _PIPE_B_CSC_PREOFF_ME 0x49134 5985 #define _PIPE_B_CSC_PREOFF_LO 0x49138 5986 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 5987 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 5988 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 5989 5990 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 5991 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 5992 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 5993 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 5994 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 5995 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 5996 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 5997 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 5998 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 5999 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 6000 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 6001 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 6002 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 6003 6004 /* VLV MIPI registers */ 6005 6006 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 6007 #define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 6008 #define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL) 6009 #define DPI_ENABLE (1 << 31) /* A + B */ 6010 #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 6011 #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 6012 #define DUAL_LINK_MODE_MASK (1 << 26) 6013 #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 6014 #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 6015 #define DITHERING_ENABLE (1 << 25) /* A + B */ 6016 #define FLOPPED_HSTX (1 << 23) 6017 #define DE_INVERT (1 << 19) /* XXX */ 6018 #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 6019 #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 6020 #define AFE_LATCHOUT (1 << 17) 6021 #define LP_OUTPUT_HOLD (1 << 16) 6022 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 6023 #define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 6024 #define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 6025 #define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 6026 #define CSB_SHIFT 9 6027 #define CSB_MASK (3 << 9) 6028 #define CSB_20MHZ (0 << 9) 6029 #define CSB_10MHZ (1 << 9) 6030 #define CSB_40MHZ (2 << 9) 6031 #define BANDGAP_MASK (1 << 8) 6032 #define BANDGAP_PNW_CIRCUIT (0 << 8) 6033 #define BANDGAP_LNC_CIRCUIT (1 << 8) 6034 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 6035 #define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 6036 #define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ 6037 #define TEARING_EFFECT_SHIFT 2 /* A + B */ 6038 #define TEARING_EFFECT_MASK (3 << 2) 6039 #define TEARING_EFFECT_OFF (0 << 2) 6040 #define TEARING_EFFECT_DSI (1 << 2) 6041 #define TEARING_EFFECT_GPIO (2 << 2) 6042 #define LANE_CONFIGURATION_SHIFT 0 6043 #define LANE_CONFIGURATION_MASK (3 << 0) 6044 #define LANE_CONFIGURATION_4LANE (0 << 0) 6045 #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 6046 #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 6047 6048 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 6049 #define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 6050 #define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) 6051 #define TEARING_EFFECT_DELAY_SHIFT 0 6052 #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 6053 6054 /* XXX: all bits reserved */ 6055 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 6056 6057 /* MIPI DSI Controller and D-PHY registers */ 6058 6059 #define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000) 6060 #define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800) 6061 #define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY) 6062 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 6063 #define ULPS_STATE_MASK (3 << 1) 6064 #define ULPS_STATE_ENTER (2 << 1) 6065 #define ULPS_STATE_EXIT (1 << 1) 6066 #define ULPS_STATE_NORMAL_OPERATION (0 << 1) 6067 #define DEVICE_READY (1 << 0) 6068 6069 #define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004) 6070 #define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804) 6071 #define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT) 6072 #define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008) 6073 #define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808) 6074 #define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN) 6075 #define TEARING_EFFECT (1 << 31) 6076 #define SPL_PKT_SENT_INTERRUPT (1 << 30) 6077 #define GEN_READ_DATA_AVAIL (1 << 29) 6078 #define LP_GENERIC_WR_FIFO_FULL (1 << 28) 6079 #define HS_GENERIC_WR_FIFO_FULL (1 << 27) 6080 #define RX_PROT_VIOLATION (1 << 26) 6081 #define RX_INVALID_TX_LENGTH (1 << 25) 6082 #define ACK_WITH_NO_ERROR (1 << 24) 6083 #define TURN_AROUND_ACK_TIMEOUT (1 << 23) 6084 #define LP_RX_TIMEOUT (1 << 22) 6085 #define HS_TX_TIMEOUT (1 << 21) 6086 #define DPI_FIFO_UNDERRUN (1 << 20) 6087 #define LOW_CONTENTION (1 << 19) 6088 #define HIGH_CONTENTION (1 << 18) 6089 #define TXDSI_VC_ID_INVALID (1 << 17) 6090 #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 6091 #define TXCHECKSUM_ERROR (1 << 15) 6092 #define TXECC_MULTIBIT_ERROR (1 << 14) 6093 #define TXECC_SINGLE_BIT_ERROR (1 << 13) 6094 #define TXFALSE_CONTROL_ERROR (1 << 12) 6095 #define RXDSI_VC_ID_INVALID (1 << 11) 6096 #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 6097 #define RXCHECKSUM_ERROR (1 << 9) 6098 #define RXECC_MULTIBIT_ERROR (1 << 8) 6099 #define RXECC_SINGLE_BIT_ERROR (1 << 7) 6100 #define RXFALSE_CONTROL_ERROR (1 << 6) 6101 #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 6102 #define RX_LP_TX_SYNC_ERROR (1 << 4) 6103 #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 6104 #define RXEOT_SYNC_ERROR (1 << 2) 6105 #define RXSOT_SYNC_ERROR (1 << 1) 6106 #define RXSOT_ERROR (1 << 0) 6107 6108 #define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c) 6109 #define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c) 6110 #define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG) 6111 #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 6112 #define CMD_MODE_NOT_SUPPORTED (0 << 13) 6113 #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 6114 #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 6115 #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 6116 #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 6117 #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 6118 #define VID_MODE_FORMAT_MASK (0xf << 7) 6119 #define VID_MODE_NOT_SUPPORTED (0 << 7) 6120 #define VID_MODE_FORMAT_RGB565 (1 << 7) 6121 #define VID_MODE_FORMAT_RGB666 (2 << 7) 6122 #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) 6123 #define VID_MODE_FORMAT_RGB888 (4 << 7) 6124 #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 6125 #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 6126 #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 6127 #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 6128 #define DATA_LANES_PRG_REG_SHIFT 0 6129 #define DATA_LANES_PRG_REG_MASK (7 << 0) 6130 6131 #define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010) 6132 #define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810) 6133 #define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT) 6134 #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 6135 6136 #define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014) 6137 #define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814) 6138 #define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT) 6139 #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 6140 6141 #define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018) 6142 #define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818) 6143 #define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) 6144 #define TURN_AROUND_TIMEOUT_MASK 0x3f 6145 6146 #define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c) 6147 #define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c) 6148 #define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) 6149 #define DEVICE_RESET_TIMER_MASK 0xffff 6150 6151 #define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020) 6152 #define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820) 6153 #define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION) 6154 #define VERTICAL_ADDRESS_SHIFT 16 6155 #define VERTICAL_ADDRESS_MASK (0xffff << 16) 6156 #define HORIZONTAL_ADDRESS_SHIFT 0 6157 #define HORIZONTAL_ADDRESS_MASK 0xffff 6158 6159 #define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024) 6160 #define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824) 6161 #define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) 6162 #define DBI_FIFO_EMPTY_HALF (0 << 0) 6163 #define DBI_FIFO_EMPTY_QUARTER (1 << 0) 6164 #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 6165 6166 /* regs below are bits 15:0 */ 6167 #define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028) 6168 #define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828) 6169 #define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) 6170 6171 #define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c) 6172 #define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c) 6173 #define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT) 6174 6175 #define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030) 6176 #define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830) 6177 #define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT) 6178 6179 #define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034) 6180 #define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834) 6181 #define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) 6182 6183 #define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038) 6184 #define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838) 6185 #define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) 6186 6187 #define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c) 6188 #define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c) 6189 #define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT) 6190 6191 #define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040) 6192 #define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840) 6193 #define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT) 6194 6195 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044) 6196 #define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844) 6197 #define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) 6198 /* regs above are bits 15:0 */ 6199 6200 #define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048) 6201 #define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848) 6202 #define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL) 6203 #define DPI_LP_MODE (1 << 6) 6204 #define BACKLIGHT_OFF (1 << 5) 6205 #define BACKLIGHT_ON (1 << 4) 6206 #define COLOR_MODE_OFF (1 << 3) 6207 #define COLOR_MODE_ON (1 << 2) 6208 #define TURN_ON (1 << 1) 6209 #define SHUTDOWN (1 << 0) 6210 6211 #define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c) 6212 #define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c) 6213 #define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA) 6214 #define COMMAND_BYTE_SHIFT 0 6215 #define COMMAND_BYTE_MASK (0x3f << 0) 6216 6217 #define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050) 6218 #define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850) 6219 #define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT) 6220 #define MASTER_INIT_TIMER_SHIFT 0 6221 #define MASTER_INIT_TIMER_MASK (0xffff << 0) 6222 6223 #define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054) 6224 #define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854) 6225 #define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) 6226 #define MAX_RETURN_PKT_SIZE_SHIFT 0 6227 #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 6228 6229 #define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058) 6230 #define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858) 6231 #define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) 6232 #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 6233 #define DISABLE_VIDEO_BTA (1 << 3) 6234 #define IP_TG_CONFIG (1 << 2) 6235 #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 6236 #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 6237 #define VIDEO_MODE_BURST (3 << 0) 6238 6239 #define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c) 6240 #define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c) 6241 #define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE) 6242 #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 6243 #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 6244 #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 6245 #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 6246 #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 6247 #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 6248 #define CLOCKSTOP (1 << 1) 6249 #define EOT_DISABLE (1 << 0) 6250 6251 #define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060) 6252 #define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860) 6253 #define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK) 6254 #define LP_BYTECLK_SHIFT 0 6255 #define LP_BYTECLK_MASK (0xffff << 0) 6256 6257 /* bits 31:0 */ 6258 #define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064) 6259 #define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864) 6260 #define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA) 6261 6262 /* bits 31:0 */ 6263 #define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068) 6264 #define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868) 6265 #define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA) 6266 6267 #define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c) 6268 #define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c) 6269 #define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL) 6270 #define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070) 6271 #define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870) 6272 #define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL) 6273 #define LONG_PACKET_WORD_COUNT_SHIFT 8 6274 #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 6275 #define SHORT_PACKET_PARAM_SHIFT 8 6276 #define SHORT_PACKET_PARAM_MASK (0xffff << 8) 6277 #define VIRTUAL_CHANNEL_SHIFT 6 6278 #define VIRTUAL_CHANNEL_MASK (3 << 6) 6279 #define DATA_TYPE_SHIFT 0 6280 #define DATA_TYPE_MASK (3f << 0) 6281 /* data type values, see include/video/mipi_display.h */ 6282 6283 #define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074) 6284 #define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874) 6285 #define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT) 6286 #define DPI_FIFO_EMPTY (1 << 28) 6287 #define DBI_FIFO_EMPTY (1 << 27) 6288 #define LP_CTRL_FIFO_EMPTY (1 << 26) 6289 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 6290 #define LP_CTRL_FIFO_FULL (1 << 24) 6291 #define HS_CTRL_FIFO_EMPTY (1 << 18) 6292 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 6293 #define HS_CTRL_FIFO_FULL (1 << 16) 6294 #define LP_DATA_FIFO_EMPTY (1 << 10) 6295 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 6296 #define LP_DATA_FIFO_FULL (1 << 8) 6297 #define HS_DATA_FIFO_EMPTY (1 << 2) 6298 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 6299 #define HS_DATA_FIFO_FULL (1 << 0) 6300 6301 #define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078) 6302 #define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878) 6303 #define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) 6304 #define DBI_HS_LP_MODE_MASK (1 << 0) 6305 #define DBI_LP_MODE (1 << 0) 6306 #define DBI_HS_MODE (0 << 0) 6307 6308 #define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080) 6309 #define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880) 6310 #define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM) 6311 #define EXIT_ZERO_COUNT_SHIFT 24 6312 #define EXIT_ZERO_COUNT_MASK (0x3f << 24) 6313 #define TRAIL_COUNT_SHIFT 16 6314 #define TRAIL_COUNT_MASK (0x1f << 16) 6315 #define CLK_ZERO_COUNT_SHIFT 8 6316 #define CLK_ZERO_COUNT_MASK (0xff << 8) 6317 #define PREPARE_COUNT_SHIFT 0 6318 #define PREPARE_COUNT_MASK (0x3f << 0) 6319 6320 /* bits 31:0 */ 6321 #define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084) 6322 #define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884) 6323 #define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL) 6324 6325 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088) 6326 #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888) 6327 #define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) 6328 #define LP_HS_SSW_CNT_SHIFT 16 6329 #define LP_HS_SSW_CNT_MASK (0xffff << 16) 6330 #define HS_LP_PWR_SW_CNT_SHIFT 0 6331 #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 6332 6333 #define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c) 6334 #define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c) 6335 #define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) 6336 #define STOP_STATE_STALL_COUNTER_SHIFT 0 6337 #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 6338 6339 #define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090) 6340 #define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890) 6341 #define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) 6342 #define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094) 6343 #define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894) 6344 #define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1) 6345 #define RX_CONTENTION_DETECTED (1 << 0) 6346 6347 /* XXX: only pipe A ?!? */ 6348 #define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100) 6349 #define DBI_TYPEC_ENABLE (1 << 31) 6350 #define DBI_TYPEC_WIP (1 << 30) 6351 #define DBI_TYPEC_OPTION_SHIFT 28 6352 #define DBI_TYPEC_OPTION_MASK (3 << 28) 6353 #define DBI_TYPEC_FREQ_SHIFT 24 6354 #define DBI_TYPEC_FREQ_MASK (0xf << 24) 6355 #define DBI_TYPEC_OVERRIDE (1 << 8) 6356 #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 6357 #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 6358 6359 6360 /* MIPI adapter registers */ 6361 6362 #define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104) 6363 #define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904) 6364 #define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL) 6365 #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 6366 #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 6367 #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 6368 #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 6369 #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 6370 #define READ_REQUEST_PRIORITY_SHIFT 3 6371 #define READ_REQUEST_PRIORITY_MASK (3 << 3) 6372 #define READ_REQUEST_PRIORITY_LOW (0 << 3) 6373 #define READ_REQUEST_PRIORITY_HIGH (3 << 3) 6374 #define RGB_FLIP_TO_BGR (1 << 2) 6375 6376 #define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108) 6377 #define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908) 6378 #define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS) 6379 #define DATA_MEM_ADDRESS_SHIFT 5 6380 #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 6381 #define DATA_VALID (1 << 0) 6382 6383 #define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c) 6384 #define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c) 6385 #define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH) 6386 #define DATA_LENGTH_SHIFT 0 6387 #define DATA_LENGTH_MASK (0xfffff << 0) 6388 6389 #define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110) 6390 #define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910) 6391 #define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) 6392 #define COMMAND_MEM_ADDRESS_SHIFT 5 6393 #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 6394 #define AUTO_PWG_ENABLE (1 << 2) 6395 #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 6396 #define COMMAND_VALID (1 << 0) 6397 6398 #define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114) 6399 #define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914) 6400 #define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH) 6401 #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 6402 #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 6403 6404 #define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118) 6405 #define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918) 6406 #define MIPI_READ_DATA_RETURN(pipe, n) \ 6407 (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 6408 6409 #define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138) 6410 #define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938) 6411 #define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) 6412 #define READ_DATA_VALID(n) (1 << (n)) 6413 6414 /* For UMS only (deprecated): */ 6415 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 6416 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 6417 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 6418 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 6419 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 6420 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 6421 6422 #endif /* _I915_REG_H_ */ 6423