1 /* 2 * 3 * Copyright 2008 (c) Intel Corporation 4 * Jesse Barnes <jbarnes@virtuousgeek.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * $FreeBSD: src/sys/dev/drm2/i915/i915_suspend.c,v 1.1 2012/05/22 11:07:44 kib Exp $ 27 */ 28 29 #include <drm/drmP.h> 30 #include "i915_drm.h" 31 #include "intel_drv.h" 32 33 static bool i915_pipe_enabled(struct drm_device *dev, enum i915_pipe pipe) 34 { 35 struct drm_i915_private *dev_priv = dev->dev_private; 36 u32 dpll_reg; 37 38 /* On IVB, 3rd pipe shares PLL with another one */ 39 if (pipe > 1) 40 return false; 41 42 if (HAS_PCH_SPLIT(dev)) 43 dpll_reg = PCH_DPLL(pipe); 44 else 45 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B; 46 47 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); 48 } 49 50 static void i915_save_palette(struct drm_device *dev, enum i915_pipe pipe) 51 { 52 struct drm_i915_private *dev_priv = dev->dev_private; 53 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); 54 u32 *array; 55 int i; 56 57 if (!i915_pipe_enabled(dev, pipe)) 58 return; 59 60 if (HAS_PCH_SPLIT(dev)) 61 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; 62 63 if (pipe == PIPE_A) 64 array = dev_priv->save_palette_a; 65 else 66 array = dev_priv->save_palette_b; 67 68 for (i = 0; i < 256; i++) 69 array[i] = I915_READ(reg + (i << 2)); 70 } 71 72 static void i915_restore_palette(struct drm_device *dev, enum i915_pipe pipe) 73 { 74 struct drm_i915_private *dev_priv = dev->dev_private; 75 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); 76 u32 *array; 77 int i; 78 79 if (!i915_pipe_enabled(dev, pipe)) 80 return; 81 82 if (HAS_PCH_SPLIT(dev)) 83 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; 84 85 if (pipe == PIPE_A) 86 array = dev_priv->save_palette_a; 87 else 88 array = dev_priv->save_palette_b; 89 90 for (i = 0; i < 256; i++) 91 I915_WRITE(reg + (i << 2), array[i]); 92 } 93 94 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) 95 { 96 struct drm_i915_private *dev_priv = dev->dev_private; 97 98 I915_WRITE8(index_port, reg); 99 return I915_READ8(data_port); 100 } 101 102 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) 103 { 104 struct drm_i915_private *dev_priv = dev->dev_private; 105 106 I915_READ8(st01); 107 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 108 return I915_READ8(VGA_AR_DATA_READ); 109 } 110 111 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) 112 { 113 struct drm_i915_private *dev_priv = dev->dev_private; 114 115 I915_READ8(st01); 116 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 117 I915_WRITE8(VGA_AR_DATA_WRITE, val); 118 } 119 120 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) 121 { 122 struct drm_i915_private *dev_priv = dev->dev_private; 123 124 I915_WRITE8(index_port, reg); 125 I915_WRITE8(data_port, val); 126 } 127 128 static void i915_save_vga(struct drm_device *dev) 129 { 130 struct drm_i915_private *dev_priv = dev->dev_private; 131 int i; 132 u16 cr_index, cr_data, st01; 133 134 /* VGA color palette registers */ 135 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); 136 137 /* MSR bits */ 138 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); 139 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 140 cr_index = VGA_CR_INDEX_CGA; 141 cr_data = VGA_CR_DATA_CGA; 142 st01 = VGA_ST01_CGA; 143 } else { 144 cr_index = VGA_CR_INDEX_MDA; 145 cr_data = VGA_CR_DATA_MDA; 146 st01 = VGA_ST01_MDA; 147 } 148 149 /* CRT controller regs */ 150 i915_write_indexed(dev, cr_index, cr_data, 0x11, 151 i915_read_indexed(dev, cr_index, cr_data, 0x11) & 152 (~0x80)); 153 for (i = 0; i <= 0x24; i++) 154 dev_priv->saveCR[i] = 155 i915_read_indexed(dev, cr_index, cr_data, i); 156 /* Make sure we don't turn off CR group 0 writes */ 157 dev_priv->saveCR[0x11] &= ~0x80; 158 159 /* Attribute controller registers */ 160 I915_READ8(st01); 161 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); 162 for (i = 0; i <= 0x14; i++) 163 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); 164 I915_READ8(st01); 165 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); 166 I915_READ8(st01); 167 168 /* Graphics controller registers */ 169 for (i = 0; i < 9; i++) 170 dev_priv->saveGR[i] = 171 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); 172 173 dev_priv->saveGR[0x10] = 174 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); 175 dev_priv->saveGR[0x11] = 176 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); 177 dev_priv->saveGR[0x18] = 178 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); 179 180 /* Sequencer registers */ 181 for (i = 0; i < 8; i++) 182 dev_priv->saveSR[i] = 183 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); 184 } 185 186 static void i915_restore_vga(struct drm_device *dev) 187 { 188 struct drm_i915_private *dev_priv = dev->dev_private; 189 int i; 190 u16 cr_index, cr_data, st01; 191 192 /* MSR bits */ 193 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); 194 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 195 cr_index = VGA_CR_INDEX_CGA; 196 cr_data = VGA_CR_DATA_CGA; 197 st01 = VGA_ST01_CGA; 198 } else { 199 cr_index = VGA_CR_INDEX_MDA; 200 cr_data = VGA_CR_DATA_MDA; 201 st01 = VGA_ST01_MDA; 202 } 203 204 /* Sequencer registers, don't write SR07 */ 205 for (i = 0; i < 7; i++) 206 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, 207 dev_priv->saveSR[i]); 208 209 /* CRT controller regs */ 210 /* Enable CR group 0 writes */ 211 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); 212 for (i = 0; i <= 0x24; i++) 213 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); 214 215 /* Graphics controller regs */ 216 for (i = 0; i < 9; i++) 217 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, 218 dev_priv->saveGR[i]); 219 220 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, 221 dev_priv->saveGR[0x10]); 222 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, 223 dev_priv->saveGR[0x11]); 224 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, 225 dev_priv->saveGR[0x18]); 226 227 /* Attribute controller registers */ 228 I915_READ8(st01); /* switch back to index mode */ 229 for (i = 0; i <= 0x14; i++) 230 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); 231 I915_READ8(st01); /* switch back to index mode */ 232 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); 233 I915_READ8(st01); 234 235 /* VGA color palette registers */ 236 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); 237 } 238 239 static void i915_save_modeset_reg(struct drm_device *dev) 240 { 241 struct drm_i915_private *dev_priv = dev->dev_private; 242 int i; 243 244 if (drm_core_check_feature(dev, DRIVER_MODESET)) 245 return; 246 247 /* Cursor state */ 248 dev_priv->saveCURACNTR = I915_READ(_CURACNTR); 249 dev_priv->saveCURAPOS = I915_READ(_CURAPOS); 250 dev_priv->saveCURABASE = I915_READ(_CURABASE); 251 dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR); 252 dev_priv->saveCURBPOS = I915_READ(_CURBPOS); 253 dev_priv->saveCURBBASE = I915_READ(_CURBBASE); 254 if (IS_GEN2(dev)) 255 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 256 257 if (HAS_PCH_SPLIT(dev)) { 258 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); 259 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); 260 } 261 262 /* Pipe & plane A info */ 263 dev_priv->savePIPEACONF = I915_READ(_PIPEACONF); 264 dev_priv->savePIPEASRC = I915_READ(_PIPEASRC); 265 if (HAS_PCH_SPLIT(dev)) { 266 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0); 267 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1); 268 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A); 269 } else { 270 dev_priv->saveFPA0 = I915_READ(_FPA0); 271 dev_priv->saveFPA1 = I915_READ(_FPA1); 272 dev_priv->saveDPLL_A = I915_READ(_DPLL_A); 273 } 274 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 275 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD); 276 dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A); 277 dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A); 278 dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A); 279 dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A); 280 dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A); 281 dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A); 282 if (!HAS_PCH_SPLIT(dev)) 283 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A); 284 285 if (HAS_PCH_SPLIT(dev)) { 286 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1); 287 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1); 288 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1); 289 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1); 290 291 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL); 292 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL); 293 294 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1); 295 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ); 296 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS); 297 298 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF); 299 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A); 300 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A); 301 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A); 302 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A); 303 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A); 304 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A); 305 } 306 307 dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR); 308 dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE); 309 dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE); 310 dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS); 311 dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR); 312 if (INTEL_INFO(dev)->gen >= 4) { 313 dev_priv->saveDSPASURF = I915_READ(_DSPASURF); 314 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF); 315 } 316 i915_save_palette(dev, PIPE_A); 317 dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT); 318 319 /* Pipe & plane B info */ 320 dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF); 321 dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC); 322 if (HAS_PCH_SPLIT(dev)) { 323 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0); 324 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1); 325 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B); 326 } else { 327 dev_priv->saveFPB0 = I915_READ(_FPB0); 328 dev_priv->saveFPB1 = I915_READ(_FPB1); 329 dev_priv->saveDPLL_B = I915_READ(_DPLL_B); 330 } 331 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 332 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD); 333 dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B); 334 dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B); 335 dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B); 336 dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B); 337 dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B); 338 dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B); 339 if (!HAS_PCH_SPLIT(dev)) 340 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B); 341 342 if (HAS_PCH_SPLIT(dev)) { 343 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1); 344 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1); 345 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1); 346 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1); 347 348 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL); 349 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL); 350 351 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1); 352 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ); 353 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS); 354 355 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF); 356 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B); 357 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B); 358 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B); 359 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B); 360 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B); 361 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B); 362 } 363 364 dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR); 365 dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE); 366 dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE); 367 dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS); 368 dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR); 369 if (INTEL_INFO(dev)->gen >= 4) { 370 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF); 371 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF); 372 } 373 i915_save_palette(dev, PIPE_B); 374 dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT); 375 376 /* Fences */ 377 switch (INTEL_INFO(dev)->gen) { 378 case 7: 379 case 6: 380 for (i = 0; i < 16; i++) 381 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 382 break; 383 case 5: 384 case 4: 385 for (i = 0; i < 16; i++) 386 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 387 break; 388 case 3: 389 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 390 for (i = 0; i < 8; i++) 391 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 392 case 2: 393 for (i = 0; i < 8; i++) 394 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 395 break; 396 } 397 398 return; 399 } 400 401 static void i915_restore_modeset_reg(struct drm_device *dev) 402 { 403 struct drm_i915_private *dev_priv = dev->dev_private; 404 int dpll_a_reg, fpa0_reg, fpa1_reg; 405 int dpll_b_reg, fpb0_reg, fpb1_reg; 406 int i; 407 408 if (drm_core_check_feature(dev, DRIVER_MODESET)) 409 return; 410 411 /* Fences */ 412 switch (INTEL_INFO(dev)->gen) { 413 case 7: 414 case 6: 415 for (i = 0; i < 16; i++) 416 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]); 417 break; 418 case 5: 419 case 4: 420 for (i = 0; i < 16; i++) 421 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]); 422 break; 423 case 3: 424 case 2: 425 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 426 for (i = 0; i < 8; i++) 427 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); 428 for (i = 0; i < 8; i++) 429 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); 430 break; 431 } 432 433 434 if (HAS_PCH_SPLIT(dev)) { 435 dpll_a_reg = _PCH_DPLL_A; 436 dpll_b_reg = _PCH_DPLL_B; 437 fpa0_reg = _PCH_FPA0; 438 fpb0_reg = _PCH_FPB0; 439 fpa1_reg = _PCH_FPA1; 440 fpb1_reg = _PCH_FPB1; 441 } else { 442 dpll_a_reg = _DPLL_A; 443 dpll_b_reg = _DPLL_B; 444 fpa0_reg = _FPA0; 445 fpb0_reg = _FPB0; 446 fpa1_reg = _FPA1; 447 fpb1_reg = _FPB1; 448 } 449 450 if (HAS_PCH_SPLIT(dev)) { 451 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); 452 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); 453 } 454 455 /* Pipe & plane A info */ 456 /* Prime the clock */ 457 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 458 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & 459 ~DPLL_VCO_ENABLE); 460 POSTING_READ(dpll_a_reg); 461 DRM_UDELAY(150); 462 } 463 I915_WRITE(fpa0_reg, dev_priv->saveFPA0); 464 I915_WRITE(fpa1_reg, dev_priv->saveFPA1); 465 /* Actually enable it */ 466 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 467 POSTING_READ(dpll_a_reg); 468 DRM_UDELAY(150); 469 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { 470 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD); 471 POSTING_READ(_DPLL_A_MD); 472 } 473 DRM_UDELAY(150); 474 475 /* Restore mode */ 476 I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A); 477 I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A); 478 I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A); 479 I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A); 480 I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A); 481 I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A); 482 if (!HAS_PCH_SPLIT(dev)) 483 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A); 484 485 if (HAS_PCH_SPLIT(dev)) { 486 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); 487 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); 488 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); 489 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1); 490 491 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); 492 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); 493 494 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1); 495 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ); 496 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS); 497 498 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF); 499 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A); 500 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A); 501 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A); 502 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A); 503 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A); 504 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A); 505 } 506 507 /* Restore plane info */ 508 I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE); 509 I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS); 510 I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC); 511 I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR); 512 I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE); 513 if (INTEL_INFO(dev)->gen >= 4) { 514 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF); 515 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF); 516 } 517 518 I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF); 519 520 i915_restore_palette(dev, PIPE_A); 521 /* Enable the plane */ 522 I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR); 523 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR)); 524 525 /* Pipe & plane B info */ 526 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 527 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B & 528 ~DPLL_VCO_ENABLE); 529 POSTING_READ(dpll_b_reg); 530 DRM_UDELAY(150); 531 } 532 I915_WRITE(fpb0_reg, dev_priv->saveFPB0); 533 I915_WRITE(fpb1_reg, dev_priv->saveFPB1); 534 /* Actually enable it */ 535 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); 536 POSTING_READ(dpll_b_reg); 537 DRM_UDELAY(150); 538 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { 539 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD); 540 POSTING_READ(_DPLL_B_MD); 541 } 542 DRM_UDELAY(150); 543 544 /* Restore mode */ 545 I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B); 546 I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B); 547 I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B); 548 I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B); 549 I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B); 550 I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B); 551 if (!HAS_PCH_SPLIT(dev)) 552 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B); 553 554 if (HAS_PCH_SPLIT(dev)) { 555 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); 556 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); 557 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); 558 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1); 559 560 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); 561 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); 562 563 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1); 564 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ); 565 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS); 566 567 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF); 568 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B); 569 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B); 570 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B); 571 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B); 572 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B); 573 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B); 574 } 575 576 /* Restore plane info */ 577 I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE); 578 I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS); 579 I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC); 580 I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR); 581 I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 582 if (INTEL_INFO(dev)->gen >= 4) { 583 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF); 584 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); 585 } 586 587 I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF); 588 589 i915_restore_palette(dev, PIPE_B); 590 /* Enable the plane */ 591 I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR); 592 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR)); 593 594 /* Cursor state */ 595 I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS); 596 I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR); 597 I915_WRITE(_CURABASE, dev_priv->saveCURABASE); 598 I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS); 599 I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR); 600 I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE); 601 if (IS_GEN2(dev)) 602 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 603 604 return; 605 } 606 607 static void i915_save_display(struct drm_device *dev) 608 { 609 struct drm_i915_private *dev_priv = dev->dev_private; 610 611 /* Display arbitration control */ 612 dev_priv->saveDSPARB = I915_READ(DSPARB); 613 614 /* This is only meaningful in non-KMS mode */ 615 /* Don't save them in KMS mode */ 616 i915_save_modeset_reg(dev); 617 618 /* CRT state */ 619 if (HAS_PCH_SPLIT(dev)) { 620 dev_priv->saveADPA = I915_READ(PCH_ADPA); 621 } else { 622 dev_priv->saveADPA = I915_READ(ADPA); 623 } 624 625 /* LVDS state */ 626 if (HAS_PCH_SPLIT(dev)) { 627 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); 628 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); 629 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); 630 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); 631 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); 632 dev_priv->saveLVDS = I915_READ(PCH_LVDS); 633 } else { 634 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); 635 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 636 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 637 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); 638 if (INTEL_INFO(dev)->gen >= 4) 639 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); 640 if (IS_MOBILE(dev) && !IS_I830(dev)) 641 dev_priv->saveLVDS = I915_READ(LVDS); 642 } 643 644 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) 645 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 646 647 if (HAS_PCH_SPLIT(dev)) { 648 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); 649 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); 650 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); 651 } else { 652 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); 653 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); 654 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); 655 } 656 657 /* Display Port state */ 658 if (SUPPORTS_INTEGRATED_DP(dev)) { 659 dev_priv->saveDP_B = I915_READ(DP_B); 660 dev_priv->saveDP_C = I915_READ(DP_C); 661 dev_priv->saveDP_D = I915_READ(DP_D); 662 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M); 663 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M); 664 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N); 665 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N); 666 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M); 667 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M); 668 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N); 669 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N); 670 } 671 /* FIXME: save TV & SDVO state */ 672 673 /* Only save FBC state on the platform that supports FBC */ 674 if (I915_HAS_FBC(dev)) { 675 if (HAS_PCH_SPLIT(dev)) { 676 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); 677 } else if (IS_GM45(dev)) { 678 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); 679 } else { 680 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); 681 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); 682 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); 683 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); 684 } 685 } 686 687 /* VGA state */ 688 dev_priv->saveVGA0 = I915_READ(VGA0); 689 dev_priv->saveVGA1 = I915_READ(VGA1); 690 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 691 if (HAS_PCH_SPLIT(dev)) 692 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); 693 else 694 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 695 696 i915_save_vga(dev); 697 } 698 699 static void i915_restore_display(struct drm_device *dev) 700 { 701 struct drm_i915_private *dev_priv = dev->dev_private; 702 703 /* Display arbitration */ 704 I915_WRITE(DSPARB, dev_priv->saveDSPARB); 705 706 /* Display port ratios (must be done before clock is set) */ 707 if (SUPPORTS_INTEGRATED_DP(dev)) { 708 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M); 709 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M); 710 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N); 711 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N); 712 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M); 713 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M); 714 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N); 715 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N); 716 } 717 718 /* This is only meaningful in non-KMS mode */ 719 /* Don't restore them in KMS mode */ 720 i915_restore_modeset_reg(dev); 721 722 /* CRT state */ 723 if (HAS_PCH_SPLIT(dev)) 724 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 725 else 726 I915_WRITE(ADPA, dev_priv->saveADPA); 727 728 /* LVDS state */ 729 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 730 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 731 732 if (HAS_PCH_SPLIT(dev)) { 733 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); 734 } else if (IS_MOBILE(dev) && !IS_I830(dev)) 735 I915_WRITE(LVDS, dev_priv->saveLVDS); 736 737 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) 738 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 739 740 if (HAS_PCH_SPLIT(dev)) { 741 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 742 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 743 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); 744 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2); 745 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 746 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 747 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); 748 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); 749 I915_WRITE(RSTDBYCTL, 750 dev_priv->saveMCHBAR_RENDER_STANDBY); 751 } else { 752 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 753 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 754 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL); 755 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 756 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 757 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); 758 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 759 } 760 761 /* Display Port state */ 762 if (SUPPORTS_INTEGRATED_DP(dev)) { 763 I915_WRITE(DP_B, dev_priv->saveDP_B); 764 I915_WRITE(DP_C, dev_priv->saveDP_C); 765 I915_WRITE(DP_D, dev_priv->saveDP_D); 766 } 767 /* FIXME: restore TV & SDVO state */ 768 769 /* only restore FBC info on the platform that supports FBC*/ 770 intel_disable_fbc(dev); 771 if (I915_HAS_FBC(dev)) { 772 if (HAS_PCH_SPLIT(dev)) { 773 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); 774 } else if (IS_GM45(dev)) { 775 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); 776 } else { 777 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); 778 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); 779 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); 780 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); 781 } 782 } 783 /* VGA state */ 784 if (HAS_PCH_SPLIT(dev)) 785 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 786 else 787 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 788 789 I915_WRITE(VGA0, dev_priv->saveVGA0); 790 I915_WRITE(VGA1, dev_priv->saveVGA1); 791 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 792 POSTING_READ(VGA_PD); 793 DRM_UDELAY(150); 794 795 i915_restore_vga(dev); 796 } 797 798 int i915_save_state(struct drm_device *dev) 799 { 800 struct drm_i915_private *dev_priv = dev->dev_private; 801 int i; 802 803 dev_priv->saveLBB = pci_read_config(dev->device, LBB, 1); 804 805 /* Hardware status page */ 806 dev_priv->saveHWS = I915_READ(HWS_PGA); 807 808 i915_save_display(dev); 809 810 /* Interrupt state */ 811 if (HAS_PCH_SPLIT(dev)) { 812 dev_priv->saveDEIER = I915_READ(DEIER); 813 dev_priv->saveDEIMR = I915_READ(DEIMR); 814 dev_priv->saveGTIER = I915_READ(GTIER); 815 dev_priv->saveGTIMR = I915_READ(GTIMR); 816 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR); 817 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR); 818 dev_priv->saveMCHBAR_RENDER_STANDBY = 819 I915_READ(RSTDBYCTL); 820 dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG); 821 } else { 822 dev_priv->saveIER = I915_READ(IER); 823 dev_priv->saveIMR = I915_READ(IMR); 824 } 825 826 if (IS_IRONLAKE_M(dev)) 827 ironlake_disable_drps(dev); 828 if (INTEL_INFO(dev)->gen >= 6) 829 gen6_disable_rps(dev); 830 831 /* Cache mode state */ 832 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 833 834 /* Memory Arbitration state */ 835 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); 836 837 /* Scratch space */ 838 for (i = 0; i < 16; i++) { 839 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); 840 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); 841 } 842 for (i = 0; i < 3; i++) 843 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 844 845 return 0; 846 } 847 848 int i915_restore_state(struct drm_device *dev) 849 { 850 struct drm_i915_private *dev_priv = dev->dev_private; 851 int i; 852 853 pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1); 854 855 856 /* Hardware status page */ 857 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 858 859 i915_restore_display(dev); 860 861 /* Interrupt state */ 862 if (HAS_PCH_SPLIT(dev)) { 863 I915_WRITE(DEIER, dev_priv->saveDEIER); 864 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 865 I915_WRITE(GTIER, dev_priv->saveGTIER); 866 I915_WRITE(GTIMR, dev_priv->saveGTIMR); 867 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); 868 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); 869 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG); 870 } else { 871 I915_WRITE(IER, dev_priv->saveIER); 872 I915_WRITE(IMR, dev_priv->saveIMR); 873 } 874 DRM_UNLOCK(dev); 875 876 if (drm_core_check_feature(dev, DRIVER_MODESET)) 877 intel_init_clock_gating(dev); 878 879 if (IS_IRONLAKE_M(dev)) { 880 ironlake_enable_drps(dev); 881 intel_init_emon(dev); 882 } 883 884 if (INTEL_INFO(dev)->gen >= 6) { 885 gen6_enable_rps(dev_priv); 886 gen6_update_ring_freq(dev_priv); 887 } 888 889 DRM_LOCK(dev); 890 891 /* Cache mode state */ 892 I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 893 894 /* Memory arbitration state */ 895 I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); 896 897 for (i = 0; i < 16; i++) { 898 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); 899 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]); 900 } 901 for (i = 0; i < 3; i++) 902 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 903 904 intel_iic_reset(dev); 905 906 return 0; 907 } 908