1 /* 2 * 3 * Copyright 2008 (c) Intel Corporation 4 * Jesse Barnes <jbarnes@virtuousgeek.org> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #include <drm/drmP.h> 28 #include <drm/i915_drm.h> 29 #include "intel_drv.h" 30 #include "i915_reg.h" 31 32 static void i915_save_display(struct drm_i915_private *dev_priv) 33 { 34 /* Display arbitration control */ 35 if (INTEL_GEN(dev_priv) <= 4) 36 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); 37 38 /* save FBC interval */ 39 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) 40 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); 41 } 42 43 static void i915_restore_display(struct drm_i915_private *dev_priv) 44 { 45 /* Display arbitration */ 46 if (INTEL_GEN(dev_priv) <= 4) 47 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); 48 49 /* only restore FBC info on the platform that supports FBC*/ 50 intel_fbc_global_disable(dev_priv); 51 52 /* restore FBC interval */ 53 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) 54 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); 55 56 i915_redisable_vga(dev_priv); 57 } 58 59 int i915_save_state(struct drm_device *dev) 60 { 61 struct drm_i915_private *dev_priv = to_i915(dev); 62 struct pci_dev *pdev = dev_priv->drm.pdev; 63 int i; 64 65 mutex_lock(&dev->struct_mutex); 66 67 i915_save_display(dev_priv); 68 69 if (IS_GEN4(dev_priv)) 70 pci_read_config_word(pdev, GCDGMBUS, 71 &dev_priv->regfile.saveGCDGMBUS); 72 73 /* Cache mode state */ 74 if (INTEL_GEN(dev_priv) < 7) 75 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 76 77 /* Memory Arbitration state */ 78 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); 79 80 /* Scratch space */ 81 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { 82 for (i = 0; i < 7; i++) { 83 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); 84 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 85 } 86 for (i = 0; i < 3; i++) 87 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); 88 } else if (IS_GEN2(dev_priv)) { 89 for (i = 0; i < 7; i++) 90 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 91 } else if (HAS_GMCH_DISPLAY(dev_priv)) { 92 for (i = 0; i < 16; i++) { 93 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); 94 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); 95 } 96 for (i = 0; i < 3; i++) 97 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); 98 } 99 100 mutex_unlock(&dev->struct_mutex); 101 102 return 0; 103 } 104 105 int i915_restore_state(struct drm_device *dev) 106 { 107 struct drm_i915_private *dev_priv = to_i915(dev); 108 struct pci_dev *pdev = dev_priv->drm.pdev; 109 int i; 110 111 mutex_lock(&dev->struct_mutex); 112 113 i915_gem_restore_fences(dev_priv); 114 115 if (IS_GEN4(dev_priv)) 116 pci_write_config_word(pdev, GCDGMBUS, 117 dev_priv->regfile.saveGCDGMBUS); 118 i915_restore_display(dev_priv); 119 120 /* Cache mode state */ 121 if (INTEL_GEN(dev_priv) < 7) 122 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 123 0xffff0000); 124 125 /* Memory arbitration state */ 126 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); 127 128 /* Scratch space */ 129 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { 130 for (i = 0; i < 7; i++) { 131 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); 132 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 133 } 134 for (i = 0; i < 3; i++) 135 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); 136 } else if (IS_GEN2(dev_priv)) { 137 for (i = 0; i < 7; i++) 138 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 139 } else if (HAS_GMCH_DISPLAY(dev_priv)) { 140 for (i = 0; i < 16; i++) { 141 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); 142 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); 143 } 144 for (i = 0; i < 3; i++) 145 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); 146 } 147 148 mutex_unlock(&dev->struct_mutex); 149 150 intel_i2c_reset(dev); 151 152 return 0; 153 } 154