1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28 #include <linux/device.h> 29 #include <linux/module.h> 30 #include <linux/stat.h> 31 #include <linux/sysfs.h> 32 #include "intel_drv.h" 33 #include "i915_drv.h" 34 35 #if 0 36 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev) 37 { 38 struct drm_minor *minor = dev_get_drvdata(kdev); 39 return to_i915(minor->dev); 40 } 41 42 #ifdef CONFIG_PM 43 static u32 calc_residency(struct drm_i915_private *dev_priv, 44 i915_reg_t reg) 45 { 46 return intel_rc6_residency(dev_priv, reg); 47 } 48 49 static ssize_t 50 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) 51 { 52 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6()); 53 } 54 55 static ssize_t 56 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 57 { 58 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 59 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); 60 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 61 } 62 63 static ssize_t 64 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) 65 { 66 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 67 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); 68 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); 69 } 70 71 static ssize_t 72 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) 73 { 74 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 75 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); 76 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); 77 } 78 79 static ssize_t 80 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 81 { 82 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 83 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); 84 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 85 } 86 87 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); 88 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); 89 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); 90 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); 91 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); 92 93 static struct attribute *rc6_attrs[] = { 94 &dev_attr_rc6_enable.attr, 95 &dev_attr_rc6_residency_ms.attr, 96 NULL 97 }; 98 99 static struct attribute_group rc6_attr_group = { 100 .name = power_group_name, 101 .attrs = rc6_attrs 102 }; 103 104 static struct attribute *rc6p_attrs[] = { 105 &dev_attr_rc6p_residency_ms.attr, 106 &dev_attr_rc6pp_residency_ms.attr, 107 NULL 108 }; 109 110 static struct attribute_group rc6p_attr_group = { 111 .name = power_group_name, 112 .attrs = rc6p_attrs 113 }; 114 115 static struct attribute *media_rc6_attrs[] = { 116 &dev_attr_media_rc6_residency_ms.attr, 117 NULL 118 }; 119 120 static struct attribute_group media_rc6_attr_group = { 121 .name = power_group_name, 122 .attrs = media_rc6_attrs 123 }; 124 #endif 125 126 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset) 127 { 128 if (!HAS_L3_DPF(dev_priv)) 129 return -EPERM; 130 131 if (offset % 4 != 0) 132 return -EINVAL; 133 134 if (offset >= GEN7_L3LOG_SIZE) 135 return -ENXIO; 136 137 return 0; 138 } 139 140 static ssize_t 141 i915_l3_read(struct file *filp, struct kobject *kobj, 142 struct bin_attribute *attr, char *buf, 143 loff_t offset, size_t count) 144 { 145 struct device *kdev = kobj_to_dev(kobj); 146 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 147 struct drm_device *dev = &dev_priv->drm; 148 int slice = (int)(uintptr_t)attr->private; 149 int ret; 150 151 count = round_down(count, 4); 152 153 ret = l3_access_valid(dev_priv, offset); 154 if (ret) 155 return ret; 156 157 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); 158 159 ret = i915_mutex_lock_interruptible(dev); 160 if (ret) 161 return ret; 162 163 if (dev_priv->l3_parity.remap_info[slice]) 164 memcpy(buf, 165 dev_priv->l3_parity.remap_info[slice] + (offset/4), 166 count); 167 else 168 memset(buf, 0, count); 169 170 mutex_unlock(&dev->struct_mutex); 171 172 return count; 173 } 174 175 static ssize_t 176 i915_l3_write(struct file *filp, struct kobject *kobj, 177 struct bin_attribute *attr, char *buf, 178 loff_t offset, size_t count) 179 { 180 struct device *kdev = kobj_to_dev(kobj); 181 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 182 struct drm_device *dev = &dev_priv->drm; 183 struct i915_gem_context *ctx; 184 u32 *temp = NULL; /* Just here to make handling failures easy */ 185 int slice = (int)(uintptr_t)attr->private; 186 int ret; 187 188 if (!HAS_HW_CONTEXTS(dev_priv)) 189 return -ENXIO; 190 191 ret = l3_access_valid(dev_priv, offset); 192 if (ret) 193 return ret; 194 195 ret = i915_mutex_lock_interruptible(dev); 196 if (ret) 197 return ret; 198 199 if (!dev_priv->l3_parity.remap_info[slice]) { 200 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); 201 if (!temp) { 202 mutex_unlock(&dev->struct_mutex); 203 return -ENOMEM; 204 } 205 } 206 207 /* TODO: Ideally we really want a GPU reset here to make sure errors 208 * aren't propagated. Since I cannot find a stable way to reset the GPU 209 * at this point it is left as a TODO. 210 */ 211 if (temp) 212 dev_priv->l3_parity.remap_info[slice] = temp; 213 214 memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count); 215 216 /* NB: We defer the remapping until we switch to the context */ 217 list_for_each_entry(ctx, &dev_priv->context_list, link) 218 ctx->remap_slice |= (1<<slice); 219 220 mutex_unlock(&dev->struct_mutex); 221 222 return count; 223 } 224 225 static struct bin_attribute dpf_attrs = { 226 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, 227 .size = GEN7_L3LOG_SIZE, 228 .read = i915_l3_read, 229 .write = i915_l3_write, 230 .mmap = NULL, 231 .private = (void *)0 232 }; 233 234 static struct bin_attribute dpf_attrs_1 = { 235 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, 236 .size = GEN7_L3LOG_SIZE, 237 .read = i915_l3_read, 238 .write = i915_l3_write, 239 .mmap = NULL, 240 .private = (void *)1 241 }; 242 243 static ssize_t gt_act_freq_mhz_show(struct device *kdev, 244 struct device_attribute *attr, char *buf) 245 { 246 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 247 int ret; 248 249 intel_runtime_pm_get(dev_priv); 250 251 mutex_lock(&dev_priv->rps.hw_lock); 252 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 253 u32 freq; 254 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 255 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); 256 } else { 257 u32 rpstat = I915_READ(GEN6_RPSTAT1); 258 if (IS_GEN9(dev_priv)) 259 ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 260 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 261 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 262 else 263 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 264 ret = intel_gpu_freq(dev_priv, ret); 265 } 266 mutex_unlock(&dev_priv->rps.hw_lock); 267 268 intel_runtime_pm_put(dev_priv); 269 270 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 271 } 272 273 static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 274 struct device_attribute *attr, char *buf) 275 { 276 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 277 278 return snprintf(buf, PAGE_SIZE, "%d\n", 279 intel_gpu_freq(dev_priv, 280 dev_priv->rps.cur_freq)); 281 } 282 283 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 284 { 285 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 286 287 return snprintf(buf, PAGE_SIZE, "%d\n", 288 intel_gpu_freq(dev_priv, 289 dev_priv->rps.boost_freq)); 290 } 291 292 static ssize_t gt_boost_freq_mhz_store(struct device *kdev, 293 struct device_attribute *attr, 294 const char *buf, size_t count) 295 { 296 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 297 u32 val; 298 ssize_t ret; 299 300 ret = kstrtou32(buf, 0, &val); 301 if (ret) 302 return ret; 303 304 /* Validate against (static) hardware limits */ 305 val = intel_freq_opcode(dev_priv, val); 306 if (val < dev_priv->rps.min_freq || val > dev_priv->rps.max_freq) 307 return -EINVAL; 308 309 mutex_lock(&dev_priv->rps.hw_lock); 310 dev_priv->rps.boost_freq = val; 311 mutex_unlock(&dev_priv->rps.hw_lock); 312 313 return count; 314 } 315 316 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, 317 struct device_attribute *attr, char *buf) 318 { 319 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 320 321 return snprintf(buf, PAGE_SIZE, "%d\n", 322 intel_gpu_freq(dev_priv, 323 dev_priv->rps.efficient_freq)); 324 } 325 326 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 327 { 328 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 329 330 return snprintf(buf, PAGE_SIZE, "%d\n", 331 intel_gpu_freq(dev_priv, 332 dev_priv->rps.max_freq_softlimit)); 333 } 334 335 static ssize_t gt_max_freq_mhz_store(struct device *kdev, 336 struct device_attribute *attr, 337 const char *buf, size_t count) 338 { 339 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 340 u32 val; 341 ssize_t ret; 342 343 ret = kstrtou32(buf, 0, &val); 344 if (ret) 345 return ret; 346 347 intel_runtime_pm_get(dev_priv); 348 349 mutex_lock(&dev_priv->rps.hw_lock); 350 351 val = intel_freq_opcode(dev_priv, val); 352 353 if (val < dev_priv->rps.min_freq || 354 val > dev_priv->rps.max_freq || 355 val < dev_priv->rps.min_freq_softlimit) { 356 mutex_unlock(&dev_priv->rps.hw_lock); 357 intel_runtime_pm_put(dev_priv); 358 return -EINVAL; 359 } 360 361 if (val > dev_priv->rps.rp0_freq) 362 DRM_DEBUG("User requested overclocking to %d\n", 363 intel_gpu_freq(dev_priv, val)); 364 365 dev_priv->rps.max_freq_softlimit = val; 366 367 val = clamp_t(int, dev_priv->rps.cur_freq, 368 dev_priv->rps.min_freq_softlimit, 369 dev_priv->rps.max_freq_softlimit); 370 371 /* We still need *_set_rps to process the new max_delay and 372 * update the interrupt limits and PMINTRMSK even though 373 * frequency request may be unchanged. */ 374 ret = intel_set_rps(dev_priv, val); 375 376 mutex_unlock(&dev_priv->rps.hw_lock); 377 378 intel_runtime_pm_put(dev_priv); 379 380 return ret ?: count; 381 } 382 383 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 384 { 385 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 386 387 return snprintf(buf, PAGE_SIZE, "%d\n", 388 intel_gpu_freq(dev_priv, 389 dev_priv->rps.min_freq_softlimit)); 390 } 391 392 static ssize_t gt_min_freq_mhz_store(struct device *kdev, 393 struct device_attribute *attr, 394 const char *buf, size_t count) 395 { 396 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 397 u32 val; 398 ssize_t ret; 399 400 ret = kstrtou32(buf, 0, &val); 401 if (ret) 402 return ret; 403 404 intel_runtime_pm_get(dev_priv); 405 406 mutex_lock(&dev_priv->rps.hw_lock); 407 408 val = intel_freq_opcode(dev_priv, val); 409 410 if (val < dev_priv->rps.min_freq || 411 val > dev_priv->rps.max_freq || 412 val > dev_priv->rps.max_freq_softlimit) { 413 mutex_unlock(&dev_priv->rps.hw_lock); 414 intel_runtime_pm_put(dev_priv); 415 return -EINVAL; 416 } 417 418 dev_priv->rps.min_freq_softlimit = val; 419 420 val = clamp_t(int, dev_priv->rps.cur_freq, 421 dev_priv->rps.min_freq_softlimit, 422 dev_priv->rps.max_freq_softlimit); 423 424 /* We still need *_set_rps to process the new min_delay and 425 * update the interrupt limits and PMINTRMSK even though 426 * frequency request may be unchanged. */ 427 ret = intel_set_rps(dev_priv, val); 428 429 mutex_unlock(&dev_priv->rps.hw_lock); 430 431 intel_runtime_pm_put(dev_priv); 432 433 return ret ?: count; 434 } 435 436 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); 437 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); 438 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO | S_IWUSR, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store); 439 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); 440 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); 441 442 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); 443 444 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); 445 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 446 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 447 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 448 449 /* For now we have a static number of RP states */ 450 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 451 { 452 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 453 u32 val; 454 455 if (attr == &dev_attr_gt_RP0_freq_mhz) 456 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); 457 else if (attr == &dev_attr_gt_RP1_freq_mhz) 458 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); 459 else if (attr == &dev_attr_gt_RPn_freq_mhz) 460 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq); 461 else 462 BUG(); 463 464 return snprintf(buf, PAGE_SIZE, "%d\n", val); 465 } 466 467 static const struct attribute *gen6_attrs[] = { 468 &dev_attr_gt_act_freq_mhz.attr, 469 &dev_attr_gt_cur_freq_mhz.attr, 470 &dev_attr_gt_boost_freq_mhz.attr, 471 &dev_attr_gt_max_freq_mhz.attr, 472 &dev_attr_gt_min_freq_mhz.attr, 473 &dev_attr_gt_RP0_freq_mhz.attr, 474 &dev_attr_gt_RP1_freq_mhz.attr, 475 &dev_attr_gt_RPn_freq_mhz.attr, 476 NULL, 477 }; 478 479 static const struct attribute *vlv_attrs[] = { 480 &dev_attr_gt_act_freq_mhz.attr, 481 &dev_attr_gt_cur_freq_mhz.attr, 482 &dev_attr_gt_boost_freq_mhz.attr, 483 &dev_attr_gt_max_freq_mhz.attr, 484 &dev_attr_gt_min_freq_mhz.attr, 485 &dev_attr_gt_RP0_freq_mhz.attr, 486 &dev_attr_gt_RP1_freq_mhz.attr, 487 &dev_attr_gt_RPn_freq_mhz.attr, 488 &dev_attr_vlv_rpe_freq_mhz.attr, 489 NULL, 490 }; 491 492 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 493 494 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 495 struct bin_attribute *attr, char *buf, 496 loff_t off, size_t count) 497 { 498 499 struct device *kdev = kobj_to_dev(kobj); 500 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 501 struct drm_i915_error_state_buf error_str; 502 struct i915_gpu_state *gpu; 503 ssize_t ret; 504 505 ret = i915_error_state_buf_init(&error_str, dev_priv, count, off); 506 if (ret) 507 return ret; 508 509 gpu = i915_first_error_state(dev_priv); 510 ret = i915_error_state_to_str(&error_str, gpu); 511 if (ret) 512 goto out; 513 514 ret = count < error_str.bytes ? count : error_str.bytes; 515 memcpy(buf, error_str.buf, ret); 516 517 out: 518 i915_gpu_state_put(gpu); 519 i915_error_state_buf_release(&error_str); 520 521 return ret; 522 } 523 524 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 525 struct bin_attribute *attr, char *buf, 526 loff_t off, size_t count) 527 { 528 struct device *kdev = kobj_to_dev(kobj); 529 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 530 531 DRM_DEBUG_DRIVER("Resetting error state\n"); 532 i915_reset_error_state(dev_priv); 533 534 return count; 535 } 536 537 static struct bin_attribute error_state_attr = { 538 .attr.name = "error", 539 .attr.mode = S_IRUSR | S_IWUSR, 540 .size = 0, 541 .read = error_state_read, 542 .write = error_state_write, 543 }; 544 #endif 545 546 static void i915_setup_error_capture(struct device *kdev) 547 { 548 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 549 DRM_ERROR("error_state sysfs setup failed\n"); 550 } 551 552 static void i915_teardown_error_capture(struct device *kdev) 553 { 554 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 555 } 556 #else 557 static void i915_setup_error_capture(struct device *kdev) {} 558 static void i915_teardown_error_capture(struct device *kdev) {} 559 #endif 560 561 void i915_setup_sysfs(struct drm_i915_private *dev_priv) 562 { 563 struct device *kdev = dev_priv->drm.primary->kdev; 564 #if 0 565 int ret; 566 567 #ifdef CONFIG_PM 568 if (HAS_RC6(dev_priv)) { 569 ret = sysfs_merge_group(&kdev->kobj, 570 &rc6_attr_group); 571 if (ret) 572 DRM_ERROR("RC6 residency sysfs setup failed\n"); 573 } 574 if (HAS_RC6p(dev_priv)) { 575 ret = sysfs_merge_group(&kdev->kobj, 576 &rc6p_attr_group); 577 if (ret) 578 DRM_ERROR("RC6p residency sysfs setup failed\n"); 579 } 580 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 581 ret = sysfs_merge_group(&kdev->kobj, 582 &media_rc6_attr_group); 583 if (ret) 584 DRM_ERROR("Media RC6 residency sysfs setup failed\n"); 585 } 586 #endif 587 if (HAS_L3_DPF(dev_priv)) { 588 ret = device_create_bin_file(kdev, &dpf_attrs); 589 if (ret) 590 DRM_ERROR("l3 parity sysfs setup failed\n"); 591 592 if (NUM_L3_SLICES(dev_priv) > 1) { 593 ret = device_create_bin_file(kdev, 594 &dpf_attrs_1); 595 if (ret) 596 DRM_ERROR("l3 parity slice 1 setup failed\n"); 597 } 598 } 599 600 ret = 0; 601 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 602 ret = sysfs_create_files(&kdev->kobj, vlv_attrs); 603 else if (INTEL_GEN(dev_priv) >= 6) 604 ret = sysfs_create_files(&kdev->kobj, gen6_attrs); 605 if (ret) 606 DRM_ERROR("RPS sysfs setup failed\n"); 607 608 #endif 609 i915_setup_error_capture(kdev); 610 } 611 612 void i915_teardown_sysfs(struct drm_i915_private *dev_priv) 613 { 614 struct device *kdev = dev_priv->drm.primary->kdev; 615 616 i915_teardown_error_capture(kdev); 617 618 #if 0 619 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 620 sysfs_remove_files(&kdev->kobj, vlv_attrs); 621 else 622 sysfs_remove_files(&kdev->kobj, gen6_attrs); 623 device_remove_bin_file(kdev, &dpf_attrs_1); 624 device_remove_bin_file(kdev, &dpf_attrs); 625 #ifdef CONFIG_PM 626 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group); 627 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group); 628 #endif 629 #endif 630 } 631