1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28 #include <drm/drmP.h> 29 #include <linux/device.h> 30 #include <linux/module.h> 31 #include "intel_drv.h" 32 #include "i915_drv.h" 33 34 #if 0 35 #define dev_to_drm_minor(d) dev_get_drvdata((d)) 36 37 #ifdef CONFIG_PM 38 static u32 calc_residency(struct drm_device *dev, const u32 reg) 39 { 40 struct drm_i915_private *dev_priv = dev->dev_private; 41 u64 raw_time; /* 32b value may overflow during fixed point math */ 42 u64 units = 128ULL, div = 100000ULL; 43 u32 ret; 44 45 if (!intel_enable_rc6(dev)) 46 return 0; 47 48 intel_runtime_pm_get(dev_priv); 49 50 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 51 if (IS_VALLEYVIEW(dev)) { 52 units = 1; 53 div = dev_priv->czclk_freq; 54 55 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) 56 units <<= 8; 57 } else if (IS_BROXTON(dev)) { 58 units = 1; 59 div = 1200; /* 833.33ns */ 60 } 61 62 raw_time = I915_READ(reg) * units; 63 ret = DIV_ROUND_UP_ULL(raw_time, div); 64 65 intel_runtime_pm_put(dev_priv); 66 return ret; 67 } 68 69 static ssize_t 70 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) 71 { 72 struct drm_minor *dminor = dev_to_drm_minor(kdev); 73 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev)); 74 } 75 76 static ssize_t 77 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 78 { 79 struct drm_minor *dminor = dev_get_drvdata(kdev); 80 u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6); 81 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 82 } 83 84 static ssize_t 85 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) 86 { 87 struct drm_minor *dminor = dev_to_drm_minor(kdev); 88 u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p); 89 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); 90 } 91 92 static ssize_t 93 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) 94 { 95 struct drm_minor *dminor = dev_to_drm_minor(kdev); 96 u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp); 97 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); 98 } 99 100 static ssize_t 101 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 102 { 103 struct drm_minor *dminor = dev_get_drvdata(kdev); 104 u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6); 105 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 106 } 107 108 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); 109 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); 110 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); 111 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); 112 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); 113 114 static struct attribute *rc6_attrs[] = { 115 &dev_attr_rc6_enable.attr, 116 &dev_attr_rc6_residency_ms.attr, 117 NULL 118 }; 119 120 static struct attribute_group rc6_attr_group = { 121 .name = power_group_name, 122 .attrs = rc6_attrs 123 }; 124 125 static struct attribute *rc6p_attrs[] = { 126 &dev_attr_rc6p_residency_ms.attr, 127 &dev_attr_rc6pp_residency_ms.attr, 128 NULL 129 }; 130 131 static struct attribute_group rc6p_attr_group = { 132 .name = power_group_name, 133 .attrs = rc6p_attrs 134 }; 135 136 static struct attribute *media_rc6_attrs[] = { 137 &dev_attr_media_rc6_residency_ms.attr, 138 NULL 139 }; 140 141 static struct attribute_group media_rc6_attr_group = { 142 .name = power_group_name, 143 .attrs = media_rc6_attrs 144 }; 145 #endif 146 147 static int l3_access_valid(struct drm_device *dev, loff_t offset) 148 { 149 if (!HAS_L3_DPF(dev)) 150 return -EPERM; 151 152 if (offset % 4 != 0) 153 return -EINVAL; 154 155 if (offset >= GEN7_L3LOG_SIZE) 156 return -ENXIO; 157 158 return 0; 159 } 160 161 static ssize_t 162 i915_l3_read(struct file *filp, struct kobject *kobj, 163 struct bin_attribute *attr, char *buf, 164 loff_t offset, size_t count) 165 { 166 struct device *dev = container_of(kobj, struct device, kobj); 167 struct drm_minor *dminor = dev_to_drm_minor(dev); 168 struct drm_device *drm_dev = dminor->dev; 169 struct drm_i915_private *dev_priv = drm_dev->dev_private; 170 int slice = (int)(uintptr_t)attr->private; 171 int ret; 172 173 count = round_down(count, 4); 174 175 ret = l3_access_valid(drm_dev, offset); 176 if (ret) 177 return ret; 178 179 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); 180 181 ret = i915_mutex_lock_interruptible(drm_dev); 182 if (ret) 183 return ret; 184 185 if (dev_priv->l3_parity.remap_info[slice]) 186 memcpy(buf, 187 dev_priv->l3_parity.remap_info[slice] + (offset/4), 188 count); 189 else 190 memset(buf, 0, count); 191 192 mutex_unlock(&drm_dev->struct_mutex); 193 194 return count; 195 } 196 197 static ssize_t 198 i915_l3_write(struct file *filp, struct kobject *kobj, 199 struct bin_attribute *attr, char *buf, 200 loff_t offset, size_t count) 201 { 202 struct device *dev = container_of(kobj, struct device, kobj); 203 struct drm_minor *dminor = dev_to_drm_minor(dev); 204 struct drm_device *drm_dev = dminor->dev; 205 struct drm_i915_private *dev_priv = drm_dev->dev_private; 206 struct intel_context *ctx; 207 u32 *temp = NULL; /* Just here to make handling failures easy */ 208 int slice = (int)(uintptr_t)attr->private; 209 int ret; 210 211 if (!HAS_HW_CONTEXTS(drm_dev)) 212 return -ENXIO; 213 214 ret = l3_access_valid(drm_dev, offset); 215 if (ret) 216 return ret; 217 218 ret = i915_mutex_lock_interruptible(drm_dev); 219 if (ret) 220 return ret; 221 222 if (!dev_priv->l3_parity.remap_info[slice]) { 223 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); 224 if (!temp) { 225 mutex_unlock(&drm_dev->struct_mutex); 226 return -ENOMEM; 227 } 228 } 229 230 ret = i915_gpu_idle(drm_dev); 231 if (ret) { 232 kfree(temp); 233 mutex_unlock(&drm_dev->struct_mutex); 234 return ret; 235 } 236 237 /* TODO: Ideally we really want a GPU reset here to make sure errors 238 * aren't propagated. Since I cannot find a stable way to reset the GPU 239 * at this point it is left as a TODO. 240 */ 241 if (temp) 242 dev_priv->l3_parity.remap_info[slice] = temp; 243 244 memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count); 245 246 /* NB: We defer the remapping until we switch to the context */ 247 list_for_each_entry(ctx, &dev_priv->context_list, link) 248 ctx->remap_slice |= (1<<slice); 249 250 mutex_unlock(&drm_dev->struct_mutex); 251 252 return count; 253 } 254 255 static struct bin_attribute dpf_attrs = { 256 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, 257 .size = GEN7_L3LOG_SIZE, 258 .read = i915_l3_read, 259 .write = i915_l3_write, 260 .mmap = NULL, 261 .private = (void *)0 262 }; 263 264 static struct bin_attribute dpf_attrs_1 = { 265 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, 266 .size = GEN7_L3LOG_SIZE, 267 .read = i915_l3_read, 268 .write = i915_l3_write, 269 .mmap = NULL, 270 .private = (void *)1 271 }; 272 273 static ssize_t gt_act_freq_mhz_show(struct device *kdev, 274 struct device_attribute *attr, char *buf) 275 { 276 struct drm_minor *minor = dev_to_drm_minor(kdev); 277 struct drm_device *dev = minor->dev; 278 struct drm_i915_private *dev_priv = dev->dev_private; 279 int ret; 280 281 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 282 283 intel_runtime_pm_get(dev_priv); 284 285 mutex_lock(&dev_priv->rps.hw_lock); 286 if (IS_VALLEYVIEW(dev_priv->dev)) { 287 u32 freq; 288 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 289 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); 290 } else { 291 u32 rpstat = I915_READ(GEN6_RPSTAT1); 292 if (IS_GEN9(dev_priv)) 293 ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 294 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 295 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 296 else 297 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 298 ret = intel_gpu_freq(dev_priv, ret); 299 } 300 mutex_unlock(&dev_priv->rps.hw_lock); 301 302 intel_runtime_pm_put(dev_priv); 303 304 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 305 } 306 307 static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 308 struct device_attribute *attr, char *buf) 309 { 310 struct drm_minor *minor = dev_to_drm_minor(kdev); 311 struct drm_device *dev = minor->dev; 312 struct drm_i915_private *dev_priv = dev->dev_private; 313 int ret; 314 315 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 316 317 intel_runtime_pm_get(dev_priv); 318 319 mutex_lock(&dev_priv->rps.hw_lock); 320 ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq); 321 mutex_unlock(&dev_priv->rps.hw_lock); 322 323 intel_runtime_pm_put(dev_priv); 324 325 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 326 } 327 328 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, 329 struct device_attribute *attr, char *buf) 330 { 331 struct drm_minor *minor = dev_to_drm_minor(kdev); 332 struct drm_device *dev = minor->dev; 333 struct drm_i915_private *dev_priv = dev->dev_private; 334 335 return snprintf(buf, PAGE_SIZE, 336 "%d\n", 337 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 338 } 339 340 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 341 { 342 struct drm_minor *minor = dev_to_drm_minor(kdev); 343 struct drm_device *dev = minor->dev; 344 struct drm_i915_private *dev_priv = dev->dev_private; 345 int ret; 346 347 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 348 349 mutex_lock(&dev_priv->rps.hw_lock); 350 ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); 351 mutex_unlock(&dev_priv->rps.hw_lock); 352 353 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 354 } 355 356 static ssize_t gt_max_freq_mhz_store(struct device *kdev, 357 struct device_attribute *attr, 358 const char *buf, size_t count) 359 { 360 struct drm_minor *minor = dev_to_drm_minor(kdev); 361 struct drm_device *dev = minor->dev; 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 u32 val; 364 ssize_t ret; 365 366 ret = kstrtou32(buf, 0, &val); 367 if (ret) 368 return ret; 369 370 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 371 372 mutex_lock(&dev_priv->rps.hw_lock); 373 374 val = intel_freq_opcode(dev_priv, val); 375 376 if (val < dev_priv->rps.min_freq || 377 val > dev_priv->rps.max_freq || 378 val < dev_priv->rps.min_freq_softlimit) { 379 mutex_unlock(&dev_priv->rps.hw_lock); 380 return -EINVAL; 381 } 382 383 if (val > dev_priv->rps.rp0_freq) 384 DRM_DEBUG("User requested overclocking to %d\n", 385 intel_gpu_freq(dev_priv, val)); 386 387 dev_priv->rps.max_freq_softlimit = val; 388 389 val = clamp_t(int, dev_priv->rps.cur_freq, 390 dev_priv->rps.min_freq_softlimit, 391 dev_priv->rps.max_freq_softlimit); 392 393 /* We still need *_set_rps to process the new max_delay and 394 * update the interrupt limits and PMINTRMSK even though 395 * frequency request may be unchanged. */ 396 intel_set_rps(dev, val); 397 398 mutex_unlock(&dev_priv->rps.hw_lock); 399 400 return count; 401 } 402 403 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 404 { 405 struct drm_minor *minor = dev_to_drm_minor(kdev); 406 struct drm_device *dev = minor->dev; 407 struct drm_i915_private *dev_priv = dev->dev_private; 408 int ret; 409 410 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 411 412 mutex_lock(&dev_priv->rps.hw_lock); 413 ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); 414 mutex_unlock(&dev_priv->rps.hw_lock); 415 416 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 417 } 418 419 static ssize_t gt_min_freq_mhz_store(struct device *kdev, 420 struct device_attribute *attr, 421 const char *buf, size_t count) 422 { 423 struct drm_minor *minor = dev_to_drm_minor(kdev); 424 struct drm_device *dev = minor->dev; 425 struct drm_i915_private *dev_priv = dev->dev_private; 426 u32 val; 427 ssize_t ret; 428 429 ret = kstrtou32(buf, 0, &val); 430 if (ret) 431 return ret; 432 433 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 434 435 mutex_lock(&dev_priv->rps.hw_lock); 436 437 val = intel_freq_opcode(dev_priv, val); 438 439 if (val < dev_priv->rps.min_freq || 440 val > dev_priv->rps.max_freq || 441 val > dev_priv->rps.max_freq_softlimit) { 442 mutex_unlock(&dev_priv->rps.hw_lock); 443 return -EINVAL; 444 } 445 446 dev_priv->rps.min_freq_softlimit = val; 447 448 val = clamp_t(int, dev_priv->rps.cur_freq, 449 dev_priv->rps.min_freq_softlimit, 450 dev_priv->rps.max_freq_softlimit); 451 452 /* We still need *_set_rps to process the new min_delay and 453 * update the interrupt limits and PMINTRMSK even though 454 * frequency request may be unchanged. */ 455 intel_set_rps(dev, val); 456 457 mutex_unlock(&dev_priv->rps.hw_lock); 458 459 return count; 460 461 } 462 463 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); 464 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); 465 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); 466 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); 467 468 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); 469 470 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); 471 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 472 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 473 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 474 475 /* For now we have a static number of RP states */ 476 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 477 { 478 struct drm_minor *minor = dev_to_drm_minor(kdev); 479 struct drm_device *dev = minor->dev; 480 struct drm_i915_private *dev_priv = dev->dev_private; 481 u32 val; 482 483 if (attr == &dev_attr_gt_RP0_freq_mhz) 484 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); 485 else if (attr == &dev_attr_gt_RP1_freq_mhz) 486 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); 487 else if (attr == &dev_attr_gt_RPn_freq_mhz) 488 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq); 489 else 490 BUG(); 491 492 return snprintf(buf, PAGE_SIZE, "%d\n", val); 493 } 494 495 static const struct attribute *gen6_attrs[] = { 496 &dev_attr_gt_act_freq_mhz.attr, 497 &dev_attr_gt_cur_freq_mhz.attr, 498 &dev_attr_gt_max_freq_mhz.attr, 499 &dev_attr_gt_min_freq_mhz.attr, 500 &dev_attr_gt_RP0_freq_mhz.attr, 501 &dev_attr_gt_RP1_freq_mhz.attr, 502 &dev_attr_gt_RPn_freq_mhz.attr, 503 NULL, 504 }; 505 506 static const struct attribute *vlv_attrs[] = { 507 &dev_attr_gt_act_freq_mhz.attr, 508 &dev_attr_gt_cur_freq_mhz.attr, 509 &dev_attr_gt_max_freq_mhz.attr, 510 &dev_attr_gt_min_freq_mhz.attr, 511 &dev_attr_gt_RP0_freq_mhz.attr, 512 &dev_attr_gt_RP1_freq_mhz.attr, 513 &dev_attr_gt_RPn_freq_mhz.attr, 514 &dev_attr_vlv_rpe_freq_mhz.attr, 515 NULL, 516 }; 517 518 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 519 struct bin_attribute *attr, char *buf, 520 loff_t off, size_t count) 521 { 522 523 struct device *kdev = container_of(kobj, struct device, kobj); 524 struct drm_minor *minor = dev_to_drm_minor(kdev); 525 struct drm_device *dev = minor->dev; 526 struct i915_error_state_file_priv error_priv; 527 struct drm_i915_error_state_buf error_str; 528 ssize_t ret_count = 0; 529 int ret; 530 531 memset(&error_priv, 0, sizeof(error_priv)); 532 533 ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off); 534 if (ret) 535 return ret; 536 537 error_priv.dev = dev; 538 i915_error_state_get(dev, &error_priv); 539 540 ret = i915_error_state_to_str(&error_str, &error_priv); 541 if (ret) 542 goto out; 543 544 ret_count = count < error_str.bytes ? count : error_str.bytes; 545 546 memcpy(buf, error_str.buf, ret_count); 547 out: 548 i915_error_state_put(&error_priv); 549 i915_error_state_buf_release(&error_str); 550 551 return ret ?: ret_count; 552 } 553 554 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 555 struct bin_attribute *attr, char *buf, 556 loff_t off, size_t count) 557 { 558 struct device *kdev = container_of(kobj, struct device, kobj); 559 struct drm_minor *minor = dev_to_drm_minor(kdev); 560 struct drm_device *dev = minor->dev; 561 int ret; 562 563 DRM_DEBUG_DRIVER("Resetting error state\n"); 564 565 ret = mutex_lock_interruptible(&dev->struct_mutex); 566 if (ret) 567 return ret; 568 569 i915_destroy_error_state(dev); 570 mutex_unlock(&dev->struct_mutex); 571 572 return count; 573 } 574 575 static struct bin_attribute error_state_attr = { 576 .attr.name = "error", 577 .attr.mode = S_IRUSR | S_IWUSR, 578 .size = 0, 579 .read = error_state_read, 580 .write = error_state_write, 581 }; 582 #endif 583 584 void i915_setup_sysfs(struct drm_device *dev) 585 { 586 #if 0 587 int ret; 588 589 #ifdef CONFIG_PM 590 if (HAS_RC6(dev)) { 591 ret = sysfs_merge_group(&dev->primary->kdev->kobj, 592 &rc6_attr_group); 593 if (ret) 594 DRM_ERROR("RC6 residency sysfs setup failed\n"); 595 } 596 if (HAS_RC6p(dev)) { 597 ret = sysfs_merge_group(&dev->primary->kdev->kobj, 598 &rc6p_attr_group); 599 if (ret) 600 DRM_ERROR("RC6p residency sysfs setup failed\n"); 601 } 602 if (IS_VALLEYVIEW(dev)) { 603 ret = sysfs_merge_group(&dev->primary->kdev->kobj, 604 &media_rc6_attr_group); 605 if (ret) 606 DRM_ERROR("Media RC6 residency sysfs setup failed\n"); 607 } 608 #endif 609 if (HAS_L3_DPF(dev)) { 610 ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs); 611 if (ret) 612 DRM_ERROR("l3 parity sysfs setup failed\n"); 613 614 if (NUM_L3_SLICES(dev) > 1) { 615 ret = device_create_bin_file(dev->primary->kdev, 616 &dpf_attrs_1); 617 if (ret) 618 DRM_ERROR("l3 parity slice 1 setup failed\n"); 619 } 620 } 621 622 ret = 0; 623 if (IS_VALLEYVIEW(dev)) 624 ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs); 625 else if (INTEL_INFO(dev)->gen >= 6) 626 ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs); 627 if (ret) 628 DRM_ERROR("RPS sysfs setup failed\n"); 629 630 ret = sysfs_create_bin_file(&dev->primary->kdev->kobj, 631 &error_state_attr); 632 if (ret) 633 DRM_ERROR("error_state sysfs setup failed\n"); 634 #endif 635 } 636 637 void i915_teardown_sysfs(struct drm_device *dev) 638 { 639 #if 0 640 sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr); 641 if (IS_VALLEYVIEW(dev)) 642 sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs); 643 else 644 sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs); 645 device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1); 646 device_remove_bin_file(dev->primary->kdev, &dpf_attrs); 647 #ifdef CONFIG_PM 648 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group); 649 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6p_attr_group); 650 #endif 651 #endif 652 } 653