1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28 #include <linux/device.h> 29 #include <linux/module.h> 30 #include <linux/stat.h> 31 #include <linux/sysfs.h> 32 #include "intel_drv.h" 33 #include "i915_drv.h" 34 35 #if 0 36 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev) 37 { 38 struct drm_minor *minor = dev_get_drvdata(kdev); 39 return to_i915(minor->dev); 40 } 41 42 #ifdef CONFIG_PM 43 static u32 calc_residency(struct drm_i915_private *dev_priv, 44 i915_reg_t reg) 45 { 46 u64 raw_time; /* 32b value may overflow during fixed point math */ 47 u64 units = 128ULL, div = 100000ULL; 48 u32 ret; 49 50 if (!intel_enable_rc6()) 51 return 0; 52 53 intel_runtime_pm_get(dev_priv); 54 55 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 56 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 57 units = 1; 58 div = dev_priv->czclk_freq; 59 60 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) 61 units <<= 8; 62 } else if (IS_BROXTON(dev_priv)) { 63 units = 1; 64 div = 1200; /* 833.33ns */ 65 } 66 67 raw_time = I915_READ(reg) * units; 68 ret = DIV_ROUND_UP_ULL(raw_time, div); 69 70 intel_runtime_pm_put(dev_priv); 71 return ret; 72 } 73 74 static ssize_t 75 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) 76 { 77 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6()); 78 } 79 80 static ssize_t 81 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 82 { 83 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 84 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); 85 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 86 } 87 88 static ssize_t 89 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) 90 { 91 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 92 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); 93 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); 94 } 95 96 static ssize_t 97 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) 98 { 99 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 100 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); 101 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); 102 } 103 104 static ssize_t 105 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 106 { 107 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 108 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); 109 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 110 } 111 112 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); 113 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); 114 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); 115 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); 116 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); 117 118 static struct attribute *rc6_attrs[] = { 119 &dev_attr_rc6_enable.attr, 120 &dev_attr_rc6_residency_ms.attr, 121 NULL 122 }; 123 124 static struct attribute_group rc6_attr_group = { 125 .name = power_group_name, 126 .attrs = rc6_attrs 127 }; 128 129 static struct attribute *rc6p_attrs[] = { 130 &dev_attr_rc6p_residency_ms.attr, 131 &dev_attr_rc6pp_residency_ms.attr, 132 NULL 133 }; 134 135 static struct attribute_group rc6p_attr_group = { 136 .name = power_group_name, 137 .attrs = rc6p_attrs 138 }; 139 140 static struct attribute *media_rc6_attrs[] = { 141 &dev_attr_media_rc6_residency_ms.attr, 142 NULL 143 }; 144 145 static struct attribute_group media_rc6_attr_group = { 146 .name = power_group_name, 147 .attrs = media_rc6_attrs 148 }; 149 #endif 150 151 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset) 152 { 153 if (!HAS_L3_DPF(dev_priv)) 154 return -EPERM; 155 156 if (offset % 4 != 0) 157 return -EINVAL; 158 159 if (offset >= GEN7_L3LOG_SIZE) 160 return -ENXIO; 161 162 return 0; 163 } 164 165 static ssize_t 166 i915_l3_read(struct file *filp, struct kobject *kobj, 167 struct bin_attribute *attr, char *buf, 168 loff_t offset, size_t count) 169 { 170 struct device *kdev = kobj_to_dev(kobj); 171 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 172 struct drm_device *dev = &dev_priv->drm; 173 int slice = (int)(uintptr_t)attr->private; 174 int ret; 175 176 count = round_down(count, 4); 177 178 ret = l3_access_valid(dev_priv, offset); 179 if (ret) 180 return ret; 181 182 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); 183 184 ret = i915_mutex_lock_interruptible(dev); 185 if (ret) 186 return ret; 187 188 if (dev_priv->l3_parity.remap_info[slice]) 189 memcpy(buf, 190 dev_priv->l3_parity.remap_info[slice] + (offset/4), 191 count); 192 else 193 memset(buf, 0, count); 194 195 mutex_unlock(&dev->struct_mutex); 196 197 return count; 198 } 199 200 static ssize_t 201 i915_l3_write(struct file *filp, struct kobject *kobj, 202 struct bin_attribute *attr, char *buf, 203 loff_t offset, size_t count) 204 { 205 struct device *kdev = kobj_to_dev(kobj); 206 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 207 struct drm_device *dev = &dev_priv->drm; 208 struct i915_gem_context *ctx; 209 u32 *temp = NULL; /* Just here to make handling failures easy */ 210 int slice = (int)(uintptr_t)attr->private; 211 int ret; 212 213 if (!HAS_HW_CONTEXTS(dev_priv)) 214 return -ENXIO; 215 216 ret = l3_access_valid(dev_priv, offset); 217 if (ret) 218 return ret; 219 220 ret = i915_mutex_lock_interruptible(dev); 221 if (ret) 222 return ret; 223 224 if (!dev_priv->l3_parity.remap_info[slice]) { 225 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); 226 if (!temp) { 227 mutex_unlock(&dev->struct_mutex); 228 return -ENOMEM; 229 } 230 } 231 232 /* TODO: Ideally we really want a GPU reset here to make sure errors 233 * aren't propagated. Since I cannot find a stable way to reset the GPU 234 * at this point it is left as a TODO. 235 */ 236 if (temp) 237 dev_priv->l3_parity.remap_info[slice] = temp; 238 239 memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count); 240 241 /* NB: We defer the remapping until we switch to the context */ 242 list_for_each_entry(ctx, &dev_priv->context_list, link) 243 ctx->remap_slice |= (1<<slice); 244 245 mutex_unlock(&dev->struct_mutex); 246 247 return count; 248 } 249 250 static struct bin_attribute dpf_attrs = { 251 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, 252 .size = GEN7_L3LOG_SIZE, 253 .read = i915_l3_read, 254 .write = i915_l3_write, 255 .mmap = NULL, 256 .private = (void *)0 257 }; 258 259 static struct bin_attribute dpf_attrs_1 = { 260 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, 261 .size = GEN7_L3LOG_SIZE, 262 .read = i915_l3_read, 263 .write = i915_l3_write, 264 .mmap = NULL, 265 .private = (void *)1 266 }; 267 268 static ssize_t gt_act_freq_mhz_show(struct device *kdev, 269 struct device_attribute *attr, char *buf) 270 { 271 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 272 int ret; 273 274 intel_runtime_pm_get(dev_priv); 275 276 mutex_lock(&dev_priv->rps.hw_lock); 277 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 278 u32 freq; 279 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 280 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); 281 } else { 282 u32 rpstat = I915_READ(GEN6_RPSTAT1); 283 if (IS_GEN9(dev_priv)) 284 ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 285 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 286 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 287 else 288 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 289 ret = intel_gpu_freq(dev_priv, ret); 290 } 291 mutex_unlock(&dev_priv->rps.hw_lock); 292 293 intel_runtime_pm_put(dev_priv); 294 295 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 296 } 297 298 static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 299 struct device_attribute *attr, char *buf) 300 { 301 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 302 303 return snprintf(buf, PAGE_SIZE, "%d\n", 304 intel_gpu_freq(dev_priv, 305 dev_priv->rps.cur_freq)); 306 } 307 308 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 309 { 310 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 311 312 return snprintf(buf, PAGE_SIZE, "%d\n", 313 intel_gpu_freq(dev_priv, 314 dev_priv->rps.boost_freq)); 315 } 316 317 static ssize_t gt_boost_freq_mhz_store(struct device *kdev, 318 struct device_attribute *attr, 319 const char *buf, size_t count) 320 { 321 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 322 u32 val; 323 ssize_t ret; 324 325 ret = kstrtou32(buf, 0, &val); 326 if (ret) 327 return ret; 328 329 /* Validate against (static) hardware limits */ 330 val = intel_freq_opcode(dev_priv, val); 331 if (val < dev_priv->rps.min_freq || val > dev_priv->rps.max_freq) 332 return -EINVAL; 333 334 mutex_lock(&dev_priv->rps.hw_lock); 335 dev_priv->rps.boost_freq = val; 336 mutex_unlock(&dev_priv->rps.hw_lock); 337 338 return count; 339 } 340 341 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, 342 struct device_attribute *attr, char *buf) 343 { 344 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 345 346 return snprintf(buf, PAGE_SIZE, "%d\n", 347 intel_gpu_freq(dev_priv, 348 dev_priv->rps.efficient_freq)); 349 } 350 351 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 352 { 353 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 354 355 return snprintf(buf, PAGE_SIZE, "%d\n", 356 intel_gpu_freq(dev_priv, 357 dev_priv->rps.max_freq_softlimit)); 358 } 359 360 static ssize_t gt_max_freq_mhz_store(struct device *kdev, 361 struct device_attribute *attr, 362 const char *buf, size_t count) 363 { 364 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 365 u32 val; 366 ssize_t ret; 367 368 ret = kstrtou32(buf, 0, &val); 369 if (ret) 370 return ret; 371 372 intel_runtime_pm_get(dev_priv); 373 374 mutex_lock(&dev_priv->rps.hw_lock); 375 376 val = intel_freq_opcode(dev_priv, val); 377 378 if (val < dev_priv->rps.min_freq || 379 val > dev_priv->rps.max_freq || 380 val < dev_priv->rps.min_freq_softlimit) { 381 mutex_unlock(&dev_priv->rps.hw_lock); 382 intel_runtime_pm_put(dev_priv); 383 return -EINVAL; 384 } 385 386 if (val > dev_priv->rps.rp0_freq) 387 DRM_DEBUG("User requested overclocking to %d\n", 388 intel_gpu_freq(dev_priv, val)); 389 390 dev_priv->rps.max_freq_softlimit = val; 391 392 val = clamp_t(int, dev_priv->rps.cur_freq, 393 dev_priv->rps.min_freq_softlimit, 394 dev_priv->rps.max_freq_softlimit); 395 396 /* We still need *_set_rps to process the new max_delay and 397 * update the interrupt limits and PMINTRMSK even though 398 * frequency request may be unchanged. */ 399 intel_set_rps(dev_priv, val); 400 401 mutex_unlock(&dev_priv->rps.hw_lock); 402 403 intel_runtime_pm_put(dev_priv); 404 405 return count; 406 } 407 408 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 409 { 410 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 411 412 return snprintf(buf, PAGE_SIZE, "%d\n", 413 intel_gpu_freq(dev_priv, 414 dev_priv->rps.min_freq_softlimit)); 415 } 416 417 static ssize_t gt_min_freq_mhz_store(struct device *kdev, 418 struct device_attribute *attr, 419 const char *buf, size_t count) 420 { 421 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 422 u32 val; 423 ssize_t ret; 424 425 ret = kstrtou32(buf, 0, &val); 426 if (ret) 427 return ret; 428 429 intel_runtime_pm_get(dev_priv); 430 431 mutex_lock(&dev_priv->rps.hw_lock); 432 433 val = intel_freq_opcode(dev_priv, val); 434 435 if (val < dev_priv->rps.min_freq || 436 val > dev_priv->rps.max_freq || 437 val > dev_priv->rps.max_freq_softlimit) { 438 mutex_unlock(&dev_priv->rps.hw_lock); 439 intel_runtime_pm_put(dev_priv); 440 return -EINVAL; 441 } 442 443 dev_priv->rps.min_freq_softlimit = val; 444 445 val = clamp_t(int, dev_priv->rps.cur_freq, 446 dev_priv->rps.min_freq_softlimit, 447 dev_priv->rps.max_freq_softlimit); 448 449 /* We still need *_set_rps to process the new min_delay and 450 * update the interrupt limits and PMINTRMSK even though 451 * frequency request may be unchanged. */ 452 intel_set_rps(dev_priv, val); 453 454 mutex_unlock(&dev_priv->rps.hw_lock); 455 456 intel_runtime_pm_put(dev_priv); 457 458 return count; 459 460 } 461 462 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); 463 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); 464 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store); 465 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); 466 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); 467 468 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); 469 470 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); 471 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 472 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 473 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 474 475 /* For now we have a static number of RP states */ 476 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 477 { 478 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 479 u32 val; 480 481 if (attr == &dev_attr_gt_RP0_freq_mhz) 482 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); 483 else if (attr == &dev_attr_gt_RP1_freq_mhz) 484 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); 485 else if (attr == &dev_attr_gt_RPn_freq_mhz) 486 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq); 487 else 488 BUG(); 489 490 return snprintf(buf, PAGE_SIZE, "%d\n", val); 491 } 492 493 static const struct attribute *gen6_attrs[] = { 494 &dev_attr_gt_act_freq_mhz.attr, 495 &dev_attr_gt_cur_freq_mhz.attr, 496 &dev_attr_gt_boost_freq_mhz.attr, 497 &dev_attr_gt_max_freq_mhz.attr, 498 &dev_attr_gt_min_freq_mhz.attr, 499 &dev_attr_gt_RP0_freq_mhz.attr, 500 &dev_attr_gt_RP1_freq_mhz.attr, 501 &dev_attr_gt_RPn_freq_mhz.attr, 502 NULL, 503 }; 504 505 static const struct attribute *vlv_attrs[] = { 506 &dev_attr_gt_act_freq_mhz.attr, 507 &dev_attr_gt_cur_freq_mhz.attr, 508 &dev_attr_gt_boost_freq_mhz.attr, 509 &dev_attr_gt_max_freq_mhz.attr, 510 &dev_attr_gt_min_freq_mhz.attr, 511 &dev_attr_gt_RP0_freq_mhz.attr, 512 &dev_attr_gt_RP1_freq_mhz.attr, 513 &dev_attr_gt_RPn_freq_mhz.attr, 514 &dev_attr_vlv_rpe_freq_mhz.attr, 515 NULL, 516 }; 517 518 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 519 520 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 521 struct bin_attribute *attr, char *buf, 522 loff_t off, size_t count) 523 { 524 525 struct device *kdev = kobj_to_dev(kobj); 526 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 527 struct drm_device *dev = &dev_priv->drm; 528 struct i915_error_state_file_priv error_priv; 529 struct drm_i915_error_state_buf error_str; 530 ssize_t ret_count = 0; 531 int ret; 532 533 memset(&error_priv, 0, sizeof(error_priv)); 534 535 ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off); 536 if (ret) 537 return ret; 538 539 error_priv.dev = dev; 540 i915_error_state_get(dev, &error_priv); 541 542 ret = i915_error_state_to_str(&error_str, &error_priv); 543 if (ret) 544 goto out; 545 546 ret_count = count < error_str.bytes ? count : error_str.bytes; 547 548 memcpy(buf, error_str.buf, ret_count); 549 out: 550 i915_error_state_put(&error_priv); 551 i915_error_state_buf_release(&error_str); 552 553 return ret ?: ret_count; 554 } 555 556 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 557 struct bin_attribute *attr, char *buf, 558 loff_t off, size_t count) 559 { 560 struct device *kdev = kobj_to_dev(kobj); 561 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 562 563 DRM_DEBUG_DRIVER("Resetting error state\n"); 564 i915_destroy_error_state(&dev_priv->drm); 565 566 return count; 567 } 568 569 static struct bin_attribute error_state_attr = { 570 .attr.name = "error", 571 .attr.mode = S_IRUSR | S_IWUSR, 572 .size = 0, 573 .read = error_state_read, 574 .write = error_state_write, 575 }; 576 #endif 577 578 static void i915_setup_error_capture(struct device *kdev) 579 { 580 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 581 DRM_ERROR("error_state sysfs setup failed\n"); 582 } 583 584 static void i915_teardown_error_capture(struct device *kdev) 585 { 586 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 587 } 588 #else 589 static void i915_setup_error_capture(struct device *kdev) {} 590 static void i915_teardown_error_capture(struct device *kdev) {} 591 #endif 592 593 void i915_setup_sysfs(struct drm_i915_private *dev_priv) 594 { 595 struct device *kdev = dev_priv->drm.primary->kdev; 596 #if 0 597 int ret; 598 599 #ifdef CONFIG_PM 600 if (HAS_RC6(dev_priv)) { 601 ret = sysfs_merge_group(&kdev->kobj, 602 &rc6_attr_group); 603 if (ret) 604 DRM_ERROR("RC6 residency sysfs setup failed\n"); 605 } 606 if (HAS_RC6p(dev_priv)) { 607 ret = sysfs_merge_group(&kdev->kobj, 608 &rc6p_attr_group); 609 if (ret) 610 DRM_ERROR("RC6p residency sysfs setup failed\n"); 611 } 612 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 613 ret = sysfs_merge_group(&kdev->kobj, 614 &media_rc6_attr_group); 615 if (ret) 616 DRM_ERROR("Media RC6 residency sysfs setup failed\n"); 617 } 618 #endif 619 if (HAS_L3_DPF(dev_priv)) { 620 ret = device_create_bin_file(kdev, &dpf_attrs); 621 if (ret) 622 DRM_ERROR("l3 parity sysfs setup failed\n"); 623 624 if (NUM_L3_SLICES(dev_priv) > 1) { 625 ret = device_create_bin_file(kdev, 626 &dpf_attrs_1); 627 if (ret) 628 DRM_ERROR("l3 parity slice 1 setup failed\n"); 629 } 630 } 631 632 ret = 0; 633 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 634 ret = sysfs_create_files(&kdev->kobj, vlv_attrs); 635 else if (INTEL_GEN(dev_priv) >= 6) 636 ret = sysfs_create_files(&kdev->kobj, gen6_attrs); 637 if (ret) 638 DRM_ERROR("RPS sysfs setup failed\n"); 639 640 #endif 641 i915_setup_error_capture(kdev); 642 } 643 644 void i915_teardown_sysfs(struct drm_i915_private *dev_priv) 645 { 646 struct device *kdev = dev_priv->drm.primary->kdev; 647 648 i915_teardown_error_capture(kdev); 649 650 #if 0 651 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 652 sysfs_remove_files(&kdev->kobj, vlv_attrs); 653 else 654 sysfs_remove_files(&kdev->kobj, gen6_attrs); 655 device_remove_bin_file(kdev, &dpf_attrs_1); 656 device_remove_bin_file(kdev, &dpf_attrs); 657 #ifdef CONFIG_PM 658 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group); 659 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group); 660 #endif 661 #endif 662 } 663