1 /* 2 * Copyright © 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: atomic modeset support 26 * 27 * The functions here implement the state management and hardware programming 28 * dispatch required by the atomic modeset infrastructure. 29 * See intel_atomic_plane.c for the plane-specific atomic functionality. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_plane_helper.h> 36 #include "intel_drv.h" 37 38 /** 39 * intel_connector_atomic_get_property - fetch connector property value 40 * @connector: connector to fetch property for 41 * @state: state containing the property value 42 * @property: property to look up 43 * @val: pointer to write property value into 44 * 45 * The DRM core does not store shadow copies of properties for 46 * atomic-capable drivers. This entrypoint is used to fetch 47 * the current value of a driver-specific connector property. 48 */ 49 int 50 intel_connector_atomic_get_property(struct drm_connector *connector, 51 const struct drm_connector_state *state, 52 struct drm_property *property, 53 uint64_t *val) 54 { 55 int i; 56 57 /* 58 * TODO: We only have atomic modeset for planes at the moment, so the 59 * crtc/connector code isn't quite ready yet. Until it's ready, 60 * continue to look up all property values in the DRM's shadow copy 61 * in obj->properties->values[]. 62 * 63 * When the crtc/connector state work matures, this function should 64 * be updated to read the values out of the state structure instead. 65 */ 66 for (i = 0; i < connector->base.properties->count; i++) { 67 if (connector->base.properties->properties[i] == property) { 68 *val = connector->base.properties->values[i]; 69 return 0; 70 } 71 } 72 73 return -EINVAL; 74 } 75 76 /* 77 * intel_crtc_duplicate_state - duplicate crtc state 78 * @crtc: drm crtc 79 * 80 * Allocates and returns a copy of the crtc state (both common and 81 * Intel-specific) for the specified crtc. 82 * 83 * Returns: The newly allocated crtc state, or NULL on failure. 84 */ 85 struct drm_crtc_state * 86 intel_crtc_duplicate_state(struct drm_crtc *crtc) 87 { 88 struct intel_crtc_state *crtc_state; 89 90 crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL); 91 if (!crtc_state) 92 return NULL; 93 94 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base); 95 96 crtc_state->update_pipe = false; 97 crtc_state->disable_lp_wm = false; 98 crtc_state->disable_cxsr = false; 99 crtc_state->update_wm_pre = false; 100 crtc_state->update_wm_post = false; 101 crtc_state->fb_changed = false; 102 crtc_state->fifo_changed = false; 103 crtc_state->wm.need_postvbl_update = false; 104 crtc_state->fb_bits = 0; 105 106 return &crtc_state->base; 107 } 108 109 /** 110 * intel_crtc_destroy_state - destroy crtc state 111 * @crtc: drm crtc 112 * 113 * Destroys the crtc state (both common and Intel-specific) for the 114 * specified crtc. 115 */ 116 void 117 intel_crtc_destroy_state(struct drm_crtc *crtc, 118 struct drm_crtc_state *state) 119 { 120 drm_atomic_helper_crtc_destroy_state(crtc, state); 121 } 122 123 /** 124 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests 125 * @dev_priv: i915 device 126 * @crtc: intel crtc 127 * @crtc_state: incoming crtc_state to validate and setup scalers 128 * 129 * This function sets up scalers based on staged scaling requests for 130 * a @crtc and its planes. It is called from crtc level check path. If request 131 * is a supportable request, it attaches scalers to requested planes and crtc. 132 * 133 * This function takes into account the current scaler(s) in use by any planes 134 * not being part of this atomic state 135 * 136 * Returns: 137 * 0 - scalers were setup succesfully 138 * error code - otherwise 139 */ 140 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 141 struct intel_crtc *intel_crtc, 142 struct intel_crtc_state *crtc_state) 143 { 144 struct drm_plane *plane = NULL; 145 struct intel_plane *intel_plane; 146 struct intel_plane_state *plane_state = NULL; 147 struct intel_crtc_scaler_state *scaler_state = 148 &crtc_state->scaler_state; 149 struct drm_atomic_state *drm_state = crtc_state->base.state; 150 int num_scalers_need; 151 int i, j; 152 153 num_scalers_need = hweight32(scaler_state->scaler_users); 154 155 /* 156 * High level flow: 157 * - staged scaler requests are already in scaler_state->scaler_users 158 * - check whether staged scaling requests can be supported 159 * - add planes using scalers that aren't in current transaction 160 * - assign scalers to requested users 161 * - as part of plane commit, scalers will be committed 162 * (i.e., either attached or detached) to respective planes in hw 163 * - as part of crtc_commit, scaler will be either attached or detached 164 * to crtc in hw 165 */ 166 167 /* fail if required scalers > available scalers */ 168 if (num_scalers_need > intel_crtc->num_scalers){ 169 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n", 170 num_scalers_need, intel_crtc->num_scalers); 171 return -EINVAL; 172 } 173 174 /* walkthrough scaler_users bits and start assigning scalers */ 175 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { 176 int *scaler_id; 177 const char *name; 178 int idx; 179 180 /* skip if scaler not required */ 181 if (!(scaler_state->scaler_users & (1 << i))) 182 continue; 183 184 if (i == SKL_CRTC_INDEX) { 185 name = "CRTC"; 186 idx = intel_crtc->base.base.id; 187 188 /* panel fitter case: assign as a crtc scaler */ 189 scaler_id = &scaler_state->scaler_id; 190 } else { 191 name = "PLANE"; 192 193 /* plane scaler case: assign as a plane scaler */ 194 /* find the plane that set the bit as scaler_user */ 195 plane = drm_state->planes[i].ptr; 196 197 /* 198 * to enable/disable hq mode, add planes that are using scaler 199 * into this transaction 200 */ 201 if (!plane) { 202 struct drm_plane_state *state; 203 plane = drm_plane_from_index(&dev_priv->drm, i); 204 state = drm_atomic_get_plane_state(drm_state, plane); 205 if (IS_ERR(state)) { 206 DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n", 207 plane->base.id); 208 return PTR_ERR(state); 209 } 210 211 /* 212 * the plane is added after plane checks are run, 213 * but since this plane is unchanged just do the 214 * minimum required validation. 215 */ 216 crtc_state->base.planes_changed = true; 217 } 218 219 intel_plane = to_intel_plane(plane); 220 idx = plane->base.id; 221 222 /* plane on different crtc cannot be a scaler user of this crtc */ 223 if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) { 224 continue; 225 } 226 227 plane_state = intel_atomic_get_existing_plane_state(drm_state, 228 intel_plane); 229 scaler_id = &plane_state->scaler_id; 230 } 231 232 if (*scaler_id < 0) { 233 /* find a free scaler */ 234 for (j = 0; j < intel_crtc->num_scalers; j++) { 235 if (!scaler_state->scalers[j].in_use) { 236 scaler_state->scalers[j].in_use = 1; 237 *scaler_id = j; 238 DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n", 239 intel_crtc->pipe, *scaler_id, name, idx); 240 break; 241 } 242 } 243 } 244 245 if (WARN_ON(*scaler_id < 0)) { 246 DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name, idx); 247 continue; 248 } 249 250 /* set scaler mode */ 251 if (IS_GEMINILAKE(dev_priv)) { 252 scaler_state->scalers[*scaler_id].mode = 0; 253 } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { 254 /* 255 * when only 1 scaler is in use on either pipe A or B, 256 * scaler 0 operates in high quality (HQ) mode. 257 * In this case use scaler 0 to take advantage of HQ mode 258 */ 259 *scaler_id = 0; 260 scaler_state->scalers[0].in_use = 1; 261 scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ; 262 scaler_state->scalers[1].in_use = 0; 263 } else { 264 scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN; 265 } 266 } 267 268 return 0; 269 } 270 271 struct drm_atomic_state * 272 intel_atomic_state_alloc(struct drm_device *dev) 273 { 274 struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 275 276 if (!state || drm_atomic_state_init(dev, &state->base) < 0) { 277 kfree(state); 278 return NULL; 279 } 280 281 return &state->base; 282 } 283 284 void intel_atomic_state_clear(struct drm_atomic_state *s) 285 { 286 struct intel_atomic_state *state = to_intel_atomic_state(s); 287 drm_atomic_state_default_clear(&state->base); 288 state->dpll_set = state->modeset = false; 289 } 290