1 /* 2 * Copyright © 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: atomic modeset support 26 * 27 * The functions here implement the state management and hardware programming 28 * dispatch required by the atomic modeset infrastructure. 29 * See intel_atomic_plane.c for the plane-specific atomic functionality. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic.h> 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_plane_helper.h> 36 #include "intel_drv.h" 37 38 /** 39 * intel_connector_atomic_get_property - fetch connector property value 40 * @connector: connector to fetch property for 41 * @state: state containing the property value 42 * @property: property to look up 43 * @val: pointer to write property value into 44 * 45 * The DRM core does not store shadow copies of properties for 46 * atomic-capable drivers. This entrypoint is used to fetch 47 * the current value of a driver-specific connector property. 48 */ 49 int 50 intel_connector_atomic_get_property(struct drm_connector *connector, 51 const struct drm_connector_state *state, 52 struct drm_property *property, 53 uint64_t *val) 54 { 55 int i; 56 57 /* 58 * TODO: We only have atomic modeset for planes at the moment, so the 59 * crtc/connector code isn't quite ready yet. Until it's ready, 60 * continue to look up all property values in the DRM's shadow copy 61 * in obj->properties->values[]. 62 * 63 * When the crtc/connector state work matures, this function should 64 * be updated to read the values out of the state structure instead. 65 */ 66 for (i = 0; i < connector->base.properties->count; i++) { 67 if (connector->base.properties->properties[i] == property) { 68 *val = connector->base.properties->values[i]; 69 return 0; 70 } 71 } 72 73 return -EINVAL; 74 } 75 76 /* 77 * intel_crtc_duplicate_state - duplicate crtc state 78 * @crtc: drm crtc 79 * 80 * Allocates and returns a copy of the crtc state (both common and 81 * Intel-specific) for the specified crtc. 82 * 83 * Returns: The newly allocated crtc state, or NULL on failure. 84 */ 85 struct drm_crtc_state * 86 intel_crtc_duplicate_state(struct drm_crtc *crtc) 87 { 88 struct intel_crtc_state *crtc_state; 89 90 crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL); 91 if (!crtc_state) 92 return NULL; 93 94 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base); 95 96 crtc_state->update_pipe = false; 97 crtc_state->disable_lp_wm = false; 98 crtc_state->disable_cxsr = false; 99 crtc_state->update_wm_pre = false; 100 crtc_state->update_wm_post = false; 101 crtc_state->fb_changed = false; 102 crtc_state->wm.need_postvbl_update = false; 103 crtc_state->fb_bits = 0; 104 105 return &crtc_state->base; 106 } 107 108 /** 109 * intel_crtc_destroy_state - destroy crtc state 110 * @crtc: drm crtc 111 * 112 * Destroys the crtc state (both common and Intel-specific) for the 113 * specified crtc. 114 */ 115 void 116 intel_crtc_destroy_state(struct drm_crtc *crtc, 117 struct drm_crtc_state *state) 118 { 119 drm_atomic_helper_crtc_destroy_state(crtc, state); 120 } 121 122 /** 123 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests 124 * @dev: DRM device 125 * @crtc: intel crtc 126 * @crtc_state: incoming crtc_state to validate and setup scalers 127 * 128 * This function sets up scalers based on staged scaling requests for 129 * a @crtc and its planes. It is called from crtc level check path. If request 130 * is a supportable request, it attaches scalers to requested planes and crtc. 131 * 132 * This function takes into account the current scaler(s) in use by any planes 133 * not being part of this atomic state 134 * 135 * Returns: 136 * 0 - scalers were setup succesfully 137 * error code - otherwise 138 */ 139 int intel_atomic_setup_scalers(struct drm_device *dev, 140 struct intel_crtc *intel_crtc, 141 struct intel_crtc_state *crtc_state) 142 { 143 struct drm_plane *plane = NULL; 144 struct intel_plane *intel_plane; 145 struct intel_plane_state *plane_state = NULL; 146 struct intel_crtc_scaler_state *scaler_state = 147 &crtc_state->scaler_state; 148 struct drm_atomic_state *drm_state = crtc_state->base.state; 149 int num_scalers_need; 150 int i, j; 151 152 num_scalers_need = hweight32(scaler_state->scaler_users); 153 154 /* 155 * High level flow: 156 * - staged scaler requests are already in scaler_state->scaler_users 157 * - check whether staged scaling requests can be supported 158 * - add planes using scalers that aren't in current transaction 159 * - assign scalers to requested users 160 * - as part of plane commit, scalers will be committed 161 * (i.e., either attached or detached) to respective planes in hw 162 * - as part of crtc_commit, scaler will be either attached or detached 163 * to crtc in hw 164 */ 165 166 /* fail if required scalers > available scalers */ 167 if (num_scalers_need > intel_crtc->num_scalers){ 168 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n", 169 num_scalers_need, intel_crtc->num_scalers); 170 return -EINVAL; 171 } 172 173 /* walkthrough scaler_users bits and start assigning scalers */ 174 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { 175 int *scaler_id; 176 const char *name; 177 int idx; 178 179 /* skip if scaler not required */ 180 if (!(scaler_state->scaler_users & (1 << i))) 181 continue; 182 183 if (i == SKL_CRTC_INDEX) { 184 name = "CRTC"; 185 idx = intel_crtc->base.base.id; 186 187 /* panel fitter case: assign as a crtc scaler */ 188 scaler_id = &scaler_state->scaler_id; 189 } else { 190 name = "PLANE"; 191 192 /* plane scaler case: assign as a plane scaler */ 193 /* find the plane that set the bit as scaler_user */ 194 plane = drm_state->planes[i].ptr; 195 196 /* 197 * to enable/disable hq mode, add planes that are using scaler 198 * into this transaction 199 */ 200 if (!plane) { 201 struct drm_plane_state *state; 202 plane = drm_plane_from_index(dev, i); 203 state = drm_atomic_get_plane_state(drm_state, plane); 204 if (IS_ERR(state)) { 205 DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n", 206 plane->base.id); 207 return PTR_ERR(state); 208 } 209 210 /* 211 * the plane is added after plane checks are run, 212 * but since this plane is unchanged just do the 213 * minimum required validation. 214 */ 215 crtc_state->base.planes_changed = true; 216 } 217 218 intel_plane = to_intel_plane(plane); 219 idx = plane->base.id; 220 221 /* plane on different crtc cannot be a scaler user of this crtc */ 222 if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) { 223 continue; 224 } 225 226 plane_state = intel_atomic_get_existing_plane_state(drm_state, 227 intel_plane); 228 scaler_id = &plane_state->scaler_id; 229 } 230 231 if (*scaler_id < 0) { 232 /* find a free scaler */ 233 for (j = 0; j < intel_crtc->num_scalers; j++) { 234 if (!scaler_state->scalers[j].in_use) { 235 scaler_state->scalers[j].in_use = 1; 236 *scaler_id = j; 237 DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n", 238 intel_crtc->pipe, *scaler_id, name, idx); 239 break; 240 } 241 } 242 } 243 244 if (WARN_ON(*scaler_id < 0)) { 245 DRM_DEBUG_KMS("Cannot find scaler for %s:%d\n", name, idx); 246 continue; 247 } 248 249 /* set scaler mode */ 250 if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { 251 /* 252 * when only 1 scaler is in use on either pipe A or B, 253 * scaler 0 operates in high quality (HQ) mode. 254 * In this case use scaler 0 to take advantage of HQ mode 255 */ 256 *scaler_id = 0; 257 scaler_state->scalers[0].in_use = 1; 258 scaler_state->scalers[0].mode = PS_SCALER_MODE_HQ; 259 scaler_state->scalers[1].in_use = 0; 260 } else { 261 scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_DYN; 262 } 263 } 264 265 return 0; 266 } 267 268 static void 269 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, 270 struct intel_shared_dpll_config *shared_dpll) 271 { 272 enum intel_dpll_id i; 273 274 /* Copy shared dpll state */ 275 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 276 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 277 278 shared_dpll[i] = pll->config; 279 } 280 } 281 282 struct intel_shared_dpll_config * 283 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) 284 { 285 struct intel_atomic_state *state = to_intel_atomic_state(s); 286 287 WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); 288 289 if (!state->dpll_set) { 290 state->dpll_set = true; 291 292 intel_atomic_duplicate_dpll_state(to_i915(s->dev), 293 state->shared_dpll); 294 } 295 296 return state->shared_dpll; 297 } 298 299 struct drm_atomic_state * 300 intel_atomic_state_alloc(struct drm_device *dev) 301 { 302 struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 303 304 if (!state || drm_atomic_state_init(dev, &state->base) < 0) { 305 kfree(state); 306 return NULL; 307 } 308 309 return &state->base; 310 } 311 312 void intel_atomic_state_clear(struct drm_atomic_state *s) 313 { 314 struct intel_atomic_state *state = to_intel_atomic_state(s); 315 drm_atomic_state_default_clear(&state->base); 316 state->dpll_set = state->modeset = false; 317 } 318