1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/kernel.h> 25 #include <drm/i915_component.h> 26 #include "intel_drv.h" 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include "i915_drv.h" 31 32 /** 33 * DOC: High Definition Audio over HDMI and Display Port 34 * 35 * The graphics and audio drivers together support High Definition Audio over 36 * HDMI and Display Port. The audio programming sequences are divided into audio 37 * codec and controller enable and disable sequences. The graphics driver 38 * handles the audio codec sequences, while the audio driver handles the audio 39 * controller sequences. 40 * 41 * The disable sequences must be performed before disabling the transcoder or 42 * port. The enable sequences may only be performed after enabling the 43 * transcoder and port, and after completed link training. Therefore the audio 44 * enable/disable sequences are part of the modeset sequence. 45 * 46 * The codec and controller sequences could be done either parallel or serial, 47 * but generally the ELDV/PD change in the codec sequence indicates to the audio 48 * driver that the controller sequence should start. Indeed, most of the 49 * co-operation between the graphics and audio drivers is handled via audio 50 * related registers. (The notable exception is the power management, not 51 * covered here.) 52 * 53 * The struct i915_audio_component is used to interact between the graphics 54 * and audio drivers. The struct i915_audio_component_ops *ops in it is 55 * defined in graphics driver and called in audio driver. The 56 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver. 57 */ 58 59 static const struct { 60 int clock; 61 u32 config; 62 } hdmi_audio_clock[] = { 63 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 64 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 65 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 66 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 67 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 68 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 69 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 70 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 71 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 72 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 73 }; 74 75 /* HDMI N/CTS table */ 76 #define TMDS_297M 297000 77 #define TMDS_296M 296703 78 static const struct { 79 int sample_rate; 80 int clock; 81 int n; 82 int cts; 83 } aud_ncts[] = { 84 { 44100, TMDS_296M, 4459, 234375 }, 85 { 44100, TMDS_297M, 4704, 247500 }, 86 { 48000, TMDS_296M, 5824, 281250 }, 87 { 48000, TMDS_297M, 5120, 247500 }, 88 { 32000, TMDS_296M, 5824, 421875 }, 89 { 32000, TMDS_297M, 3072, 222750 }, 90 { 88200, TMDS_296M, 8918, 234375 }, 91 { 88200, TMDS_297M, 9408, 247500 }, 92 { 96000, TMDS_296M, 11648, 281250 }, 93 { 96000, TMDS_297M, 10240, 247500 }, 94 { 176400, TMDS_296M, 17836, 234375 }, 95 { 176400, TMDS_297M, 18816, 247500 }, 96 { 192000, TMDS_296M, 23296, 281250 }, 97 { 192000, TMDS_297M, 20480, 247500 }, 98 }; 99 100 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 101 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) 102 { 103 int i; 104 105 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 106 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 107 break; 108 } 109 110 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 111 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 112 adjusted_mode->crtc_clock); 113 i = 1; 114 } 115 116 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 117 hdmi_audio_clock[i].clock, 118 hdmi_audio_clock[i].config); 119 120 return hdmi_audio_clock[i].config; 121 } 122 123 static int audio_config_get_n(const struct drm_display_mode *mode, int rate) 124 { 125 int i; 126 127 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) { 128 if ((rate == aud_ncts[i].sample_rate) && 129 (mode->clock == aud_ncts[i].clock)) { 130 return aud_ncts[i].n; 131 } 132 } 133 return 0; 134 } 135 136 static uint32_t audio_config_setup_n_reg(int n, uint32_t val) 137 { 138 int n_low, n_up; 139 uint32_t tmp = val; 140 141 n_low = n & 0xfff; 142 n_up = (n >> 12) & 0xff; 143 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK); 144 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) | 145 (n_low << AUD_CONFIG_LOWER_N_SHIFT) | 146 AUD_CONFIG_N_PROG_ENABLE); 147 return tmp; 148 } 149 150 /* check whether N/CTS/M need be set manually */ 151 static bool audio_rate_need_prog(struct intel_crtc *crtc, 152 const struct drm_display_mode *mode) 153 { 154 if (((mode->clock == TMDS_297M) || 155 (mode->clock == TMDS_296M)) && 156 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 157 return true; 158 else 159 return false; 160 } 161 162 static bool intel_eld_uptodate(struct drm_connector *connector, 163 int reg_eldv, uint32_t bits_eldv, 164 int reg_elda, uint32_t bits_elda, 165 int reg_edid) 166 { 167 struct drm_i915_private *dev_priv = connector->dev->dev_private; 168 uint8_t *eld = connector->eld; 169 uint32_t tmp; 170 int i; 171 172 tmp = I915_READ(reg_eldv); 173 tmp &= bits_eldv; 174 175 if (!tmp) 176 return false; 177 178 tmp = I915_READ(reg_elda); 179 tmp &= ~bits_elda; 180 I915_WRITE(reg_elda, tmp); 181 182 for (i = 0; i < drm_eld_size(eld) / 4; i++) 183 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 184 return false; 185 186 return true; 187 } 188 189 static void g4x_audio_codec_disable(struct intel_encoder *encoder) 190 { 191 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 192 uint32_t eldv, tmp; 193 194 DRM_DEBUG_KMS("Disable audio codec\n"); 195 196 tmp = I915_READ(G4X_AUD_VID_DID); 197 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 198 eldv = G4X_ELDV_DEVCL_DEVBLC; 199 else 200 eldv = G4X_ELDV_DEVCTG; 201 202 /* Invalidate ELD */ 203 tmp = I915_READ(G4X_AUD_CNTL_ST); 204 tmp &= ~eldv; 205 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 206 } 207 208 static void g4x_audio_codec_enable(struct drm_connector *connector, 209 struct intel_encoder *encoder, 210 const struct drm_display_mode *adjusted_mode) 211 { 212 struct drm_i915_private *dev_priv = connector->dev->dev_private; 213 uint8_t *eld = connector->eld; 214 uint32_t eldv; 215 uint32_t tmp; 216 int len, i; 217 218 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); 219 220 tmp = I915_READ(G4X_AUD_VID_DID); 221 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 222 eldv = G4X_ELDV_DEVCL_DEVBLC; 223 else 224 eldv = G4X_ELDV_DEVCTG; 225 226 if (intel_eld_uptodate(connector, 227 G4X_AUD_CNTL_ST, eldv, 228 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 229 G4X_HDMIW_HDMIEDID)) 230 return; 231 232 tmp = I915_READ(G4X_AUD_CNTL_ST); 233 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 234 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 235 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 236 237 len = min(drm_eld_size(eld) / 4, len); 238 DRM_DEBUG_DRIVER("ELD size %d\n", len); 239 for (i = 0; i < len; i++) 240 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 241 242 tmp = I915_READ(G4X_AUD_CNTL_ST); 243 tmp |= eldv; 244 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 245 } 246 247 static void hsw_audio_codec_disable(struct intel_encoder *encoder) 248 { 249 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 250 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 251 enum i915_pipe pipe = intel_crtc->pipe; 252 uint32_t tmp; 253 254 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); 255 256 mutex_lock(&dev_priv->av_mutex); 257 258 /* Disable timestamps */ 259 tmp = I915_READ(HSW_AUD_CFG(pipe)); 260 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 261 tmp |= AUD_CONFIG_N_PROG_ENABLE; 262 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 263 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 264 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 265 tmp |= AUD_CONFIG_N_VALUE_INDEX; 266 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 267 268 /* Invalidate ELD */ 269 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 270 tmp &= ~AUDIO_ELD_VALID(pipe); 271 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); 272 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 273 274 mutex_unlock(&dev_priv->av_mutex); 275 } 276 277 static void hsw_audio_codec_enable(struct drm_connector *connector, 278 struct intel_encoder *encoder, 279 const struct drm_display_mode *adjusted_mode) 280 { 281 struct drm_i915_private *dev_priv = connector->dev->dev_private; 282 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 283 enum i915_pipe pipe = intel_crtc->pipe; 284 struct i915_audio_component *acomp = dev_priv->audio_component; 285 const uint8_t *eld = connector->eld; 286 struct intel_digital_port *intel_dig_port = 287 enc_to_dig_port(&encoder->base); 288 enum port port = intel_dig_port->port; 289 uint32_t tmp; 290 int len, i; 291 int n, rate; 292 293 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", 294 pipe_name(pipe), drm_eld_size(eld)); 295 296 mutex_lock(&dev_priv->av_mutex); 297 298 /* Enable audio presence detect, invalidate ELD */ 299 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 300 tmp |= AUDIO_OUTPUT_ENABLE(pipe); 301 tmp &= ~AUDIO_ELD_VALID(pipe); 302 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 303 304 /* 305 * FIXME: We're supposed to wait for vblank here, but we have vblanks 306 * disabled during the mode set. The proper fix would be to push the 307 * rest of the setup into a vblank work item, queued here, but the 308 * infrastructure is not there yet. 309 */ 310 311 /* Reset ELD write address */ 312 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); 313 tmp &= ~IBX_ELD_ADDRESS_MASK; 314 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); 315 316 /* Up to 84 bytes of hw ELD buffer */ 317 len = min(drm_eld_size(eld), 84); 318 for (i = 0; i < len / 4; i++) 319 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const uint32_t *)eld + i)); 320 321 /* ELD valid */ 322 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 323 tmp |= AUDIO_ELD_VALID(pipe); 324 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 325 326 /* Enable timestamps */ 327 tmp = I915_READ(HSW_AUD_CFG(pipe)); 328 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 329 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 330 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 331 tmp |= AUD_CONFIG_N_VALUE_INDEX; 332 else 333 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); 334 335 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 336 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) { 337 if (!acomp) 338 rate = 0; 339 else if (port >= PORT_A && port <= PORT_E) 340 rate = acomp->aud_sample_rate[port]; 341 else { 342 DRM_ERROR("invalid port: %d\n", port); 343 rate = 0; 344 } 345 n = audio_config_get_n(adjusted_mode, rate); 346 if (n != 0) 347 tmp = audio_config_setup_n_reg(n, tmp); 348 else 349 DRM_DEBUG_KMS("no suitable N value is found\n"); 350 } 351 352 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 353 354 mutex_unlock(&dev_priv->av_mutex); 355 } 356 357 static void ilk_audio_codec_disable(struct intel_encoder *encoder) 358 { 359 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 360 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 361 struct intel_digital_port *intel_dig_port = 362 enc_to_dig_port(&encoder->base); 363 enum port port = intel_dig_port->port; 364 enum i915_pipe pipe = intel_crtc->pipe; 365 uint32_t tmp, eldv; 366 int aud_config; 367 int aud_cntrl_st2; 368 369 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", 370 port_name(port), pipe_name(pipe)); 371 372 if (WARN_ON(port == PORT_A)) 373 return; 374 375 if (HAS_PCH_IBX(dev_priv->dev)) { 376 aud_config = IBX_AUD_CFG(pipe); 377 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 378 } else if (IS_VALLEYVIEW(dev_priv)) { 379 aud_config = VLV_AUD_CFG(pipe); 380 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 381 } else { 382 aud_config = CPT_AUD_CFG(pipe); 383 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 384 } 385 386 /* Disable timestamps */ 387 tmp = I915_READ(aud_config); 388 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 389 tmp |= AUD_CONFIG_N_PROG_ENABLE; 390 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 391 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 392 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 393 tmp |= AUD_CONFIG_N_VALUE_INDEX; 394 I915_WRITE(aud_config, tmp); 395 396 eldv = IBX_ELD_VALID(port); 397 398 /* Invalidate ELD */ 399 tmp = I915_READ(aud_cntrl_st2); 400 tmp &= ~eldv; 401 I915_WRITE(aud_cntrl_st2, tmp); 402 } 403 404 static void ilk_audio_codec_enable(struct drm_connector *connector, 405 struct intel_encoder *encoder, 406 const struct drm_display_mode *adjusted_mode) 407 { 408 struct drm_i915_private *dev_priv = connector->dev->dev_private; 409 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 410 struct intel_digital_port *intel_dig_port = 411 enc_to_dig_port(&encoder->base); 412 enum port port = intel_dig_port->port; 413 enum i915_pipe pipe = intel_crtc->pipe; 414 uint8_t *eld = connector->eld; 415 uint32_t eldv; 416 uint32_t tmp; 417 int len, i; 418 int hdmiw_hdmiedid; 419 int aud_config; 420 int aud_cntl_st; 421 int aud_cntrl_st2; 422 423 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", 424 port_name(port), pipe_name(pipe), drm_eld_size(eld)); 425 426 if (WARN_ON(port == PORT_A)) 427 return; 428 429 /* 430 * FIXME: We're supposed to wait for vblank here, but we have vblanks 431 * disabled during the mode set. The proper fix would be to push the 432 * rest of the setup into a vblank work item, queued here, but the 433 * infrastructure is not there yet. 434 */ 435 436 if (HAS_PCH_IBX(connector->dev)) { 437 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 438 aud_config = IBX_AUD_CFG(pipe); 439 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 440 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 441 } else if (IS_VALLEYVIEW(connector->dev)) { 442 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 443 aud_config = VLV_AUD_CFG(pipe); 444 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 445 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 446 } else { 447 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 448 aud_config = CPT_AUD_CFG(pipe); 449 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 450 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 451 } 452 453 eldv = IBX_ELD_VALID(port); 454 455 /* Invalidate ELD */ 456 tmp = I915_READ(aud_cntrl_st2); 457 tmp &= ~eldv; 458 I915_WRITE(aud_cntrl_st2, tmp); 459 460 /* Reset ELD write address */ 461 tmp = I915_READ(aud_cntl_st); 462 tmp &= ~IBX_ELD_ADDRESS_MASK; 463 I915_WRITE(aud_cntl_st, tmp); 464 465 /* Up to 84 bytes of hw ELD buffer */ 466 len = min(drm_eld_size(eld), 84); 467 for (i = 0; i < len / 4; i++) 468 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 469 470 /* ELD valid */ 471 tmp = I915_READ(aud_cntrl_st2); 472 tmp |= eldv; 473 I915_WRITE(aud_cntrl_st2, tmp); 474 475 /* Enable timestamps */ 476 tmp = I915_READ(aud_config); 477 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 478 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 479 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 480 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 481 tmp |= AUD_CONFIG_N_VALUE_INDEX; 482 else 483 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); 484 I915_WRITE(aud_config, tmp); 485 } 486 487 /** 488 * intel_audio_codec_enable - Enable the audio codec for HD audio 489 * @intel_encoder: encoder on which to enable audio 490 * 491 * The enable sequences may only be performed after enabling the transcoder and 492 * port, and after completed link training. 493 */ 494 void intel_audio_codec_enable(struct intel_encoder *intel_encoder) 495 { 496 struct drm_encoder *encoder = &intel_encoder->base; 497 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 498 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 499 struct drm_connector *connector; 500 struct drm_device *dev = encoder->dev; 501 struct drm_i915_private *dev_priv = dev->dev_private; 502 struct i915_audio_component *acomp = dev_priv->audio_component; 503 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 504 enum port port = intel_dig_port->port; 505 506 connector = drm_select_eld(encoder); 507 if (!connector) 508 return; 509 510 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 511 connector->base.id, 512 connector->name, 513 connector->encoder->base.id, 514 connector->encoder->name); 515 516 /* ELD Conn_Type */ 517 connector->eld[5] &= ~(3 << 2); 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 519 connector->eld[5] |= (1 << 2); 520 521 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 522 523 if (dev_priv->display.audio_codec_enable) 524 dev_priv->display.audio_codec_enable(connector, intel_encoder, 525 adjusted_mode); 526 527 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 528 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); 529 } 530 531 /** 532 * intel_audio_codec_disable - Disable the audio codec for HD audio 533 * @intel_encoder: encoder on which to disable audio 534 * 535 * The disable sequences must be performed before disabling the transcoder or 536 * port. 537 */ 538 void intel_audio_codec_disable(struct intel_encoder *intel_encoder) 539 { 540 struct drm_encoder *encoder = &intel_encoder->base; 541 struct drm_device *dev = encoder->dev; 542 struct drm_i915_private *dev_priv = dev->dev_private; 543 struct i915_audio_component *acomp = dev_priv->audio_component; 544 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 545 enum port port = intel_dig_port->port; 546 547 if (dev_priv->display.audio_codec_disable) 548 dev_priv->display.audio_codec_disable(intel_encoder); 549 550 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 551 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); 552 } 553 554 /** 555 * intel_init_audio - Set up chip specific audio functions 556 * @dev: drm device 557 */ 558 void intel_init_audio(struct drm_device *dev) 559 { 560 struct drm_i915_private *dev_priv = dev->dev_private; 561 562 if (IS_G4X(dev)) { 563 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 564 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 565 } else if (IS_VALLEYVIEW(dev)) { 566 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 567 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 568 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { 569 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 570 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 571 } else if (HAS_PCH_SPLIT(dev)) { 572 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 573 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 574 } 575 } 576 577 static void i915_audio_component_get_power(struct device *dev) 578 { 579 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 580 } 581 582 static void i915_audio_component_put_power(struct device *dev) 583 { 584 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 585 } 586 587 static void i915_audio_component_codec_wake_override(struct device *dev, 588 bool enable) 589 { 590 struct drm_i915_private *dev_priv = dev_to_i915(dev); 591 u32 tmp; 592 593 if (!IS_SKYLAKE(dev_priv)) 594 return; 595 596 /* 597 * Enable/disable generating the codec wake signal, overriding the 598 * internal logic to generate the codec wake to controller. 599 */ 600 tmp = I915_READ(HSW_AUD_CHICKENBIT); 601 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 602 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 603 usleep_range(1000, 1500); 604 605 if (enable) { 606 tmp = I915_READ(HSW_AUD_CHICKENBIT); 607 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 608 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 609 usleep_range(1000, 1500); 610 } 611 } 612 613 /* Get CDCLK in kHz */ 614 static int i915_audio_component_get_cdclk_freq(struct device *dev) 615 { 616 struct drm_i915_private *dev_priv = dev_to_i915(dev); 617 int ret; 618 619 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 620 return -ENODEV; 621 622 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 623 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev); 624 625 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 626 627 return ret; 628 } 629 630 static int i915_audio_component_sync_audio_rate(struct device *dev, 631 int port, int rate) 632 { 633 struct drm_i915_private *dev_priv = dev_to_i915(dev); 634 struct drm_device *drm_dev = dev_priv->dev; 635 struct intel_encoder *intel_encoder; 636 struct intel_digital_port *intel_dig_port; 637 struct intel_crtc *crtc; 638 struct drm_display_mode *mode; 639 struct i915_audio_component *acomp = dev_priv->audio_component; 640 enum i915_pipe pipe = -1; 641 u32 tmp; 642 int n; 643 644 /* HSW, BDW SKL need this fix */ 645 if (!IS_SKYLAKE(dev_priv) && 646 !IS_BROADWELL(dev_priv) && 647 !IS_HASWELL(dev_priv)) 648 return 0; 649 650 mutex_lock(&dev_priv->av_mutex); 651 /* 1. get the pipe */ 652 for_each_intel_encoder(drm_dev, intel_encoder) { 653 if (intel_encoder->type != INTEL_OUTPUT_HDMI) 654 continue; 655 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 656 if (port == intel_dig_port->port) { 657 crtc = to_intel_crtc(intel_encoder->base.crtc); 658 if (!crtc) { 659 DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__); 660 continue; 661 } 662 pipe = crtc->pipe; 663 break; 664 } 665 } 666 667 if (pipe == INVALID_PIPE) { 668 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port)); 669 mutex_unlock(&dev_priv->av_mutex); 670 return -ENODEV; 671 } 672 DRM_DEBUG_KMS("pipe %c connects port %c\n", 673 pipe_name(pipe), port_name(port)); 674 mode = &crtc->config->base.adjusted_mode; 675 676 /* port must be valid now, otherwise the pipe will be invalid */ 677 acomp->aud_sample_rate[port] = rate; 678 679 /* 2. check whether to set the N/CTS/M manually or not */ 680 if (!audio_rate_need_prog(crtc, mode)) { 681 tmp = I915_READ(HSW_AUD_CFG(pipe)); 682 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 683 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 684 mutex_unlock(&dev_priv->av_mutex); 685 return 0; 686 } 687 688 n = audio_config_get_n(mode, rate); 689 if (n == 0) { 690 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n", 691 port_name(port)); 692 tmp = I915_READ(HSW_AUD_CFG(pipe)); 693 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 694 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 695 mutex_unlock(&dev_priv->av_mutex); 696 return 0; 697 } 698 699 /* 3. set the N/CTS/M */ 700 tmp = I915_READ(HSW_AUD_CFG(pipe)); 701 tmp = audio_config_setup_n_reg(n, tmp); 702 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 703 704 mutex_unlock(&dev_priv->av_mutex); 705 return 0; 706 } 707 708 static const struct i915_audio_component_ops i915_audio_component_ops = { 709 .owner = THIS_MODULE, 710 .get_power = i915_audio_component_get_power, 711 .put_power = i915_audio_component_put_power, 712 .codec_wake_override = i915_audio_component_codec_wake_override, 713 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 714 .sync_audio_rate = i915_audio_component_sync_audio_rate, 715 }; 716 717 #if 0 718 static int i915_audio_component_bind(struct device *i915_dev, 719 struct device *hda_dev, void *data) 720 { 721 struct i915_audio_component *acomp = data; 722 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); 723 int i; 724 725 if (WARN_ON(acomp->ops || acomp->dev)) 726 return -EEXIST; 727 728 drm_modeset_lock_all(dev_priv->dev); 729 acomp->ops = &i915_audio_component_ops; 730 acomp->dev = i915_dev; 731 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 732 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 733 acomp->aud_sample_rate[i] = 0; 734 dev_priv->audio_component = acomp; 735 drm_modeset_unlock_all(dev_priv->dev); 736 737 return 0; 738 } 739 740 static void i915_audio_component_unbind(struct device *i915_dev, 741 struct device *hda_dev, void *data) 742 { 743 struct i915_audio_component *acomp = data; 744 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); 745 746 drm_modeset_lock_all(dev_priv->dev); 747 acomp->ops = NULL; 748 acomp->dev = NULL; 749 dev_priv->audio_component = NULL; 750 drm_modeset_unlock_all(dev_priv->dev); 751 } 752 753 static const struct component_ops i915_audio_component_bind_ops = { 754 .bind = i915_audio_component_bind, 755 .unbind = i915_audio_component_unbind, 756 }; 757 #endif 758 759 /** 760 * i915_audio_component_init - initialize and register the audio component 761 * @dev_priv: i915 device instance 762 * 763 * This will register with the component framework a child component which 764 * will bind dynamically to the snd_hda_intel driver's corresponding master 765 * component when the latter is registered. During binding the child 766 * initializes an instance of struct i915_audio_component which it receives 767 * from the master. The master can then start to use the interface defined by 768 * this struct. Each side can break the binding at any point by deregistering 769 * its own component after which each side's component unbind callback is 770 * called. 771 * 772 * We ignore any error during registration and continue with reduced 773 * functionality (i.e. without HDMI audio). 774 */ 775 void i915_audio_component_init(struct drm_i915_private *dev_priv) 776 { 777 #if 0 778 int ret; 779 780 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops); 781 if (ret < 0) { 782 DRM_ERROR("failed to add audio component (%d)\n", ret); 783 /* continue with reduced functionality */ 784 return; 785 } 786 #endif 787 788 dev_priv->audio_component_registered = true; 789 } 790 791 /** 792 * i915_audio_component_cleanup - deregister the audio component 793 * @dev_priv: i915 device instance 794 * 795 * Deregisters the audio component, breaking any existing binding to the 796 * corresponding snd_hda_intel driver's master component. 797 */ 798 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 799 { 800 if (!dev_priv->audio_component_registered) 801 return; 802 803 #if 0 804 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops); 805 #endif 806 dev_priv->audio_component_registered = false; 807 } 808