1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/kernel.h> 25 #include <drm/i915_component.h> 26 #include "intel_drv.h" 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include "intel_drv.h" 31 #include "i915_drv.h" 32 33 /** 34 * DOC: High Definition Audio over HDMI and Display Port 35 * 36 * The graphics and audio drivers together support High Definition Audio over 37 * HDMI and Display Port. The audio programming sequences are divided into audio 38 * codec and controller enable and disable sequences. The graphics driver 39 * handles the audio codec sequences, while the audio driver handles the audio 40 * controller sequences. 41 * 42 * The disable sequences must be performed before disabling the transcoder or 43 * port. The enable sequences may only be performed after enabling the 44 * transcoder and port, and after completed link training. 45 * 46 * The codec and controller sequences could be done either parallel or serial, 47 * but generally the ELDV/PD change in the codec sequence indicates to the audio 48 * driver that the controller sequence should start. Indeed, most of the 49 * co-operation between the graphics and audio drivers is handled via audio 50 * related registers. (The notable exception is the power management, not 51 * covered here.) 52 */ 53 54 static const struct { 55 int clock; 56 u32 config; 57 } hdmi_audio_clock[] = { 58 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 59 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 60 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 61 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 62 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 63 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 64 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 65 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 66 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 67 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 68 }; 69 70 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 71 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) 72 { 73 int i; 74 75 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 76 if (mode->clock == hdmi_audio_clock[i].clock) 77 break; 78 } 79 80 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 81 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); 82 i = 1; 83 } 84 85 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 86 hdmi_audio_clock[i].clock, 87 hdmi_audio_clock[i].config); 88 89 return hdmi_audio_clock[i].config; 90 } 91 92 static bool intel_eld_uptodate(struct drm_connector *connector, 93 int reg_eldv, uint32_t bits_eldv, 94 int reg_elda, uint32_t bits_elda, 95 int reg_edid) 96 { 97 struct drm_i915_private *dev_priv = connector->dev->dev_private; 98 uint8_t *eld = connector->eld; 99 uint32_t tmp; 100 int i; 101 102 tmp = I915_READ(reg_eldv); 103 tmp &= bits_eldv; 104 105 if (!tmp) 106 return false; 107 108 tmp = I915_READ(reg_elda); 109 tmp &= ~bits_elda; 110 I915_WRITE(reg_elda, tmp); 111 112 for (i = 0; i < drm_eld_size(eld) / 4; i++) 113 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 114 return false; 115 116 return true; 117 } 118 119 static void g4x_audio_codec_disable(struct intel_encoder *encoder) 120 { 121 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 122 uint32_t eldv, tmp; 123 124 DRM_DEBUG_KMS("Disable audio codec\n"); 125 126 tmp = I915_READ(G4X_AUD_VID_DID); 127 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 128 eldv = G4X_ELDV_DEVCL_DEVBLC; 129 else 130 eldv = G4X_ELDV_DEVCTG; 131 132 /* Invalidate ELD */ 133 tmp = I915_READ(G4X_AUD_CNTL_ST); 134 tmp &= ~eldv; 135 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 136 } 137 138 static void g4x_audio_codec_enable(struct drm_connector *connector, 139 struct intel_encoder *encoder, 140 struct drm_display_mode *mode) 141 { 142 struct drm_i915_private *dev_priv = connector->dev->dev_private; 143 uint8_t *eld = connector->eld; 144 uint32_t eldv; 145 uint32_t tmp; 146 int len, i; 147 148 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); 149 150 tmp = I915_READ(G4X_AUD_VID_DID); 151 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 152 eldv = G4X_ELDV_DEVCL_DEVBLC; 153 else 154 eldv = G4X_ELDV_DEVCTG; 155 156 if (intel_eld_uptodate(connector, 157 G4X_AUD_CNTL_ST, eldv, 158 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 159 G4X_HDMIW_HDMIEDID)) 160 return; 161 162 tmp = I915_READ(G4X_AUD_CNTL_ST); 163 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 164 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 165 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 166 167 len = min(drm_eld_size(eld) / 4, len); 168 DRM_DEBUG_DRIVER("ELD size %d\n", len); 169 for (i = 0; i < len; i++) 170 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 171 172 tmp = I915_READ(G4X_AUD_CNTL_ST); 173 tmp |= eldv; 174 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 175 } 176 177 static void hsw_audio_codec_disable(struct intel_encoder *encoder) 178 { 179 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 180 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 181 enum i915_pipe pipe = intel_crtc->pipe; 182 uint32_t tmp; 183 184 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); 185 186 /* Disable timestamps */ 187 tmp = I915_READ(HSW_AUD_CFG(pipe)); 188 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 189 tmp |= AUD_CONFIG_N_PROG_ENABLE; 190 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 191 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 192 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 193 tmp |= AUD_CONFIG_N_VALUE_INDEX; 194 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 195 196 /* Invalidate ELD */ 197 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 198 tmp &= ~AUDIO_ELD_VALID(pipe); 199 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); 200 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 201 } 202 203 static void hsw_audio_codec_enable(struct drm_connector *connector, 204 struct intel_encoder *encoder, 205 struct drm_display_mode *mode) 206 { 207 struct drm_i915_private *dev_priv = connector->dev->dev_private; 208 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 209 enum i915_pipe pipe = intel_crtc->pipe; 210 const uint8_t *eld = connector->eld; 211 uint32_t tmp; 212 int len, i; 213 214 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", 215 pipe_name(pipe), drm_eld_size(eld)); 216 217 /* Enable audio presence detect, invalidate ELD */ 218 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 219 tmp |= AUDIO_OUTPUT_ENABLE(pipe); 220 tmp &= ~AUDIO_ELD_VALID(pipe); 221 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 222 223 /* 224 * FIXME: We're supposed to wait for vblank here, but we have vblanks 225 * disabled during the mode set. The proper fix would be to push the 226 * rest of the setup into a vblank work item, queued here, but the 227 * infrastructure is not there yet. 228 */ 229 230 /* Reset ELD write address */ 231 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); 232 tmp &= ~IBX_ELD_ADDRESS_MASK; 233 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); 234 235 /* Up to 84 bytes of hw ELD buffer */ 236 len = min(drm_eld_size(eld), 84); 237 for (i = 0; i < len / 4; i++) 238 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const uint32_t *)eld + i)); 239 240 /* ELD valid */ 241 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 242 tmp |= AUDIO_ELD_VALID(pipe); 243 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 244 245 /* Enable timestamps */ 246 tmp = I915_READ(HSW_AUD_CFG(pipe)); 247 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 248 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 249 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 250 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 251 tmp |= AUD_CONFIG_N_VALUE_INDEX; 252 else 253 tmp |= audio_config_hdmi_pixel_clock(mode); 254 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 255 } 256 257 static void ilk_audio_codec_disable(struct intel_encoder *encoder) 258 { 259 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 260 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 261 struct intel_digital_port *intel_dig_port = 262 enc_to_dig_port(&encoder->base); 263 enum port port = intel_dig_port->port; 264 enum i915_pipe pipe = intel_crtc->pipe; 265 uint32_t tmp, eldv; 266 int aud_config; 267 int aud_cntrl_st2; 268 269 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", 270 port_name(port), pipe_name(pipe)); 271 272 if (HAS_PCH_IBX(dev_priv->dev)) { 273 aud_config = IBX_AUD_CFG(pipe); 274 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 275 } else if (IS_VALLEYVIEW(dev_priv)) { 276 aud_config = VLV_AUD_CFG(pipe); 277 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 278 } else { 279 aud_config = CPT_AUD_CFG(pipe); 280 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 281 } 282 283 /* Disable timestamps */ 284 tmp = I915_READ(aud_config); 285 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 286 tmp |= AUD_CONFIG_N_PROG_ENABLE; 287 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 288 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 289 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 290 tmp |= AUD_CONFIG_N_VALUE_INDEX; 291 I915_WRITE(aud_config, tmp); 292 293 if (WARN_ON(!port)) { 294 eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | 295 IBX_ELD_VALID(PORT_D); 296 } else { 297 eldv = IBX_ELD_VALID(port); 298 } 299 300 /* Invalidate ELD */ 301 tmp = I915_READ(aud_cntrl_st2); 302 tmp &= ~eldv; 303 I915_WRITE(aud_cntrl_st2, tmp); 304 } 305 306 static void ilk_audio_codec_enable(struct drm_connector *connector, 307 struct intel_encoder *encoder, 308 struct drm_display_mode *mode) 309 { 310 struct drm_i915_private *dev_priv = connector->dev->dev_private; 311 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 312 struct intel_digital_port *intel_dig_port = 313 enc_to_dig_port(&encoder->base); 314 enum port port = intel_dig_port->port; 315 enum i915_pipe pipe = intel_crtc->pipe; 316 uint8_t *eld = connector->eld; 317 uint32_t eldv; 318 uint32_t tmp; 319 int len, i; 320 int hdmiw_hdmiedid; 321 int aud_config; 322 int aud_cntl_st; 323 int aud_cntrl_st2; 324 325 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", 326 port_name(port), pipe_name(pipe), drm_eld_size(eld)); 327 328 /* 329 * FIXME: We're supposed to wait for vblank here, but we have vblanks 330 * disabled during the mode set. The proper fix would be to push the 331 * rest of the setup into a vblank work item, queued here, but the 332 * infrastructure is not there yet. 333 */ 334 335 if (HAS_PCH_IBX(connector->dev)) { 336 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 337 aud_config = IBX_AUD_CFG(pipe); 338 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 339 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 340 } else if (IS_VALLEYVIEW(connector->dev)) { 341 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 342 aud_config = VLV_AUD_CFG(pipe); 343 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 344 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 345 } else { 346 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 347 aud_config = CPT_AUD_CFG(pipe); 348 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 349 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 350 } 351 352 if (WARN_ON(!port)) { 353 eldv = IBX_ELD_VALID(PORT_B) | IBX_ELD_VALID(PORT_C) | 354 IBX_ELD_VALID(PORT_D); 355 } else { 356 eldv = IBX_ELD_VALID(port); 357 } 358 359 /* Invalidate ELD */ 360 tmp = I915_READ(aud_cntrl_st2); 361 tmp &= ~eldv; 362 I915_WRITE(aud_cntrl_st2, tmp); 363 364 /* Reset ELD write address */ 365 tmp = I915_READ(aud_cntl_st); 366 tmp &= ~IBX_ELD_ADDRESS_MASK; 367 I915_WRITE(aud_cntl_st, tmp); 368 369 /* Up to 84 bytes of hw ELD buffer */ 370 len = min(drm_eld_size(eld), 84); 371 for (i = 0; i < len / 4; i++) 372 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 373 374 /* ELD valid */ 375 tmp = I915_READ(aud_cntrl_st2); 376 tmp |= eldv; 377 I915_WRITE(aud_cntrl_st2, tmp); 378 379 /* Enable timestamps */ 380 tmp = I915_READ(aud_config); 381 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 382 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 383 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 384 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 385 tmp |= AUD_CONFIG_N_VALUE_INDEX; 386 else 387 tmp |= audio_config_hdmi_pixel_clock(mode); 388 I915_WRITE(aud_config, tmp); 389 } 390 391 /** 392 * intel_audio_codec_enable - Enable the audio codec for HD audio 393 * @intel_encoder: encoder on which to enable audio 394 * 395 * The enable sequences may only be performed after enabling the transcoder and 396 * port, and after completed link training. 397 */ 398 void intel_audio_codec_enable(struct intel_encoder *intel_encoder) 399 { 400 struct drm_encoder *encoder = &intel_encoder->base; 401 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 402 struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; 403 struct drm_connector *connector; 404 struct drm_device *dev = encoder->dev; 405 struct drm_i915_private *dev_priv = dev->dev_private; 406 407 connector = drm_select_eld(encoder, mode); 408 if (!connector) 409 return; 410 411 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 412 connector->base.id, 413 connector->name, 414 connector->encoder->base.id, 415 connector->encoder->name); 416 417 /* ELD Conn_Type */ 418 connector->eld[5] &= ~(3 << 2); 419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 420 connector->eld[5] |= (1 << 2); 421 422 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; 423 424 if (dev_priv->display.audio_codec_enable) 425 dev_priv->display.audio_codec_enable(connector, intel_encoder, mode); 426 } 427 428 /** 429 * intel_audio_codec_disable - Disable the audio codec for HD audio 430 * @encoder: encoder on which to disable audio 431 * 432 * The disable sequences must be performed before disabling the transcoder or 433 * port. 434 */ 435 void intel_audio_codec_disable(struct intel_encoder *encoder) 436 { 437 struct drm_device *dev = encoder->base.dev; 438 struct drm_i915_private *dev_priv = dev->dev_private; 439 440 if (dev_priv->display.audio_codec_disable) 441 dev_priv->display.audio_codec_disable(encoder); 442 } 443 444 /** 445 * intel_init_audio - Set up chip specific audio functions 446 * @dev: drm device 447 */ 448 void intel_init_audio(struct drm_device *dev) 449 { 450 struct drm_i915_private *dev_priv = dev->dev_private; 451 452 if (IS_G4X(dev)) { 453 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 454 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 455 } else if (IS_VALLEYVIEW(dev)) { 456 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 457 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 458 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { 459 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 460 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 461 } else if (HAS_PCH_SPLIT(dev)) { 462 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 463 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 464 } 465 } 466 467 static void i915_audio_component_get_power(struct device *dev) 468 { 469 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 470 } 471 472 static void i915_audio_component_put_power(struct device *dev) 473 { 474 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 475 } 476 477 /* Get CDCLK in kHz */ 478 static int i915_audio_component_get_cdclk_freq(struct device *dev) 479 { 480 struct drm_i915_private *dev_priv = dev_to_i915(dev); 481 int ret; 482 483 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 484 return -ENODEV; 485 486 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 487 ret = intel_ddi_get_cdclk_freq(dev_priv); 488 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 489 490 return ret; 491 } 492 493 static const struct i915_audio_component_ops i915_audio_component_ops = { 494 .owner = THIS_MODULE, 495 .get_power = i915_audio_component_get_power, 496 .put_power = i915_audio_component_put_power, 497 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 498 }; 499 500 #if 0 501 static int i915_audio_component_bind(struct device *i915_dev, 502 struct device *hda_dev, void *data) 503 { 504 struct i915_audio_component *acomp = data; 505 506 if (WARN_ON(acomp->ops || acomp->dev)) 507 return -EEXIST; 508 509 acomp->ops = &i915_audio_component_ops; 510 acomp->dev = i915_dev; 511 512 return 0; 513 } 514 515 static void i915_audio_component_unbind(struct device *i915_dev, 516 struct device *hda_dev, void *data) 517 { 518 struct i915_audio_component *acomp = data; 519 520 acomp->ops = NULL; 521 acomp->dev = NULL; 522 } 523 524 static const struct component_ops i915_audio_component_bind_ops = { 525 .bind = i915_audio_component_bind, 526 .unbind = i915_audio_component_unbind, 527 }; 528 #endif 529 530 /** 531 * i915_audio_component_init - initialize and register the audio component 532 * @dev_priv: i915 device instance 533 * 534 * This will register with the component framework a child component which 535 * will bind dynamically to the snd_hda_intel driver's corresponding master 536 * component when the latter is registered. During binding the child 537 * initializes an instance of struct i915_audio_component which it receives 538 * from the master. The master can then start to use the interface defined by 539 * this struct. Each side can break the binding at any point by deregistering 540 * its own component after which each side's component unbind callback is 541 * called. 542 * 543 * We ignore any error during registration and continue with reduced 544 * functionality (i.e. without HDMI audio). 545 */ 546 void i915_audio_component_init(struct drm_i915_private *dev_priv) 547 { 548 #if 0 549 int ret; 550 551 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops); 552 if (ret < 0) { 553 DRM_ERROR("failed to add audio component (%d)\n", ret); 554 /* continue with reduced functionality */ 555 return; 556 } 557 #endif 558 559 dev_priv->audio_component_registered = true; 560 } 561 562 /** 563 * i915_audio_component_cleanup - deregister the audio component 564 * @dev_priv: i915 device instance 565 * 566 * Deregisters the audio component, breaking any existing binding to the 567 * corresponding snd_hda_intel driver's master component. 568 */ 569 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 570 { 571 if (!dev_priv->audio_component_registered) 572 return; 573 574 #if 0 575 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops); 576 #endif 577 dev_priv->audio_component_registered = false; 578 } 579