1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/component.h> 26 #include <drm/i915_component.h> 27 #include "intel_drv.h" 28 29 #include <drm/drmP.h> 30 #include <drm/drm_edid.h> 31 #include "i915_drv.h" 32 33 /** 34 * DOC: High Definition Audio over HDMI and Display Port 35 * 36 * The graphics and audio drivers together support High Definition Audio over 37 * HDMI and Display Port. The audio programming sequences are divided into audio 38 * codec and controller enable and disable sequences. The graphics driver 39 * handles the audio codec sequences, while the audio driver handles the audio 40 * controller sequences. 41 * 42 * The disable sequences must be performed before disabling the transcoder or 43 * port. The enable sequences may only be performed after enabling the 44 * transcoder and port, and after completed link training. Therefore the audio 45 * enable/disable sequences are part of the modeset sequence. 46 * 47 * The codec and controller sequences could be done either parallel or serial, 48 * but generally the ELDV/PD change in the codec sequence indicates to the audio 49 * driver that the controller sequence should start. Indeed, most of the 50 * co-operation between the graphics and audio drivers is handled via audio 51 * related registers. (The notable exception is the power management, not 52 * covered here.) 53 * 54 * The struct i915_audio_component is used to interact between the graphics 55 * and audio drivers. The struct i915_audio_component_ops *ops in it is 56 * defined in graphics driver and called in audio driver. The 57 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver. 58 */ 59 60 static const struct { 61 int clock; 62 u32 config; 63 } hdmi_audio_clock[] = { 64 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 67 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 69 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 72 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 74 }; 75 76 /* HDMI N/CTS table */ 77 #define TMDS_297M 297000 78 #define TMDS_296M 296703 79 static const struct { 80 int sample_rate; 81 int clock; 82 int n; 83 int cts; 84 } aud_ncts[] = { 85 { 44100, TMDS_296M, 4459, 234375 }, 86 { 44100, TMDS_297M, 4704, 247500 }, 87 { 48000, TMDS_296M, 5824, 281250 }, 88 { 48000, TMDS_297M, 5120, 247500 }, 89 { 32000, TMDS_296M, 5824, 421875 }, 90 { 32000, TMDS_297M, 3072, 222750 }, 91 { 88200, TMDS_296M, 8918, 234375 }, 92 { 88200, TMDS_297M, 9408, 247500 }, 93 { 96000, TMDS_296M, 11648, 281250 }, 94 { 96000, TMDS_297M, 10240, 247500 }, 95 { 176400, TMDS_296M, 17836, 234375 }, 96 { 176400, TMDS_297M, 18816, 247500 }, 97 { 192000, TMDS_296M, 23296, 281250 }, 98 { 192000, TMDS_297M, 20480, 247500 }, 99 }; 100 101 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 102 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) 103 { 104 int i; 105 106 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 107 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 108 break; 109 } 110 111 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 112 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 113 adjusted_mode->crtc_clock); 114 i = 1; 115 } 116 117 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 118 hdmi_audio_clock[i].clock, 119 hdmi_audio_clock[i].config); 120 121 return hdmi_audio_clock[i].config; 122 } 123 124 static int audio_config_get_n(const struct drm_display_mode *mode, int rate) 125 { 126 int i; 127 128 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) { 129 if ((rate == aud_ncts[i].sample_rate) && 130 (mode->clock == aud_ncts[i].clock)) { 131 return aud_ncts[i].n; 132 } 133 } 134 return 0; 135 } 136 137 static uint32_t audio_config_setup_n_reg(int n, uint32_t val) 138 { 139 int n_low, n_up; 140 uint32_t tmp = val; 141 142 n_low = n & 0xfff; 143 n_up = (n >> 12) & 0xff; 144 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK); 145 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) | 146 (n_low << AUD_CONFIG_LOWER_N_SHIFT) | 147 AUD_CONFIG_N_PROG_ENABLE); 148 return tmp; 149 } 150 151 /* check whether N/CTS/M need be set manually */ 152 static bool audio_rate_need_prog(struct intel_crtc *crtc, 153 const struct drm_display_mode *mode) 154 { 155 if (((mode->clock == TMDS_297M) || 156 (mode->clock == TMDS_296M)) && 157 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) 158 return true; 159 else 160 return false; 161 } 162 163 static bool intel_eld_uptodate(struct drm_connector *connector, 164 i915_reg_t reg_eldv, uint32_t bits_eldv, 165 i915_reg_t reg_elda, uint32_t bits_elda, 166 i915_reg_t reg_edid) 167 { 168 struct drm_i915_private *dev_priv = to_i915(connector->dev); 169 uint8_t *eld = connector->eld; 170 uint32_t tmp; 171 int i; 172 173 tmp = I915_READ(reg_eldv); 174 tmp &= bits_eldv; 175 176 if (!tmp) 177 return false; 178 179 tmp = I915_READ(reg_elda); 180 tmp &= ~bits_elda; 181 I915_WRITE(reg_elda, tmp); 182 183 for (i = 0; i < drm_eld_size(eld) / 4; i++) 184 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 185 return false; 186 187 return true; 188 } 189 190 static void g4x_audio_codec_disable(struct intel_encoder *encoder) 191 { 192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 193 uint32_t eldv, tmp; 194 195 DRM_DEBUG_KMS("Disable audio codec\n"); 196 197 tmp = I915_READ(G4X_AUD_VID_DID); 198 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 199 eldv = G4X_ELDV_DEVCL_DEVBLC; 200 else 201 eldv = G4X_ELDV_DEVCTG; 202 203 /* Invalidate ELD */ 204 tmp = I915_READ(G4X_AUD_CNTL_ST); 205 tmp &= ~eldv; 206 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 207 } 208 209 static void g4x_audio_codec_enable(struct drm_connector *connector, 210 struct intel_encoder *encoder, 211 const struct drm_display_mode *adjusted_mode) 212 { 213 struct drm_i915_private *dev_priv = to_i915(connector->dev); 214 uint8_t *eld = connector->eld; 215 uint32_t eldv; 216 uint32_t tmp; 217 int len, i; 218 219 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); 220 221 tmp = I915_READ(G4X_AUD_VID_DID); 222 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 223 eldv = G4X_ELDV_DEVCL_DEVBLC; 224 else 225 eldv = G4X_ELDV_DEVCTG; 226 227 if (intel_eld_uptodate(connector, 228 G4X_AUD_CNTL_ST, eldv, 229 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 230 G4X_HDMIW_HDMIEDID)) 231 return; 232 233 tmp = I915_READ(G4X_AUD_CNTL_ST); 234 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 235 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 236 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 237 238 len = min(drm_eld_size(eld) / 4, len); 239 DRM_DEBUG_DRIVER("ELD size %d\n", len); 240 for (i = 0; i < len; i++) 241 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 242 243 tmp = I915_READ(G4X_AUD_CNTL_ST); 244 tmp |= eldv; 245 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 246 } 247 248 static void hsw_audio_codec_disable(struct intel_encoder *encoder) 249 { 250 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 251 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 252 enum i915_pipe pipe = intel_crtc->pipe; 253 uint32_t tmp; 254 255 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); 256 257 mutex_lock(&dev_priv->av_mutex); 258 259 /* Disable timestamps */ 260 tmp = I915_READ(HSW_AUD_CFG(pipe)); 261 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 262 tmp |= AUD_CONFIG_N_PROG_ENABLE; 263 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 264 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 265 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 266 tmp |= AUD_CONFIG_N_VALUE_INDEX; 267 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 268 269 /* Invalidate ELD */ 270 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 271 tmp &= ~AUDIO_ELD_VALID(pipe); 272 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); 273 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 274 275 mutex_unlock(&dev_priv->av_mutex); 276 } 277 278 static void hsw_audio_codec_enable(struct drm_connector *connector, 279 struct intel_encoder *encoder, 280 const struct drm_display_mode *adjusted_mode) 281 { 282 struct drm_i915_private *dev_priv = to_i915(connector->dev); 283 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 284 enum i915_pipe pipe = intel_crtc->pipe; 285 struct i915_audio_component *acomp = dev_priv->audio_component; 286 const uint8_t *eld = connector->eld; 287 struct intel_digital_port *intel_dig_port = 288 enc_to_dig_port(&encoder->base); 289 enum port port = intel_dig_port->port; 290 uint32_t tmp; 291 int len, i; 292 int n, rate; 293 294 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", 295 pipe_name(pipe), drm_eld_size(eld)); 296 297 mutex_lock(&dev_priv->av_mutex); 298 299 /* Enable audio presence detect, invalidate ELD */ 300 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 301 tmp |= AUDIO_OUTPUT_ENABLE(pipe); 302 tmp &= ~AUDIO_ELD_VALID(pipe); 303 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 304 305 /* 306 * FIXME: We're supposed to wait for vblank here, but we have vblanks 307 * disabled during the mode set. The proper fix would be to push the 308 * rest of the setup into a vblank work item, queued here, but the 309 * infrastructure is not there yet. 310 */ 311 312 /* Reset ELD write address */ 313 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); 314 tmp &= ~IBX_ELD_ADDRESS_MASK; 315 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); 316 317 /* Up to 84 bytes of hw ELD buffer */ 318 len = min(drm_eld_size(eld), 84); 319 for (i = 0; i < len / 4; i++) 320 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); 321 322 /* ELD valid */ 323 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 324 tmp |= AUDIO_ELD_VALID(pipe); 325 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 326 327 /* Enable timestamps */ 328 tmp = I915_READ(HSW_AUD_CFG(pipe)); 329 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 330 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 331 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 332 tmp |= AUD_CONFIG_N_VALUE_INDEX; 333 else 334 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); 335 336 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 337 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) { 338 if (!acomp) 339 rate = 0; 340 else if (port >= PORT_A && port <= PORT_E) 341 rate = acomp->aud_sample_rate[port]; 342 else { 343 DRM_ERROR("invalid port: %d\n", port); 344 rate = 0; 345 } 346 n = audio_config_get_n(adjusted_mode, rate); 347 if (n != 0) 348 tmp = audio_config_setup_n_reg(n, tmp); 349 else 350 DRM_DEBUG_KMS("no suitable N value is found\n"); 351 } 352 353 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 354 355 mutex_unlock(&dev_priv->av_mutex); 356 } 357 358 static void ilk_audio_codec_disable(struct intel_encoder *encoder) 359 { 360 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 361 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 362 struct intel_digital_port *intel_dig_port = 363 enc_to_dig_port(&encoder->base); 364 enum port port = intel_dig_port->port; 365 enum i915_pipe pipe = intel_crtc->pipe; 366 uint32_t tmp, eldv; 367 i915_reg_t aud_config, aud_cntrl_st2; 368 369 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", 370 port_name(port), pipe_name(pipe)); 371 372 if (WARN_ON(port == PORT_A)) 373 return; 374 375 if (HAS_PCH_IBX(dev_priv)) { 376 aud_config = IBX_AUD_CFG(pipe); 377 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 378 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 379 aud_config = VLV_AUD_CFG(pipe); 380 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 381 } else { 382 aud_config = CPT_AUD_CFG(pipe); 383 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 384 } 385 386 /* Disable timestamps */ 387 tmp = I915_READ(aud_config); 388 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 389 tmp |= AUD_CONFIG_N_PROG_ENABLE; 390 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 391 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 392 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 393 tmp |= AUD_CONFIG_N_VALUE_INDEX; 394 I915_WRITE(aud_config, tmp); 395 396 eldv = IBX_ELD_VALID(port); 397 398 /* Invalidate ELD */ 399 tmp = I915_READ(aud_cntrl_st2); 400 tmp &= ~eldv; 401 I915_WRITE(aud_cntrl_st2, tmp); 402 } 403 404 static void ilk_audio_codec_enable(struct drm_connector *connector, 405 struct intel_encoder *encoder, 406 const struct drm_display_mode *adjusted_mode) 407 { 408 struct drm_i915_private *dev_priv = to_i915(connector->dev); 409 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 410 struct intel_digital_port *intel_dig_port = 411 enc_to_dig_port(&encoder->base); 412 enum port port = intel_dig_port->port; 413 enum i915_pipe pipe = intel_crtc->pipe; 414 uint8_t *eld = connector->eld; 415 uint32_t eldv; 416 uint32_t tmp; 417 int len, i; 418 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 419 420 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", 421 port_name(port), pipe_name(pipe), drm_eld_size(eld)); 422 423 if (WARN_ON(port == PORT_A)) 424 return; 425 426 /* 427 * FIXME: We're supposed to wait for vblank here, but we have vblanks 428 * disabled during the mode set. The proper fix would be to push the 429 * rest of the setup into a vblank work item, queued here, but the 430 * infrastructure is not there yet. 431 */ 432 433 if (HAS_PCH_IBX(connector->dev)) { 434 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 435 aud_config = IBX_AUD_CFG(pipe); 436 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 437 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 438 } else if (IS_VALLEYVIEW(connector->dev) || 439 IS_CHERRYVIEW(connector->dev)) { 440 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 441 aud_config = VLV_AUD_CFG(pipe); 442 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 443 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 444 } else { 445 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 446 aud_config = CPT_AUD_CFG(pipe); 447 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 448 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 449 } 450 451 eldv = IBX_ELD_VALID(port); 452 453 /* Invalidate ELD */ 454 tmp = I915_READ(aud_cntrl_st2); 455 tmp &= ~eldv; 456 I915_WRITE(aud_cntrl_st2, tmp); 457 458 /* Reset ELD write address */ 459 tmp = I915_READ(aud_cntl_st); 460 tmp &= ~IBX_ELD_ADDRESS_MASK; 461 I915_WRITE(aud_cntl_st, tmp); 462 463 /* Up to 84 bytes of hw ELD buffer */ 464 len = min(drm_eld_size(eld), 84); 465 for (i = 0; i < len / 4; i++) 466 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 467 468 /* ELD valid */ 469 tmp = I915_READ(aud_cntrl_st2); 470 tmp |= eldv; 471 I915_WRITE(aud_cntrl_st2, tmp); 472 473 /* Enable timestamps */ 474 tmp = I915_READ(aud_config); 475 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 476 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 477 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 478 if (intel_crtc_has_dp_encoder(intel_crtc->config)) 479 tmp |= AUD_CONFIG_N_VALUE_INDEX; 480 else 481 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); 482 I915_WRITE(aud_config, tmp); 483 } 484 485 /** 486 * intel_audio_codec_enable - Enable the audio codec for HD audio 487 * @intel_encoder: encoder on which to enable audio 488 * 489 * The enable sequences may only be performed after enabling the transcoder and 490 * port, and after completed link training. 491 */ 492 void intel_audio_codec_enable(struct intel_encoder *intel_encoder) 493 { 494 struct drm_encoder *encoder = &intel_encoder->base; 495 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 496 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 497 struct drm_connector *connector; 498 struct drm_device *dev = encoder->dev; 499 struct drm_i915_private *dev_priv = to_i915(dev); 500 struct i915_audio_component *acomp = dev_priv->audio_component; 501 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 502 enum port port = intel_dig_port->port; 503 504 connector = drm_select_eld(encoder); 505 if (!connector) 506 return; 507 508 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 509 connector->base.id, 510 connector->name, 511 connector->encoder->base.id, 512 connector->encoder->name); 513 514 /* ELD Conn_Type */ 515 connector->eld[5] &= ~(3 << 2); 516 if (intel_crtc_has_dp_encoder(crtc->config)) 517 connector->eld[5] |= (1 << 2); 518 519 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 520 521 if (dev_priv->display.audio_codec_enable) 522 dev_priv->display.audio_codec_enable(connector, intel_encoder, 523 adjusted_mode); 524 525 mutex_lock(&dev_priv->av_mutex); 526 intel_dig_port->audio_connector = connector; 527 /* referred in audio callbacks */ 528 dev_priv->dig_port_map[port] = intel_encoder; 529 mutex_unlock(&dev_priv->av_mutex); 530 531 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 532 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); 533 } 534 535 /** 536 * intel_audio_codec_disable - Disable the audio codec for HD audio 537 * @intel_encoder: encoder on which to disable audio 538 * 539 * The disable sequences must be performed before disabling the transcoder or 540 * port. 541 */ 542 void intel_audio_codec_disable(struct intel_encoder *intel_encoder) 543 { 544 struct drm_encoder *encoder = &intel_encoder->base; 545 struct drm_device *dev = encoder->dev; 546 struct drm_i915_private *dev_priv = to_i915(dev); 547 struct i915_audio_component *acomp = dev_priv->audio_component; 548 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 549 enum port port = intel_dig_port->port; 550 551 if (dev_priv->display.audio_codec_disable) 552 dev_priv->display.audio_codec_disable(intel_encoder); 553 554 mutex_lock(&dev_priv->av_mutex); 555 intel_dig_port->audio_connector = NULL; 556 dev_priv->dig_port_map[port] = NULL; 557 mutex_unlock(&dev_priv->av_mutex); 558 559 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 560 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); 561 } 562 563 /** 564 * intel_init_audio_hooks - Set up chip specific audio hooks 565 * @dev_priv: device private 566 */ 567 void intel_init_audio_hooks(struct drm_i915_private *dev_priv) 568 { 569 if (IS_G4X(dev_priv)) { 570 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 571 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 572 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 573 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 574 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 575 } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) { 576 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 577 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 578 } else if (HAS_PCH_SPLIT(dev_priv)) { 579 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 580 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 581 } 582 } 583 584 #if 0 /* unused */ 585 static void i915_audio_component_get_power(struct device *dev) 586 { 587 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 588 } 589 590 static void i915_audio_component_put_power(struct device *dev) 591 { 592 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 593 } 594 595 static void i915_audio_component_codec_wake_override(struct device *dev, 596 bool enable) 597 { 598 struct drm_i915_private *dev_priv = dev_to_i915(dev); 599 u32 tmp; 600 601 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) 602 return; 603 604 i915_audio_component_get_power(dev); 605 606 /* 607 * Enable/disable generating the codec wake signal, overriding the 608 * internal logic to generate the codec wake to controller. 609 */ 610 tmp = I915_READ(HSW_AUD_CHICKENBIT); 611 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 612 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 613 usleep_range(1000, 1500); 614 615 if (enable) { 616 tmp = I915_READ(HSW_AUD_CHICKENBIT); 617 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 618 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 619 usleep_range(1000, 1500); 620 } 621 622 i915_audio_component_put_power(dev); 623 } 624 625 /* Get CDCLK in kHz */ 626 static int i915_audio_component_get_cdclk_freq(struct device *dev) 627 { 628 struct drm_i915_private *dev_priv = dev_to_i915(dev); 629 630 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 631 return -ENODEV; 632 633 return dev_priv->cdclk_freq; 634 } 635 636 static int i915_audio_component_sync_audio_rate(struct device *dev, 637 int port, int rate) 638 { 639 struct drm_i915_private *dev_priv = dev_to_i915(dev); 640 struct intel_encoder *intel_encoder; 641 struct intel_crtc *crtc; 642 struct drm_display_mode *mode; 643 struct i915_audio_component *acomp = dev_priv->audio_component; 644 enum i915_pipe pipe = INVALID_PIPE; 645 u32 tmp; 646 int n; 647 int err = 0; 648 649 /* HSW, BDW, SKL, KBL need this fix */ 650 if (!IS_SKYLAKE(dev_priv) && 651 !IS_KABYLAKE(dev_priv) && 652 !IS_BROADWELL(dev_priv) && 653 !IS_HASWELL(dev_priv)) 654 return 0; 655 656 i915_audio_component_get_power(dev); 657 mutex_lock(&dev_priv->av_mutex); 658 /* 1. get the pipe */ 659 intel_encoder = dev_priv->dig_port_map[port]; 660 /* intel_encoder might be NULL for DP MST */ 661 if (!intel_encoder || !intel_encoder->base.crtc || 662 intel_encoder->type != INTEL_OUTPUT_HDMI) { 663 DRM_DEBUG_KMS("no valid port %c\n", port_name(port)); 664 err = -ENODEV; 665 goto unlock; 666 } 667 crtc = to_intel_crtc(intel_encoder->base.crtc); 668 pipe = crtc->pipe; 669 if (pipe == INVALID_PIPE) { 670 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port)); 671 err = -ENODEV; 672 goto unlock; 673 } 674 675 DRM_DEBUG_KMS("pipe %c connects port %c\n", 676 pipe_name(pipe), port_name(port)); 677 mode = &crtc->config->base.adjusted_mode; 678 679 /* port must be valid now, otherwise the pipe will be invalid */ 680 acomp->aud_sample_rate[port] = rate; 681 682 /* 2. check whether to set the N/CTS/M manually or not */ 683 if (!audio_rate_need_prog(crtc, mode)) { 684 tmp = I915_READ(HSW_AUD_CFG(pipe)); 685 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 686 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 687 goto unlock; 688 } 689 690 n = audio_config_get_n(mode, rate); 691 if (n == 0) { 692 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n", 693 port_name(port)); 694 tmp = I915_READ(HSW_AUD_CFG(pipe)); 695 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 696 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 697 goto unlock; 698 } 699 700 /* 3. set the N/CTS/M */ 701 tmp = I915_READ(HSW_AUD_CFG(pipe)); 702 tmp = audio_config_setup_n_reg(n, tmp); 703 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 704 705 unlock: 706 mutex_unlock(&dev_priv->av_mutex); 707 i915_audio_component_put_power(dev); 708 return err; 709 } 710 711 static int i915_audio_component_get_eld(struct device *dev, int port, 712 bool *enabled, 713 unsigned char *buf, int max_bytes) 714 { 715 struct drm_i915_private *dev_priv = dev_to_i915(dev); 716 struct intel_encoder *intel_encoder; 717 struct intel_digital_port *intel_dig_port; 718 const u8 *eld; 719 int ret = -EINVAL; 720 721 mutex_lock(&dev_priv->av_mutex); 722 intel_encoder = dev_priv->dig_port_map[port]; 723 /* intel_encoder might be NULL for DP MST */ 724 if (intel_encoder) { 725 ret = 0; 726 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 727 *enabled = intel_dig_port->audio_connector != NULL; 728 if (*enabled) { 729 eld = intel_dig_port->audio_connector->eld; 730 ret = drm_eld_size(eld); 731 memcpy(buf, eld, min(max_bytes, ret)); 732 } 733 } 734 735 mutex_unlock(&dev_priv->av_mutex); 736 return ret; 737 } 738 739 static const struct i915_audio_component_ops i915_audio_component_ops = { 740 .owner = THIS_MODULE, 741 .get_power = i915_audio_component_get_power, 742 .put_power = i915_audio_component_put_power, 743 .codec_wake_override = i915_audio_component_codec_wake_override, 744 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 745 .sync_audio_rate = i915_audio_component_sync_audio_rate, 746 .get_eld = i915_audio_component_get_eld, 747 }; 748 749 static int i915_audio_component_bind(struct device *i915_dev, 750 struct device *hda_dev, void *data) 751 { 752 struct i915_audio_component *acomp = data; 753 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); 754 int i; 755 756 if (WARN_ON(acomp->ops || acomp->dev)) 757 return -EEXIST; 758 759 drm_modeset_lock_all(&dev_priv->drm); 760 acomp->ops = &i915_audio_component_ops; 761 acomp->dev = i915_dev; 762 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 763 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 764 acomp->aud_sample_rate[i] = 0; 765 dev_priv->audio_component = acomp; 766 drm_modeset_unlock_all(&dev_priv->drm); 767 768 return 0; 769 } 770 771 static void i915_audio_component_unbind(struct device *i915_dev, 772 struct device *hda_dev, void *data) 773 { 774 struct i915_audio_component *acomp = data; 775 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); 776 777 drm_modeset_lock_all(&dev_priv->drm); 778 acomp->ops = NULL; 779 acomp->dev = NULL; 780 dev_priv->audio_component = NULL; 781 drm_modeset_unlock_all(&dev_priv->drm); 782 } 783 784 static const struct component_ops i915_audio_component_bind_ops = { 785 .bind = i915_audio_component_bind, 786 .unbind = i915_audio_component_unbind, 787 }; 788 #endif 789 790 /** 791 * i915_audio_component_init - initialize and register the audio component 792 * @dev_priv: i915 device instance 793 * 794 * This will register with the component framework a child component which 795 * will bind dynamically to the snd_hda_intel driver's corresponding master 796 * component when the latter is registered. During binding the child 797 * initializes an instance of struct i915_audio_component which it receives 798 * from the master. The master can then start to use the interface defined by 799 * this struct. Each side can break the binding at any point by deregistering 800 * its own component after which each side's component unbind callback is 801 * called. 802 * 803 * We ignore any error during registration and continue with reduced 804 * functionality (i.e. without HDMI audio). 805 */ 806 void i915_audio_component_init(struct drm_i915_private *dev_priv) 807 { 808 #if 0 809 int ret; 810 811 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops); 812 if (ret < 0) { 813 DRM_ERROR("failed to add audio component (%d)\n", ret); 814 /* continue with reduced functionality */ 815 return; 816 } 817 #endif 818 819 dev_priv->audio_component_registered = true; 820 } 821 822 /** 823 * i915_audio_component_cleanup - deregister the audio component 824 * @dev_priv: i915 device instance 825 * 826 * Deregisters the audio component, breaking any existing binding to the 827 * corresponding snd_hda_intel driver's master component. 828 */ 829 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 830 { 831 if (!dev_priv->audio_component_registered) 832 return; 833 834 #if 0 835 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops); 836 #endif 837 dev_priv->audio_component_registered = false; 838 } 839