1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 /* 25 * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away 26 * the VBT from the rest of the driver. Add the parsed, clean data to struct 27 * intel_vbt_data within struct drm_i915_private. 28 */ 29 30 #ifndef _INTEL_BIOS_H_ 31 #define _INTEL_BIOS_H_ 32 33 struct edp_power_seq { 34 u16 t1_t3; 35 u16 t8; 36 u16 t9; 37 u16 t10; 38 u16 t11_t12; 39 } __packed; 40 41 /* MIPI Sequence Block definitions */ 42 enum mipi_seq { 43 MIPI_SEQ_END = 0, 44 MIPI_SEQ_ASSERT_RESET, 45 MIPI_SEQ_INIT_OTP, 46 MIPI_SEQ_DISPLAY_ON, 47 MIPI_SEQ_DISPLAY_OFF, 48 MIPI_SEQ_DEASSERT_RESET, 49 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ 50 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ 51 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ 52 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */ 53 MIPI_SEQ_POWER_ON, /* sequence block v3+ */ 54 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */ 55 MIPI_SEQ_MAX 56 }; 57 58 enum mipi_seq_element { 59 MIPI_SEQ_ELEM_END = 0, 60 MIPI_SEQ_ELEM_SEND_PKT, 61 MIPI_SEQ_ELEM_DELAY, 62 MIPI_SEQ_ELEM_GPIO, 63 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */ 64 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */ 65 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */ 66 MIPI_SEQ_ELEM_MAX 67 }; 68 69 #define MIPI_DSI_UNDEFINED_PANEL_ID 0 70 #define MIPI_DSI_GENERIC_PANEL_ID 1 71 72 struct mipi_config { 73 u16 panel_id; 74 75 /* General Params */ 76 u32 enable_dithering:1; 77 u32 rsvd1:1; 78 u32 is_bridge:1; 79 80 u32 panel_arch_type:2; 81 u32 is_cmd_mode:1; 82 83 #define NON_BURST_SYNC_PULSE 0x1 84 #define NON_BURST_SYNC_EVENTS 0x2 85 #define BURST_MODE 0x3 86 u32 video_transfer_mode:2; 87 88 u32 cabc_supported:1; 89 #define PPS_BLC_PMIC 0 90 #define PPS_BLC_SOC 1 91 u32 pwm_blc:1; 92 93 /* Bit 13:10 */ 94 #define PIXEL_FORMAT_RGB565 0x1 95 #define PIXEL_FORMAT_RGB666 0x2 96 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 97 #define PIXEL_FORMAT_RGB888 0x4 98 u32 videomode_color_format:4; 99 100 /* Bit 15:14 */ 101 #define ENABLE_ROTATION_0 0x0 102 #define ENABLE_ROTATION_90 0x1 103 #define ENABLE_ROTATION_180 0x2 104 #define ENABLE_ROTATION_270 0x3 105 u32 rotation:2; 106 u32 bta_enabled:1; 107 u32 rsvd2:15; 108 109 /* 2 byte Port Description */ 110 #define DUAL_LINK_NOT_SUPPORTED 0 111 #define DUAL_LINK_FRONT_BACK 1 112 #define DUAL_LINK_PIXEL_ALT 2 113 u16 dual_link:2; 114 u16 lane_cnt:2; 115 u16 pixel_overlap:3; 116 u16 rsvd3:9; 117 118 u16 rsvd4; 119 120 u8 rsvd5; 121 u32 target_burst_mode_freq; 122 u32 dsi_ddr_clk; 123 u32 bridge_ref_clk; 124 125 #define BYTE_CLK_SEL_20MHZ 0 126 #define BYTE_CLK_SEL_10MHZ 1 127 #define BYTE_CLK_SEL_5MHZ 2 128 u8 byte_clk_sel:2; 129 130 u8 rsvd6:6; 131 132 /* DPHY Flags */ 133 u16 dphy_param_valid:1; 134 u16 eot_pkt_disabled:1; 135 u16 enable_clk_stop:1; 136 u16 rsvd7:13; 137 138 u32 hs_tx_timeout; 139 u32 lp_rx_timeout; 140 u32 turn_around_timeout; 141 u32 device_reset_timer; 142 u32 master_init_timer; 143 u32 dbi_bw_timer; 144 u32 lp_byte_clk_val; 145 146 /* 4 byte Dphy Params */ 147 u32 prepare_cnt:6; 148 u32 rsvd8:2; 149 u32 clk_zero_cnt:8; 150 u32 trail_cnt:5; 151 u32 rsvd9:3; 152 u32 exit_zero_cnt:6; 153 u32 rsvd10:2; 154 155 u32 clk_lane_switch_cnt; 156 u32 hl_switch_cnt; 157 158 u32 rsvd11[6]; 159 160 /* timings based on dphy spec */ 161 u8 tclk_miss; 162 u8 tclk_post; 163 u8 rsvd12; 164 u8 tclk_pre; 165 u8 tclk_prepare; 166 u8 tclk_settle; 167 u8 tclk_term_enable; 168 u8 tclk_trail; 169 u16 tclk_prepare_clkzero; 170 u8 rsvd13; 171 u8 td_term_enable; 172 u8 teot; 173 u8 ths_exit; 174 u8 ths_prepare; 175 u16 ths_prepare_hszero; 176 u8 rsvd14; 177 u8 ths_settle; 178 u8 ths_skip; 179 u8 ths_trail; 180 u8 tinit; 181 u8 tlpx; 182 u8 rsvd15[3]; 183 184 /* GPIOs */ 185 u8 panel_enable; 186 u8 bl_enable; 187 u8 pwm_enable; 188 u8 reset_r_n; 189 u8 pwr_down_r; 190 u8 stdby_r_n; 191 192 } __packed; 193 194 /* all delays have a unit of 100us */ 195 struct mipi_pps_data { 196 u16 panel_on_delay; 197 u16 bl_enable_delay; 198 u16 bl_disable_delay; 199 u16 panel_off_delay; 200 u16 panel_power_cycle_delay; 201 } __packed; 202 203 #endif /* _INTEL_BIOS_H_ */ 204