1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 /* 25 * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away 26 * the VBT from the rest of the driver. Add the parsed, clean data to struct 27 * intel_vbt_data within struct drm_i915_private. 28 */ 29 30 #ifndef _INTEL_BIOS_H_ 31 #define _INTEL_BIOS_H_ 32 33 enum intel_backlight_type { 34 INTEL_BACKLIGHT_PMIC, 35 INTEL_BACKLIGHT_LPSS, 36 INTEL_BACKLIGHT_DISPLAY_DDI, 37 INTEL_BACKLIGHT_DSI_DCS, 38 INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE, 39 }; 40 41 struct edp_power_seq { 42 u16 t1_t3; 43 u16 t8; 44 u16 t9; 45 u16 t10; 46 u16 t11_t12; 47 } __packed; 48 49 /* MIPI Sequence Block definitions */ 50 enum mipi_seq { 51 MIPI_SEQ_END = 0, 52 MIPI_SEQ_ASSERT_RESET, 53 MIPI_SEQ_INIT_OTP, 54 MIPI_SEQ_DISPLAY_ON, 55 MIPI_SEQ_DISPLAY_OFF, 56 MIPI_SEQ_DEASSERT_RESET, 57 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ 58 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ 59 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ 60 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */ 61 MIPI_SEQ_POWER_ON, /* sequence block v3+ */ 62 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */ 63 MIPI_SEQ_MAX 64 }; 65 66 enum mipi_seq_element { 67 MIPI_SEQ_ELEM_END = 0, 68 MIPI_SEQ_ELEM_SEND_PKT, 69 MIPI_SEQ_ELEM_DELAY, 70 MIPI_SEQ_ELEM_GPIO, 71 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */ 72 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */ 73 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */ 74 MIPI_SEQ_ELEM_MAX 75 }; 76 77 #define MIPI_DSI_UNDEFINED_PANEL_ID 0 78 #define MIPI_DSI_GENERIC_PANEL_ID 1 79 80 struct mipi_config { 81 u16 panel_id; 82 83 /* General Params */ 84 u32 enable_dithering:1; 85 u32 rsvd1:1; 86 u32 is_bridge:1; 87 88 u32 panel_arch_type:2; 89 u32 is_cmd_mode:1; 90 91 #define NON_BURST_SYNC_PULSE 0x1 92 #define NON_BURST_SYNC_EVENTS 0x2 93 #define BURST_MODE 0x3 94 u32 video_transfer_mode:2; 95 96 u32 cabc_supported:1; 97 #define PPS_BLC_PMIC 0 98 #define PPS_BLC_SOC 1 99 u32 pwm_blc:1; 100 101 /* Bit 13:10 */ 102 #define PIXEL_FORMAT_RGB565 0x1 103 #define PIXEL_FORMAT_RGB666 0x2 104 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 105 #define PIXEL_FORMAT_RGB888 0x4 106 u32 videomode_color_format:4; 107 108 /* Bit 15:14 */ 109 #define ENABLE_ROTATION_0 0x0 110 #define ENABLE_ROTATION_90 0x1 111 #define ENABLE_ROTATION_180 0x2 112 #define ENABLE_ROTATION_270 0x3 113 u32 rotation:2; 114 u32 bta_enabled:1; 115 u32 rsvd2:15; 116 117 /* 2 byte Port Description */ 118 #define DUAL_LINK_NOT_SUPPORTED 0 119 #define DUAL_LINK_FRONT_BACK 1 120 #define DUAL_LINK_PIXEL_ALT 2 121 u16 dual_link:2; 122 u16 lane_cnt:2; 123 u16 pixel_overlap:3; 124 u16 rgb_flip:1; 125 #define DL_DCS_PORT_A 0x00 126 #define DL_DCS_PORT_C 0x01 127 #define DL_DCS_PORT_A_AND_C 0x02 128 u16 dl_dcs_cabc_ports:2; 129 u16 dl_dcs_backlight_ports:2; 130 u16 rsvd3:4; 131 132 u16 rsvd4; 133 134 u8 rsvd5; 135 u32 target_burst_mode_freq; 136 u32 dsi_ddr_clk; 137 u32 bridge_ref_clk; 138 139 #define BYTE_CLK_SEL_20MHZ 0 140 #define BYTE_CLK_SEL_10MHZ 1 141 #define BYTE_CLK_SEL_5MHZ 2 142 u8 byte_clk_sel:2; 143 144 u8 rsvd6:6; 145 146 /* DPHY Flags */ 147 u16 dphy_param_valid:1; 148 u16 eot_pkt_disabled:1; 149 u16 enable_clk_stop:1; 150 u16 rsvd7:13; 151 152 u32 hs_tx_timeout; 153 u32 lp_rx_timeout; 154 u32 turn_around_timeout; 155 u32 device_reset_timer; 156 u32 master_init_timer; 157 u32 dbi_bw_timer; 158 u32 lp_byte_clk_val; 159 160 /* 4 byte Dphy Params */ 161 u32 prepare_cnt:6; 162 u32 rsvd8:2; 163 u32 clk_zero_cnt:8; 164 u32 trail_cnt:5; 165 u32 rsvd9:3; 166 u32 exit_zero_cnt:6; 167 u32 rsvd10:2; 168 169 u32 clk_lane_switch_cnt; 170 u32 hl_switch_cnt; 171 172 u32 rsvd11[6]; 173 174 /* timings based on dphy spec */ 175 u8 tclk_miss; 176 u8 tclk_post; 177 u8 rsvd12; 178 u8 tclk_pre; 179 u8 tclk_prepare; 180 u8 tclk_settle; 181 u8 tclk_term_enable; 182 u8 tclk_trail; 183 u16 tclk_prepare_clkzero; 184 u8 rsvd13; 185 u8 td_term_enable; 186 u8 teot; 187 u8 ths_exit; 188 u8 ths_prepare; 189 u16 ths_prepare_hszero; 190 u8 rsvd14; 191 u8 ths_settle; 192 u8 ths_skip; 193 u8 ths_trail; 194 u8 tinit; 195 u8 tlpx; 196 u8 rsvd15[3]; 197 198 /* GPIOs */ 199 u8 panel_enable; 200 u8 bl_enable; 201 u8 pwm_enable; 202 u8 reset_r_n; 203 u8 pwr_down_r; 204 u8 stdby_r_n; 205 206 } __packed; 207 208 /* all delays have a unit of 100us */ 209 struct mipi_pps_data { 210 u16 panel_on_delay; 211 u16 bl_enable_delay; 212 u16 bl_disable_delay; 213 u16 panel_off_delay; 214 u16 panel_power_cycle_delay; 215 } __packed; 216 217 #endif /* _INTEL_BIOS_H_ */ 218