1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_drv.h" 25 26 /** 27 * DOC: CDCLK / RAWCLK 28 * 29 * The display engine uses several different clocks to do its work. There 30 * are two main clocks involved that aren't directly related to the actual 31 * pixel clock or any symbol/bit clock of the actual output port. These 32 * are the core display clock (CDCLK) and RAWCLK. 33 * 34 * CDCLK clocks most of the display pipe logic, and thus its frequency 35 * must be high enough to support the rate at which pixels are flowing 36 * through the pipes. Downscaling must also be accounted as that increases 37 * the effective pixel rate. 38 * 39 * On several platforms the CDCLK frequency can be changed dynamically 40 * to minimize power consumption for a given display configuration. 41 * Typically changes to the CDCLK frequency require all the display pipes 42 * to be shut down while the frequency is being changed. 43 * 44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 45 * DMC will not change the active CDCLK frequency however, so that part 46 * will still be performed by the driver directly. 47 * 48 * RAWCLK is a fixed frequency clock, often used by various auxiliary 49 * blocks such as AUX CH or backlight PWM. Hence the only thing we 50 * really need to know about RAWCLK is its frequency so that various 51 * dividers can be programmed correctly. 52 */ 53 54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 55 struct intel_cdclk_state *cdclk_state) 56 { 57 cdclk_state->cdclk = 133333; 58 } 59 60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 61 struct intel_cdclk_state *cdclk_state) 62 { 63 cdclk_state->cdclk = 200000; 64 } 65 66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 67 struct intel_cdclk_state *cdclk_state) 68 { 69 cdclk_state->cdclk = 266667; 70 } 71 72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 73 struct intel_cdclk_state *cdclk_state) 74 { 75 cdclk_state->cdclk = 333333; 76 } 77 78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 79 struct intel_cdclk_state *cdclk_state) 80 { 81 cdclk_state->cdclk = 400000; 82 } 83 84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 85 struct intel_cdclk_state *cdclk_state) 86 { 87 cdclk_state->cdclk = 450000; 88 } 89 90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 91 struct intel_cdclk_state *cdclk_state) 92 { 93 struct pci_dev *pdev = dev_priv->drm.pdev; 94 u16 hpllcc = 0; 95 96 /* 97 * 852GM/852GMV only supports 133 MHz and the HPLLCC 98 * encoding is different :( 99 * FIXME is this the right way to detect 852GM/852GMV? 100 */ 101 if (pdev->revision == 0x1) { 102 cdclk_state->cdclk = 133333; 103 return; 104 } 105 106 pci_bus_read_config_word(pdev->bus, 107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 108 109 /* Assume that the hardware is in the high speed state. This 110 * should be the default. 111 */ 112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 113 case GC_CLOCK_133_200: 114 case GC_CLOCK_133_200_2: 115 case GC_CLOCK_100_200: 116 cdclk_state->cdclk = 200000; 117 break; 118 case GC_CLOCK_166_250: 119 cdclk_state->cdclk = 250000; 120 break; 121 case GC_CLOCK_100_133: 122 cdclk_state->cdclk = 133333; 123 break; 124 case GC_CLOCK_133_266: 125 case GC_CLOCK_133_266_2: 126 case GC_CLOCK_166_266: 127 cdclk_state->cdclk = 266667; 128 break; 129 } 130 } 131 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 133 struct intel_cdclk_state *cdclk_state) 134 { 135 struct pci_dev *pdev = dev_priv->drm.pdev; 136 u16 gcfgc = 0; 137 138 pci_read_config_word(pdev, GCFGC, &gcfgc); 139 140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 141 cdclk_state->cdclk = 133333; 142 return; 143 } 144 145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 146 case GC_DISPLAY_CLOCK_333_320_MHZ: 147 cdclk_state->cdclk = 333333; 148 break; 149 default: 150 case GC_DISPLAY_CLOCK_190_200_MHZ: 151 cdclk_state->cdclk = 190000; 152 break; 153 } 154 } 155 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 157 struct intel_cdclk_state *cdclk_state) 158 { 159 struct pci_dev *pdev = dev_priv->drm.pdev; 160 u16 gcfgc = 0; 161 162 pci_read_config_word(pdev, GCFGC, &gcfgc); 163 164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 165 cdclk_state->cdclk = 133333; 166 return; 167 } 168 169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 170 case GC_DISPLAY_CLOCK_333_320_MHZ: 171 cdclk_state->cdclk = 320000; 172 break; 173 default: 174 case GC_DISPLAY_CLOCK_190_200_MHZ: 175 cdclk_state->cdclk = 200000; 176 break; 177 } 178 } 179 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 181 { 182 static const unsigned int blb_vco[8] = { 183 [0] = 3200000, 184 [1] = 4000000, 185 [2] = 5333333, 186 [3] = 4800000, 187 [4] = 6400000, 188 }; 189 static const unsigned int pnv_vco[8] = { 190 [0] = 3200000, 191 [1] = 4000000, 192 [2] = 5333333, 193 [3] = 4800000, 194 [4] = 2666667, 195 }; 196 static const unsigned int cl_vco[8] = { 197 [0] = 3200000, 198 [1] = 4000000, 199 [2] = 5333333, 200 [3] = 6400000, 201 [4] = 3333333, 202 [5] = 3566667, 203 [6] = 4266667, 204 }; 205 static const unsigned int elk_vco[8] = { 206 [0] = 3200000, 207 [1] = 4000000, 208 [2] = 5333333, 209 [3] = 4800000, 210 }; 211 static const unsigned int ctg_vco[8] = { 212 [0] = 3200000, 213 [1] = 4000000, 214 [2] = 5333333, 215 [3] = 6400000, 216 [4] = 2666667, 217 [5] = 4266667, 218 }; 219 const unsigned int *vco_table; 220 unsigned int vco; 221 uint8_t tmp = 0; 222 223 /* FIXME other chipsets? */ 224 if (IS_GM45(dev_priv)) 225 vco_table = ctg_vco; 226 else if (IS_G45(dev_priv)) 227 vco_table = elk_vco; 228 else if (IS_I965GM(dev_priv)) 229 vco_table = cl_vco; 230 else if (IS_PINEVIEW(dev_priv)) 231 vco_table = pnv_vco; 232 else if (IS_G33(dev_priv)) 233 vco_table = blb_vco; 234 else 235 return 0; 236 237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 238 239 vco = vco_table[tmp & 0x7]; 240 if (vco == 0) 241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); 242 else 243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); 244 245 return vco; 246 } 247 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 249 struct intel_cdclk_state *cdclk_state) 250 { 251 struct pci_dev *pdev = dev_priv->drm.pdev; 252 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; 253 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; 254 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; 255 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; 256 const uint8_t *div_table; 257 unsigned int cdclk_sel; 258 uint16_t tmp = 0; 259 260 cdclk_state->vco = intel_hpll_vco(dev_priv); 261 262 pci_read_config_word(pdev, GCFGC, &tmp); 263 264 cdclk_sel = (tmp >> 4) & 0x7; 265 266 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 267 goto fail; 268 269 switch (cdclk_state->vco) { 270 case 3200000: 271 div_table = div_3200; 272 break; 273 case 4000000: 274 div_table = div_4000; 275 break; 276 case 4800000: 277 div_table = div_4800; 278 break; 279 case 5333333: 280 div_table = div_5333; 281 break; 282 default: 283 goto fail; 284 } 285 286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, 287 div_table[cdclk_sel]); 288 return; 289 290 fail: 291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 292 cdclk_state->vco, tmp); 293 cdclk_state->cdclk = 190476; 294 } 295 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 297 struct intel_cdclk_state *cdclk_state) 298 { 299 struct pci_dev *pdev = dev_priv->drm.pdev; 300 u16 gcfgc = 0; 301 302 pci_read_config_word(pdev, GCFGC, &gcfgc); 303 304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 305 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 306 cdclk_state->cdclk = 266667; 307 break; 308 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 309 cdclk_state->cdclk = 333333; 310 break; 311 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 312 cdclk_state->cdclk = 444444; 313 break; 314 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 315 cdclk_state->cdclk = 200000; 316 break; 317 default: 318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); 319 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 320 cdclk_state->cdclk = 133333; 321 break; 322 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 323 cdclk_state->cdclk = 166667; 324 break; 325 } 326 } 327 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 329 struct intel_cdclk_state *cdclk_state) 330 { 331 struct pci_dev *pdev = dev_priv->drm.pdev; 332 static const uint8_t div_3200[] = { 16, 10, 8 }; 333 static const uint8_t div_4000[] = { 20, 12, 10 }; 334 static const uint8_t div_5333[] = { 24, 16, 14 }; 335 const uint8_t *div_table; 336 unsigned int cdclk_sel; 337 uint16_t tmp = 0; 338 339 cdclk_state->vco = intel_hpll_vco(dev_priv); 340 341 pci_read_config_word(pdev, GCFGC, &tmp); 342 343 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 344 345 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 346 goto fail; 347 348 switch (cdclk_state->vco) { 349 case 3200000: 350 div_table = div_3200; 351 break; 352 case 4000000: 353 div_table = div_4000; 354 break; 355 case 5333333: 356 div_table = div_5333; 357 break; 358 default: 359 goto fail; 360 } 361 362 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, 363 div_table[cdclk_sel]); 364 return; 365 366 fail: 367 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 368 cdclk_state->vco, tmp); 369 cdclk_state->cdclk = 200000; 370 } 371 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 373 struct intel_cdclk_state *cdclk_state) 374 { 375 struct pci_dev *pdev = dev_priv->drm.pdev; 376 unsigned int cdclk_sel; 377 uint16_t tmp = 0; 378 379 cdclk_state->vco = intel_hpll_vco(dev_priv); 380 381 pci_read_config_word(pdev, GCFGC, &tmp); 382 383 cdclk_sel = (tmp >> 12) & 0x1; 384 385 switch (cdclk_state->vco) { 386 case 2666667: 387 case 4000000: 388 case 5333333: 389 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; 390 break; 391 case 3200000: 392 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; 393 break; 394 default: 395 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 396 cdclk_state->vco, tmp); 397 cdclk_state->cdclk = 222222; 398 break; 399 } 400 } 401 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 403 struct intel_cdclk_state *cdclk_state) 404 { 405 uint32_t lcpll = I915_READ(LCPLL_CTL); 406 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 407 408 if (lcpll & LCPLL_CD_SOURCE_FCLK) 409 cdclk_state->cdclk = 800000; 410 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 411 cdclk_state->cdclk = 450000; 412 else if (freq == LCPLL_CLK_FREQ_450) 413 cdclk_state->cdclk = 450000; 414 else if (IS_HSW_ULT(dev_priv)) 415 cdclk_state->cdclk = 337500; 416 else 417 cdclk_state->cdclk = 540000; 418 } 419 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, 421 int max_pixclk) 422 { 423 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 424 333333 : 320000; 425 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; 426 427 /* 428 * We seem to get an unstable or solid color picture at 200MHz. 429 * Not sure what's wrong. For now use 200MHz only when all pipes 430 * are off. 431 */ 432 if (!IS_CHERRYVIEW(dev_priv) && 433 max_pixclk > freq_320*limit/100) 434 return 400000; 435 else if (max_pixclk > 266667*limit/100) 436 return freq_320; 437 else if (max_pixclk > 0) 438 return 266667; 439 else 440 return 200000; 441 } 442 443 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 444 struct intel_cdclk_state *cdclk_state) 445 { 446 cdclk_state->vco = vlv_get_hpll_vco(dev_priv); 447 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 448 CCK_DISPLAY_CLOCK_CONTROL, 449 cdclk_state->vco); 450 } 451 452 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 453 { 454 unsigned int credits, default_credits; 455 456 if (IS_CHERRYVIEW(dev_priv)) 457 default_credits = PFI_CREDIT(12); 458 else 459 default_credits = PFI_CREDIT(8); 460 461 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 462 /* CHV suggested value is 31 or 63 */ 463 if (IS_CHERRYVIEW(dev_priv)) 464 credits = PFI_CREDIT_63; 465 else 466 credits = PFI_CREDIT(15); 467 } else { 468 credits = default_credits; 469 } 470 471 /* 472 * WA - write default credits before re-programming 473 * FIXME: should we also set the resend bit here? 474 */ 475 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 476 default_credits); 477 478 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | 479 credits | PFI_CREDIT_RESEND); 480 481 /* 482 * FIXME is this guaranteed to clear 483 * immediately or should we poll for it? 484 */ 485 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); 486 } 487 488 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 489 const struct intel_cdclk_state *cdclk_state) 490 { 491 int cdclk = cdclk_state->cdclk; 492 u32 val, cmd; 493 494 /* There are cases where we can end up here with power domains 495 * off and a CDCLK frequency other than the minimum, like when 496 * issuing a modeset without actually changing any display after 497 * a system suspend. So grab the PIPE-A domain, which covers 498 * the HW blocks needed for the following programming. 499 */ 500 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); 501 502 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 503 cmd = 2; 504 else if (cdclk == 266667) 505 cmd = 1; 506 else 507 cmd = 0; 508 509 mutex_lock(&dev_priv->rps.hw_lock); 510 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 511 val &= ~DSPFREQGUAR_MASK; 512 val |= (cmd << DSPFREQGUAR_SHIFT); 513 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 514 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & 515 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 516 50)) { 517 DRM_ERROR("timed out waiting for CDclk change\n"); 518 } 519 mutex_unlock(&dev_priv->rps.hw_lock); 520 521 mutex_lock(&dev_priv->sb_lock); 522 523 if (cdclk == 400000) { 524 u32 divider; 525 526 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 527 cdclk) - 1; 528 529 /* adjust cdclk divider */ 530 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 531 val &= ~CCK_FREQUENCY_VALUES; 532 val |= divider; 533 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 534 535 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 536 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 537 50)) 538 DRM_ERROR("timed out waiting for CDclk change\n"); 539 } 540 541 /* adjust self-refresh exit latency value */ 542 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 543 val &= ~0x7f; 544 545 /* 546 * For high bandwidth configs, we set a higher latency in the bunit 547 * so that the core display fetch happens in time to avoid underruns. 548 */ 549 if (cdclk == 400000) 550 val |= 4500 / 250; /* 4.5 usec */ 551 else 552 val |= 3000 / 250; /* 3.0 usec */ 553 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 554 555 mutex_unlock(&dev_priv->sb_lock); 556 557 intel_update_cdclk(dev_priv); 558 559 vlv_program_pfi_credits(dev_priv); 560 561 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); 562 } 563 564 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 565 const struct intel_cdclk_state *cdclk_state) 566 { 567 int cdclk = cdclk_state->cdclk; 568 u32 val, cmd; 569 570 switch (cdclk) { 571 case 333333: 572 case 320000: 573 case 266667: 574 case 200000: 575 break; 576 default: 577 MISSING_CASE(cdclk); 578 return; 579 } 580 581 /* There are cases where we can end up here with power domains 582 * off and a CDCLK frequency other than the minimum, like when 583 * issuing a modeset without actually changing any display after 584 * a system suspend. So grab the PIPE-A domain, which covers 585 * the HW blocks needed for the following programming. 586 */ 587 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); 588 589 /* 590 * Specs are full of misinformation, but testing on actual 591 * hardware has shown that we just need to write the desired 592 * CCK divider into the Punit register. 593 */ 594 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 595 596 mutex_lock(&dev_priv->rps.hw_lock); 597 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 598 val &= ~DSPFREQGUAR_MASK_CHV; 599 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 600 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 601 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & 602 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 603 50)) { 604 DRM_ERROR("timed out waiting for CDclk change\n"); 605 } 606 mutex_unlock(&dev_priv->rps.hw_lock); 607 608 intel_update_cdclk(dev_priv); 609 610 vlv_program_pfi_credits(dev_priv); 611 612 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); 613 } 614 615 static int bdw_calc_cdclk(int max_pixclk) 616 { 617 if (max_pixclk > 540000) 618 return 675000; 619 else if (max_pixclk > 450000) 620 return 540000; 621 else if (max_pixclk > 337500) 622 return 450000; 623 else 624 return 337500; 625 } 626 627 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 628 struct intel_cdclk_state *cdclk_state) 629 { 630 uint32_t lcpll = I915_READ(LCPLL_CTL); 631 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 632 633 if (lcpll & LCPLL_CD_SOURCE_FCLK) 634 cdclk_state->cdclk = 800000; 635 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 636 cdclk_state->cdclk = 450000; 637 else if (freq == LCPLL_CLK_FREQ_450) 638 cdclk_state->cdclk = 450000; 639 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 640 cdclk_state->cdclk = 540000; 641 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 642 cdclk_state->cdclk = 337500; 643 else 644 cdclk_state->cdclk = 675000; 645 } 646 647 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 648 const struct intel_cdclk_state *cdclk_state) 649 { 650 int cdclk = cdclk_state->cdclk; 651 uint32_t val, data; 652 int ret; 653 654 if (WARN((I915_READ(LCPLL_CTL) & 655 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 656 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 657 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 658 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 659 "trying to change cdclk frequency with cdclk not enabled\n")) 660 return; 661 662 mutex_lock(&dev_priv->rps.hw_lock); 663 ret = sandybridge_pcode_write(dev_priv, 664 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 665 mutex_unlock(&dev_priv->rps.hw_lock); 666 if (ret) { 667 DRM_ERROR("failed to inform pcode about cdclk change\n"); 668 return; 669 } 670 671 val = I915_READ(LCPLL_CTL); 672 val |= LCPLL_CD_SOURCE_FCLK; 673 I915_WRITE(LCPLL_CTL, val); 674 675 if (wait_for_us(I915_READ(LCPLL_CTL) & 676 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 677 DRM_ERROR("Switching to FCLK failed\n"); 678 679 val = I915_READ(LCPLL_CTL); 680 val &= ~LCPLL_CLK_FREQ_MASK; 681 682 switch (cdclk) { 683 case 450000: 684 val |= LCPLL_CLK_FREQ_450; 685 data = 0; 686 break; 687 case 540000: 688 val |= LCPLL_CLK_FREQ_54O_BDW; 689 data = 1; 690 break; 691 case 337500: 692 val |= LCPLL_CLK_FREQ_337_5_BDW; 693 data = 2; 694 break; 695 case 675000: 696 val |= LCPLL_CLK_FREQ_675_BDW; 697 data = 3; 698 break; 699 default: 700 WARN(1, "invalid cdclk frequency\n"); 701 return; 702 } 703 704 I915_WRITE(LCPLL_CTL, val); 705 706 val = I915_READ(LCPLL_CTL); 707 val &= ~LCPLL_CD_SOURCE_FCLK; 708 I915_WRITE(LCPLL_CTL, val); 709 710 if (wait_for_us((I915_READ(LCPLL_CTL) & 711 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 712 DRM_ERROR("Switching back to LCPLL failed\n"); 713 714 mutex_lock(&dev_priv->rps.hw_lock); 715 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); 716 mutex_unlock(&dev_priv->rps.hw_lock); 717 718 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 719 720 intel_update_cdclk(dev_priv); 721 722 WARN(cdclk != dev_priv->cdclk.hw.cdclk, 723 "cdclk requested %d kHz but got %d kHz\n", 724 cdclk, dev_priv->cdclk.hw.cdclk); 725 } 726 727 static int skl_calc_cdclk(int max_pixclk, int vco) 728 { 729 if (vco == 8640000) { 730 if (max_pixclk > 540000) 731 return 617143; 732 else if (max_pixclk > 432000) 733 return 540000; 734 else if (max_pixclk > 308571) 735 return 432000; 736 else 737 return 308571; 738 } else { 739 if (max_pixclk > 540000) 740 return 675000; 741 else if (max_pixclk > 450000) 742 return 540000; 743 else if (max_pixclk > 337500) 744 return 450000; 745 else 746 return 337500; 747 } 748 } 749 750 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 751 struct intel_cdclk_state *cdclk_state) 752 { 753 u32 val; 754 755 cdclk_state->ref = 24000; 756 cdclk_state->vco = 0; 757 758 val = I915_READ(LCPLL1_CTL); 759 if ((val & LCPLL_PLL_ENABLE) == 0) 760 return; 761 762 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) 763 return; 764 765 val = I915_READ(DPLL_CTRL1); 766 767 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 768 DPLL_CTRL1_SSC(SKL_DPLL0) | 769 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 770 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 771 return; 772 773 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 774 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 775 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 776 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 777 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 778 cdclk_state->vco = 8100000; 779 break; 780 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 781 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 782 cdclk_state->vco = 8640000; 783 break; 784 default: 785 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 786 break; 787 } 788 } 789 790 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 791 struct intel_cdclk_state *cdclk_state) 792 { 793 u32 cdctl; 794 795 skl_dpll0_update(dev_priv, cdclk_state); 796 797 cdclk_state->cdclk = cdclk_state->ref; 798 799 if (cdclk_state->vco == 0) 800 return; 801 802 cdctl = I915_READ(CDCLK_CTL); 803 804 if (cdclk_state->vco == 8640000) { 805 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 806 case CDCLK_FREQ_450_432: 807 cdclk_state->cdclk = 432000; 808 break; 809 case CDCLK_FREQ_337_308: 810 cdclk_state->cdclk = 308571; 811 break; 812 case CDCLK_FREQ_540: 813 cdclk_state->cdclk = 540000; 814 break; 815 case CDCLK_FREQ_675_617: 816 cdclk_state->cdclk = 617143; 817 break; 818 default: 819 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 820 break; 821 } 822 } else { 823 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 824 case CDCLK_FREQ_450_432: 825 cdclk_state->cdclk = 450000; 826 break; 827 case CDCLK_FREQ_337_308: 828 cdclk_state->cdclk = 337500; 829 break; 830 case CDCLK_FREQ_540: 831 cdclk_state->cdclk = 540000; 832 break; 833 case CDCLK_FREQ_675_617: 834 cdclk_state->cdclk = 675000; 835 break; 836 default: 837 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 838 break; 839 } 840 } 841 } 842 843 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 844 static int skl_cdclk_decimal(int cdclk) 845 { 846 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 847 } 848 849 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 850 int vco) 851 { 852 bool changed = dev_priv->skl_preferred_vco_freq != vco; 853 854 dev_priv->skl_preferred_vco_freq = vco; 855 856 if (changed) 857 intel_update_max_cdclk(dev_priv); 858 } 859 860 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 861 { 862 int min_cdclk = skl_calc_cdclk(0, vco); 863 u32 val; 864 865 WARN_ON(vco != 8100000 && vco != 8640000); 866 867 /* select the minimum CDCLK before enabling DPLL 0 */ 868 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); 869 I915_WRITE(CDCLK_CTL, val); 870 POSTING_READ(CDCLK_CTL); 871 872 /* 873 * We always enable DPLL0 with the lowest link rate possible, but still 874 * taking into account the VCO required to operate the eDP panel at the 875 * desired frequency. The usual DP link rates operate with a VCO of 876 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 877 * The modeset code is responsible for the selection of the exact link 878 * rate later on, with the constraint of choosing a frequency that 879 * works with vco. 880 */ 881 val = I915_READ(DPLL_CTRL1); 882 883 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | 884 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 885 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); 886 if (vco == 8640000) 887 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 888 SKL_DPLL0); 889 else 890 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 891 SKL_DPLL0); 892 893 I915_WRITE(DPLL_CTRL1, val); 894 POSTING_READ(DPLL_CTRL1); 895 896 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); 897 898 if (intel_wait_for_register(dev_priv, 899 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 900 5)) 901 DRM_ERROR("DPLL0 not locked\n"); 902 903 dev_priv->cdclk.hw.vco = vco; 904 905 /* We'll want to keep using the current vco from now on. */ 906 skl_set_preferred_cdclk_vco(dev_priv, vco); 907 } 908 909 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 910 { 911 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); 912 if (intel_wait_for_register(dev_priv, 913 LCPLL1_CTL, LCPLL_PLL_LOCK, 0, 914 1)) 915 DRM_ERROR("Couldn't disable DPLL0\n"); 916 917 dev_priv->cdclk.hw.vco = 0; 918 } 919 920 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 921 const struct intel_cdclk_state *cdclk_state) 922 { 923 int cdclk = cdclk_state->cdclk; 924 int vco = cdclk_state->vco; 925 u32 freq_select, pcu_ack; 926 int ret; 927 928 WARN_ON((cdclk == 24000) != (vco == 0)); 929 930 mutex_lock(&dev_priv->rps.hw_lock); 931 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, 932 SKL_CDCLK_PREPARE_FOR_CHANGE, 933 SKL_CDCLK_READY_FOR_CHANGE, 934 SKL_CDCLK_READY_FOR_CHANGE, 3); 935 mutex_unlock(&dev_priv->rps.hw_lock); 936 if (ret) { 937 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", 938 ret); 939 return; 940 } 941 942 /* set CDCLK_CTL */ 943 switch (cdclk) { 944 case 450000: 945 case 432000: 946 freq_select = CDCLK_FREQ_450_432; 947 pcu_ack = 1; 948 break; 949 case 540000: 950 freq_select = CDCLK_FREQ_540; 951 pcu_ack = 2; 952 break; 953 case 308571: 954 case 337500: 955 default: 956 freq_select = CDCLK_FREQ_337_308; 957 pcu_ack = 0; 958 break; 959 case 617143: 960 case 675000: 961 freq_select = CDCLK_FREQ_675_617; 962 pcu_ack = 3; 963 break; 964 } 965 966 if (dev_priv->cdclk.hw.vco != 0 && 967 dev_priv->cdclk.hw.vco != vco) 968 skl_dpll0_disable(dev_priv); 969 970 if (dev_priv->cdclk.hw.vco != vco) 971 skl_dpll0_enable(dev_priv, vco); 972 973 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); 974 POSTING_READ(CDCLK_CTL); 975 976 /* inform PCU of the change */ 977 mutex_lock(&dev_priv->rps.hw_lock); 978 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); 979 mutex_unlock(&dev_priv->rps.hw_lock); 980 981 intel_update_cdclk(dev_priv); 982 } 983 984 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 985 { 986 uint32_t cdctl, expected; 987 988 /* 989 * check if the pre-os initialized the display 990 * There is SWF18 scratchpad register defined which is set by the 991 * pre-os which can be used by the OS drivers to check the status 992 */ 993 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 994 goto sanitize; 995 996 intel_update_cdclk(dev_priv); 997 /* Is PLL enabled and locked ? */ 998 if (dev_priv->cdclk.hw.vco == 0 || 999 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) 1000 goto sanitize; 1001 1002 /* DPLL okay; verify the cdclock 1003 * 1004 * Noticed in some instances that the freq selection is correct but 1005 * decimal part is programmed wrong from BIOS where pre-os does not 1006 * enable display. Verify the same as well. 1007 */ 1008 cdctl = I915_READ(CDCLK_CTL); 1009 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1010 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1011 if (cdctl == expected) 1012 /* All well; nothing to sanitize */ 1013 return; 1014 1015 sanitize: 1016 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 1017 1018 /* force cdclk programming */ 1019 dev_priv->cdclk.hw.cdclk = 0; 1020 /* force full PLL disable + enable */ 1021 dev_priv->cdclk.hw.vco = -1; 1022 } 1023 1024 /** 1025 * skl_init_cdclk - Initialize CDCLK on SKL 1026 * @dev_priv: i915 device 1027 * 1028 * Initialize CDCLK for SKL and derivatives. This is generally 1029 * done only during the display core initialization sequence, 1030 * after which the DMC will take care of turning CDCLK off/on 1031 * as needed. 1032 */ 1033 void skl_init_cdclk(struct drm_i915_private *dev_priv) 1034 { 1035 struct intel_cdclk_state cdclk_state; 1036 1037 skl_sanitize_cdclk(dev_priv); 1038 1039 if (dev_priv->cdclk.hw.cdclk != 0 && 1040 dev_priv->cdclk.hw.vco != 0) { 1041 /* 1042 * Use the current vco as our initial 1043 * guess as to what the preferred vco is. 1044 */ 1045 if (dev_priv->skl_preferred_vco_freq == 0) 1046 skl_set_preferred_cdclk_vco(dev_priv, 1047 dev_priv->cdclk.hw.vco); 1048 return; 1049 } 1050 1051 cdclk_state = dev_priv->cdclk.hw; 1052 1053 cdclk_state.vco = dev_priv->skl_preferred_vco_freq; 1054 if (cdclk_state.vco == 0) 1055 cdclk_state.vco = 8100000; 1056 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); 1057 1058 skl_set_cdclk(dev_priv, &cdclk_state); 1059 } 1060 1061 /** 1062 * skl_uninit_cdclk - Uninitialize CDCLK on SKL 1063 * @dev_priv: i915 device 1064 * 1065 * Uninitialize CDCLK for SKL and derivatives. This is done only 1066 * during the display core uninitialization sequence. 1067 */ 1068 void skl_uninit_cdclk(struct drm_i915_private *dev_priv) 1069 { 1070 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; 1071 1072 cdclk_state.cdclk = cdclk_state.ref; 1073 cdclk_state.vco = 0; 1074 1075 skl_set_cdclk(dev_priv, &cdclk_state); 1076 } 1077 1078 static int bxt_calc_cdclk(int max_pixclk) 1079 { 1080 if (max_pixclk > 576000) 1081 return 624000; 1082 else if (max_pixclk > 384000) 1083 return 576000; 1084 else if (max_pixclk > 288000) 1085 return 384000; 1086 else if (max_pixclk > 144000) 1087 return 288000; 1088 else 1089 return 144000; 1090 } 1091 1092 static int glk_calc_cdclk(int max_pixclk) 1093 { 1094 if (max_pixclk > 2 * 158400) 1095 return 316800; 1096 else if (max_pixclk > 2 * 79200) 1097 return 158400; 1098 else 1099 return 79200; 1100 } 1101 1102 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1103 { 1104 int ratio; 1105 1106 if (cdclk == dev_priv->cdclk.hw.ref) 1107 return 0; 1108 1109 switch (cdclk) { 1110 default: 1111 MISSING_CASE(cdclk); 1112 case 144000: 1113 case 288000: 1114 case 384000: 1115 case 576000: 1116 ratio = 60; 1117 break; 1118 case 624000: 1119 ratio = 65; 1120 break; 1121 } 1122 1123 return dev_priv->cdclk.hw.ref * ratio; 1124 } 1125 1126 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1127 { 1128 int ratio; 1129 1130 if (cdclk == dev_priv->cdclk.hw.ref) 1131 return 0; 1132 1133 switch (cdclk) { 1134 default: 1135 MISSING_CASE(cdclk); 1136 case 79200: 1137 case 158400: 1138 case 316800: 1139 ratio = 33; 1140 break; 1141 } 1142 1143 return dev_priv->cdclk.hw.ref * ratio; 1144 } 1145 1146 static void bxt_de_pll_update(struct drm_i915_private *dev_priv, 1147 struct intel_cdclk_state *cdclk_state) 1148 { 1149 u32 val; 1150 1151 cdclk_state->ref = 19200; 1152 cdclk_state->vco = 0; 1153 1154 val = I915_READ(BXT_DE_PLL_ENABLE); 1155 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) 1156 return; 1157 1158 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) 1159 return; 1160 1161 val = I915_READ(BXT_DE_PLL_CTL); 1162 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref; 1163 } 1164 1165 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1166 struct intel_cdclk_state *cdclk_state) 1167 { 1168 u32 divider; 1169 int div; 1170 1171 bxt_de_pll_update(dev_priv, cdclk_state); 1172 1173 cdclk_state->cdclk = cdclk_state->ref; 1174 1175 if (cdclk_state->vco == 0) 1176 return; 1177 1178 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1179 1180 switch (divider) { 1181 case BXT_CDCLK_CD2X_DIV_SEL_1: 1182 div = 2; 1183 break; 1184 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1185 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); 1186 div = 3; 1187 break; 1188 case BXT_CDCLK_CD2X_DIV_SEL_2: 1189 div = 4; 1190 break; 1191 case BXT_CDCLK_CD2X_DIV_SEL_4: 1192 div = 8; 1193 break; 1194 default: 1195 MISSING_CASE(divider); 1196 return; 1197 } 1198 1199 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); 1200 } 1201 1202 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1203 { 1204 I915_WRITE(BXT_DE_PLL_ENABLE, 0); 1205 1206 /* Timeout 200us */ 1207 if (intel_wait_for_register(dev_priv, 1208 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, 1209 1)) 1210 DRM_ERROR("timeout waiting for DE PLL unlock\n"); 1211 1212 dev_priv->cdclk.hw.vco = 0; 1213 } 1214 1215 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1216 { 1217 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); 1218 u32 val; 1219 1220 val = I915_READ(BXT_DE_PLL_CTL); 1221 val &= ~BXT_DE_PLL_RATIO_MASK; 1222 val |= BXT_DE_PLL_RATIO(ratio); 1223 I915_WRITE(BXT_DE_PLL_CTL, val); 1224 1225 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1226 1227 /* Timeout 200us */ 1228 if (intel_wait_for_register(dev_priv, 1229 BXT_DE_PLL_ENABLE, 1230 BXT_DE_PLL_LOCK, 1231 BXT_DE_PLL_LOCK, 1232 1)) 1233 DRM_ERROR("timeout waiting for DE PLL lock\n"); 1234 1235 dev_priv->cdclk.hw.vco = vco; 1236 } 1237 1238 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1239 const struct intel_cdclk_state *cdclk_state) 1240 { 1241 int cdclk = cdclk_state->cdclk; 1242 int vco = cdclk_state->vco; 1243 u32 val, divider; 1244 int ret; 1245 1246 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1247 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1248 case 8: 1249 divider = BXT_CDCLK_CD2X_DIV_SEL_4; 1250 break; 1251 case 4: 1252 divider = BXT_CDCLK_CD2X_DIV_SEL_2; 1253 break; 1254 case 3: 1255 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); 1256 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; 1257 break; 1258 case 2: 1259 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 1260 break; 1261 default: 1262 WARN_ON(cdclk != dev_priv->cdclk.hw.ref); 1263 WARN_ON(vco != 0); 1264 1265 divider = BXT_CDCLK_CD2X_DIV_SEL_1; 1266 break; 1267 } 1268 1269 /* Inform power controller of upcoming frequency change */ 1270 mutex_lock(&dev_priv->rps.hw_lock); 1271 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 1272 0x80000000); 1273 mutex_unlock(&dev_priv->rps.hw_lock); 1274 1275 if (ret) { 1276 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", 1277 ret, cdclk); 1278 return; 1279 } 1280 1281 if (dev_priv->cdclk.hw.vco != 0 && 1282 dev_priv->cdclk.hw.vco != vco) 1283 bxt_de_pll_disable(dev_priv); 1284 1285 if (dev_priv->cdclk.hw.vco != vco) 1286 bxt_de_pll_enable(dev_priv, vco); 1287 1288 val = divider | skl_cdclk_decimal(cdclk); 1289 /* 1290 * FIXME if only the cd2x divider needs changing, it could be done 1291 * without shutting off the pipe (if only one pipe is active). 1292 */ 1293 val |= BXT_CDCLK_CD2X_PIPE_NONE; 1294 /* 1295 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1296 * enable otherwise. 1297 */ 1298 if (cdclk >= 500000) 1299 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1300 I915_WRITE(CDCLK_CTL, val); 1301 1302 mutex_lock(&dev_priv->rps.hw_lock); 1303 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, 1304 DIV_ROUND_UP(cdclk, 25000)); 1305 mutex_unlock(&dev_priv->rps.hw_lock); 1306 1307 if (ret) { 1308 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", 1309 ret, cdclk); 1310 return; 1311 } 1312 1313 intel_update_cdclk(dev_priv); 1314 } 1315 1316 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 1317 { 1318 u32 cdctl, expected; 1319 1320 intel_update_cdclk(dev_priv); 1321 1322 if (dev_priv->cdclk.hw.vco == 0 || 1323 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref) 1324 goto sanitize; 1325 1326 /* DPLL okay; verify the cdclock 1327 * 1328 * Some BIOS versions leave an incorrect decimal frequency value and 1329 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 1330 * so sanitize this register. 1331 */ 1332 cdctl = I915_READ(CDCLK_CTL); 1333 /* 1334 * Let's ignore the pipe field, since BIOS could have configured the 1335 * dividers both synching to an active pipe, or asynchronously 1336 * (PIPE_NONE). 1337 */ 1338 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; 1339 1340 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | 1341 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); 1342 /* 1343 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1344 * enable otherwise. 1345 */ 1346 if (dev_priv->cdclk.hw.cdclk >= 500000) 1347 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1348 1349 if (cdctl == expected) 1350 /* All well; nothing to sanitize */ 1351 return; 1352 1353 sanitize: 1354 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); 1355 1356 /* force cdclk programming */ 1357 dev_priv->cdclk.hw.cdclk = 0; 1358 1359 /* force full PLL disable + enable */ 1360 dev_priv->cdclk.hw.vco = -1; 1361 } 1362 1363 /** 1364 * bxt_init_cdclk - Initialize CDCLK on BXT 1365 * @dev_priv: i915 device 1366 * 1367 * Initialize CDCLK for BXT and derivatives. This is generally 1368 * done only during the display core initialization sequence, 1369 * after which the DMC will take care of turning CDCLK off/on 1370 * as needed. 1371 */ 1372 void bxt_init_cdclk(struct drm_i915_private *dev_priv) 1373 { 1374 struct intel_cdclk_state cdclk_state; 1375 1376 bxt_sanitize_cdclk(dev_priv); 1377 1378 if (dev_priv->cdclk.hw.cdclk != 0 && 1379 dev_priv->cdclk.hw.vco != 0) 1380 return; 1381 1382 cdclk_state = dev_priv->cdclk.hw; 1383 1384 /* 1385 * FIXME: 1386 * - The initial CDCLK needs to be read from VBT. 1387 * Need to make this change after VBT has changes for BXT. 1388 */ 1389 if (IS_GEMINILAKE(dev_priv)) { 1390 cdclk_state.cdclk = glk_calc_cdclk(0); 1391 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); 1392 } else { 1393 cdclk_state.cdclk = bxt_calc_cdclk(0); 1394 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); 1395 } 1396 1397 bxt_set_cdclk(dev_priv, &cdclk_state); 1398 } 1399 1400 /** 1401 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT 1402 * @dev_priv: i915 device 1403 * 1404 * Uninitialize CDCLK for BXT and derivatives. This is done only 1405 * during the display core uninitialization sequence. 1406 */ 1407 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) 1408 { 1409 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; 1410 1411 cdclk_state.cdclk = cdclk_state.ref; 1412 cdclk_state.vco = 0; 1413 1414 bxt_set_cdclk(dev_priv, &cdclk_state); 1415 } 1416 1417 /** 1418 * intel_cdclk_state_compare - Determine if two CDCLK states differ 1419 * @a: first CDCLK state 1420 * @b: second CDCLK state 1421 * 1422 * Returns: 1423 * True if the CDCLK states are identical, false if they differ. 1424 */ 1425 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a, 1426 const struct intel_cdclk_state *b) 1427 { 1428 return memcmp(a, b, sizeof(*a)) == 0; 1429 } 1430 1431 /** 1432 * intel_set_cdclk - Push the CDCLK state to the hardware 1433 * @dev_priv: i915 device 1434 * @cdclk_state: new CDCLK state 1435 * 1436 * Program the hardware based on the passed in CDCLK state, 1437 * if necessary. 1438 */ 1439 void intel_set_cdclk(struct drm_i915_private *dev_priv, 1440 const struct intel_cdclk_state *cdclk_state) 1441 { 1442 if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state)) 1443 return; 1444 1445 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) 1446 return; 1447 1448 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n", 1449 cdclk_state->cdclk, cdclk_state->vco, 1450 cdclk_state->ref); 1451 1452 dev_priv->display.set_cdclk(dev_priv, cdclk_state); 1453 } 1454 1455 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, 1456 int pixel_rate) 1457 { 1458 struct drm_i915_private *dev_priv = 1459 to_i915(crtc_state->base.crtc->dev); 1460 1461 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 1462 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) 1463 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); 1464 1465 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 1466 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 1467 * there may be audio corruption or screen corruption." This cdclk 1468 * restriction for GLK is 316.8 MHz and since GLK can output two 1469 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz. 1470 */ 1471 if (intel_crtc_has_dp_encoder(crtc_state) && 1472 crtc_state->has_audio && 1473 crtc_state->port_clock >= 540000 && 1474 crtc_state->lane_count == 4) { 1475 if (IS_GEMINILAKE(dev_priv)) 1476 pixel_rate = max(2 * 316800, pixel_rate); 1477 else 1478 pixel_rate = max(432000, pixel_rate); 1479 } 1480 1481 /* According to BSpec, "The CD clock frequency must be at least twice 1482 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1483 * The check for GLK has to be adjusted as the platform can output 1484 * two pixels per clock. 1485 */ 1486 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) { 1487 if (IS_GEMINILAKE(dev_priv)) 1488 pixel_rate = max(2 * 2 * 96000, pixel_rate); 1489 else 1490 pixel_rate = max(2 * 96000, pixel_rate); 1491 } 1492 1493 return pixel_rate; 1494 } 1495 1496 /* compute the max rate for new configuration */ 1497 static int intel_max_pixel_rate(struct drm_atomic_state *state) 1498 { 1499 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 1500 struct drm_i915_private *dev_priv = to_i915(state->dev); 1501 struct drm_crtc *crtc; 1502 struct drm_crtc_state *cstate; 1503 struct intel_crtc_state *crtc_state; 1504 unsigned int max_pixel_rate = 0, i; 1505 enum i915_pipe pipe; 1506 1507 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, 1508 sizeof(intel_state->min_pixclk)); 1509 1510 for_each_new_crtc_in_state(state, crtc, cstate, i) { 1511 int pixel_rate; 1512 1513 crtc_state = to_intel_crtc_state(cstate); 1514 if (!crtc_state->base.enable) { 1515 intel_state->min_pixclk[i] = 0; 1516 continue; 1517 } 1518 1519 pixel_rate = crtc_state->pixel_rate; 1520 1521 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) 1522 pixel_rate = 1523 bdw_adjust_min_pipe_pixel_rate(crtc_state, 1524 pixel_rate); 1525 1526 intel_state->min_pixclk[i] = pixel_rate; 1527 } 1528 1529 for_each_pipe(dev_priv, pipe) 1530 max_pixel_rate = max(intel_state->min_pixclk[pipe], 1531 max_pixel_rate); 1532 1533 return max_pixel_rate; 1534 } 1535 1536 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state) 1537 { 1538 struct drm_i915_private *dev_priv = to_i915(state->dev); 1539 int max_pixclk = intel_max_pixel_rate(state); 1540 struct intel_atomic_state *intel_state = 1541 to_intel_atomic_state(state); 1542 int cdclk; 1543 1544 cdclk = vlv_calc_cdclk(dev_priv, max_pixclk); 1545 1546 if (cdclk > dev_priv->max_cdclk_freq) { 1547 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 1548 cdclk, dev_priv->max_cdclk_freq); 1549 return -EINVAL; 1550 } 1551 1552 intel_state->cdclk.logical.cdclk = cdclk; 1553 1554 if (!intel_state->active_crtcs) { 1555 cdclk = vlv_calc_cdclk(dev_priv, 0); 1556 1557 intel_state->cdclk.actual.cdclk = cdclk; 1558 } else { 1559 intel_state->cdclk.actual = 1560 intel_state->cdclk.logical; 1561 } 1562 1563 return 0; 1564 } 1565 1566 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state) 1567 { 1568 struct drm_i915_private *dev_priv = to_i915(state->dev); 1569 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 1570 int max_pixclk = intel_max_pixel_rate(state); 1571 int cdclk; 1572 1573 /* 1574 * FIXME should also account for plane ratio 1575 * once 64bpp pixel formats are supported. 1576 */ 1577 cdclk = bdw_calc_cdclk(max_pixclk); 1578 1579 if (cdclk > dev_priv->max_cdclk_freq) { 1580 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 1581 cdclk, dev_priv->max_cdclk_freq); 1582 return -EINVAL; 1583 } 1584 1585 intel_state->cdclk.logical.cdclk = cdclk; 1586 1587 if (!intel_state->active_crtcs) { 1588 cdclk = bdw_calc_cdclk(0); 1589 1590 intel_state->cdclk.actual.cdclk = cdclk; 1591 } else { 1592 intel_state->cdclk.actual = 1593 intel_state->cdclk.logical; 1594 } 1595 1596 return 0; 1597 } 1598 1599 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) 1600 { 1601 struct intel_atomic_state *intel_state = to_intel_atomic_state(state); 1602 struct drm_i915_private *dev_priv = to_i915(state->dev); 1603 const int max_pixclk = intel_max_pixel_rate(state); 1604 int cdclk, vco; 1605 1606 vco = intel_state->cdclk.logical.vco; 1607 if (!vco) 1608 vco = dev_priv->skl_preferred_vco_freq; 1609 1610 /* 1611 * FIXME should also account for plane ratio 1612 * once 64bpp pixel formats are supported. 1613 */ 1614 cdclk = skl_calc_cdclk(max_pixclk, vco); 1615 1616 if (cdclk > dev_priv->max_cdclk_freq) { 1617 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 1618 cdclk, dev_priv->max_cdclk_freq); 1619 return -EINVAL; 1620 } 1621 1622 intel_state->cdclk.logical.vco = vco; 1623 intel_state->cdclk.logical.cdclk = cdclk; 1624 1625 if (!intel_state->active_crtcs) { 1626 cdclk = skl_calc_cdclk(0, vco); 1627 1628 intel_state->cdclk.actual.vco = vco; 1629 intel_state->cdclk.actual.cdclk = cdclk; 1630 } else { 1631 intel_state->cdclk.actual = 1632 intel_state->cdclk.logical; 1633 } 1634 1635 return 0; 1636 } 1637 1638 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) 1639 { 1640 struct drm_i915_private *dev_priv = to_i915(state->dev); 1641 int max_pixclk = intel_max_pixel_rate(state); 1642 struct intel_atomic_state *intel_state = 1643 to_intel_atomic_state(state); 1644 int cdclk, vco; 1645 1646 if (IS_GEMINILAKE(dev_priv)) { 1647 cdclk = glk_calc_cdclk(max_pixclk); 1648 vco = glk_de_pll_vco(dev_priv, cdclk); 1649 } else { 1650 cdclk = bxt_calc_cdclk(max_pixclk); 1651 vco = bxt_de_pll_vco(dev_priv, cdclk); 1652 } 1653 1654 if (cdclk > dev_priv->max_cdclk_freq) { 1655 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", 1656 cdclk, dev_priv->max_cdclk_freq); 1657 return -EINVAL; 1658 } 1659 1660 intel_state->cdclk.logical.vco = vco; 1661 intel_state->cdclk.logical.cdclk = cdclk; 1662 1663 if (!intel_state->active_crtcs) { 1664 if (IS_GEMINILAKE(dev_priv)) { 1665 cdclk = glk_calc_cdclk(0); 1666 vco = glk_de_pll_vco(dev_priv, cdclk); 1667 } else { 1668 cdclk = bxt_calc_cdclk(0); 1669 vco = bxt_de_pll_vco(dev_priv, cdclk); 1670 } 1671 1672 intel_state->cdclk.actual.vco = vco; 1673 intel_state->cdclk.actual.cdclk = cdclk; 1674 } else { 1675 intel_state->cdclk.actual = 1676 intel_state->cdclk.logical; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 1683 { 1684 int max_cdclk_freq = dev_priv->max_cdclk_freq; 1685 1686 if (IS_GEMINILAKE(dev_priv)) 1687 return 2 * max_cdclk_freq; 1688 else if (INTEL_INFO(dev_priv)->gen >= 9 || 1689 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1690 return max_cdclk_freq; 1691 else if (IS_CHERRYVIEW(dev_priv)) 1692 return max_cdclk_freq*95/100; 1693 else if (INTEL_INFO(dev_priv)->gen < 4) 1694 return 2*max_cdclk_freq*90/100; 1695 else 1696 return max_cdclk_freq*90/100; 1697 } 1698 1699 /** 1700 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 1701 * @dev_priv: i915 device 1702 * 1703 * Determine the maximum CDCLK frequency the platform supports, and also 1704 * derive the maximum dot clock frequency the maximum CDCLK frequency 1705 * allows. 1706 */ 1707 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 1708 { 1709 if (IS_GEN9_BC(dev_priv)) { 1710 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 1711 int max_cdclk, vco; 1712 1713 vco = dev_priv->skl_preferred_vco_freq; 1714 WARN_ON(vco != 8100000 && vco != 8640000); 1715 1716 /* 1717 * Use the lower (vco 8640) cdclk values as a 1718 * first guess. skl_calc_cdclk() will correct it 1719 * if the preferred vco is 8100 instead. 1720 */ 1721 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 1722 max_cdclk = 617143; 1723 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 1724 max_cdclk = 540000; 1725 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 1726 max_cdclk = 432000; 1727 else 1728 max_cdclk = 308571; 1729 1730 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 1731 } else if (IS_GEMINILAKE(dev_priv)) { 1732 dev_priv->max_cdclk_freq = 316800; 1733 } else if (IS_BROXTON(dev_priv)) { 1734 dev_priv->max_cdclk_freq = 624000; 1735 } else if (IS_BROADWELL(dev_priv)) { 1736 /* 1737 * FIXME with extra cooling we can allow 1738 * 540 MHz for ULX and 675 Mhz for ULT. 1739 * How can we know if extra cooling is 1740 * available? PCI ID, VTB, something else? 1741 */ 1742 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) 1743 dev_priv->max_cdclk_freq = 450000; 1744 else if (IS_BDW_ULX(dev_priv)) 1745 dev_priv->max_cdclk_freq = 450000; 1746 else if (IS_BDW_ULT(dev_priv)) 1747 dev_priv->max_cdclk_freq = 540000; 1748 else 1749 dev_priv->max_cdclk_freq = 675000; 1750 } else if (IS_CHERRYVIEW(dev_priv)) { 1751 dev_priv->max_cdclk_freq = 320000; 1752 } else if (IS_VALLEYVIEW(dev_priv)) { 1753 dev_priv->max_cdclk_freq = 400000; 1754 } else { 1755 /* otherwise assume cdclk is fixed */ 1756 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; 1757 } 1758 1759 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 1760 1761 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", 1762 dev_priv->max_cdclk_freq); 1763 1764 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", 1765 dev_priv->max_dotclk_freq); 1766 } 1767 1768 /** 1769 * intel_update_cdclk - Determine the current CDCLK frequency 1770 * @dev_priv: i915 device 1771 * 1772 * Determine the current CDCLK frequency. 1773 */ 1774 void intel_update_cdclk(struct drm_i915_private *dev_priv) 1775 { 1776 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); 1777 1778 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", 1779 dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco, 1780 dev_priv->cdclk.hw.ref); 1781 1782 /* 1783 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 1784 * Programmng [sic] note: bit[9:2] should be programmed to the number 1785 * of cdclk that generates 4MHz reference clock freq which is used to 1786 * generate GMBus clock. This will vary with the cdclk freq. 1787 */ 1788 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1789 I915_WRITE(GMBUSFREQ_VLV, 1790 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); 1791 } 1792 1793 static int pch_rawclk(struct drm_i915_private *dev_priv) 1794 { 1795 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 1796 } 1797 1798 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 1799 { 1800 /* RAWCLK_FREQ_VLV register updated from power well code */ 1801 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 1802 CCK_DISPLAY_REF_CLOCK_CONTROL); 1803 } 1804 1805 static int g4x_hrawclk(struct drm_i915_private *dev_priv) 1806 { 1807 uint32_t clkcfg; 1808 1809 /* hrawclock is 1/4 the FSB frequency */ 1810 clkcfg = I915_READ(CLKCFG); 1811 switch (clkcfg & CLKCFG_FSB_MASK) { 1812 case CLKCFG_FSB_400: 1813 return 100000; 1814 case CLKCFG_FSB_533: 1815 return 133333; 1816 case CLKCFG_FSB_667: 1817 return 166667; 1818 case CLKCFG_FSB_800: 1819 return 200000; 1820 case CLKCFG_FSB_1067: 1821 case CLKCFG_FSB_1067_ALT: 1822 return 266667; 1823 case CLKCFG_FSB_1333: 1824 case CLKCFG_FSB_1333_ALT: 1825 return 333333; 1826 default: 1827 return 133333; 1828 } 1829 } 1830 1831 /** 1832 * intel_update_rawclk - Determine the current RAWCLK frequency 1833 * @dev_priv: i915 device 1834 * 1835 * Determine the current RAWCLK frequency. RAWCLK is a fixed 1836 * frequency clock so this needs to done only once. 1837 */ 1838 void intel_update_rawclk(struct drm_i915_private *dev_priv) 1839 { 1840 if (HAS_PCH_SPLIT(dev_priv)) 1841 dev_priv->rawclk_freq = pch_rawclk(dev_priv); 1842 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1843 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); 1844 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) 1845 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); 1846 else 1847 /* no rawclk on other platforms, or no need to know it */ 1848 return; 1849 1850 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); 1851 } 1852 1853 /** 1854 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 1855 * @dev_priv: i915 device 1856 */ 1857 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 1858 { 1859 if (IS_CHERRYVIEW(dev_priv)) { 1860 dev_priv->display.set_cdclk = chv_set_cdclk; 1861 dev_priv->display.modeset_calc_cdclk = 1862 vlv_modeset_calc_cdclk; 1863 } else if (IS_VALLEYVIEW(dev_priv)) { 1864 dev_priv->display.set_cdclk = vlv_set_cdclk; 1865 dev_priv->display.modeset_calc_cdclk = 1866 vlv_modeset_calc_cdclk; 1867 } else if (IS_BROADWELL(dev_priv)) { 1868 dev_priv->display.set_cdclk = bdw_set_cdclk; 1869 dev_priv->display.modeset_calc_cdclk = 1870 bdw_modeset_calc_cdclk; 1871 } else if (IS_GEN9_LP(dev_priv)) { 1872 dev_priv->display.set_cdclk = bxt_set_cdclk; 1873 dev_priv->display.modeset_calc_cdclk = 1874 bxt_modeset_calc_cdclk; 1875 } else if (IS_GEN9_BC(dev_priv)) { 1876 dev_priv->display.set_cdclk = skl_set_cdclk; 1877 dev_priv->display.modeset_calc_cdclk = 1878 skl_modeset_calc_cdclk; 1879 } 1880 1881 if (IS_GEN9_BC(dev_priv)) 1882 dev_priv->display.get_cdclk = skl_get_cdclk; 1883 else if (IS_GEN9_LP(dev_priv)) 1884 dev_priv->display.get_cdclk = bxt_get_cdclk; 1885 else if (IS_BROADWELL(dev_priv)) 1886 dev_priv->display.get_cdclk = bdw_get_cdclk; 1887 else if (IS_HASWELL(dev_priv)) 1888 dev_priv->display.get_cdclk = hsw_get_cdclk; 1889 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1890 dev_priv->display.get_cdclk = vlv_get_cdclk; 1891 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) 1892 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 1893 else if (IS_GEN5(dev_priv)) 1894 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; 1895 else if (IS_GM45(dev_priv)) 1896 dev_priv->display.get_cdclk = gm45_get_cdclk; 1897 else if (IS_G45(dev_priv)) 1898 dev_priv->display.get_cdclk = g33_get_cdclk; 1899 else if (IS_I965GM(dev_priv)) 1900 dev_priv->display.get_cdclk = i965gm_get_cdclk; 1901 else if (IS_I965G(dev_priv)) 1902 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 1903 else if (IS_PINEVIEW(dev_priv)) 1904 dev_priv->display.get_cdclk = pnv_get_cdclk; 1905 else if (IS_G33(dev_priv)) 1906 dev_priv->display.get_cdclk = g33_get_cdclk; 1907 else if (IS_I945GM(dev_priv)) 1908 dev_priv->display.get_cdclk = i945gm_get_cdclk; 1909 else if (IS_I945G(dev_priv)) 1910 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; 1911 else if (IS_I915GM(dev_priv)) 1912 dev_priv->display.get_cdclk = i915gm_get_cdclk; 1913 else if (IS_I915G(dev_priv)) 1914 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; 1915 else if (IS_I865G(dev_priv)) 1916 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; 1917 else if (IS_I85X(dev_priv)) 1918 dev_priv->display.get_cdclk = i85x_get_cdclk; 1919 else if (IS_I845G(dev_priv)) 1920 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; 1921 else { /* 830 */ 1922 WARN(!IS_I830(dev_priv), 1923 "Unknown platform. Assuming 133 MHz CDCLK\n"); 1924 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; 1925 } 1926 } 1927