1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "intel_drv.h" 26 27 #define CTM_COEFF_SIGN (1ULL << 63) 28 29 #define CTM_COEFF_1_0 (1ULL << 32) 30 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1) 31 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1) 32 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1) 33 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1) 34 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1) 35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1) 36 37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255) 38 39 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0) 40 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1)) 41 42 #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256) 43 44 /* Post offset values for RGB->YCBCR conversion */ 45 #define POSTOFF_RGB_TO_YUV_HI 0x800 46 #define POSTOFF_RGB_TO_YUV_ME 0x100 47 #define POSTOFF_RGB_TO_YUV_LO 0x800 48 49 /* 50 * These values are direct register values specified in the Bspec, 51 * for RGB->YUV conversion matrix (colorspace BT709) 52 */ 53 #define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8 54 #define CSC_RGB_TO_YUV_BU 0x37e80000 55 #define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0 56 #define CSC_RGB_TO_YUV_BY 0xb5280000 57 #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 58 #define CSC_RGB_TO_YUV_BV 0x1e080000 59 60 /* 61 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point 62 * format). This macro takes the coefficient we want transformed and the 63 * number of fractional bits. 64 * 65 * We only have a 9 bits precision window which slides depending on the value 66 * of the CTM coefficient and we write the value from bit 3. We also round the 67 * value. 68 */ 69 #define I9XX_CSC_COEFF_FP(coeff, fbits) \ 70 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8) 71 72 #define I9XX_CSC_COEFF_LIMITED_RANGE \ 73 I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9) 74 #define I9XX_CSC_COEFF_1_0 \ 75 ((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8)) 76 77 static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state) 78 { 79 return !state->degamma_lut && 80 !state->ctm && 81 state->gamma_lut && 82 state->gamma_lut->length == LEGACY_LUT_LENGTH; 83 } 84 85 /* 86 * When using limited range, multiply the matrix given by userspace by 87 * the matrix that we would use for the limited range. We do the 88 * multiplication in U2.30 format. 89 */ 90 static void ctm_mult_by_limited(uint64_t *result, int64_t *input) 91 { 92 int i; 93 94 for (i = 0; i < 9; i++) 95 result[i] = 0; 96 97 for (i = 0; i < 3; i++) { 98 int64_t user_coeff = input[i * 3 + i]; 99 uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2; 100 uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 101 0, 102 CTM_COEFF_4_0 - 1) >> 2; 103 104 result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27; 105 if (CTM_COEFF_NEGATIVE(user_coeff)) 106 result[i * 3 + i] |= CTM_COEFF_SIGN; 107 } 108 } 109 110 static void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc) 111 { 112 int pipe = intel_crtc->pipe; 113 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 114 115 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); 116 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); 117 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); 118 119 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU); 120 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU); 121 122 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY); 123 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY); 124 125 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV); 126 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV); 127 128 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI); 129 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME); 130 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO); 131 I915_WRITE(PIPE_CSC_MODE(pipe), 0); 132 } 133 134 /* Set up the pipe CSC unit. */ 135 static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) 136 { 137 struct drm_crtc *crtc = crtc_state->crtc; 138 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 140 int i, pipe = intel_crtc->pipe; 141 uint16_t coeffs[9] = { 0, }; 142 struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state); 143 144 if (intel_crtc_state->ycbcr420) { 145 i9xx_load_ycbcr_conversion_matrix(intel_crtc); 146 return; 147 } else if (crtc_state->ctm) { 148 struct drm_color_ctm *ctm = 149 (struct drm_color_ctm *)crtc_state->ctm->data; 150 uint64_t input[9] = { 0, }; 151 152 if (intel_crtc_state->limited_color_range) { 153 ctm_mult_by_limited(input, (int64_t *)ctm->matrix); 154 } else { 155 for (i = 0; i < ARRAY_SIZE(input); i++) 156 input[i] = ctm->matrix[i]; 157 } 158 159 /* 160 * Convert fixed point S31.32 input to format supported by the 161 * hardware. 162 */ 163 for (i = 0; i < ARRAY_SIZE(coeffs); i++) { 164 uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i]; 165 166 /* 167 * Clamp input value to min/max supported by 168 * hardware. 169 */ 170 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); 171 172 /* sign bit */ 173 if (CTM_COEFF_NEGATIVE(input[i])) 174 coeffs[i] |= 1 << 15; 175 176 if (abs_coeff < CTM_COEFF_0_125) 177 coeffs[i] |= (3 << 12) | 178 I9XX_CSC_COEFF_FP(abs_coeff, 12); 179 else if (abs_coeff < CTM_COEFF_0_25) 180 coeffs[i] |= (2 << 12) | 181 I9XX_CSC_COEFF_FP(abs_coeff, 11); 182 else if (abs_coeff < CTM_COEFF_0_5) 183 coeffs[i] |= (1 << 12) | 184 I9XX_CSC_COEFF_FP(abs_coeff, 10); 185 else if (abs_coeff < CTM_COEFF_1_0) 186 coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9); 187 else if (abs_coeff < CTM_COEFF_2_0) 188 coeffs[i] |= (7 << 12) | 189 I9XX_CSC_COEFF_FP(abs_coeff, 8); 190 else 191 coeffs[i] |= (6 << 12) | 192 I9XX_CSC_COEFF_FP(abs_coeff, 7); 193 } 194 } else { 195 /* 196 * Load an identity matrix if no coefficients are provided. 197 * 198 * TODO: Check what kind of values actually come out of the 199 * pipe with these coeff/postoff values and adjust to get the 200 * best accuracy. Perhaps we even need to take the bpc value 201 * into consideration. 202 */ 203 for (i = 0; i < 3; i++) { 204 if (intel_crtc_state->limited_color_range) 205 coeffs[i * 3 + i] = 206 I9XX_CSC_COEFF_LIMITED_RANGE; 207 else 208 coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0; 209 } 210 } 211 212 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]); 213 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16); 214 215 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]); 216 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16); 217 218 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]); 219 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16); 220 221 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); 222 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); 223 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); 224 225 if (INTEL_GEN(dev_priv) > 6) { 226 uint16_t postoff = 0; 227 228 if (intel_crtc_state->limited_color_range) 229 postoff = (16 * (1 << 12) / 255) & 0x1fff; 230 231 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); 232 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); 233 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); 234 235 I915_WRITE(PIPE_CSC_MODE(pipe), 0); 236 } else { 237 uint32_t mode = CSC_MODE_YUV_TO_RGB; 238 239 if (intel_crtc_state->limited_color_range) 240 mode |= CSC_BLACK_SCREEN_OFFSET; 241 242 I915_WRITE(PIPE_CSC_MODE(pipe), mode); 243 } 244 } 245 246 /* 247 * Set up the pipe CSC unit on CherryView. 248 */ 249 static void cherryview_load_csc_matrix(struct drm_crtc_state *state) 250 { 251 struct drm_crtc *crtc = state->crtc; 252 struct drm_device *dev = crtc->dev; 253 struct drm_i915_private *dev_priv = to_i915(dev); 254 int pipe = to_intel_crtc(crtc)->pipe; 255 uint32_t mode; 256 257 if (state->ctm) { 258 struct drm_color_ctm *ctm = 259 (struct drm_color_ctm *) state->ctm->data; 260 uint16_t coeffs[9] = { 0, }; 261 int i; 262 263 for (i = 0; i < ARRAY_SIZE(coeffs); i++) { 264 uint64_t abs_coeff = 265 ((1ULL << 63) - 1) & ctm->matrix[i]; 266 267 /* Round coefficient. */ 268 abs_coeff += 1 << (32 - 13); 269 /* Clamp to hardware limits. */ 270 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); 271 272 /* Write coefficients in S3.12 format. */ 273 if (ctm->matrix[i] & (1ULL << 63)) 274 coeffs[i] = 1 << 15; 275 coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; 276 coeffs[i] |= (abs_coeff >> 20) & 0xfff; 277 } 278 279 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), 280 coeffs[1] << 16 | coeffs[0]); 281 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), 282 coeffs[3] << 16 | coeffs[2]); 283 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), 284 coeffs[5] << 16 | coeffs[4]); 285 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), 286 coeffs[7] << 16 | coeffs[6]); 287 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]); 288 } 289 290 mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0); 291 if (!crtc_state_is_legacy_gamma(state)) { 292 mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | 293 (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0); 294 } 295 I915_WRITE(CGM_PIPE_MODE(pipe), mode); 296 } 297 298 void intel_color_set_csc(struct drm_crtc_state *crtc_state) 299 { 300 struct drm_device *dev = crtc_state->crtc->dev; 301 struct drm_i915_private *dev_priv = to_i915(dev); 302 303 if (dev_priv->display.load_csc_matrix) 304 dev_priv->display.load_csc_matrix(crtc_state); 305 } 306 307 /* Loads the legacy palette/gamma unit for the CRTC. */ 308 static void i9xx_load_luts_internal(struct drm_crtc *crtc, 309 struct drm_property_blob *blob, 310 struct intel_crtc_state *crtc_state) 311 { 312 struct drm_device *dev = crtc->dev; 313 struct drm_i915_private *dev_priv = to_i915(dev); 314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 315 enum i915_pipe pipe = intel_crtc->pipe; 316 int i; 317 318 if (HAS_GMCH_DISPLAY(dev_priv)) { 319 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 320 assert_dsi_pll_enabled(dev_priv); 321 else 322 assert_pll_enabled(dev_priv, pipe); 323 } 324 325 if (blob) { 326 struct drm_color_lut *lut = (struct drm_color_lut *) blob->data; 327 for (i = 0; i < 256; i++) { 328 uint32_t word = 329 (drm_color_lut_extract(lut[i].red, 8) << 16) | 330 (drm_color_lut_extract(lut[i].green, 8) << 8) | 331 drm_color_lut_extract(lut[i].blue, 8); 332 333 if (HAS_GMCH_DISPLAY(dev_priv)) 334 I915_WRITE(PALETTE(pipe, i), word); 335 else 336 I915_WRITE(LGC_PALETTE(pipe, i), word); 337 } 338 } else { 339 for (i = 0; i < 256; i++) { 340 uint32_t word = (i << 16) | (i << 8) | i; 341 342 if (HAS_GMCH_DISPLAY(dev_priv)) 343 I915_WRITE(PALETTE(pipe, i), word); 344 else 345 I915_WRITE(LGC_PALETTE(pipe, i), word); 346 } 347 } 348 } 349 350 static void i9xx_load_luts(struct drm_crtc_state *crtc_state) 351 { 352 i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut, 353 to_intel_crtc_state(crtc_state)); 354 } 355 356 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */ 357 static void haswell_load_luts(struct drm_crtc_state *crtc_state) 358 { 359 struct drm_crtc *crtc = crtc_state->crtc; 360 struct drm_device *dev = crtc->dev; 361 struct drm_i915_private *dev_priv = to_i915(dev); 362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 363 struct intel_crtc_state *intel_crtc_state = 364 to_intel_crtc_state(crtc_state); 365 bool reenable_ips = false; 366 367 /* 368 * Workaround : Do not read or write the pipe palette/gamma data while 369 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. 370 */ 371 if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled && 372 (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) { 373 hsw_disable_ips(intel_crtc); 374 reenable_ips = true; 375 } 376 377 intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; 378 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); 379 380 i9xx_load_luts(crtc_state); 381 382 if (reenable_ips) 383 hsw_enable_ips(intel_crtc); 384 } 385 386 static void bdw_load_degamma_lut(struct drm_crtc_state *state) 387 { 388 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); 389 enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe; 390 uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 391 392 I915_WRITE(PREC_PAL_INDEX(pipe), 393 PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT); 394 395 if (state->degamma_lut) { 396 struct drm_color_lut *lut = 397 (struct drm_color_lut *) state->degamma_lut->data; 398 399 for (i = 0; i < lut_size; i++) { 400 uint32_t word = 401 drm_color_lut_extract(lut[i].red, 10) << 20 | 402 drm_color_lut_extract(lut[i].green, 10) << 10 | 403 drm_color_lut_extract(lut[i].blue, 10); 404 405 I915_WRITE(PREC_PAL_DATA(pipe), word); 406 } 407 } else { 408 for (i = 0; i < lut_size; i++) { 409 uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); 410 411 I915_WRITE(PREC_PAL_DATA(pipe), 412 (v << 20) | (v << 10) | v); 413 } 414 } 415 } 416 417 static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset) 418 { 419 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); 420 enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe; 421 uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 422 423 WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK); 424 425 I915_WRITE(PREC_PAL_INDEX(pipe), 426 (offset ? PAL_PREC_SPLIT_MODE : 0) | 427 PAL_PREC_AUTO_INCREMENT | 428 offset); 429 430 if (state->gamma_lut) { 431 struct drm_color_lut *lut = 432 (struct drm_color_lut *) state->gamma_lut->data; 433 434 for (i = 0; i < lut_size; i++) { 435 uint32_t word = 436 (drm_color_lut_extract(lut[i].red, 10) << 20) | 437 (drm_color_lut_extract(lut[i].green, 10) << 10) | 438 drm_color_lut_extract(lut[i].blue, 10); 439 440 I915_WRITE(PREC_PAL_DATA(pipe), word); 441 } 442 443 /* Program the max register to clamp values > 1.0. */ 444 i = lut_size - 1; 445 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), 446 drm_color_lut_extract(lut[i].red, 16)); 447 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), 448 drm_color_lut_extract(lut[i].green, 16)); 449 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), 450 drm_color_lut_extract(lut[i].blue, 16)); 451 } else { 452 for (i = 0; i < lut_size; i++) { 453 uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); 454 455 I915_WRITE(PREC_PAL_DATA(pipe), 456 (v << 20) | (v << 10) | v); 457 } 458 459 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1); 460 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1); 461 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1); 462 } 463 } 464 465 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */ 466 static void broadwell_load_luts(struct drm_crtc_state *state) 467 { 468 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); 469 struct intel_crtc_state *intel_state = to_intel_crtc_state(state); 470 enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe; 471 472 if (crtc_state_is_legacy_gamma(state)) { 473 haswell_load_luts(state); 474 return; 475 } 476 477 bdw_load_degamma_lut(state); 478 bdw_load_gamma_lut(state, 479 INTEL_INFO(dev_priv)->color.degamma_lut_size); 480 481 intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; 482 I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT); 483 POSTING_READ(GAMMA_MODE(pipe)); 484 485 /* 486 * Reset the index, otherwise it prevents the legacy palette to be 487 * written properly. 488 */ 489 I915_WRITE(PREC_PAL_INDEX(pipe), 0); 490 } 491 492 static void glk_load_degamma_lut(struct drm_crtc_state *state) 493 { 494 struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); 495 enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe; 496 const uint32_t lut_size = 33; 497 uint32_t i; 498 499 /* 500 * When setting the auto-increment bit, the hardware seems to 501 * ignore the index bits, so we need to reset it to index 0 502 * separately. 503 */ 504 I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0); 505 I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT); 506 507 /* 508 * FIXME: The pipe degamma table in geminilake doesn't support 509 * different values per channel, so this just loads a linear table. 510 */ 511 for (i = 0; i < lut_size; i++) { 512 uint32_t v = (i * (1 << 16)) / (lut_size - 1); 513 514 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v); 515 } 516 517 /* Clamp values > 1.0. */ 518 while (i++ < 35) 519 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); 520 } 521 522 static void glk_load_luts(struct drm_crtc_state *state) 523 { 524 struct drm_crtc *crtc = state->crtc; 525 struct drm_device *dev = crtc->dev; 526 struct drm_i915_private *dev_priv = to_i915(dev); 527 struct intel_crtc_state *intel_state = to_intel_crtc_state(state); 528 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 529 530 glk_load_degamma_lut(state); 531 532 if (crtc_state_is_legacy_gamma(state)) { 533 haswell_load_luts(state); 534 return; 535 } 536 537 bdw_load_gamma_lut(state, 0); 538 539 intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT; 540 I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT); 541 POSTING_READ(GAMMA_MODE(pipe)); 542 } 543 544 /* Loads the palette/gamma unit for the CRTC on CherryView. */ 545 static void cherryview_load_luts(struct drm_crtc_state *state) 546 { 547 struct drm_crtc *crtc = state->crtc; 548 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 549 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 550 struct drm_color_lut *lut; 551 uint32_t i, lut_size; 552 uint32_t word0, word1; 553 554 if (crtc_state_is_legacy_gamma(state)) { 555 /* Turn off degamma/gamma on CGM block. */ 556 I915_WRITE(CGM_PIPE_MODE(pipe), 557 (state->ctm ? CGM_PIPE_MODE_CSC : 0)); 558 i9xx_load_luts_internal(crtc, state->gamma_lut, 559 to_intel_crtc_state(state)); 560 return; 561 } 562 563 if (state->degamma_lut) { 564 lut = (struct drm_color_lut *) state->degamma_lut->data; 565 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; 566 for (i = 0; i < lut_size; i++) { 567 /* Write LUT in U0.14 format. */ 568 word0 = 569 (drm_color_lut_extract(lut[i].green, 14) << 16) | 570 drm_color_lut_extract(lut[i].blue, 14); 571 word1 = drm_color_lut_extract(lut[i].red, 14); 572 573 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0); 574 I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1); 575 } 576 } 577 578 if (state->gamma_lut) { 579 lut = (struct drm_color_lut *) state->gamma_lut->data; 580 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; 581 for (i = 0; i < lut_size; i++) { 582 /* Write LUT in U0.10 format. */ 583 word0 = 584 (drm_color_lut_extract(lut[i].green, 10) << 16) | 585 drm_color_lut_extract(lut[i].blue, 10); 586 word1 = drm_color_lut_extract(lut[i].red, 10); 587 588 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0); 589 I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1); 590 } 591 } 592 593 I915_WRITE(CGM_PIPE_MODE(pipe), 594 (state->ctm ? CGM_PIPE_MODE_CSC : 0) | 595 (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) | 596 (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0)); 597 598 /* 599 * Also program a linear LUT in the legacy block (behind the 600 * CGM block). 601 */ 602 i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state)); 603 } 604 605 void intel_color_load_luts(struct drm_crtc_state *crtc_state) 606 { 607 struct drm_device *dev = crtc_state->crtc->dev; 608 struct drm_i915_private *dev_priv = to_i915(dev); 609 610 dev_priv->display.load_luts(crtc_state); 611 } 612 613 int intel_color_check(struct drm_crtc *crtc, 614 struct drm_crtc_state *crtc_state) 615 { 616 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 617 size_t gamma_length, degamma_length; 618 619 degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size * 620 sizeof(struct drm_color_lut); 621 gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size * 622 sizeof(struct drm_color_lut); 623 624 /* 625 * We allow both degamma & gamma luts at the right size or 626 * NULL. 627 */ 628 if ((!crtc_state->degamma_lut || 629 crtc_state->degamma_lut->length == degamma_length) && 630 (!crtc_state->gamma_lut || 631 crtc_state->gamma_lut->length == gamma_length)) 632 return 0; 633 634 /* 635 * We also allow no degamma lut/ctm and a gamma lut at the legacy 636 * size (256 entries). 637 */ 638 if (crtc_state_is_legacy_gamma(crtc_state)) 639 return 0; 640 641 return -EINVAL; 642 } 643 644 void intel_color_init(struct drm_crtc *crtc) 645 { 646 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 647 648 drm_mode_crtc_set_gamma_size(crtc, 256); 649 650 if (IS_CHERRYVIEW(dev_priv)) { 651 dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix; 652 dev_priv->display.load_luts = cherryview_load_luts; 653 } else if (IS_HASWELL(dev_priv)) { 654 dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; 655 dev_priv->display.load_luts = haswell_load_luts; 656 } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || 657 IS_BROXTON(dev_priv)) { 658 dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; 659 dev_priv->display.load_luts = broadwell_load_luts; 660 } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { 661 dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix; 662 dev_priv->display.load_luts = glk_load_luts; 663 } else { 664 dev_priv->display.load_luts = i9xx_load_luts; 665 } 666 667 /* Enable color management support when we have degamma & gamma LUTs. */ 668 if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && 669 INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) 670 drm_crtc_enable_color_mgmt(crtc, 671 INTEL_INFO(dev_priv)->color.degamma_lut_size, 672 true, 673 INTEL_INFO(dev_priv)->color.gamma_lut_size); 674 } 675