1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 /* Here's the desired hotplug mode */ 39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 44 ADPA_CRT_HOTPLUG_ENABLE) 45 46 struct intel_crt { 47 struct intel_encoder base; 48 /* DPMS state is stored in the connector, which we need in the 49 * encoder's enable/disable callbacks */ 50 struct intel_connector *connector; 51 bool force_hotplug_required; 52 u32 adpa_reg; 53 }; 54 55 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 56 { 57 return container_of(encoder, struct intel_crt, base); 58 } 59 60 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 61 { 62 return intel_encoder_to_crt(intel_attached_encoder(connector)); 63 } 64 65 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 66 enum i915_pipe *pipe) 67 { 68 struct drm_device *dev = encoder->base.dev; 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 struct intel_crt *crt = intel_encoder_to_crt(encoder); 71 enum intel_display_power_domain power_domain; 72 u32 tmp; 73 74 power_domain = intel_display_port_power_domain(encoder); 75 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 76 return false; 77 78 tmp = I915_READ(crt->adpa_reg); 79 80 if (!(tmp & ADPA_DAC_ENABLE)) 81 return false; 82 83 if (HAS_PCH_CPT(dev)) 84 *pipe = PORT_TO_PIPE_CPT(tmp); 85 else 86 *pipe = PORT_TO_PIPE(tmp); 87 88 return true; 89 } 90 91 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 92 { 93 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 94 struct intel_crt *crt = intel_encoder_to_crt(encoder); 95 u32 tmp, flags = 0; 96 97 tmp = I915_READ(crt->adpa_reg); 98 99 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 100 flags |= DRM_MODE_FLAG_PHSYNC; 101 else 102 flags |= DRM_MODE_FLAG_NHSYNC; 103 104 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 105 flags |= DRM_MODE_FLAG_PVSYNC; 106 else 107 flags |= DRM_MODE_FLAG_NVSYNC; 108 109 return flags; 110 } 111 112 static void intel_crt_get_config(struct intel_encoder *encoder, 113 struct intel_crtc_state *pipe_config) 114 { 115 struct drm_device *dev = encoder->base.dev; 116 int dotclock; 117 118 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 119 120 dotclock = pipe_config->port_clock; 121 122 if (HAS_PCH_SPLIT(dev)) 123 ironlake_check_encoder_dotclock(pipe_config, dotclock); 124 125 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 126 } 127 128 static void hsw_crt_get_config(struct intel_encoder *encoder, 129 struct intel_crtc_state *pipe_config) 130 { 131 intel_ddi_get_config(encoder, pipe_config); 132 133 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 134 DRM_MODE_FLAG_NHSYNC | 135 DRM_MODE_FLAG_PVSYNC | 136 DRM_MODE_FLAG_NVSYNC); 137 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 138 } 139 140 static void hsw_crt_pre_enable(struct intel_encoder *encoder) 141 { 142 struct drm_device *dev = encoder->base.dev; 143 struct drm_i915_private *dev_priv = dev->dev_private; 144 145 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); 146 I915_WRITE(SPLL_CTL, 147 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); 148 POSTING_READ(SPLL_CTL); 149 udelay(20); 150 } 151 152 /* Note: The caller is required to filter out dpms modes not supported by the 153 * platform. */ 154 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 155 { 156 struct drm_device *dev = encoder->base.dev; 157 struct drm_i915_private *dev_priv = dev->dev_private; 158 struct intel_crt *crt = intel_encoder_to_crt(encoder); 159 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 160 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 161 u32 adpa; 162 163 if (INTEL_INFO(dev)->gen >= 5) 164 adpa = ADPA_HOTPLUG_BITS; 165 else 166 adpa = 0; 167 168 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 169 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 170 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 171 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 172 173 /* For CPT allow 3 pipe config, for others just use A or B */ 174 if (HAS_PCH_LPT(dev)) 175 ; /* Those bits don't exist here */ 176 else if (HAS_PCH_CPT(dev)) 177 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 178 else if (crtc->pipe == 0) 179 adpa |= ADPA_PIPE_A_SELECT; 180 else 181 adpa |= ADPA_PIPE_B_SELECT; 182 183 if (!HAS_PCH_SPLIT(dev)) 184 I915_WRITE(BCLRPAT(crtc->pipe), 0); 185 186 switch (mode) { 187 case DRM_MODE_DPMS_ON: 188 adpa |= ADPA_DAC_ENABLE; 189 break; 190 case DRM_MODE_DPMS_STANDBY: 191 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 192 break; 193 case DRM_MODE_DPMS_SUSPEND: 194 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 195 break; 196 case DRM_MODE_DPMS_OFF: 197 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 198 break; 199 } 200 201 I915_WRITE(crt->adpa_reg, adpa); 202 } 203 204 static void intel_disable_crt(struct intel_encoder *encoder) 205 { 206 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 207 } 208 209 210 static void hsw_crt_post_disable(struct intel_encoder *encoder) 211 { 212 struct drm_device *dev = encoder->base.dev; 213 struct drm_i915_private *dev_priv = dev->dev_private; 214 uint32_t val; 215 216 DRM_DEBUG_KMS("Disabling SPLL\n"); 217 val = I915_READ(SPLL_CTL); 218 WARN_ON(!(val & SPLL_PLL_ENABLE)); 219 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 220 POSTING_READ(SPLL_CTL); 221 } 222 223 static void intel_enable_crt(struct intel_encoder *encoder) 224 { 225 struct intel_crt *crt = intel_encoder_to_crt(encoder); 226 227 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 228 } 229 230 /* Special dpms function to support cloning between dvo/sdvo/crt. */ 231 static void intel_crt_dpms(struct drm_connector *connector, int mode) 232 { 233 struct drm_device *dev = connector->dev; 234 struct intel_encoder *encoder = intel_attached_encoder(connector); 235 struct drm_crtc *crtc; 236 int old_dpms; 237 238 /* PCH platforms and VLV only support on/off. */ 239 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) 240 mode = DRM_MODE_DPMS_OFF; 241 242 if (mode == connector->dpms) 243 return; 244 245 old_dpms = connector->dpms; 246 connector->dpms = mode; 247 248 /* Only need to change hw state when actually enabled */ 249 crtc = encoder->base.crtc; 250 if (!crtc) { 251 encoder->connectors_active = false; 252 return; 253 } 254 255 /* We need the pipe to run for anything but OFF. */ 256 if (mode == DRM_MODE_DPMS_OFF) 257 encoder->connectors_active = false; 258 else 259 encoder->connectors_active = true; 260 261 /* We call connector dpms manually below in case pipe dpms doesn't 262 * change due to cloning. */ 263 if (mode < old_dpms) { 264 /* From off to on, enable the pipe first. */ 265 intel_crtc_update_dpms(crtc); 266 267 intel_crt_set_dpms(encoder, mode); 268 } else { 269 intel_crt_set_dpms(encoder, mode); 270 271 intel_crtc_update_dpms(crtc); 272 } 273 274 intel_modeset_check_state(connector->dev); 275 } 276 277 static enum drm_mode_status 278 intel_crt_mode_valid(struct drm_connector *connector, 279 struct drm_display_mode *mode) 280 { 281 struct drm_device *dev = connector->dev; 282 283 int max_clock = 0; 284 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 285 return MODE_NO_DBLESCAN; 286 287 if (mode->clock < 25000) 288 return MODE_CLOCK_LOW; 289 290 if (IS_GEN2(dev)) 291 max_clock = 350000; 292 else 293 max_clock = 400000; 294 if (mode->clock > max_clock) 295 return MODE_CLOCK_HIGH; 296 297 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 298 if (HAS_PCH_LPT(dev) && 299 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 300 return MODE_CLOCK_HIGH; 301 302 return MODE_OK; 303 } 304 305 static bool intel_crt_compute_config(struct intel_encoder *encoder, 306 struct intel_crtc_state *pipe_config) 307 { 308 struct drm_device *dev = encoder->base.dev; 309 310 if (HAS_PCH_SPLIT(dev)) 311 pipe_config->has_pch_encoder = true; 312 313 /* LPT FDI RX only supports 8bpc. */ 314 if (HAS_PCH_LPT(dev)) 315 pipe_config->pipe_bpp = 24; 316 317 /* FDI must always be 2.7 GHz */ 318 if (HAS_DDI(dev)) { 319 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 320 pipe_config->port_clock = 135000 * 2; 321 } 322 323 return true; 324 } 325 326 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 327 { 328 struct drm_device *dev = connector->dev; 329 struct intel_crt *crt = intel_attached_crt(connector); 330 struct drm_i915_private *dev_priv = dev->dev_private; 331 u32 adpa; 332 bool ret; 333 334 /* The first time through, trigger an explicit detection cycle */ 335 if (crt->force_hotplug_required) { 336 bool turn_off_dac = HAS_PCH_SPLIT(dev); 337 u32 save_adpa; 338 339 crt->force_hotplug_required = 0; 340 341 save_adpa = adpa = I915_READ(crt->adpa_reg); 342 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 343 344 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 345 if (turn_off_dac) 346 adpa &= ~ADPA_DAC_ENABLE; 347 348 I915_WRITE(crt->adpa_reg, adpa); 349 350 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 351 1000)) 352 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 353 354 if (turn_off_dac) { 355 I915_WRITE(crt->adpa_reg, save_adpa); 356 POSTING_READ(crt->adpa_reg); 357 } 358 } 359 360 /* Check the status to see if both blue and green are on now */ 361 adpa = I915_READ(crt->adpa_reg); 362 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 363 ret = true; 364 else 365 ret = false; 366 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 367 368 return ret; 369 } 370 371 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 372 { 373 struct drm_device *dev = connector->dev; 374 struct intel_crt *crt = intel_attached_crt(connector); 375 struct drm_i915_private *dev_priv = dev->dev_private; 376 u32 adpa; 377 bool ret; 378 u32 save_adpa; 379 380 save_adpa = adpa = I915_READ(crt->adpa_reg); 381 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 382 383 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 384 385 I915_WRITE(crt->adpa_reg, adpa); 386 387 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 388 1000)) { 389 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 390 I915_WRITE(crt->adpa_reg, save_adpa); 391 } 392 393 /* Check the status to see if both blue and green are on now */ 394 adpa = I915_READ(crt->adpa_reg); 395 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 396 ret = true; 397 else 398 ret = false; 399 400 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 401 402 return ret; 403 } 404 405 /** 406 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 407 * 408 * Not for i915G/i915GM 409 * 410 * \return true if CRT is connected. 411 * \return false if CRT is disconnected. 412 */ 413 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 414 { 415 struct drm_device *dev = connector->dev; 416 struct drm_i915_private *dev_priv = dev->dev_private; 417 u32 hotplug_en, orig, stat; 418 bool ret = false; 419 int i, tries = 0; 420 421 if (HAS_PCH_SPLIT(dev)) 422 return intel_ironlake_crt_detect_hotplug(connector); 423 424 if (IS_VALLEYVIEW(dev)) 425 return valleyview_crt_detect_hotplug(connector); 426 427 /* 428 * On 4 series desktop, CRT detect sequence need to be done twice 429 * to get a reliable result. 430 */ 431 432 if (IS_G4X(dev) && !IS_GM45(dev)) 433 tries = 2; 434 else 435 tries = 1; 436 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 437 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 438 439 for (i = 0; i < tries ; i++) { 440 /* turn on the FORCE_DETECT */ 441 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 442 /* wait for FORCE_DETECT to go off */ 443 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 444 CRT_HOTPLUG_FORCE_DETECT) == 0, 445 1000)) 446 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 447 } 448 449 stat = I915_READ(PORT_HOTPLUG_STAT); 450 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 451 ret = true; 452 453 /* clear the interrupt we just generated, if any */ 454 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 455 456 /* and put the bits back */ 457 I915_WRITE(PORT_HOTPLUG_EN, orig); 458 459 return ret; 460 } 461 462 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 463 struct i2c_adapter *i2c) 464 { 465 struct edid *edid; 466 467 edid = drm_get_edid(connector, i2c); 468 469 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 470 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 471 intel_gmbus_force_bit(i2c, true); 472 edid = drm_get_edid(connector, i2c); 473 intel_gmbus_force_bit(i2c, false); 474 } 475 476 return edid; 477 } 478 479 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 480 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 481 struct i2c_adapter *adapter) 482 { 483 struct edid *edid; 484 int ret; 485 486 edid = intel_crt_get_edid(connector, adapter); 487 if (!edid) 488 return 0; 489 490 ret = intel_connector_update_modes(connector, edid); 491 kfree(edid); 492 493 return ret; 494 } 495 496 static bool intel_crt_detect_ddc(struct drm_connector *connector) 497 { 498 struct intel_crt *crt = intel_attached_crt(connector); 499 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 500 struct edid *edid; 501 struct i2c_adapter *i2c; 502 503 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 504 505 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 506 edid = intel_crt_get_edid(connector, i2c); 507 508 if (edid) { 509 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 510 511 /* 512 * This may be a DVI-I connector with a shared DDC 513 * link between analog and digital outputs, so we 514 * have to check the EDID input spec of the attached device. 515 */ 516 if (!is_digital) { 517 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 518 return true; 519 } 520 521 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 522 } else { 523 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 524 } 525 526 kfree(edid); 527 528 return false; 529 } 530 531 static enum drm_connector_status 532 intel_crt_load_detect(struct intel_crt *crt) 533 { 534 struct drm_device *dev = crt->base.base.dev; 535 struct drm_i915_private *dev_priv = dev->dev_private; 536 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 537 uint32_t save_bclrpat; 538 uint32_t save_vtotal; 539 uint32_t vtotal, vactive; 540 uint32_t vsample; 541 uint32_t vblank, vblank_start, vblank_end; 542 uint32_t dsl; 543 uint32_t bclrpat_reg; 544 uint32_t vtotal_reg; 545 uint32_t vblank_reg; 546 uint32_t vsync_reg; 547 uint32_t pipeconf_reg; 548 uint32_t pipe_dsl_reg; 549 uint8_t st00; 550 enum drm_connector_status status; 551 552 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 553 554 bclrpat_reg = BCLRPAT(pipe); 555 vtotal_reg = VTOTAL(pipe); 556 vblank_reg = VBLANK(pipe); 557 vsync_reg = VSYNC(pipe); 558 pipeconf_reg = PIPECONF(pipe); 559 pipe_dsl_reg = PIPEDSL(pipe); 560 561 save_bclrpat = I915_READ(bclrpat_reg); 562 save_vtotal = I915_READ(vtotal_reg); 563 vblank = I915_READ(vblank_reg); 564 565 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 566 vactive = (save_vtotal & 0x7ff) + 1; 567 568 vblank_start = (vblank & 0xfff) + 1; 569 vblank_end = ((vblank >> 16) & 0xfff) + 1; 570 571 /* Set the border color to purple. */ 572 I915_WRITE(bclrpat_reg, 0x500050); 573 574 if (!IS_GEN2(dev)) { 575 uint32_t pipeconf = I915_READ(pipeconf_reg); 576 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 577 POSTING_READ(pipeconf_reg); 578 /* Wait for next Vblank to substitue 579 * border color for Color info */ 580 intel_wait_for_vblank(dev, pipe); 581 st00 = I915_READ8(VGA_MSR_WRITE); 582 status = ((st00 & (1 << 4)) != 0) ? 583 connector_status_connected : 584 connector_status_disconnected; 585 586 I915_WRITE(pipeconf_reg, pipeconf); 587 } else { 588 bool restore_vblank = false; 589 int count, detect; 590 591 /* 592 * If there isn't any border, add some. 593 * Yes, this will flicker 594 */ 595 if (vblank_start <= vactive && vblank_end >= vtotal) { 596 uint32_t vsync = I915_READ(vsync_reg); 597 uint32_t vsync_start = (vsync & 0xffff) + 1; 598 599 vblank_start = vsync_start; 600 I915_WRITE(vblank_reg, 601 (vblank_start - 1) | 602 ((vblank_end - 1) << 16)); 603 restore_vblank = true; 604 } 605 /* sample in the vertical border, selecting the larger one */ 606 if (vblank_start - vactive >= vtotal - vblank_end) 607 vsample = (vblank_start + vactive) >> 1; 608 else 609 vsample = (vtotal + vblank_end) >> 1; 610 611 /* 612 * Wait for the border to be displayed 613 */ 614 while (I915_READ(pipe_dsl_reg) >= vactive) 615 ; 616 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 617 ; 618 /* 619 * Watch ST00 for an entire scanline 620 */ 621 detect = 0; 622 count = 0; 623 do { 624 count++; 625 /* Read the ST00 VGA status register */ 626 st00 = I915_READ8(VGA_MSR_WRITE); 627 if (st00 & (1 << 4)) 628 detect++; 629 } while ((I915_READ(pipe_dsl_reg) == dsl)); 630 631 /* restore vblank if necessary */ 632 if (restore_vblank) 633 I915_WRITE(vblank_reg, vblank); 634 /* 635 * If more than 3/4 of the scanline detected a monitor, 636 * then it is assumed to be present. This works even on i830, 637 * where there isn't any way to force the border color across 638 * the screen 639 */ 640 status = detect * 4 > count * 3 ? 641 connector_status_connected : 642 connector_status_disconnected; 643 } 644 645 /* Restore previous settings */ 646 I915_WRITE(bclrpat_reg, save_bclrpat); 647 648 return status; 649 } 650 651 static enum drm_connector_status 652 intel_crt_detect(struct drm_connector *connector, bool force) 653 { 654 struct drm_device *dev = connector->dev; 655 struct drm_i915_private *dev_priv = dev->dev_private; 656 struct intel_crt *crt = intel_attached_crt(connector); 657 struct intel_encoder *intel_encoder = &crt->base; 658 enum intel_display_power_domain power_domain; 659 enum drm_connector_status status; 660 struct intel_load_detect_pipe tmp; 661 struct drm_modeset_acquire_ctx ctx; 662 663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 664 connector->base.id, connector->name, 665 force); 666 667 power_domain = intel_display_port_power_domain(intel_encoder); 668 intel_display_power_get(dev_priv, power_domain); 669 670 if (I915_HAS_HOTPLUG(dev)) { 671 /* We can not rely on the HPD pin always being correctly wired 672 * up, for example many KVM do not pass it through, and so 673 * only trust an assertion that the monitor is connected. 674 */ 675 if (intel_crt_detect_hotplug(connector)) { 676 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 677 status = connector_status_connected; 678 goto out; 679 } else 680 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 681 } 682 683 if (intel_crt_detect_ddc(connector)) { 684 status = connector_status_connected; 685 goto out; 686 } 687 688 /* Load detection is broken on HPD capable machines. Whoever wants a 689 * broken monitor (without edid) to work behind a broken kvm (that fails 690 * to have the right resistors for HP detection) needs to fix this up. 691 * For now just bail out. */ 692 if (I915_HAS_HOTPLUG(dev)) { 693 status = connector_status_disconnected; 694 goto out; 695 } 696 697 if (!force) { 698 status = connector->status; 699 goto out; 700 } 701 702 drm_modeset_acquire_init(&ctx, 0); 703 704 /* for pre-945g platforms use load detect */ 705 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 706 if (intel_crt_detect_ddc(connector)) 707 status = connector_status_connected; 708 else 709 status = intel_crt_load_detect(crt); 710 intel_release_load_detect_pipe(connector, &tmp); 711 } else 712 status = connector_status_unknown; 713 714 drm_modeset_drop_locks(&ctx); 715 drm_modeset_acquire_fini(&ctx); 716 717 out: 718 intel_display_power_put(dev_priv, power_domain); 719 return status; 720 } 721 722 static void intel_crt_destroy(struct drm_connector *connector) 723 { 724 drm_connector_cleanup(connector); 725 kfree(connector); 726 } 727 728 static int intel_crt_get_modes(struct drm_connector *connector) 729 { 730 struct drm_device *dev = connector->dev; 731 struct drm_i915_private *dev_priv = dev->dev_private; 732 struct intel_crt *crt = intel_attached_crt(connector); 733 struct intel_encoder *intel_encoder = &crt->base; 734 enum intel_display_power_domain power_domain; 735 int ret; 736 struct i2c_adapter *i2c; 737 738 power_domain = intel_display_port_power_domain(intel_encoder); 739 intel_display_power_get(dev_priv, power_domain); 740 741 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 742 ret = intel_crt_ddc_get_modes(connector, i2c); 743 if (ret || !IS_G4X(dev)) 744 goto out; 745 746 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 747 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); 748 ret = intel_crt_ddc_get_modes(connector, i2c); 749 750 out: 751 intel_display_power_put(dev_priv, power_domain); 752 753 return ret; 754 } 755 756 static int intel_crt_set_property(struct drm_connector *connector, 757 struct drm_property *property, 758 uint64_t value) 759 { 760 return 0; 761 } 762 763 static void intel_crt_reset(struct drm_connector *connector) 764 { 765 struct drm_device *dev = connector->dev; 766 struct drm_i915_private *dev_priv = dev->dev_private; 767 struct intel_crt *crt = intel_attached_crt(connector); 768 769 if (INTEL_INFO(dev)->gen >= 5) { 770 u32 adpa; 771 772 adpa = I915_READ(crt->adpa_reg); 773 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 774 adpa |= ADPA_HOTPLUG_BITS; 775 I915_WRITE(crt->adpa_reg, adpa); 776 POSTING_READ(crt->adpa_reg); 777 778 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 779 crt->force_hotplug_required = 1; 780 } 781 782 } 783 784 /* 785 * Routines for controlling stuff on the analog port 786 */ 787 788 static const struct drm_connector_funcs intel_crt_connector_funcs = { 789 .reset = intel_crt_reset, 790 .dpms = intel_crt_dpms, 791 .detect = intel_crt_detect, 792 .fill_modes = drm_helper_probe_single_connector_modes, 793 .destroy = intel_crt_destroy, 794 .set_property = intel_crt_set_property, 795 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 796 .atomic_get_property = intel_connector_atomic_get_property, 797 }; 798 799 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 800 .mode_valid = intel_crt_mode_valid, 801 .get_modes = intel_crt_get_modes, 802 .best_encoder = intel_best_encoder, 803 }; 804 805 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 806 .destroy = intel_encoder_destroy, 807 }; 808 809 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 810 { 811 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 812 return 1; 813 } 814 815 static const struct dmi_system_id intel_no_crt[] = { 816 { 817 .callback = intel_no_crt_dmi_callback, 818 .ident = "ACER ZGB", 819 .matches = { 820 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 821 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 822 }, 823 }, 824 { 825 .callback = intel_no_crt_dmi_callback, 826 .ident = "DELL XPS 8700", 827 .matches = { 828 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 829 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 830 }, 831 }, 832 { } 833 }; 834 835 void intel_crt_init(struct drm_device *dev) 836 { 837 struct drm_connector *connector; 838 struct intel_crt *crt; 839 struct intel_connector *intel_connector; 840 struct drm_i915_private *dev_priv = dev->dev_private; 841 842 /* Skip machines without VGA that falsely report hotplug events */ 843 if (dmi_check_system(intel_no_crt)) 844 return; 845 846 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 847 if (!crt) 848 return; 849 850 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 851 if (!intel_connector) { 852 kfree(crt); 853 return; 854 } 855 856 connector = &intel_connector->base; 857 crt->connector = intel_connector; 858 drm_connector_init(dev, &intel_connector->base, 859 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 860 861 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 862 DRM_MODE_ENCODER_DAC); 863 864 intel_connector_attach_encoder(intel_connector, &crt->base); 865 866 crt->base.type = INTEL_OUTPUT_ANALOG; 867 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 868 if (IS_I830(dev)) 869 crt->base.crtc_mask = (1 << 0); 870 else 871 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 872 873 if (IS_GEN2(dev)) 874 connector->interlace_allowed = 0; 875 else 876 connector->interlace_allowed = 1; 877 connector->doublescan_allowed = 0; 878 879 if (HAS_PCH_SPLIT(dev)) 880 crt->adpa_reg = PCH_ADPA; 881 else if (IS_VALLEYVIEW(dev)) 882 crt->adpa_reg = VLV_ADPA; 883 else 884 crt->adpa_reg = ADPA; 885 886 crt->base.compute_config = intel_crt_compute_config; 887 crt->base.disable = intel_disable_crt; 888 crt->base.enable = intel_enable_crt; 889 if (I915_HAS_HOTPLUG(dev)) 890 crt->base.hpd_pin = HPD_CRT; 891 if (HAS_DDI(dev)) { 892 crt->base.get_config = hsw_crt_get_config; 893 crt->base.get_hw_state = intel_ddi_get_hw_state; 894 crt->base.pre_enable = hsw_crt_pre_enable; 895 crt->base.post_disable = hsw_crt_post_disable; 896 } else { 897 crt->base.get_config = intel_crt_get_config; 898 crt->base.get_hw_state = intel_crt_get_hw_state; 899 } 900 intel_connector->get_hw_state = intel_connector_get_hw_state; 901 intel_connector->unregister = intel_connector_unregister; 902 903 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 904 905 drm_connector_register(connector); 906 907 if (!I915_HAS_HOTPLUG(dev)) 908 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 909 910 /* 911 * Configure the automatic hotplug detection stuff 912 */ 913 crt->force_hotplug_required = 0; 914 915 /* 916 * TODO: find a proper way to discover whether we need to set the the 917 * polarity and link reversal bits or not, instead of relying on the 918 * BIOS. 919 */ 920 if (HAS_PCH_LPT(dev)) { 921 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 922 FDI_RX_LINK_REVERSAL_OVERRIDE; 923 924 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; 925 } 926 927 intel_crt_reset(connector); 928 } 929