1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 39 /* Here's the desired hotplug mode */ 40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 45 ADPA_CRT_HOTPLUG_ENABLE) 46 47 struct intel_crt { 48 struct intel_encoder base; 49 /* DPMS state is stored in the connector, which we need in the 50 * encoder's enable/disable callbacks */ 51 struct intel_connector *connector; 52 bool force_hotplug_required; 53 i915_reg_t adpa_reg; 54 }; 55 56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 57 { 58 return container_of(encoder, struct intel_crt, base); 59 } 60 61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 62 { 63 return intel_encoder_to_crt(intel_attached_encoder(connector)); 64 } 65 66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 67 enum i915_pipe *pipe) 68 { 69 struct drm_device *dev = encoder->base.dev; 70 struct drm_i915_private *dev_priv = to_i915(dev); 71 struct intel_crt *crt = intel_encoder_to_crt(encoder); 72 u32 tmp; 73 bool ret; 74 75 if (!intel_display_power_get_if_enabled(dev_priv, 76 encoder->power_domain)) 77 return false; 78 79 ret = false; 80 81 tmp = I915_READ(crt->adpa_reg); 82 83 if (!(tmp & ADPA_DAC_ENABLE)) 84 goto out; 85 86 if (HAS_PCH_CPT(dev_priv)) 87 *pipe = PORT_TO_PIPE_CPT(tmp); 88 else 89 *pipe = PORT_TO_PIPE(tmp); 90 91 ret = true; 92 out: 93 intel_display_power_put(dev_priv, encoder->power_domain); 94 95 return ret; 96 } 97 98 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 99 { 100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 101 struct intel_crt *crt = intel_encoder_to_crt(encoder); 102 u32 tmp, flags = 0; 103 104 tmp = I915_READ(crt->adpa_reg); 105 106 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 107 flags |= DRM_MODE_FLAG_PHSYNC; 108 else 109 flags |= DRM_MODE_FLAG_NHSYNC; 110 111 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 112 flags |= DRM_MODE_FLAG_PVSYNC; 113 else 114 flags |= DRM_MODE_FLAG_NVSYNC; 115 116 return flags; 117 } 118 119 static void intel_crt_get_config(struct intel_encoder *encoder, 120 struct intel_crtc_state *pipe_config) 121 { 122 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 123 124 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 125 } 126 127 static void hsw_crt_get_config(struct intel_encoder *encoder, 128 struct intel_crtc_state *pipe_config) 129 { 130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 131 132 intel_ddi_get_config(encoder, pipe_config); 133 134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 135 DRM_MODE_FLAG_NHSYNC | 136 DRM_MODE_FLAG_PVSYNC | 137 DRM_MODE_FLAG_NVSYNC); 138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 139 140 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 141 } 142 143 /* Note: The caller is required to filter out dpms modes not supported by the 144 * platform. */ 145 static void intel_crt_set_dpms(struct intel_encoder *encoder, 146 struct intel_crtc_state *crtc_state, 147 int mode) 148 { 149 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 150 struct intel_crt *crt = intel_encoder_to_crt(encoder); 151 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 152 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 153 u32 adpa; 154 155 if (INTEL_GEN(dev_priv) >= 5) 156 adpa = ADPA_HOTPLUG_BITS; 157 else 158 adpa = 0; 159 160 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 161 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 162 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 163 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 164 165 /* For CPT allow 3 pipe config, for others just use A or B */ 166 if (HAS_PCH_LPT(dev_priv)) 167 ; /* Those bits don't exist here */ 168 else if (HAS_PCH_CPT(dev_priv)) 169 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 170 else if (crtc->pipe == 0) 171 adpa |= ADPA_PIPE_A_SELECT; 172 else 173 adpa |= ADPA_PIPE_B_SELECT; 174 175 if (!HAS_PCH_SPLIT(dev_priv)) 176 I915_WRITE(BCLRPAT(crtc->pipe), 0); 177 178 switch (mode) { 179 case DRM_MODE_DPMS_ON: 180 adpa |= ADPA_DAC_ENABLE; 181 break; 182 case DRM_MODE_DPMS_STANDBY: 183 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 184 break; 185 case DRM_MODE_DPMS_SUSPEND: 186 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 187 break; 188 case DRM_MODE_DPMS_OFF: 189 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 190 break; 191 } 192 193 I915_WRITE(crt->adpa_reg, adpa); 194 } 195 196 static void intel_disable_crt(struct intel_encoder *encoder, 197 struct intel_crtc_state *old_crtc_state, 198 struct drm_connector_state *old_conn_state) 199 { 200 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 201 } 202 203 static void pch_disable_crt(struct intel_encoder *encoder, 204 struct intel_crtc_state *old_crtc_state, 205 struct drm_connector_state *old_conn_state) 206 { 207 } 208 209 static void pch_post_disable_crt(struct intel_encoder *encoder, 210 struct intel_crtc_state *old_crtc_state, 211 struct drm_connector_state *old_conn_state) 212 { 213 intel_disable_crt(encoder, old_crtc_state, old_conn_state); 214 } 215 216 static void hsw_post_disable_crt(struct intel_encoder *encoder, 217 struct intel_crtc_state *old_crtc_state, 218 struct drm_connector_state *old_conn_state) 219 { 220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 221 222 pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); 223 224 lpt_disable_pch_transcoder(dev_priv); 225 lpt_disable_iclkip(dev_priv); 226 227 intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); 228 } 229 230 static void intel_enable_crt(struct intel_encoder *encoder, 231 struct intel_crtc_state *pipe_config, 232 struct drm_connector_state *conn_state) 233 { 234 intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON); 235 } 236 237 static enum drm_mode_status 238 intel_crt_mode_valid(struct drm_connector *connector, 239 struct drm_display_mode *mode) 240 { 241 struct drm_device *dev = connector->dev; 242 struct drm_i915_private *dev_priv = to_i915(dev); 243 int max_dotclk = dev_priv->max_dotclk_freq; 244 int max_clock; 245 246 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 247 return MODE_NO_DBLESCAN; 248 249 if (mode->clock < 25000) 250 return MODE_CLOCK_LOW; 251 252 if (HAS_PCH_LPT(dev_priv)) 253 max_clock = 180000; 254 else if (IS_VALLEYVIEW(dev_priv)) 255 /* 256 * 270 MHz due to current DPLL limits, 257 * DAC limit supposedly 355 MHz. 258 */ 259 max_clock = 270000; 260 else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) 261 max_clock = 400000; 262 else 263 max_clock = 350000; 264 if (mode->clock > max_clock) 265 return MODE_CLOCK_HIGH; 266 267 if (mode->clock > max_dotclk) 268 return MODE_CLOCK_HIGH; 269 270 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 271 if (HAS_PCH_LPT(dev_priv) && 272 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 273 return MODE_CLOCK_HIGH; 274 275 return MODE_OK; 276 } 277 278 static bool intel_crt_compute_config(struct intel_encoder *encoder, 279 struct intel_crtc_state *pipe_config, 280 struct drm_connector_state *conn_state) 281 { 282 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 283 284 if (HAS_PCH_SPLIT(dev_priv)) 285 pipe_config->has_pch_encoder = true; 286 287 /* LPT FDI RX only supports 8bpc. */ 288 if (HAS_PCH_LPT(dev_priv)) { 289 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 290 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 291 return false; 292 } 293 294 pipe_config->pipe_bpp = 24; 295 } 296 297 /* FDI must always be 2.7 GHz */ 298 if (HAS_DDI(dev_priv)) 299 pipe_config->port_clock = 135000 * 2; 300 301 return true; 302 } 303 304 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 305 { 306 struct drm_device *dev = connector->dev; 307 struct intel_crt *crt = intel_attached_crt(connector); 308 struct drm_i915_private *dev_priv = to_i915(dev); 309 u32 adpa; 310 bool ret; 311 312 /* The first time through, trigger an explicit detection cycle */ 313 if (crt->force_hotplug_required) { 314 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 315 u32 save_adpa; 316 317 crt->force_hotplug_required = 0; 318 319 save_adpa = adpa = I915_READ(crt->adpa_reg); 320 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 321 322 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 323 if (turn_off_dac) 324 adpa &= ~ADPA_DAC_ENABLE; 325 326 I915_WRITE(crt->adpa_reg, adpa); 327 328 if (intel_wait_for_register(dev_priv, 329 crt->adpa_reg, 330 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 331 1000)) 332 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 333 334 if (turn_off_dac) { 335 I915_WRITE(crt->adpa_reg, save_adpa); 336 POSTING_READ(crt->adpa_reg); 337 } 338 } 339 340 /* Check the status to see if both blue and green are on now */ 341 adpa = I915_READ(crt->adpa_reg); 342 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 343 ret = true; 344 else 345 ret = false; 346 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 347 348 return ret; 349 } 350 351 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 352 { 353 struct drm_device *dev = connector->dev; 354 struct intel_crt *crt = intel_attached_crt(connector); 355 struct drm_i915_private *dev_priv = to_i915(dev); 356 bool reenable_hpd; 357 u32 adpa; 358 bool ret; 359 u32 save_adpa; 360 361 /* 362 * Doing a force trigger causes a hpd interrupt to get sent, which can 363 * get us stuck in a loop if we're polling: 364 * - We enable power wells and reset the ADPA 365 * - output_poll_exec does force probe on VGA, triggering a hpd 366 * - HPD handler waits for poll to unlock dev->mode_config.mutex 367 * - output_poll_exec shuts off the ADPA, unlocks 368 * dev->mode_config.mutex 369 * - HPD handler runs, resets ADPA and brings us back to the start 370 * 371 * Just disable HPD interrupts here to prevent this 372 */ 373 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 374 375 save_adpa = adpa = I915_READ(crt->adpa_reg); 376 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 377 378 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 379 380 I915_WRITE(crt->adpa_reg, adpa); 381 382 if (intel_wait_for_register(dev_priv, 383 crt->adpa_reg, 384 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 385 1000)) { 386 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 387 I915_WRITE(crt->adpa_reg, save_adpa); 388 } 389 390 /* Check the status to see if both blue and green are on now */ 391 adpa = I915_READ(crt->adpa_reg); 392 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 393 ret = true; 394 else 395 ret = false; 396 397 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 398 399 if (reenable_hpd) 400 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 401 402 return ret; 403 } 404 405 /** 406 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 407 * 408 * Not for i915G/i915GM 409 * 410 * \return true if CRT is connected. 411 * \return false if CRT is disconnected. 412 */ 413 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 414 { 415 struct drm_device *dev = connector->dev; 416 struct drm_i915_private *dev_priv = to_i915(dev); 417 u32 stat; 418 bool ret = false; 419 int i, tries = 0; 420 421 if (HAS_PCH_SPLIT(dev_priv)) 422 return intel_ironlake_crt_detect_hotplug(connector); 423 424 if (IS_VALLEYVIEW(dev_priv)) 425 return valleyview_crt_detect_hotplug(connector); 426 427 /* 428 * On 4 series desktop, CRT detect sequence need to be done twice 429 * to get a reliable result. 430 */ 431 432 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) 433 tries = 2; 434 else 435 tries = 1; 436 437 for (i = 0; i < tries ; i++) { 438 /* turn on the FORCE_DETECT */ 439 i915_hotplug_interrupt_update(dev_priv, 440 CRT_HOTPLUG_FORCE_DETECT, 441 CRT_HOTPLUG_FORCE_DETECT); 442 /* wait for FORCE_DETECT to go off */ 443 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN, 444 CRT_HOTPLUG_FORCE_DETECT, 0, 445 1000)) 446 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 447 } 448 449 stat = I915_READ(PORT_HOTPLUG_STAT); 450 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 451 ret = true; 452 453 /* clear the interrupt we just generated, if any */ 454 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 455 456 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 457 458 return ret; 459 } 460 461 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 462 struct i2c_adapter *i2c) 463 { 464 struct edid *edid; 465 466 edid = drm_get_edid(connector, i2c); 467 468 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 469 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 470 intel_gmbus_force_bit(i2c, true); 471 edid = drm_get_edid(connector, i2c); 472 intel_gmbus_force_bit(i2c, false); 473 } 474 475 return edid; 476 } 477 478 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 479 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 480 struct i2c_adapter *adapter) 481 { 482 struct edid *edid; 483 int ret; 484 485 edid = intel_crt_get_edid(connector, adapter); 486 if (!edid) 487 return 0; 488 489 ret = intel_connector_update_modes(connector, edid); 490 kfree(edid); 491 492 return ret; 493 } 494 495 static bool intel_crt_detect_ddc(struct drm_connector *connector) 496 { 497 struct intel_crt *crt = intel_attached_crt(connector); 498 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 499 struct edid *edid; 500 struct i2c_adapter *i2c; 501 bool ret = false; 502 503 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 504 505 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 506 edid = intel_crt_get_edid(connector, i2c); 507 508 if (edid) { 509 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 510 511 /* 512 * This may be a DVI-I connector with a shared DDC 513 * link between analog and digital outputs, so we 514 * have to check the EDID input spec of the attached device. 515 */ 516 if (!is_digital) { 517 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 518 ret = true; 519 } else { 520 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 521 } 522 } else { 523 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 524 } 525 526 kfree(edid); 527 528 return ret; 529 } 530 531 static enum drm_connector_status 532 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) 533 { 534 struct drm_device *dev = crt->base.base.dev; 535 struct drm_i915_private *dev_priv = to_i915(dev); 536 uint32_t save_bclrpat; 537 uint32_t save_vtotal; 538 uint32_t vtotal, vactive; 539 uint32_t vsample; 540 uint32_t vblank, vblank_start, vblank_end; 541 uint32_t dsl; 542 i915_reg_t bclrpat_reg, vtotal_reg, 543 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 544 uint8_t st00; 545 enum drm_connector_status status; 546 547 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 548 549 bclrpat_reg = BCLRPAT(pipe); 550 vtotal_reg = VTOTAL(pipe); 551 vblank_reg = VBLANK(pipe); 552 vsync_reg = VSYNC(pipe); 553 pipeconf_reg = PIPECONF(pipe); 554 pipe_dsl_reg = PIPEDSL(pipe); 555 556 save_bclrpat = I915_READ(bclrpat_reg); 557 save_vtotal = I915_READ(vtotal_reg); 558 vblank = I915_READ(vblank_reg); 559 560 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 561 vactive = (save_vtotal & 0x7ff) + 1; 562 563 vblank_start = (vblank & 0xfff) + 1; 564 vblank_end = ((vblank >> 16) & 0xfff) + 1; 565 566 /* Set the border color to purple. */ 567 I915_WRITE(bclrpat_reg, 0x500050); 568 569 if (!IS_GEN2(dev_priv)) { 570 uint32_t pipeconf = I915_READ(pipeconf_reg); 571 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 572 POSTING_READ(pipeconf_reg); 573 /* Wait for next Vblank to substitue 574 * border color for Color info */ 575 intel_wait_for_vblank(dev_priv, pipe); 576 st00 = I915_READ8(_VGA_MSR_WRITE); 577 status = ((st00 & (1 << 4)) != 0) ? 578 connector_status_connected : 579 connector_status_disconnected; 580 581 I915_WRITE(pipeconf_reg, pipeconf); 582 } else { 583 bool restore_vblank = false; 584 int count, detect; 585 586 /* 587 * If there isn't any border, add some. 588 * Yes, this will flicker 589 */ 590 if (vblank_start <= vactive && vblank_end >= vtotal) { 591 uint32_t vsync = I915_READ(vsync_reg); 592 uint32_t vsync_start = (vsync & 0xffff) + 1; 593 594 vblank_start = vsync_start; 595 I915_WRITE(vblank_reg, 596 (vblank_start - 1) | 597 ((vblank_end - 1) << 16)); 598 restore_vblank = true; 599 } 600 /* sample in the vertical border, selecting the larger one */ 601 if (vblank_start - vactive >= vtotal - vblank_end) 602 vsample = (vblank_start + vactive) >> 1; 603 else 604 vsample = (vtotal + vblank_end) >> 1; 605 606 /* 607 * Wait for the border to be displayed 608 */ 609 while (I915_READ(pipe_dsl_reg) >= vactive) 610 ; 611 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 612 ; 613 /* 614 * Watch ST00 for an entire scanline 615 */ 616 detect = 0; 617 count = 0; 618 do { 619 count++; 620 /* Read the ST00 VGA status register */ 621 st00 = I915_READ8(_VGA_MSR_WRITE); 622 if (st00 & (1 << 4)) 623 detect++; 624 } while ((I915_READ(pipe_dsl_reg) == dsl)); 625 626 /* restore vblank if necessary */ 627 if (restore_vblank) 628 I915_WRITE(vblank_reg, vblank); 629 /* 630 * If more than 3/4 of the scanline detected a monitor, 631 * then it is assumed to be present. This works even on i830, 632 * where there isn't any way to force the border color across 633 * the screen 634 */ 635 status = detect * 4 > count * 3 ? 636 connector_status_connected : 637 connector_status_disconnected; 638 } 639 640 /* Restore previous settings */ 641 I915_WRITE(bclrpat_reg, save_bclrpat); 642 643 return status; 644 } 645 646 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 647 { 648 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 649 return 1; 650 } 651 652 static const struct dmi_system_id intel_spurious_crt_detect[] = { 653 { 654 .callback = intel_spurious_crt_detect_dmi_callback, 655 .ident = "ACER ZGB", 656 .matches = { 657 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 658 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 659 }, 660 }, 661 { 662 .callback = intel_spurious_crt_detect_dmi_callback, 663 .ident = "Intel DZ77BH-55K", 664 .matches = { 665 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 666 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 667 }, 668 }, 669 { } 670 }; 671 672 static int 673 intel_crt_detect(struct drm_connector *connector, 674 struct drm_modeset_acquire_ctx *ctx, 675 bool force) 676 { 677 struct drm_i915_private *dev_priv = to_i915(connector->dev); 678 struct intel_crt *crt = intel_attached_crt(connector); 679 struct intel_encoder *intel_encoder = &crt->base; 680 int status, ret; 681 struct intel_load_detect_pipe tmp; 682 683 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 684 connector->base.id, connector->name, 685 force); 686 687 /* Skip machines without VGA that falsely report hotplug events */ 688 if (dmi_check_system(intel_spurious_crt_detect)) 689 return connector_status_disconnected; 690 691 intel_display_power_get(dev_priv, intel_encoder->power_domain); 692 693 if (I915_HAS_HOTPLUG(dev_priv)) { 694 /* We can not rely on the HPD pin always being correctly wired 695 * up, for example many KVM do not pass it through, and so 696 * only trust an assertion that the monitor is connected. 697 */ 698 if (intel_crt_detect_hotplug(connector)) { 699 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 700 status = connector_status_connected; 701 goto out; 702 } else 703 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 704 } 705 706 if (intel_crt_detect_ddc(connector)) { 707 status = connector_status_connected; 708 goto out; 709 } 710 711 /* Load detection is broken on HPD capable machines. Whoever wants a 712 * broken monitor (without edid) to work behind a broken kvm (that fails 713 * to have the right resistors for HP detection) needs to fix this up. 714 * For now just bail out. */ 715 if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) { 716 status = connector_status_disconnected; 717 goto out; 718 } 719 720 if (!force) { 721 status = connector->status; 722 goto out; 723 } 724 725 /* for pre-945g platforms use load detect */ 726 ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx); 727 if (ret > 0) { 728 if (intel_crt_detect_ddc(connector)) 729 status = connector_status_connected; 730 else if (INTEL_GEN(dev_priv) < 4) 731 status = intel_crt_load_detect(crt, 732 to_intel_crtc(connector->state->crtc)->pipe); 733 else if (i915.load_detect_test) 734 status = connector_status_disconnected; 735 else 736 status = connector_status_unknown; 737 intel_release_load_detect_pipe(connector, &tmp, ctx); 738 } else if (ret == 0) 739 status = connector_status_unknown; 740 else if (ret < 0) 741 status = ret; 742 743 out: 744 intel_display_power_put(dev_priv, intel_encoder->power_domain); 745 return status; 746 } 747 748 static void intel_crt_destroy(struct drm_connector *connector) 749 { 750 drm_connector_cleanup(connector); 751 kfree(connector); 752 } 753 754 static int intel_crt_get_modes(struct drm_connector *connector) 755 { 756 struct drm_device *dev = connector->dev; 757 struct drm_i915_private *dev_priv = to_i915(dev); 758 struct intel_crt *crt = intel_attached_crt(connector); 759 struct intel_encoder *intel_encoder = &crt->base; 760 int ret; 761 struct i2c_adapter *i2c; 762 763 intel_display_power_get(dev_priv, intel_encoder->power_domain); 764 765 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 766 ret = intel_crt_ddc_get_modes(connector, i2c); 767 if (ret || !IS_G4X(dev_priv)) 768 goto out; 769 770 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 771 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 772 ret = intel_crt_ddc_get_modes(connector, i2c); 773 774 out: 775 intel_display_power_put(dev_priv, intel_encoder->power_domain); 776 777 return ret; 778 } 779 780 static int intel_crt_set_property(struct drm_connector *connector, 781 struct drm_property *property, 782 uint64_t value) 783 { 784 return 0; 785 } 786 787 void intel_crt_reset(struct drm_encoder *encoder) 788 { 789 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 790 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 791 792 if (INTEL_GEN(dev_priv) >= 5) { 793 u32 adpa; 794 795 adpa = I915_READ(crt->adpa_reg); 796 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 797 adpa |= ADPA_HOTPLUG_BITS; 798 I915_WRITE(crt->adpa_reg, adpa); 799 POSTING_READ(crt->adpa_reg); 800 801 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 802 crt->force_hotplug_required = 1; 803 } 804 805 } 806 807 /* 808 * Routines for controlling stuff on the analog port 809 */ 810 811 static const struct drm_connector_funcs intel_crt_connector_funcs = { 812 .dpms = drm_atomic_helper_connector_dpms, 813 .fill_modes = drm_helper_probe_single_connector_modes, 814 .late_register = intel_connector_register, 815 .early_unregister = intel_connector_unregister, 816 .destroy = intel_crt_destroy, 817 .set_property = intel_crt_set_property, 818 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 819 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 820 .atomic_get_property = intel_connector_atomic_get_property, 821 }; 822 823 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 824 .detect_ctx = intel_crt_detect, 825 .mode_valid = intel_crt_mode_valid, 826 .get_modes = intel_crt_get_modes, 827 }; 828 829 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 830 .reset = intel_crt_reset, 831 .destroy = intel_encoder_destroy, 832 }; 833 834 void intel_crt_init(struct drm_i915_private *dev_priv) 835 { 836 struct drm_connector *connector; 837 struct intel_crt *crt; 838 struct intel_connector *intel_connector; 839 i915_reg_t adpa_reg; 840 u32 adpa; 841 842 if (HAS_PCH_SPLIT(dev_priv)) 843 adpa_reg = PCH_ADPA; 844 else if (IS_VALLEYVIEW(dev_priv)) 845 adpa_reg = VLV_ADPA; 846 else 847 adpa_reg = ADPA; 848 849 adpa = I915_READ(adpa_reg); 850 if ((adpa & ADPA_DAC_ENABLE) == 0) { 851 /* 852 * On some machines (some IVB at least) CRT can be 853 * fused off, but there's no known fuse bit to 854 * indicate that. On these machine the ADPA register 855 * works normally, except the DAC enable bit won't 856 * take. So the only way to tell is attempt to enable 857 * it and see what happens. 858 */ 859 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 860 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 861 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 862 return; 863 I915_WRITE(adpa_reg, adpa); 864 } 865 866 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 867 if (!crt) 868 return; 869 870 intel_connector = intel_connector_alloc(); 871 if (!intel_connector) { 872 kfree(crt); 873 return; 874 } 875 876 connector = &intel_connector->base; 877 crt->connector = intel_connector; 878 drm_connector_init(&dev_priv->drm, &intel_connector->base, 879 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 880 881 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, 882 DRM_MODE_ENCODER_DAC, "CRT"); 883 884 intel_connector_attach_encoder(intel_connector, &crt->base); 885 886 crt->base.type = INTEL_OUTPUT_ANALOG; 887 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 888 if (IS_I830(dev_priv)) 889 crt->base.crtc_mask = (1 << 0); 890 else 891 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 892 893 if (IS_GEN2(dev_priv)) 894 connector->interlace_allowed = 0; 895 else 896 connector->interlace_allowed = 1; 897 connector->doublescan_allowed = 0; 898 899 crt->adpa_reg = adpa_reg; 900 901 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 902 903 crt->base.compute_config = intel_crt_compute_config; 904 if (HAS_PCH_SPLIT(dev_priv)) { 905 crt->base.disable = pch_disable_crt; 906 crt->base.post_disable = pch_post_disable_crt; 907 } else { 908 crt->base.disable = intel_disable_crt; 909 } 910 crt->base.enable = intel_enable_crt; 911 if (I915_HAS_HOTPLUG(dev_priv) && 912 !dmi_check_system(intel_spurious_crt_detect)) 913 crt->base.hpd_pin = HPD_CRT; 914 if (HAS_DDI(dev_priv)) { 915 crt->base.port = PORT_E; 916 crt->base.get_config = hsw_crt_get_config; 917 crt->base.get_hw_state = intel_ddi_get_hw_state; 918 crt->base.post_disable = hsw_post_disable_crt; 919 } else { 920 crt->base.port = PORT_NONE; 921 crt->base.get_config = intel_crt_get_config; 922 crt->base.get_hw_state = intel_crt_get_hw_state; 923 } 924 intel_connector->get_hw_state = intel_connector_get_hw_state; 925 926 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 927 928 if (!I915_HAS_HOTPLUG(dev_priv)) 929 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 930 931 /* 932 * Configure the automatic hotplug detection stuff 933 */ 934 crt->force_hotplug_required = 0; 935 936 /* 937 * TODO: find a proper way to discover whether we need to set the the 938 * polarity and link reversal bits or not, instead of relying on the 939 * BIOS. 940 */ 941 if (HAS_PCH_LPT(dev_priv)) { 942 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 943 FDI_RX_LINK_REVERSAL_OVERRIDE; 944 945 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 946 } 947 948 intel_crt_reset(&crt->base.base); 949 } 950