1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 /* Here's the desired hotplug mode */ 39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 44 ADPA_CRT_HOTPLUG_ENABLE) 45 46 struct intel_crt { 47 struct intel_encoder base; 48 /* DPMS state is stored in the connector, which we need in the 49 * encoder's enable/disable callbacks */ 50 struct intel_connector *connector; 51 bool force_hotplug_required; 52 i915_reg_t adpa_reg; 53 }; 54 55 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 56 { 57 return container_of(encoder, struct intel_crt, base); 58 } 59 60 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 61 { 62 return intel_encoder_to_crt(intel_attached_encoder(connector)); 63 } 64 65 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 66 enum i915_pipe *pipe) 67 { 68 struct drm_device *dev = encoder->base.dev; 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 struct intel_crt *crt = intel_encoder_to_crt(encoder); 71 enum intel_display_power_domain power_domain; 72 u32 tmp; 73 bool ret; 74 75 power_domain = intel_display_port_power_domain(encoder); 76 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 77 return false; 78 79 ret = false; 80 81 tmp = I915_READ(crt->adpa_reg); 82 83 if (!(tmp & ADPA_DAC_ENABLE)) 84 goto out; 85 86 if (HAS_PCH_CPT(dev)) 87 *pipe = PORT_TO_PIPE_CPT(tmp); 88 else 89 *pipe = PORT_TO_PIPE(tmp); 90 91 ret = true; 92 out: 93 intel_display_power_put(dev_priv, power_domain); 94 95 return ret; 96 } 97 98 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 99 { 100 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 101 struct intel_crt *crt = intel_encoder_to_crt(encoder); 102 u32 tmp, flags = 0; 103 104 tmp = I915_READ(crt->adpa_reg); 105 106 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 107 flags |= DRM_MODE_FLAG_PHSYNC; 108 else 109 flags |= DRM_MODE_FLAG_NHSYNC; 110 111 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 112 flags |= DRM_MODE_FLAG_PVSYNC; 113 else 114 flags |= DRM_MODE_FLAG_NVSYNC; 115 116 return flags; 117 } 118 119 static void intel_crt_get_config(struct intel_encoder *encoder, 120 struct intel_crtc_state *pipe_config) 121 { 122 struct drm_device *dev = encoder->base.dev; 123 int dotclock; 124 125 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 126 127 dotclock = pipe_config->port_clock; 128 129 if (HAS_PCH_SPLIT(dev)) 130 ironlake_check_encoder_dotclock(pipe_config, dotclock); 131 132 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 133 } 134 135 static void hsw_crt_get_config(struct intel_encoder *encoder, 136 struct intel_crtc_state *pipe_config) 137 { 138 intel_ddi_get_config(encoder, pipe_config); 139 140 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 141 DRM_MODE_FLAG_NHSYNC | 142 DRM_MODE_FLAG_PVSYNC | 143 DRM_MODE_FLAG_NVSYNC); 144 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 145 } 146 147 /* Note: The caller is required to filter out dpms modes not supported by the 148 * platform. */ 149 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 150 { 151 struct drm_device *dev = encoder->base.dev; 152 struct drm_i915_private *dev_priv = dev->dev_private; 153 struct intel_crt *crt = intel_encoder_to_crt(encoder); 154 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 155 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 156 u32 adpa; 157 158 if (INTEL_INFO(dev)->gen >= 5) 159 adpa = ADPA_HOTPLUG_BITS; 160 else 161 adpa = 0; 162 163 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 164 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 165 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 166 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 167 168 /* For CPT allow 3 pipe config, for others just use A or B */ 169 if (HAS_PCH_LPT(dev)) 170 ; /* Those bits don't exist here */ 171 else if (HAS_PCH_CPT(dev)) 172 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 173 else if (crtc->pipe == 0) 174 adpa |= ADPA_PIPE_A_SELECT; 175 else 176 adpa |= ADPA_PIPE_B_SELECT; 177 178 if (!HAS_PCH_SPLIT(dev)) 179 I915_WRITE(BCLRPAT(crtc->pipe), 0); 180 181 switch (mode) { 182 case DRM_MODE_DPMS_ON: 183 adpa |= ADPA_DAC_ENABLE; 184 break; 185 case DRM_MODE_DPMS_STANDBY: 186 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 187 break; 188 case DRM_MODE_DPMS_SUSPEND: 189 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 190 break; 191 case DRM_MODE_DPMS_OFF: 192 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 193 break; 194 } 195 196 I915_WRITE(crt->adpa_reg, adpa); 197 } 198 199 static void intel_disable_crt(struct intel_encoder *encoder) 200 { 201 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 202 } 203 204 static void pch_disable_crt(struct intel_encoder *encoder) 205 { 206 } 207 208 static void pch_post_disable_crt(struct intel_encoder *encoder) 209 { 210 intel_disable_crt(encoder); 211 } 212 213 static void intel_enable_crt(struct intel_encoder *encoder) 214 { 215 struct intel_crt *crt = intel_encoder_to_crt(encoder); 216 217 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 218 } 219 220 static enum drm_mode_status 221 intel_crt_mode_valid(struct drm_connector *connector, 222 struct drm_display_mode *mode) 223 { 224 struct drm_device *dev = connector->dev; 225 226 int max_clock = 0; 227 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 228 return MODE_NO_DBLESCAN; 229 230 if (mode->clock < 25000) 231 return MODE_CLOCK_LOW; 232 233 if (IS_GEN2(dev)) 234 max_clock = 350000; 235 else 236 max_clock = 400000; 237 if (mode->clock > max_clock) 238 return MODE_CLOCK_HIGH; 239 240 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 241 if (HAS_PCH_LPT(dev) && 242 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 243 return MODE_CLOCK_HIGH; 244 245 return MODE_OK; 246 } 247 248 static bool intel_crt_compute_config(struct intel_encoder *encoder, 249 struct intel_crtc_state *pipe_config) 250 { 251 struct drm_device *dev = encoder->base.dev; 252 253 if (HAS_PCH_SPLIT(dev)) 254 pipe_config->has_pch_encoder = true; 255 256 /* LPT FDI RX only supports 8bpc. */ 257 if (HAS_PCH_LPT(dev)) 258 pipe_config->pipe_bpp = 24; 259 260 /* FDI must always be 2.7 GHz */ 261 if (HAS_DDI(dev)) { 262 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 263 pipe_config->port_clock = 135000 * 2; 264 265 pipe_config->dpll_hw_state.wrpll = 0; 266 pipe_config->dpll_hw_state.spll = 267 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; 268 } 269 270 return true; 271 } 272 273 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 274 { 275 struct drm_device *dev = connector->dev; 276 struct intel_crt *crt = intel_attached_crt(connector); 277 struct drm_i915_private *dev_priv = dev->dev_private; 278 u32 adpa; 279 bool ret; 280 281 /* The first time through, trigger an explicit detection cycle */ 282 if (crt->force_hotplug_required) { 283 bool turn_off_dac = HAS_PCH_SPLIT(dev); 284 u32 save_adpa; 285 286 crt->force_hotplug_required = 0; 287 288 save_adpa = adpa = I915_READ(crt->adpa_reg); 289 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 290 291 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 292 if (turn_off_dac) 293 adpa &= ~ADPA_DAC_ENABLE; 294 295 I915_WRITE(crt->adpa_reg, adpa); 296 297 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 298 1000)) 299 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 300 301 if (turn_off_dac) { 302 I915_WRITE(crt->adpa_reg, save_adpa); 303 POSTING_READ(crt->adpa_reg); 304 } 305 } 306 307 /* Check the status to see if both blue and green are on now */ 308 adpa = I915_READ(crt->adpa_reg); 309 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 310 ret = true; 311 else 312 ret = false; 313 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 314 315 return ret; 316 } 317 318 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 319 { 320 struct drm_device *dev = connector->dev; 321 struct intel_crt *crt = intel_attached_crt(connector); 322 struct drm_i915_private *dev_priv = dev->dev_private; 323 u32 adpa; 324 bool ret; 325 u32 save_adpa; 326 327 save_adpa = adpa = I915_READ(crt->adpa_reg); 328 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 329 330 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 331 332 I915_WRITE(crt->adpa_reg, adpa); 333 334 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 335 1000)) { 336 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 337 I915_WRITE(crt->adpa_reg, save_adpa); 338 } 339 340 /* Check the status to see if both blue and green are on now */ 341 adpa = I915_READ(crt->adpa_reg); 342 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 343 ret = true; 344 else 345 ret = false; 346 347 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 348 349 return ret; 350 } 351 352 /** 353 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 354 * 355 * Not for i915G/i915GM 356 * 357 * \return true if CRT is connected. 358 * \return false if CRT is disconnected. 359 */ 360 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 361 { 362 struct drm_device *dev = connector->dev; 363 struct drm_i915_private *dev_priv = dev->dev_private; 364 u32 stat; 365 bool ret = false; 366 int i, tries = 0; 367 368 if (HAS_PCH_SPLIT(dev)) 369 return intel_ironlake_crt_detect_hotplug(connector); 370 371 if (IS_VALLEYVIEW(dev)) 372 return valleyview_crt_detect_hotplug(connector); 373 374 /* 375 * On 4 series desktop, CRT detect sequence need to be done twice 376 * to get a reliable result. 377 */ 378 379 if (IS_G4X(dev) && !IS_GM45(dev)) 380 tries = 2; 381 else 382 tries = 1; 383 384 for (i = 0; i < tries ; i++) { 385 /* turn on the FORCE_DETECT */ 386 i915_hotplug_interrupt_update(dev_priv, 387 CRT_HOTPLUG_FORCE_DETECT, 388 CRT_HOTPLUG_FORCE_DETECT); 389 /* wait for FORCE_DETECT to go off */ 390 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 391 CRT_HOTPLUG_FORCE_DETECT) == 0, 392 1000)) 393 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 394 } 395 396 stat = I915_READ(PORT_HOTPLUG_STAT); 397 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 398 ret = true; 399 400 /* clear the interrupt we just generated, if any */ 401 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 402 403 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 404 405 return ret; 406 } 407 408 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 409 struct i2c_adapter *i2c) 410 { 411 struct edid *edid; 412 413 edid = drm_get_edid(connector, i2c); 414 415 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 416 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 417 intel_gmbus_force_bit(i2c, true); 418 edid = drm_get_edid(connector, i2c); 419 intel_gmbus_force_bit(i2c, false); 420 } 421 422 return edid; 423 } 424 425 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 426 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 427 struct i2c_adapter *adapter) 428 { 429 struct edid *edid; 430 int ret; 431 432 edid = intel_crt_get_edid(connector, adapter); 433 if (!edid) 434 return 0; 435 436 ret = intel_connector_update_modes(connector, edid); 437 kfree(edid); 438 439 return ret; 440 } 441 442 static bool intel_crt_detect_ddc(struct drm_connector *connector) 443 { 444 struct intel_crt *crt = intel_attached_crt(connector); 445 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 446 struct edid *edid; 447 struct i2c_adapter *i2c; 448 449 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 450 451 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 452 edid = intel_crt_get_edid(connector, i2c); 453 454 if (edid) { 455 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 456 457 /* 458 * This may be a DVI-I connector with a shared DDC 459 * link between analog and digital outputs, so we 460 * have to check the EDID input spec of the attached device. 461 */ 462 if (!is_digital) { 463 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 464 return true; 465 } 466 467 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 468 } else { 469 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 470 } 471 472 kfree(edid); 473 474 return false; 475 } 476 477 static enum drm_connector_status 478 intel_crt_load_detect(struct intel_crt *crt) 479 { 480 struct drm_device *dev = crt->base.base.dev; 481 struct drm_i915_private *dev_priv = dev->dev_private; 482 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 483 uint32_t save_bclrpat; 484 uint32_t save_vtotal; 485 uint32_t vtotal, vactive; 486 uint32_t vsample; 487 uint32_t vblank, vblank_start, vblank_end; 488 uint32_t dsl; 489 i915_reg_t bclrpat_reg, vtotal_reg, 490 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 491 uint8_t st00; 492 enum drm_connector_status status; 493 494 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 495 496 bclrpat_reg = BCLRPAT(pipe); 497 vtotal_reg = VTOTAL(pipe); 498 vblank_reg = VBLANK(pipe); 499 vsync_reg = VSYNC(pipe); 500 pipeconf_reg = PIPECONF(pipe); 501 pipe_dsl_reg = PIPEDSL(pipe); 502 503 save_bclrpat = I915_READ(bclrpat_reg); 504 save_vtotal = I915_READ(vtotal_reg); 505 vblank = I915_READ(vblank_reg); 506 507 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 508 vactive = (save_vtotal & 0x7ff) + 1; 509 510 vblank_start = (vblank & 0xfff) + 1; 511 vblank_end = ((vblank >> 16) & 0xfff) + 1; 512 513 /* Set the border color to purple. */ 514 I915_WRITE(bclrpat_reg, 0x500050); 515 516 if (!IS_GEN2(dev)) { 517 uint32_t pipeconf = I915_READ(pipeconf_reg); 518 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 519 POSTING_READ(pipeconf_reg); 520 /* Wait for next Vblank to substitue 521 * border color for Color info */ 522 intel_wait_for_vblank(dev, pipe); 523 st00 = I915_READ8(_VGA_MSR_WRITE); 524 status = ((st00 & (1 << 4)) != 0) ? 525 connector_status_connected : 526 connector_status_disconnected; 527 528 I915_WRITE(pipeconf_reg, pipeconf); 529 } else { 530 bool restore_vblank = false; 531 int count, detect; 532 533 /* 534 * If there isn't any border, add some. 535 * Yes, this will flicker 536 */ 537 if (vblank_start <= vactive && vblank_end >= vtotal) { 538 uint32_t vsync = I915_READ(vsync_reg); 539 uint32_t vsync_start = (vsync & 0xffff) + 1; 540 541 vblank_start = vsync_start; 542 I915_WRITE(vblank_reg, 543 (vblank_start - 1) | 544 ((vblank_end - 1) << 16)); 545 restore_vblank = true; 546 } 547 /* sample in the vertical border, selecting the larger one */ 548 if (vblank_start - vactive >= vtotal - vblank_end) 549 vsample = (vblank_start + vactive) >> 1; 550 else 551 vsample = (vtotal + vblank_end) >> 1; 552 553 /* 554 * Wait for the border to be displayed 555 */ 556 while (I915_READ(pipe_dsl_reg) >= vactive) 557 ; 558 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 559 ; 560 /* 561 * Watch ST00 for an entire scanline 562 */ 563 detect = 0; 564 count = 0; 565 do { 566 count++; 567 /* Read the ST00 VGA status register */ 568 st00 = I915_READ8(_VGA_MSR_WRITE); 569 if (st00 & (1 << 4)) 570 detect++; 571 } while ((I915_READ(pipe_dsl_reg) == dsl)); 572 573 /* restore vblank if necessary */ 574 if (restore_vblank) 575 I915_WRITE(vblank_reg, vblank); 576 /* 577 * If more than 3/4 of the scanline detected a monitor, 578 * then it is assumed to be present. This works even on i830, 579 * where there isn't any way to force the border color across 580 * the screen 581 */ 582 status = detect * 4 > count * 3 ? 583 connector_status_connected : 584 connector_status_disconnected; 585 } 586 587 /* Restore previous settings */ 588 I915_WRITE(bclrpat_reg, save_bclrpat); 589 590 return status; 591 } 592 593 static enum drm_connector_status 594 intel_crt_detect(struct drm_connector *connector, bool force) 595 { 596 struct drm_device *dev = connector->dev; 597 struct drm_i915_private *dev_priv = dev->dev_private; 598 struct intel_crt *crt = intel_attached_crt(connector); 599 struct intel_encoder *intel_encoder = &crt->base; 600 enum intel_display_power_domain power_domain; 601 enum drm_connector_status status; 602 struct intel_load_detect_pipe tmp; 603 struct drm_modeset_acquire_ctx ctx; 604 605 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 606 connector->base.id, connector->name, 607 force); 608 609 power_domain = intel_display_port_power_domain(intel_encoder); 610 intel_display_power_get(dev_priv, power_domain); 611 612 if (I915_HAS_HOTPLUG(dev)) { 613 /* We can not rely on the HPD pin always being correctly wired 614 * up, for example many KVM do not pass it through, and so 615 * only trust an assertion that the monitor is connected. 616 */ 617 if (intel_crt_detect_hotplug(connector)) { 618 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 619 status = connector_status_connected; 620 goto out; 621 } else 622 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 623 } 624 625 if (intel_crt_detect_ddc(connector)) { 626 status = connector_status_connected; 627 goto out; 628 } 629 630 /* Load detection is broken on HPD capable machines. Whoever wants a 631 * broken monitor (without edid) to work behind a broken kvm (that fails 632 * to have the right resistors for HP detection) needs to fix this up. 633 * For now just bail out. */ 634 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 635 status = connector_status_disconnected; 636 goto out; 637 } 638 639 if (!force) { 640 status = connector->status; 641 goto out; 642 } 643 644 drm_modeset_acquire_init(&ctx, 0); 645 646 /* for pre-945g platforms use load detect */ 647 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 648 if (intel_crt_detect_ddc(connector)) 649 status = connector_status_connected; 650 else if (INTEL_INFO(dev)->gen < 4) 651 status = intel_crt_load_detect(crt); 652 else 653 status = connector_status_unknown; 654 intel_release_load_detect_pipe(connector, &tmp, &ctx); 655 } else 656 status = connector_status_unknown; 657 658 drm_modeset_drop_locks(&ctx); 659 drm_modeset_acquire_fini(&ctx); 660 661 out: 662 intel_display_power_put(dev_priv, power_domain); 663 return status; 664 } 665 666 static void intel_crt_destroy(struct drm_connector *connector) 667 { 668 drm_connector_cleanup(connector); 669 kfree(connector); 670 } 671 672 static int intel_crt_get_modes(struct drm_connector *connector) 673 { 674 struct drm_device *dev = connector->dev; 675 struct drm_i915_private *dev_priv = dev->dev_private; 676 struct intel_crt *crt = intel_attached_crt(connector); 677 struct intel_encoder *intel_encoder = &crt->base; 678 enum intel_display_power_domain power_domain; 679 int ret; 680 struct i2c_adapter *i2c; 681 682 power_domain = intel_display_port_power_domain(intel_encoder); 683 intel_display_power_get(dev_priv, power_domain); 684 685 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 686 ret = intel_crt_ddc_get_modes(connector, i2c); 687 if (ret || !IS_G4X(dev)) 688 goto out; 689 690 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 691 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 692 ret = intel_crt_ddc_get_modes(connector, i2c); 693 694 out: 695 intel_display_power_put(dev_priv, power_domain); 696 697 return ret; 698 } 699 700 static int intel_crt_set_property(struct drm_connector *connector, 701 struct drm_property *property, 702 uint64_t value) 703 { 704 return 0; 705 } 706 707 static void intel_crt_reset(struct drm_connector *connector) 708 { 709 struct drm_device *dev = connector->dev; 710 struct drm_i915_private *dev_priv = dev->dev_private; 711 struct intel_crt *crt = intel_attached_crt(connector); 712 713 if (INTEL_INFO(dev)->gen >= 5) { 714 u32 adpa; 715 716 adpa = I915_READ(crt->adpa_reg); 717 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 718 adpa |= ADPA_HOTPLUG_BITS; 719 I915_WRITE(crt->adpa_reg, adpa); 720 POSTING_READ(crt->adpa_reg); 721 722 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 723 crt->force_hotplug_required = 1; 724 } 725 726 } 727 728 /* 729 * Routines for controlling stuff on the analog port 730 */ 731 732 static const struct drm_connector_funcs intel_crt_connector_funcs = { 733 .reset = intel_crt_reset, 734 .dpms = drm_atomic_helper_connector_dpms, 735 .detect = intel_crt_detect, 736 .fill_modes = drm_helper_probe_single_connector_modes, 737 .destroy = intel_crt_destroy, 738 .set_property = intel_crt_set_property, 739 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 740 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 741 .atomic_get_property = intel_connector_atomic_get_property, 742 }; 743 744 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 745 .mode_valid = intel_crt_mode_valid, 746 .get_modes = intel_crt_get_modes, 747 .best_encoder = intel_best_encoder, 748 }; 749 750 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 751 .destroy = intel_encoder_destroy, 752 }; 753 754 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 755 { 756 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 757 return 1; 758 } 759 760 static const struct dmi_system_id intel_no_crt[] = { 761 { 762 .callback = intel_no_crt_dmi_callback, 763 .ident = "ACER ZGB", 764 .matches = { 765 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 766 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 767 }, 768 }, 769 { 770 .callback = intel_no_crt_dmi_callback, 771 .ident = "DELL XPS 8700", 772 .matches = { 773 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 774 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 775 }, 776 }, 777 { } 778 }; 779 780 void intel_crt_init(struct drm_device *dev) 781 { 782 struct drm_connector *connector; 783 struct intel_crt *crt; 784 struct intel_connector *intel_connector; 785 struct drm_i915_private *dev_priv = dev->dev_private; 786 i915_reg_t adpa_reg; 787 u32 adpa; 788 789 /* Skip machines without VGA that falsely report hotplug events */ 790 if (dmi_check_system(intel_no_crt)) 791 return; 792 793 if (HAS_PCH_SPLIT(dev)) 794 adpa_reg = PCH_ADPA; 795 else if (IS_VALLEYVIEW(dev)) 796 adpa_reg = VLV_ADPA; 797 else 798 adpa_reg = ADPA; 799 800 adpa = I915_READ(adpa_reg); 801 if ((adpa & ADPA_DAC_ENABLE) == 0) { 802 /* 803 * On some machines (some IVB at least) CRT can be 804 * fused off, but there's no known fuse bit to 805 * indicate that. On these machine the ADPA register 806 * works normally, except the DAC enable bit won't 807 * take. So the only way to tell is attempt to enable 808 * it and see what happens. 809 */ 810 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 811 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 812 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 813 return; 814 I915_WRITE(adpa_reg, adpa); 815 } 816 817 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 818 if (!crt) 819 return; 820 821 intel_connector = intel_connector_alloc(); 822 if (!intel_connector) { 823 kfree(crt); 824 return; 825 } 826 827 connector = &intel_connector->base; 828 crt->connector = intel_connector; 829 drm_connector_init(dev, &intel_connector->base, 830 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 831 832 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 833 DRM_MODE_ENCODER_DAC, NULL); 834 835 intel_connector_attach_encoder(intel_connector, &crt->base); 836 837 crt->base.type = INTEL_OUTPUT_ANALOG; 838 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 839 if (IS_I830(dev)) 840 crt->base.crtc_mask = (1 << 0); 841 else 842 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 843 844 if (IS_GEN2(dev)) 845 connector->interlace_allowed = 0; 846 else 847 connector->interlace_allowed = 1; 848 connector->doublescan_allowed = 0; 849 850 crt->adpa_reg = adpa_reg; 851 852 crt->base.compute_config = intel_crt_compute_config; 853 if (HAS_PCH_SPLIT(dev)) { 854 crt->base.disable = pch_disable_crt; 855 crt->base.post_disable = pch_post_disable_crt; 856 } else { 857 crt->base.disable = intel_disable_crt; 858 } 859 crt->base.enable = intel_enable_crt; 860 if (I915_HAS_HOTPLUG(dev)) 861 crt->base.hpd_pin = HPD_CRT; 862 if (HAS_DDI(dev)) { 863 crt->base.get_config = hsw_crt_get_config; 864 crt->base.get_hw_state = intel_ddi_get_hw_state; 865 } else { 866 crt->base.get_config = intel_crt_get_config; 867 crt->base.get_hw_state = intel_crt_get_hw_state; 868 } 869 intel_connector->get_hw_state = intel_connector_get_hw_state; 870 intel_connector->unregister = intel_connector_unregister; 871 872 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 873 874 drm_connector_register(connector); 875 876 if (!I915_HAS_HOTPLUG(dev)) 877 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 878 879 /* 880 * Configure the automatic hotplug detection stuff 881 */ 882 crt->force_hotplug_required = 0; 883 884 /* 885 * TODO: find a proper way to discover whether we need to set the the 886 * polarity and link reversal bits or not, instead of relying on the 887 * BIOS. 888 */ 889 if (HAS_PCH_LPT(dev)) { 890 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 891 FDI_RX_LINK_REVERSAL_OVERRIDE; 892 893 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 894 } 895 896 intel_crt_reset(connector); 897 } 898