1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/drm_edid.h> 33 #include "intel_drv.h" 34 #include <drm/i915_drm.h> 35 #include "i915_drv.h" 36 37 /* Here's the desired hotplug mode */ 38 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 39 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 40 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 41 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 42 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 43 ADPA_CRT_HOTPLUG_ENABLE) 44 45 struct intel_crt { 46 struct intel_encoder base; 47 /* DPMS state is stored in the connector, which we need in the 48 * encoder's enable/disable callbacks */ 49 struct intel_connector *connector; 50 bool force_hotplug_required; 51 u32 adpa_reg; 52 }; 53 54 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 55 { 56 return container_of(encoder, struct intel_crt, base); 57 } 58 59 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 60 { 61 return intel_encoder_to_crt(intel_attached_encoder(connector)); 62 } 63 64 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 65 enum i915_pipe *pipe) 66 { 67 struct drm_device *dev = encoder->base.dev; 68 struct drm_i915_private *dev_priv = dev->dev_private; 69 struct intel_crt *crt = intel_encoder_to_crt(encoder); 70 enum intel_display_power_domain power_domain; 71 u32 tmp; 72 73 power_domain = intel_display_port_power_domain(encoder); 74 if (!intel_display_power_enabled(dev_priv, power_domain)) 75 return false; 76 77 tmp = I915_READ(crt->adpa_reg); 78 79 if (!(tmp & ADPA_DAC_ENABLE)) 80 return false; 81 82 if (HAS_PCH_CPT(dev)) 83 *pipe = PORT_TO_PIPE_CPT(tmp); 84 else 85 *pipe = PORT_TO_PIPE(tmp); 86 87 return true; 88 } 89 90 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 91 { 92 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 93 struct intel_crt *crt = intel_encoder_to_crt(encoder); 94 u32 tmp, flags = 0; 95 96 tmp = I915_READ(crt->adpa_reg); 97 98 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 99 flags |= DRM_MODE_FLAG_PHSYNC; 100 else 101 flags |= DRM_MODE_FLAG_NHSYNC; 102 103 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 104 flags |= DRM_MODE_FLAG_PVSYNC; 105 else 106 flags |= DRM_MODE_FLAG_NVSYNC; 107 108 return flags; 109 } 110 111 static void intel_crt_get_config(struct intel_encoder *encoder, 112 struct intel_crtc_config *pipe_config) 113 { 114 struct drm_device *dev = encoder->base.dev; 115 int dotclock; 116 117 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); 118 119 dotclock = pipe_config->port_clock; 120 121 if (HAS_PCH_SPLIT(dev)) 122 ironlake_check_encoder_dotclock(pipe_config, dotclock); 123 124 pipe_config->adjusted_mode.crtc_clock = dotclock; 125 } 126 127 static void hsw_crt_get_config(struct intel_encoder *encoder, 128 struct intel_crtc_config *pipe_config) 129 { 130 intel_ddi_get_config(encoder, pipe_config); 131 132 pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 133 DRM_MODE_FLAG_NHSYNC | 134 DRM_MODE_FLAG_PVSYNC | 135 DRM_MODE_FLAG_NVSYNC); 136 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); 137 } 138 139 /* Note: The caller is required to filter out dpms modes not supported by the 140 * platform. */ 141 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 142 { 143 struct drm_device *dev = encoder->base.dev; 144 struct drm_i915_private *dev_priv = dev->dev_private; 145 struct intel_crt *crt = intel_encoder_to_crt(encoder); 146 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 147 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 148 u32 adpa; 149 150 if (INTEL_INFO(dev)->gen >= 5) 151 adpa = ADPA_HOTPLUG_BITS; 152 else 153 adpa = 0; 154 155 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 156 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 157 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 158 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 159 160 /* For CPT allow 3 pipe config, for others just use A or B */ 161 if (HAS_PCH_LPT(dev)) 162 ; /* Those bits don't exist here */ 163 else if (HAS_PCH_CPT(dev)) 164 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 165 else if (crtc->pipe == 0) 166 adpa |= ADPA_PIPE_A_SELECT; 167 else 168 adpa |= ADPA_PIPE_B_SELECT; 169 170 if (!HAS_PCH_SPLIT(dev)) 171 I915_WRITE(BCLRPAT(crtc->pipe), 0); 172 173 switch (mode) { 174 case DRM_MODE_DPMS_ON: 175 adpa |= ADPA_DAC_ENABLE; 176 break; 177 case DRM_MODE_DPMS_STANDBY: 178 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 179 break; 180 case DRM_MODE_DPMS_SUSPEND: 181 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 182 break; 183 case DRM_MODE_DPMS_OFF: 184 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 185 break; 186 } 187 188 I915_WRITE(crt->adpa_reg, adpa); 189 } 190 191 static void intel_disable_crt(struct intel_encoder *encoder) 192 { 193 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 194 } 195 196 static void intel_enable_crt(struct intel_encoder *encoder) 197 { 198 struct intel_crt *crt = intel_encoder_to_crt(encoder); 199 200 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 201 } 202 203 /* Special dpms function to support cloning between dvo/sdvo/crt. */ 204 static void intel_crt_dpms(struct drm_connector *connector, int mode) 205 { 206 struct drm_device *dev = connector->dev; 207 struct intel_encoder *encoder = intel_attached_encoder(connector); 208 struct drm_crtc *crtc; 209 int old_dpms; 210 211 /* PCH platforms and VLV only support on/off. */ 212 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) 213 mode = DRM_MODE_DPMS_OFF; 214 215 if (mode == connector->dpms) 216 return; 217 218 old_dpms = connector->dpms; 219 connector->dpms = mode; 220 221 /* Only need to change hw state when actually enabled */ 222 crtc = encoder->base.crtc; 223 if (!crtc) { 224 encoder->connectors_active = false; 225 return; 226 } 227 228 /* We need the pipe to run for anything but OFF. */ 229 if (mode == DRM_MODE_DPMS_OFF) 230 encoder->connectors_active = false; 231 else 232 encoder->connectors_active = true; 233 234 /* We call connector dpms manually below in case pipe dpms doesn't 235 * change due to cloning. */ 236 if (mode < old_dpms) { 237 /* From off to on, enable the pipe first. */ 238 intel_crtc_update_dpms(crtc); 239 240 intel_crt_set_dpms(encoder, mode); 241 } else { 242 intel_crt_set_dpms(encoder, mode); 243 244 intel_crtc_update_dpms(crtc); 245 } 246 247 intel_modeset_check_state(connector->dev); 248 } 249 250 static enum drm_mode_status 251 intel_crt_mode_valid(struct drm_connector *connector, 252 struct drm_display_mode *mode) 253 { 254 struct drm_device *dev = connector->dev; 255 256 int max_clock = 0; 257 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 258 return MODE_NO_DBLESCAN; 259 260 if (mode->clock < 25000) 261 return MODE_CLOCK_LOW; 262 263 if (IS_GEN2(dev)) 264 max_clock = 350000; 265 else 266 max_clock = 400000; 267 if (mode->clock > max_clock) 268 return MODE_CLOCK_HIGH; 269 270 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 271 if (HAS_PCH_LPT(dev) && 272 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 273 return MODE_CLOCK_HIGH; 274 275 return MODE_OK; 276 } 277 278 static bool intel_crt_compute_config(struct intel_encoder *encoder, 279 struct intel_crtc_config *pipe_config) 280 { 281 struct drm_device *dev = encoder->base.dev; 282 283 if (HAS_PCH_SPLIT(dev)) 284 pipe_config->has_pch_encoder = true; 285 286 /* LPT FDI RX only supports 8bpc. */ 287 if (HAS_PCH_LPT(dev)) 288 pipe_config->pipe_bpp = 24; 289 290 /* FDI must always be 2.7 GHz */ 291 if (HAS_DDI(dev)) 292 pipe_config->port_clock = 135000 * 2; 293 294 return true; 295 } 296 297 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 298 { 299 struct drm_device *dev = connector->dev; 300 struct intel_crt *crt = intel_attached_crt(connector); 301 struct drm_i915_private *dev_priv = dev->dev_private; 302 u32 adpa; 303 bool ret; 304 305 /* The first time through, trigger an explicit detection cycle */ 306 if (crt->force_hotplug_required) { 307 bool turn_off_dac = HAS_PCH_SPLIT(dev); 308 u32 save_adpa; 309 310 crt->force_hotplug_required = 0; 311 312 save_adpa = adpa = I915_READ(crt->adpa_reg); 313 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 314 315 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 316 if (turn_off_dac) 317 adpa &= ~ADPA_DAC_ENABLE; 318 319 I915_WRITE(crt->adpa_reg, adpa); 320 321 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 322 1000)) 323 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 324 325 if (turn_off_dac) { 326 I915_WRITE(crt->adpa_reg, save_adpa); 327 POSTING_READ(crt->adpa_reg); 328 } 329 } 330 331 /* Check the status to see if both blue and green are on now */ 332 adpa = I915_READ(crt->adpa_reg); 333 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 334 ret = true; 335 else 336 ret = false; 337 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 338 339 return ret; 340 } 341 342 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 343 { 344 struct drm_device *dev = connector->dev; 345 struct intel_crt *crt = intel_attached_crt(connector); 346 struct drm_i915_private *dev_priv = dev->dev_private; 347 u32 adpa; 348 bool ret; 349 u32 save_adpa; 350 351 save_adpa = adpa = I915_READ(crt->adpa_reg); 352 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 353 354 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 355 356 I915_WRITE(crt->adpa_reg, adpa); 357 358 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 359 1000)) { 360 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 361 I915_WRITE(crt->adpa_reg, save_adpa); 362 } 363 364 /* Check the status to see if both blue and green are on now */ 365 adpa = I915_READ(crt->adpa_reg); 366 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 367 ret = true; 368 else 369 ret = false; 370 371 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 372 373 return ret; 374 } 375 376 /** 377 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 378 * 379 * Not for i915G/i915GM 380 * 381 * \return true if CRT is connected. 382 * \return false if CRT is disconnected. 383 */ 384 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 385 { 386 struct drm_device *dev = connector->dev; 387 struct drm_i915_private *dev_priv = dev->dev_private; 388 u32 hotplug_en, orig, stat; 389 bool ret = false; 390 int i, tries = 0; 391 392 if (HAS_PCH_SPLIT(dev)) 393 return intel_ironlake_crt_detect_hotplug(connector); 394 395 if (IS_VALLEYVIEW(dev)) 396 return valleyview_crt_detect_hotplug(connector); 397 398 /* 399 * On 4 series desktop, CRT detect sequence need to be done twice 400 * to get a reliable result. 401 */ 402 403 if (IS_G4X(dev) && !IS_GM45(dev)) 404 tries = 2; 405 else 406 tries = 1; 407 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 408 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 409 410 for (i = 0; i < tries ; i++) { 411 /* turn on the FORCE_DETECT */ 412 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 413 /* wait for FORCE_DETECT to go off */ 414 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 415 CRT_HOTPLUG_FORCE_DETECT) == 0, 416 1000)) 417 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 418 } 419 420 stat = I915_READ(PORT_HOTPLUG_STAT); 421 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 422 ret = true; 423 424 /* clear the interrupt we just generated, if any */ 425 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 426 427 /* and put the bits back */ 428 I915_WRITE(PORT_HOTPLUG_EN, orig); 429 430 return ret; 431 } 432 433 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 434 struct i2c_adapter *i2c) 435 { 436 struct edid *edid; 437 438 edid = drm_get_edid(connector, i2c); 439 440 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 441 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 442 intel_gmbus_force_bit(i2c, true); 443 edid = drm_get_edid(connector, i2c); 444 intel_gmbus_force_bit(i2c, false); 445 } 446 447 return edid; 448 } 449 450 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 451 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 452 struct i2c_adapter *adapter) 453 { 454 struct edid *edid; 455 int ret; 456 457 edid = intel_crt_get_edid(connector, adapter); 458 if (!edid) 459 return 0; 460 461 ret = intel_connector_update_modes(connector, edid); 462 kfree(edid); 463 464 return ret; 465 } 466 467 static bool intel_crt_detect_ddc(struct drm_connector *connector) 468 { 469 struct intel_crt *crt = intel_attached_crt(connector); 470 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 471 struct edid *edid; 472 struct i2c_adapter *i2c; 473 474 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 475 476 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 477 edid = intel_crt_get_edid(connector, i2c); 478 479 if (edid) { 480 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 481 482 /* 483 * This may be a DVI-I connector with a shared DDC 484 * link between analog and digital outputs, so we 485 * have to check the EDID input spec of the attached device. 486 */ 487 if (!is_digital) { 488 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 489 return true; 490 } 491 492 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 493 } else { 494 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 495 } 496 497 kfree(edid); 498 499 return false; 500 } 501 502 static enum drm_connector_status 503 intel_crt_load_detect(struct intel_crt *crt) 504 { 505 struct drm_device *dev = crt->base.base.dev; 506 struct drm_i915_private *dev_priv = dev->dev_private; 507 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 508 uint32_t save_bclrpat; 509 uint32_t save_vtotal; 510 uint32_t vtotal, vactive; 511 uint32_t vsample; 512 uint32_t vblank, vblank_start, vblank_end; 513 uint32_t dsl; 514 uint32_t bclrpat_reg; 515 uint32_t vtotal_reg; 516 uint32_t vblank_reg; 517 uint32_t vsync_reg; 518 uint32_t pipeconf_reg; 519 uint32_t pipe_dsl_reg; 520 uint8_t st00; 521 enum drm_connector_status status; 522 523 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 524 525 bclrpat_reg = BCLRPAT(pipe); 526 vtotal_reg = VTOTAL(pipe); 527 vblank_reg = VBLANK(pipe); 528 vsync_reg = VSYNC(pipe); 529 pipeconf_reg = PIPECONF(pipe); 530 pipe_dsl_reg = PIPEDSL(pipe); 531 532 save_bclrpat = I915_READ(bclrpat_reg); 533 save_vtotal = I915_READ(vtotal_reg); 534 vblank = I915_READ(vblank_reg); 535 536 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 537 vactive = (save_vtotal & 0x7ff) + 1; 538 539 vblank_start = (vblank & 0xfff) + 1; 540 vblank_end = ((vblank >> 16) & 0xfff) + 1; 541 542 /* Set the border color to purple. */ 543 I915_WRITE(bclrpat_reg, 0x500050); 544 545 if (!IS_GEN2(dev)) { 546 uint32_t pipeconf = I915_READ(pipeconf_reg); 547 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 548 POSTING_READ(pipeconf_reg); 549 /* Wait for next Vblank to substitue 550 * border color for Color info */ 551 intel_wait_for_vblank(dev, pipe); 552 st00 = I915_READ8(VGA_MSR_WRITE); 553 status = ((st00 & (1 << 4)) != 0) ? 554 connector_status_connected : 555 connector_status_disconnected; 556 557 I915_WRITE(pipeconf_reg, pipeconf); 558 } else { 559 bool restore_vblank = false; 560 int count, detect; 561 562 /* 563 * If there isn't any border, add some. 564 * Yes, this will flicker 565 */ 566 if (vblank_start <= vactive && vblank_end >= vtotal) { 567 uint32_t vsync = I915_READ(vsync_reg); 568 uint32_t vsync_start = (vsync & 0xffff) + 1; 569 570 vblank_start = vsync_start; 571 I915_WRITE(vblank_reg, 572 (vblank_start - 1) | 573 ((vblank_end - 1) << 16)); 574 restore_vblank = true; 575 } 576 /* sample in the vertical border, selecting the larger one */ 577 if (vblank_start - vactive >= vtotal - vblank_end) 578 vsample = (vblank_start + vactive) >> 1; 579 else 580 vsample = (vtotal + vblank_end) >> 1; 581 582 /* 583 * Wait for the border to be displayed 584 */ 585 while (I915_READ(pipe_dsl_reg) >= vactive) 586 ; 587 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 588 ; 589 /* 590 * Watch ST00 for an entire scanline 591 */ 592 detect = 0; 593 count = 0; 594 do { 595 count++; 596 /* Read the ST00 VGA status register */ 597 st00 = I915_READ8(VGA_MSR_WRITE); 598 if (st00 & (1 << 4)) 599 detect++; 600 } while ((I915_READ(pipe_dsl_reg) == dsl)); 601 602 /* restore vblank if necessary */ 603 if (restore_vblank) 604 I915_WRITE(vblank_reg, vblank); 605 /* 606 * If more than 3/4 of the scanline detected a monitor, 607 * then it is assumed to be present. This works even on i830, 608 * where there isn't any way to force the border color across 609 * the screen 610 */ 611 status = detect * 4 > count * 3 ? 612 connector_status_connected : 613 connector_status_disconnected; 614 } 615 616 /* Restore previous settings */ 617 I915_WRITE(bclrpat_reg, save_bclrpat); 618 619 return status; 620 } 621 622 static enum drm_connector_status 623 intel_crt_detect(struct drm_connector *connector, bool force) 624 { 625 struct drm_device *dev = connector->dev; 626 struct drm_i915_private *dev_priv = dev->dev_private; 627 struct intel_crt *crt = intel_attached_crt(connector); 628 struct intel_encoder *intel_encoder = &crt->base; 629 enum intel_display_power_domain power_domain; 630 enum drm_connector_status status; 631 struct intel_load_detect_pipe tmp; 632 struct drm_modeset_acquire_ctx ctx; 633 634 intel_runtime_pm_get(dev_priv); 635 636 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 637 connector->base.id, connector->name, 638 force); 639 640 power_domain = intel_display_port_power_domain(intel_encoder); 641 intel_display_power_get(dev_priv, power_domain); 642 643 if (I915_HAS_HOTPLUG(dev)) { 644 /* We can not rely on the HPD pin always being correctly wired 645 * up, for example many KVM do not pass it through, and so 646 * only trust an assertion that the monitor is connected. 647 */ 648 if (intel_crt_detect_hotplug(connector)) { 649 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 650 status = connector_status_connected; 651 goto out; 652 } else 653 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 654 } 655 656 if (intel_crt_detect_ddc(connector)) { 657 status = connector_status_connected; 658 goto out; 659 } 660 661 /* Load detection is broken on HPD capable machines. Whoever wants a 662 * broken monitor (without edid) to work behind a broken kvm (that fails 663 * to have the right resistors for HP detection) needs to fix this up. 664 * For now just bail out. */ 665 if (I915_HAS_HOTPLUG(dev)) { 666 status = connector_status_disconnected; 667 goto out; 668 } 669 670 if (!force) { 671 status = connector->status; 672 goto out; 673 } 674 675 /* for pre-945g platforms use load detect */ 676 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 677 if (intel_crt_detect_ddc(connector)) 678 status = connector_status_connected; 679 else 680 status = intel_crt_load_detect(crt); 681 intel_release_load_detect_pipe(connector, &tmp, &ctx); 682 } else 683 status = connector_status_unknown; 684 685 out: 686 intel_display_power_put(dev_priv, power_domain); 687 intel_runtime_pm_put(dev_priv); 688 689 return status; 690 } 691 692 static void intel_crt_destroy(struct drm_connector *connector) 693 { 694 drm_connector_cleanup(connector); 695 kfree(connector); 696 } 697 698 static int intel_crt_get_modes(struct drm_connector *connector) 699 { 700 struct drm_device *dev = connector->dev; 701 struct drm_i915_private *dev_priv = dev->dev_private; 702 struct intel_crt *crt = intel_attached_crt(connector); 703 struct intel_encoder *intel_encoder = &crt->base; 704 enum intel_display_power_domain power_domain; 705 int ret; 706 struct i2c_adapter *i2c; 707 708 power_domain = intel_display_port_power_domain(intel_encoder); 709 intel_display_power_get(dev_priv, power_domain); 710 711 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 712 ret = intel_crt_ddc_get_modes(connector, i2c); 713 if (ret || !IS_G4X(dev)) 714 goto out; 715 716 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 717 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); 718 ret = intel_crt_ddc_get_modes(connector, i2c); 719 720 out: 721 intel_display_power_put(dev_priv, power_domain); 722 723 return ret; 724 } 725 726 static int intel_crt_set_property(struct drm_connector *connector, 727 struct drm_property *property, 728 uint64_t value) 729 { 730 return 0; 731 } 732 733 static void intel_crt_reset(struct drm_connector *connector) 734 { 735 struct drm_device *dev = connector->dev; 736 struct drm_i915_private *dev_priv = dev->dev_private; 737 struct intel_crt *crt = intel_attached_crt(connector); 738 739 if (INTEL_INFO(dev)->gen >= 5) { 740 u32 adpa; 741 742 adpa = I915_READ(crt->adpa_reg); 743 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 744 adpa |= ADPA_HOTPLUG_BITS; 745 I915_WRITE(crt->adpa_reg, adpa); 746 POSTING_READ(crt->adpa_reg); 747 748 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); 749 crt->force_hotplug_required = 1; 750 } 751 752 } 753 754 /* 755 * Routines for controlling stuff on the analog port 756 */ 757 758 static const struct drm_connector_funcs intel_crt_connector_funcs = { 759 .reset = intel_crt_reset, 760 .dpms = intel_crt_dpms, 761 .detect = intel_crt_detect, 762 .fill_modes = drm_helper_probe_single_connector_modes, 763 .destroy = intel_crt_destroy, 764 .set_property = intel_crt_set_property, 765 }; 766 767 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 768 .mode_valid = intel_crt_mode_valid, 769 .get_modes = intel_crt_get_modes, 770 .best_encoder = intel_best_encoder, 771 }; 772 773 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 774 .destroy = intel_encoder_destroy, 775 }; 776 777 static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) 778 { 779 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 780 return 1; 781 } 782 783 static const struct dmi_system_id intel_no_crt[] = { 784 { 785 .callback = intel_no_crt_dmi_callback, 786 .ident = "ACER ZGB", 787 .matches = { 788 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 789 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 790 }, 791 }, 792 { 793 .callback = intel_no_crt_dmi_callback, 794 .ident = "DELL XPS 8700", 795 .matches = { 796 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 797 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 798 }, 799 }, 800 { } 801 }; 802 803 void intel_crt_init(struct drm_device *dev) 804 { 805 struct drm_connector *connector; 806 struct intel_crt *crt; 807 struct intel_connector *intel_connector; 808 struct drm_i915_private *dev_priv = dev->dev_private; 809 810 /* Skip machines without VGA that falsely report hotplug events */ 811 if (dmi_check_system(intel_no_crt)) 812 return; 813 814 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 815 if (!crt) 816 return; 817 818 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 819 if (!intel_connector) { 820 kfree(crt); 821 return; 822 } 823 824 connector = &intel_connector->base; 825 crt->connector = intel_connector; 826 drm_connector_init(dev, &intel_connector->base, 827 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 828 829 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 830 DRM_MODE_ENCODER_DAC); 831 832 intel_connector_attach_encoder(intel_connector, &crt->base); 833 834 crt->base.type = INTEL_OUTPUT_ANALOG; 835 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 836 if (IS_I830(dev)) 837 crt->base.crtc_mask = (1 << 0); 838 else 839 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 840 841 if (IS_GEN2(dev)) 842 connector->interlace_allowed = 0; 843 else 844 connector->interlace_allowed = 1; 845 connector->doublescan_allowed = 0; 846 847 if (HAS_PCH_SPLIT(dev)) 848 crt->adpa_reg = PCH_ADPA; 849 else if (IS_VALLEYVIEW(dev)) 850 crt->adpa_reg = VLV_ADPA; 851 else 852 crt->adpa_reg = ADPA; 853 854 crt->base.compute_config = intel_crt_compute_config; 855 crt->base.disable = intel_disable_crt; 856 crt->base.enable = intel_enable_crt; 857 if (I915_HAS_HOTPLUG(dev)) 858 crt->base.hpd_pin = HPD_CRT; 859 if (HAS_DDI(dev)) { 860 crt->base.get_config = hsw_crt_get_config; 861 crt->base.get_hw_state = intel_ddi_get_hw_state; 862 } else { 863 crt->base.get_config = intel_crt_get_config; 864 crt->base.get_hw_state = intel_crt_get_hw_state; 865 } 866 intel_connector->get_hw_state = intel_connector_get_hw_state; 867 intel_connector->unregister = intel_connector_unregister; 868 869 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 870 871 drm_sysfs_connector_add(connector); 872 873 if (!I915_HAS_HOTPLUG(dev)) 874 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 875 876 /* 877 * Configure the automatic hotplug detection stuff 878 */ 879 crt->force_hotplug_required = 0; 880 881 /* 882 * TODO: find a proper way to discover whether we need to set the the 883 * polarity and link reversal bits or not, instead of relying on the 884 * BIOS. 885 */ 886 if (HAS_PCH_LPT(dev)) { 887 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 888 FDI_RX_LINK_REVERSAL_OVERRIDE; 889 890 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; 891 } 892 893 intel_crt_reset(connector); 894 } 895