1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <drm/drmP.h> 28 #include <drm/drm_crtc.h> 29 #include <drm/drm_crtc_helper.h> 30 #include <drm/drm_edid.h> 31 #include "intel_drv.h" 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 35 /* Here's the desired hotplug mode */ 36 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 37 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 38 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 39 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 40 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 41 ADPA_CRT_HOTPLUG_ENABLE) 42 43 struct intel_crt { 44 struct intel_encoder base; 45 /* DPMS state is stored in the connector, which we need in the 46 * encoder's enable/disable callbacks */ 47 struct intel_connector *connector; 48 bool force_hotplug_required; 49 u32 adpa_reg; 50 }; 51 52 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 53 { 54 return container_of(intel_attached_encoder(connector), 55 struct intel_crt, base); 56 } 57 58 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 59 { 60 return container_of(encoder, struct intel_crt, base); 61 } 62 63 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 64 enum i915_pipe *pipe) 65 { 66 struct drm_device *dev = encoder->base.dev; 67 struct drm_i915_private *dev_priv = dev->dev_private; 68 struct intel_crt *crt = intel_encoder_to_crt(encoder); 69 u32 tmp; 70 71 tmp = I915_READ(crt->adpa_reg); 72 73 if (!(tmp & ADPA_DAC_ENABLE)) 74 return false; 75 76 if (HAS_PCH_CPT(dev)) 77 *pipe = PORT_TO_PIPE_CPT(tmp); 78 else 79 *pipe = PORT_TO_PIPE(tmp); 80 81 return true; 82 } 83 84 /* Note: The caller is required to filter out dpms modes not supported by the 85 * platform. */ 86 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 87 { 88 struct drm_device *dev = encoder->base.dev; 89 struct drm_i915_private *dev_priv = dev->dev_private; 90 struct intel_crt *crt = intel_encoder_to_crt(encoder); 91 u32 temp; 92 93 temp = I915_READ(crt->adpa_reg); 94 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 95 temp &= ~ADPA_DAC_ENABLE; 96 97 switch (mode) { 98 case DRM_MODE_DPMS_ON: 99 temp |= ADPA_DAC_ENABLE; 100 break; 101 case DRM_MODE_DPMS_STANDBY: 102 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 103 break; 104 case DRM_MODE_DPMS_SUSPEND: 105 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 106 break; 107 case DRM_MODE_DPMS_OFF: 108 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 109 break; 110 } 111 112 I915_WRITE(crt->adpa_reg, temp); 113 } 114 115 static void intel_disable_crt(struct intel_encoder *encoder) 116 { 117 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 118 } 119 120 static void intel_enable_crt(struct intel_encoder *encoder) 121 { 122 struct intel_crt *crt = intel_encoder_to_crt(encoder); 123 124 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 125 } 126 127 128 static void intel_crt_dpms(struct drm_connector *connector, int mode) 129 { 130 struct drm_device *dev = connector->dev; 131 struct intel_encoder *encoder = intel_attached_encoder(connector); 132 struct drm_crtc *crtc; 133 int old_dpms; 134 135 /* PCH platforms and VLV only support on/off. */ 136 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) 137 mode = DRM_MODE_DPMS_OFF; 138 139 if (mode == connector->dpms) 140 return; 141 142 old_dpms = connector->dpms; 143 connector->dpms = mode; 144 145 /* Only need to change hw state when actually enabled */ 146 crtc = encoder->base.crtc; 147 if (!crtc) { 148 encoder->connectors_active = false; 149 return; 150 } 151 152 /* We need the pipe to run for anything but OFF. */ 153 if (mode == DRM_MODE_DPMS_OFF) 154 encoder->connectors_active = false; 155 else 156 encoder->connectors_active = true; 157 158 if (mode < old_dpms) { 159 /* From off to on, enable the pipe first. */ 160 intel_crtc_update_dpms(crtc); 161 162 intel_crt_set_dpms(encoder, mode); 163 } else { 164 intel_crt_set_dpms(encoder, mode); 165 166 intel_crtc_update_dpms(crtc); 167 } 168 169 intel_modeset_check_state(connector->dev); 170 } 171 172 static int intel_crt_mode_valid(struct drm_connector *connector, 173 struct drm_display_mode *mode) 174 { 175 struct drm_device *dev = connector->dev; 176 177 int max_clock = 0; 178 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 179 return MODE_NO_DBLESCAN; 180 181 if (mode->clock < 25000) 182 return MODE_CLOCK_LOW; 183 184 if (IS_GEN2(dev)) 185 max_clock = 350000; 186 else 187 max_clock = 400000; 188 if (mode->clock > max_clock) 189 return MODE_CLOCK_HIGH; 190 191 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 192 if (HAS_PCH_LPT(dev) && 193 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 194 return MODE_CLOCK_HIGH; 195 196 return MODE_OK; 197 } 198 199 static bool intel_crt_mode_fixup(struct drm_encoder *encoder, 200 const struct drm_display_mode *mode, 201 struct drm_display_mode *adjusted_mode) 202 { 203 return true; 204 } 205 206 static void intel_crt_mode_set(struct drm_encoder *encoder, 207 struct drm_display_mode *mode, 208 struct drm_display_mode *adjusted_mode) 209 { 210 211 struct drm_device *dev = encoder->dev; 212 struct drm_crtc *crtc = encoder->crtc; 213 struct intel_crt *crt = 214 intel_encoder_to_crt(to_intel_encoder(encoder)); 215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 216 struct drm_i915_private *dev_priv = dev->dev_private; 217 u32 adpa; 218 219 if (HAS_PCH_SPLIT(dev)) 220 adpa = ADPA_HOTPLUG_BITS; 221 else 222 adpa = 0; 223 224 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 225 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 226 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 227 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 228 229 /* For CPT allow 3 pipe config, for others just use A or B */ 230 if (HAS_PCH_LPT(dev)) 231 ; /* Those bits don't exist here */ 232 else if (HAS_PCH_CPT(dev)) 233 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); 234 else if (intel_crtc->pipe == 0) 235 adpa |= ADPA_PIPE_A_SELECT; 236 else 237 adpa |= ADPA_PIPE_B_SELECT; 238 239 if (!HAS_PCH_SPLIT(dev)) 240 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); 241 242 I915_WRITE(crt->adpa_reg, adpa); 243 } 244 245 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 246 { 247 struct drm_device *dev = connector->dev; 248 struct intel_crt *crt = intel_attached_crt(connector); 249 struct drm_i915_private *dev_priv = dev->dev_private; 250 u32 adpa; 251 bool ret; 252 253 /* The first time through, trigger an explicit detection cycle */ 254 if (crt->force_hotplug_required) { 255 bool turn_off_dac = HAS_PCH_SPLIT(dev); 256 u32 save_adpa; 257 258 crt->force_hotplug_required = 0; 259 260 save_adpa = adpa = I915_READ(PCH_ADPA); 261 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 262 263 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 264 if (turn_off_dac) 265 adpa &= ~ADPA_DAC_ENABLE; 266 267 I915_WRITE(PCH_ADPA, adpa); 268 269 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 270 1000)) 271 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 272 273 if (turn_off_dac) { 274 I915_WRITE(PCH_ADPA, save_adpa); 275 POSTING_READ(PCH_ADPA); 276 } 277 } 278 279 /* Check the status to see if both blue and green are on now */ 280 adpa = I915_READ(PCH_ADPA); 281 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 282 ret = true; 283 else 284 ret = false; 285 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 286 287 return ret; 288 } 289 290 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 291 { 292 struct drm_device *dev = connector->dev; 293 struct drm_i915_private *dev_priv = dev->dev_private; 294 u32 adpa; 295 bool ret; 296 u32 save_adpa; 297 298 save_adpa = adpa = I915_READ(ADPA); 299 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 300 301 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 302 303 I915_WRITE(ADPA, adpa); 304 305 if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 306 1000)) { 307 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 308 I915_WRITE(ADPA, save_adpa); 309 } 310 311 /* Check the status to see if both blue and green are on now */ 312 adpa = I915_READ(ADPA); 313 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 314 ret = true; 315 else 316 ret = false; 317 318 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 319 320 /* FIXME: debug force function and remove */ 321 ret = true; 322 323 return ret; 324 } 325 326 /** 327 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 328 * 329 * Not for i915G/i915GM 330 * 331 * \return true if CRT is connected. 332 * \return false if CRT is disconnected. 333 */ 334 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 335 { 336 struct drm_device *dev = connector->dev; 337 struct drm_i915_private *dev_priv = dev->dev_private; 338 u32 hotplug_en, orig, stat; 339 bool ret = false; 340 int i, tries = 0; 341 342 if (HAS_PCH_SPLIT(dev)) 343 return intel_ironlake_crt_detect_hotplug(connector); 344 345 if (IS_VALLEYVIEW(dev)) 346 return valleyview_crt_detect_hotplug(connector); 347 348 /* 349 * On 4 series desktop, CRT detect sequence need to be done twice 350 * to get a reliable result. 351 */ 352 353 if (IS_G4X(dev) && !IS_GM45(dev)) 354 tries = 2; 355 else 356 tries = 1; 357 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 358 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 359 360 for (i = 0; i < tries ; i++) { 361 /* turn on the FORCE_DETECT */ 362 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 363 /* wait for FORCE_DETECT to go off */ 364 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 365 CRT_HOTPLUG_FORCE_DETECT) == 0, 366 1000)) 367 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 368 } 369 370 stat = I915_READ(PORT_HOTPLUG_STAT); 371 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 372 ret = true; 373 374 /* clear the interrupt we just generated, if any */ 375 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 376 377 /* and put the bits back */ 378 I915_WRITE(PORT_HOTPLUG_EN, orig); 379 380 return ret; 381 } 382 383 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 384 struct device *i2c) 385 { 386 struct edid *edid; 387 388 edid = drm_get_edid(connector, i2c); 389 390 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 391 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 392 intel_gmbus_force_bit(i2c, true); 393 edid = drm_get_edid(connector, i2c); 394 intel_gmbus_force_bit(i2c, false); 395 } 396 397 return edid; 398 } 399 400 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 401 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 402 struct device *adapter) 403 { 404 struct edid *edid; 405 int ret; 406 407 edid = intel_crt_get_edid(connector, adapter); 408 if (!edid) 409 return 0; 410 411 ret = intel_connector_update_modes(connector, edid); 412 kfree(edid, M_DRM); 413 414 return ret; 415 } 416 417 static bool intel_crt_detect_ddc(struct drm_connector *connector) 418 { 419 struct intel_crt *crt = intel_attached_crt(connector); 420 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 421 struct edid *edid; 422 struct device *i2c; 423 424 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 425 426 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); 427 edid = intel_crt_get_edid(connector, i2c); 428 429 if (edid) { 430 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 431 432 /* 433 * This may be a DVI-I connector with a shared DDC 434 * link between analog and digital outputs, so we 435 * have to check the EDID input spec of the attached device. 436 */ 437 if (!is_digital) { 438 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 439 return true; 440 } 441 442 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 443 } else { 444 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 445 } 446 447 drm_free(edid, M_DRM); 448 449 return false; 450 } 451 452 static enum drm_connector_status 453 intel_crt_load_detect(struct intel_crt *crt) 454 { 455 struct drm_device *dev = crt->base.base.dev; 456 struct drm_i915_private *dev_priv = dev->dev_private; 457 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 458 uint32_t save_bclrpat; 459 uint32_t save_vtotal; 460 uint32_t vtotal, vactive; 461 uint32_t vsample; 462 uint32_t vblank, vblank_start, vblank_end; 463 uint32_t dsl; 464 uint32_t bclrpat_reg; 465 uint32_t vtotal_reg; 466 uint32_t vblank_reg; 467 uint32_t vsync_reg; 468 uint32_t pipeconf_reg; 469 uint32_t pipe_dsl_reg; 470 uint8_t st00; 471 enum drm_connector_status status; 472 473 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 474 475 bclrpat_reg = BCLRPAT(pipe); 476 vtotal_reg = VTOTAL(pipe); 477 vblank_reg = VBLANK(pipe); 478 vsync_reg = VSYNC(pipe); 479 pipeconf_reg = PIPECONF(pipe); 480 pipe_dsl_reg = PIPEDSL(pipe); 481 482 save_bclrpat = I915_READ(bclrpat_reg); 483 save_vtotal = I915_READ(vtotal_reg); 484 vblank = I915_READ(vblank_reg); 485 486 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 487 vactive = (save_vtotal & 0x7ff) + 1; 488 489 vblank_start = (vblank & 0xfff) + 1; 490 vblank_end = ((vblank >> 16) & 0xfff) + 1; 491 492 /* Set the border color to purple. */ 493 I915_WRITE(bclrpat_reg, 0x500050); 494 495 if (!IS_GEN2(dev)) { 496 uint32_t pipeconf = I915_READ(pipeconf_reg); 497 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 498 POSTING_READ(pipeconf_reg); 499 /* Wait for next Vblank to substitue 500 * border color for Color info */ 501 intel_wait_for_vblank(dev, pipe); 502 st00 = I915_READ8(VGA_MSR_WRITE); 503 status = ((st00 & (1 << 4)) != 0) ? 504 connector_status_connected : 505 connector_status_disconnected; 506 507 I915_WRITE(pipeconf_reg, pipeconf); 508 } else { 509 bool restore_vblank = false; 510 int count, detect; 511 512 /* 513 * If there isn't any border, add some. 514 * Yes, this will flicker 515 */ 516 if (vblank_start <= vactive && vblank_end >= vtotal) { 517 uint32_t vsync = I915_READ(vsync_reg); 518 uint32_t vsync_start = (vsync & 0xffff) + 1; 519 520 vblank_start = vsync_start; 521 I915_WRITE(vblank_reg, 522 (vblank_start - 1) | 523 ((vblank_end - 1) << 16)); 524 restore_vblank = true; 525 } 526 /* sample in the vertical border, selecting the larger one */ 527 if (vblank_start - vactive >= vtotal - vblank_end) 528 vsample = (vblank_start + vactive) >> 1; 529 else 530 vsample = (vtotal + vblank_end) >> 1; 531 532 /* 533 * Wait for the border to be displayed 534 */ 535 while (I915_READ(pipe_dsl_reg) >= vactive) 536 ; 537 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 538 ; 539 /* 540 * Watch ST00 for an entire scanline 541 */ 542 detect = 0; 543 count = 0; 544 do { 545 count++; 546 /* Read the ST00 VGA status register */ 547 st00 = I915_READ8(VGA_MSR_WRITE); 548 if (st00 & (1 << 4)) 549 detect++; 550 } while ((I915_READ(pipe_dsl_reg) == dsl)); 551 552 /* restore vblank if necessary */ 553 if (restore_vblank) 554 I915_WRITE(vblank_reg, vblank); 555 /* 556 * If more than 3/4 of the scanline detected a monitor, 557 * then it is assumed to be present. This works even on i830, 558 * where there isn't any way to force the border color across 559 * the screen 560 */ 561 status = detect * 4 > count * 3 ? 562 connector_status_connected : 563 connector_status_disconnected; 564 } 565 566 /* Restore previous settings */ 567 I915_WRITE(bclrpat_reg, save_bclrpat); 568 569 return status; 570 } 571 572 static enum drm_connector_status 573 intel_crt_detect(struct drm_connector *connector, bool force) 574 { 575 struct drm_device *dev = connector->dev; 576 struct intel_crt *crt = intel_attached_crt(connector); 577 enum drm_connector_status status; 578 struct intel_load_detect_pipe tmp; 579 580 if (I915_HAS_HOTPLUG(dev)) { 581 /* We can not rely on the HPD pin always being correctly wired 582 * up, for example many KVM do not pass it through, and so 583 * only trust an assertion that the monitor is connected. 584 */ 585 if (intel_crt_detect_hotplug(connector)) { 586 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 587 return connector_status_connected; 588 } else 589 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 590 } 591 592 if (intel_crt_detect_ddc(connector)) 593 return connector_status_connected; 594 595 /* Load detection is broken on HPD capable machines. Whoever wants a 596 * broken monitor (without edid) to work behind a broken kvm (that fails 597 * to have the right resistors for HP detection) needs to fix this up. 598 * For now just bail out. */ 599 if (I915_HAS_HOTPLUG(dev)) 600 return connector_status_disconnected; 601 602 if (!force) 603 return connector->status; 604 605 /* for pre-945g platforms use load detect */ 606 if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { 607 if (intel_crt_detect_ddc(connector)) 608 status = connector_status_connected; 609 else 610 status = intel_crt_load_detect(crt); 611 intel_release_load_detect_pipe(connector, &tmp); 612 } else 613 status = connector_status_unknown; 614 615 return status; 616 } 617 618 static void intel_crt_destroy(struct drm_connector *connector) 619 { 620 #if 0 621 drm_sysfs_connector_remove(connector); 622 #endif 623 drm_connector_cleanup(connector); 624 drm_free(connector, M_DRM); 625 } 626 627 static int intel_crt_get_modes(struct drm_connector *connector) 628 { 629 struct drm_device *dev = connector->dev; 630 struct drm_i915_private *dev_priv = dev->dev_private; 631 int ret; 632 struct device *i2c; 633 634 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); 635 ret = intel_crt_ddc_get_modes(connector, i2c); 636 if (ret || !IS_G4X(dev)) 637 return ret; 638 639 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 640 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); 641 return intel_crt_ddc_get_modes(connector, i2c); 642 } 643 644 static int intel_crt_set_property(struct drm_connector *connector, 645 struct drm_property *property, 646 uint64_t value) 647 { 648 return 0; 649 } 650 651 static void intel_crt_reset(struct drm_connector *connector) 652 { 653 struct drm_device *dev = connector->dev; 654 struct drm_i915_private *dev_priv = dev->dev_private; 655 struct intel_crt *crt = intel_attached_crt(connector); 656 657 if (HAS_PCH_SPLIT(dev)) { 658 u32 adpa; 659 660 adpa = I915_READ(PCH_ADPA); 661 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 662 adpa |= ADPA_HOTPLUG_BITS; 663 I915_WRITE(PCH_ADPA, adpa); 664 POSTING_READ(PCH_ADPA); 665 666 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); 667 crt->force_hotplug_required = 1; 668 } 669 670 } 671 672 /* 673 * Routines for controlling stuff on the analog port 674 */ 675 676 static const struct drm_encoder_helper_funcs crt_encoder_funcs = { 677 .mode_fixup = intel_crt_mode_fixup, 678 .mode_set = intel_crt_mode_set, 679 .disable = intel_encoder_noop, 680 }; 681 682 static const struct drm_connector_funcs intel_crt_connector_funcs = { 683 .reset = intel_crt_reset, 684 .dpms = intel_crt_dpms, 685 .detect = intel_crt_detect, 686 .fill_modes = drm_helper_probe_single_connector_modes, 687 .destroy = intel_crt_destroy, 688 .set_property = intel_crt_set_property, 689 }; 690 691 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 692 .mode_valid = intel_crt_mode_valid, 693 .get_modes = intel_crt_get_modes, 694 .best_encoder = intel_best_encoder, 695 }; 696 697 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 698 .destroy = intel_encoder_destroy, 699 }; 700 701 static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) 702 { 703 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 704 return 1; 705 } 706 707 static const struct dmi_system_id intel_no_crt[] = { 708 { 709 .callback = intel_no_crt_dmi_callback, 710 .ident = "ACER ZGB", 711 .matches = { 712 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 713 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 714 }, 715 }, 716 { } 717 }; 718 719 void intel_crt_init(struct drm_device *dev) 720 { 721 struct drm_connector *connector; 722 struct intel_crt *crt; 723 struct intel_connector *intel_connector; 724 struct drm_i915_private *dev_priv = dev->dev_private; 725 726 /* Skip machines without VGA that falsely report hotplug events */ 727 if (dmi_check_system(intel_no_crt)) 728 return; 729 730 crt = kmalloc(sizeof(struct intel_crt), M_DRM, M_WAITOK | M_ZERO); 731 if (!crt) 732 return; 733 734 intel_connector = kmalloc(sizeof(struct intel_connector), M_DRM, 735 M_WAITOK | M_ZERO); 736 if (!intel_connector) { 737 kfree(crt, M_DRM); 738 return; 739 } 740 741 connector = &intel_connector->base; 742 crt->connector = intel_connector; 743 drm_connector_init(dev, &intel_connector->base, 744 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 745 746 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 747 DRM_MODE_ENCODER_DAC); 748 749 intel_connector_attach_encoder(intel_connector, &crt->base); 750 751 crt->base.type = INTEL_OUTPUT_ANALOG; 752 crt->base.cloneable = true; 753 if (IS_I830(dev)) 754 crt->base.crtc_mask = (1 << 0); 755 else 756 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 757 758 if (IS_GEN2(dev)) 759 connector->interlace_allowed = 0; 760 else 761 connector->interlace_allowed = 1; 762 connector->doublescan_allowed = 0; 763 764 if (HAS_PCH_SPLIT(dev)) 765 crt->adpa_reg = PCH_ADPA; 766 else if (IS_VALLEYVIEW(dev)) 767 crt->adpa_reg = VLV_ADPA; 768 else 769 crt->adpa_reg = ADPA; 770 771 crt->base.disable = intel_disable_crt; 772 crt->base.enable = intel_enable_crt; 773 if (IS_HASWELL(dev)) 774 crt->base.get_hw_state = intel_ddi_get_hw_state; 775 else 776 crt->base.get_hw_state = intel_crt_get_hw_state; 777 intel_connector->get_hw_state = intel_connector_get_hw_state; 778 779 drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs); 780 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 781 782 #if 0 783 drm_sysfs_connector_add(connector); 784 #endif 785 786 if (I915_HAS_HOTPLUG(dev)) 787 connector->polled = DRM_CONNECTOR_POLL_HPD; 788 else 789 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 790 791 /* 792 * Configure the automatic hotplug detection stuff 793 */ 794 crt->force_hotplug_required = 0; 795 796 dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; 797 798 /* 799 * TODO: find a proper way to discover whether we need to set the the 800 * polarity and link reversal bits or not, instead of relying on the 801 * BIOS. 802 */ 803 if (HAS_PCH_LPT(dev)) { 804 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 805 FDI_RX_LINK_REVERSAL_OVERRIDE; 806 807 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; 808 } 809 } 810