1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 39 /* Here's the desired hotplug mode */ 40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 45 ADPA_CRT_HOTPLUG_ENABLE) 46 47 struct intel_crt { 48 struct intel_encoder base; 49 /* DPMS state is stored in the connector, which we need in the 50 * encoder's enable/disable callbacks */ 51 struct intel_connector *connector; 52 bool force_hotplug_required; 53 i915_reg_t adpa_reg; 54 }; 55 56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 57 { 58 return container_of(encoder, struct intel_crt, base); 59 } 60 61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 62 { 63 return intel_encoder_to_crt(intel_attached_encoder(connector)); 64 } 65 66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 67 enum i915_pipe *pipe) 68 { 69 struct drm_device *dev = encoder->base.dev; 70 struct drm_i915_private *dev_priv = dev->dev_private; 71 struct intel_crt *crt = intel_encoder_to_crt(encoder); 72 enum intel_display_power_domain power_domain; 73 u32 tmp; 74 bool ret; 75 76 power_domain = intel_display_port_power_domain(encoder); 77 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 78 return false; 79 80 ret = false; 81 82 tmp = I915_READ(crt->adpa_reg); 83 84 if (!(tmp & ADPA_DAC_ENABLE)) 85 goto out; 86 87 if (HAS_PCH_CPT(dev)) 88 *pipe = PORT_TO_PIPE_CPT(tmp); 89 else 90 *pipe = PORT_TO_PIPE(tmp); 91 92 ret = true; 93 out: 94 intel_display_power_put(dev_priv, power_domain); 95 96 return ret; 97 } 98 99 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 100 { 101 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 102 struct intel_crt *crt = intel_encoder_to_crt(encoder); 103 u32 tmp, flags = 0; 104 105 tmp = I915_READ(crt->adpa_reg); 106 107 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 108 flags |= DRM_MODE_FLAG_PHSYNC; 109 else 110 flags |= DRM_MODE_FLAG_NHSYNC; 111 112 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 113 flags |= DRM_MODE_FLAG_PVSYNC; 114 else 115 flags |= DRM_MODE_FLAG_NVSYNC; 116 117 return flags; 118 } 119 120 static void intel_crt_get_config(struct intel_encoder *encoder, 121 struct intel_crtc_state *pipe_config) 122 { 123 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 124 125 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 126 } 127 128 static void hsw_crt_get_config(struct intel_encoder *encoder, 129 struct intel_crtc_state *pipe_config) 130 { 131 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 132 133 intel_ddi_get_config(encoder, pipe_config); 134 135 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 136 DRM_MODE_FLAG_NHSYNC | 137 DRM_MODE_FLAG_PVSYNC | 138 DRM_MODE_FLAG_NVSYNC); 139 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 140 141 pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 142 } 143 144 /* Note: The caller is required to filter out dpms modes not supported by the 145 * platform. */ 146 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 147 { 148 struct drm_device *dev = encoder->base.dev; 149 struct drm_i915_private *dev_priv = dev->dev_private; 150 struct intel_crt *crt = intel_encoder_to_crt(encoder); 151 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 152 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 153 u32 adpa; 154 155 if (INTEL_INFO(dev)->gen >= 5) 156 adpa = ADPA_HOTPLUG_BITS; 157 else 158 adpa = 0; 159 160 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 161 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 162 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 163 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 164 165 /* For CPT allow 3 pipe config, for others just use A or B */ 166 if (HAS_PCH_LPT(dev)) 167 ; /* Those bits don't exist here */ 168 else if (HAS_PCH_CPT(dev)) 169 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 170 else if (crtc->pipe == 0) 171 adpa |= ADPA_PIPE_A_SELECT; 172 else 173 adpa |= ADPA_PIPE_B_SELECT; 174 175 if (!HAS_PCH_SPLIT(dev)) 176 I915_WRITE(BCLRPAT(crtc->pipe), 0); 177 178 switch (mode) { 179 case DRM_MODE_DPMS_ON: 180 adpa |= ADPA_DAC_ENABLE; 181 break; 182 case DRM_MODE_DPMS_STANDBY: 183 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 184 break; 185 case DRM_MODE_DPMS_SUSPEND: 186 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 187 break; 188 case DRM_MODE_DPMS_OFF: 189 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 190 break; 191 } 192 193 I915_WRITE(crt->adpa_reg, adpa); 194 } 195 196 static void intel_disable_crt(struct intel_encoder *encoder) 197 { 198 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 199 } 200 201 static void pch_disable_crt(struct intel_encoder *encoder) 202 { 203 } 204 205 static void pch_post_disable_crt(struct intel_encoder *encoder) 206 { 207 intel_disable_crt(encoder); 208 } 209 210 static void intel_enable_crt(struct intel_encoder *encoder) 211 { 212 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON); 213 } 214 215 static enum drm_mode_status 216 intel_crt_mode_valid(struct drm_connector *connector, 217 struct drm_display_mode *mode) 218 { 219 struct drm_device *dev = connector->dev; 220 int max_dotclk = to_i915(dev)->max_dotclk_freq; 221 int max_clock; 222 223 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 224 return MODE_NO_DBLESCAN; 225 226 if (mode->clock < 25000) 227 return MODE_CLOCK_LOW; 228 229 if (HAS_PCH_LPT(dev)) 230 max_clock = 180000; 231 else if (IS_VALLEYVIEW(dev)) 232 /* 233 * 270 MHz due to current DPLL limits, 234 * DAC limit supposedly 355 MHz. 235 */ 236 max_clock = 270000; 237 else if (IS_GEN3(dev) || IS_GEN4(dev)) 238 max_clock = 400000; 239 else 240 max_clock = 350000; 241 if (mode->clock > max_clock) 242 return MODE_CLOCK_HIGH; 243 244 if (mode->clock > max_dotclk) 245 return MODE_CLOCK_HIGH; 246 247 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 248 if (HAS_PCH_LPT(dev) && 249 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 250 return MODE_CLOCK_HIGH; 251 252 return MODE_OK; 253 } 254 255 static bool intel_crt_compute_config(struct intel_encoder *encoder, 256 struct intel_crtc_state *pipe_config) 257 { 258 struct drm_device *dev = encoder->base.dev; 259 260 if (HAS_PCH_SPLIT(dev)) 261 pipe_config->has_pch_encoder = true; 262 263 /* LPT FDI RX only supports 8bpc. */ 264 if (HAS_PCH_LPT(dev)) { 265 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 266 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 267 return false; 268 } 269 270 pipe_config->pipe_bpp = 24; 271 } 272 273 /* FDI must always be 2.7 GHz */ 274 if (HAS_DDI(dev)) 275 pipe_config->port_clock = 135000 * 2; 276 277 return true; 278 } 279 280 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 281 { 282 struct drm_device *dev = connector->dev; 283 struct intel_crt *crt = intel_attached_crt(connector); 284 struct drm_i915_private *dev_priv = dev->dev_private; 285 u32 adpa; 286 bool ret; 287 288 /* The first time through, trigger an explicit detection cycle */ 289 if (crt->force_hotplug_required) { 290 bool turn_off_dac = HAS_PCH_SPLIT(dev); 291 u32 save_adpa; 292 293 crt->force_hotplug_required = 0; 294 295 save_adpa = adpa = I915_READ(crt->adpa_reg); 296 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 297 298 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 299 if (turn_off_dac) 300 adpa &= ~ADPA_DAC_ENABLE; 301 302 I915_WRITE(crt->adpa_reg, adpa); 303 304 if (intel_wait_for_register(dev_priv, 305 crt->adpa_reg, 306 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 307 1000)) 308 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 309 310 if (turn_off_dac) { 311 I915_WRITE(crt->adpa_reg, save_adpa); 312 POSTING_READ(crt->adpa_reg); 313 } 314 } 315 316 /* Check the status to see if both blue and green are on now */ 317 adpa = I915_READ(crt->adpa_reg); 318 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 319 ret = true; 320 else 321 ret = false; 322 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 323 324 return ret; 325 } 326 327 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 328 { 329 struct drm_device *dev = connector->dev; 330 struct intel_crt *crt = intel_attached_crt(connector); 331 struct drm_i915_private *dev_priv = dev->dev_private; 332 bool reenable_hpd; 333 u32 adpa; 334 bool ret; 335 u32 save_adpa; 336 337 /* 338 * Doing a force trigger causes a hpd interrupt to get sent, which can 339 * get us stuck in a loop if we're polling: 340 * - We enable power wells and reset the ADPA 341 * - output_poll_exec does force probe on VGA, triggering a hpd 342 * - HPD handler waits for poll to unlock dev->mode_config.mutex 343 * - output_poll_exec shuts off the ADPA, unlocks 344 * dev->mode_config.mutex 345 * - HPD handler runs, resets ADPA and brings us back to the start 346 * 347 * Just disable HPD interrupts here to prevent this 348 */ 349 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 350 351 save_adpa = adpa = I915_READ(crt->adpa_reg); 352 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 353 354 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 355 356 I915_WRITE(crt->adpa_reg, adpa); 357 358 if (intel_wait_for_register(dev_priv, 359 crt->adpa_reg, 360 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, 361 1000)) { 362 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 363 I915_WRITE(crt->adpa_reg, save_adpa); 364 } 365 366 /* Check the status to see if both blue and green are on now */ 367 adpa = I915_READ(crt->adpa_reg); 368 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 369 ret = true; 370 else 371 ret = false; 372 373 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 374 375 if (reenable_hpd) 376 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 377 378 return ret; 379 } 380 381 /** 382 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 383 * 384 * Not for i915G/i915GM 385 * 386 * \return true if CRT is connected. 387 * \return false if CRT is disconnected. 388 */ 389 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 390 { 391 struct drm_device *dev = connector->dev; 392 struct drm_i915_private *dev_priv = dev->dev_private; 393 u32 stat; 394 bool ret = false; 395 int i, tries = 0; 396 397 if (HAS_PCH_SPLIT(dev)) 398 return intel_ironlake_crt_detect_hotplug(connector); 399 400 if (IS_VALLEYVIEW(dev)) 401 return valleyview_crt_detect_hotplug(connector); 402 403 /* 404 * On 4 series desktop, CRT detect sequence need to be done twice 405 * to get a reliable result. 406 */ 407 408 if (IS_G4X(dev) && !IS_GM45(dev)) 409 tries = 2; 410 else 411 tries = 1; 412 413 for (i = 0; i < tries ; i++) { 414 /* turn on the FORCE_DETECT */ 415 i915_hotplug_interrupt_update(dev_priv, 416 CRT_HOTPLUG_FORCE_DETECT, 417 CRT_HOTPLUG_FORCE_DETECT); 418 /* wait for FORCE_DETECT to go off */ 419 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN, 420 CRT_HOTPLUG_FORCE_DETECT, 0, 421 1000)) 422 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 423 } 424 425 stat = I915_READ(PORT_HOTPLUG_STAT); 426 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 427 ret = true; 428 429 /* clear the interrupt we just generated, if any */ 430 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 431 432 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 433 434 return ret; 435 } 436 437 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 438 struct i2c_adapter *i2c) 439 { 440 struct edid *edid; 441 442 edid = drm_get_edid(connector, i2c); 443 444 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 445 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 446 intel_gmbus_force_bit(i2c, true); 447 edid = drm_get_edid(connector, i2c); 448 intel_gmbus_force_bit(i2c, false); 449 } 450 451 return edid; 452 } 453 454 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 455 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 456 struct i2c_adapter *adapter) 457 { 458 struct edid *edid; 459 int ret; 460 461 edid = intel_crt_get_edid(connector, adapter); 462 if (!edid) 463 return 0; 464 465 ret = intel_connector_update_modes(connector, edid); 466 kfree(edid); 467 468 return ret; 469 } 470 471 static bool intel_crt_detect_ddc(struct drm_connector *connector) 472 { 473 struct intel_crt *crt = intel_attached_crt(connector); 474 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 475 struct edid *edid; 476 struct i2c_adapter *i2c; 477 478 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 479 480 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 481 edid = intel_crt_get_edid(connector, i2c); 482 483 if (edid) { 484 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 485 486 /* 487 * This may be a DVI-I connector with a shared DDC 488 * link between analog and digital outputs, so we 489 * have to check the EDID input spec of the attached device. 490 */ 491 if (!is_digital) { 492 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 493 return true; 494 } 495 496 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 497 } else { 498 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 499 } 500 501 kfree(edid); 502 503 return false; 504 } 505 506 static enum drm_connector_status 507 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) 508 { 509 struct drm_device *dev = crt->base.base.dev; 510 struct drm_i915_private *dev_priv = dev->dev_private; 511 uint32_t save_bclrpat; 512 uint32_t save_vtotal; 513 uint32_t vtotal, vactive; 514 uint32_t vsample; 515 uint32_t vblank, vblank_start, vblank_end; 516 uint32_t dsl; 517 i915_reg_t bclrpat_reg, vtotal_reg, 518 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 519 uint8_t st00; 520 enum drm_connector_status status; 521 522 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 523 524 bclrpat_reg = BCLRPAT(pipe); 525 vtotal_reg = VTOTAL(pipe); 526 vblank_reg = VBLANK(pipe); 527 vsync_reg = VSYNC(pipe); 528 pipeconf_reg = PIPECONF(pipe); 529 pipe_dsl_reg = PIPEDSL(pipe); 530 531 save_bclrpat = I915_READ(bclrpat_reg); 532 save_vtotal = I915_READ(vtotal_reg); 533 vblank = I915_READ(vblank_reg); 534 535 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 536 vactive = (save_vtotal & 0x7ff) + 1; 537 538 vblank_start = (vblank & 0xfff) + 1; 539 vblank_end = ((vblank >> 16) & 0xfff) + 1; 540 541 /* Set the border color to purple. */ 542 I915_WRITE(bclrpat_reg, 0x500050); 543 544 if (!IS_GEN2(dev)) { 545 uint32_t pipeconf = I915_READ(pipeconf_reg); 546 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 547 POSTING_READ(pipeconf_reg); 548 /* Wait for next Vblank to substitue 549 * border color for Color info */ 550 intel_wait_for_vblank(dev, pipe); 551 st00 = I915_READ8(_VGA_MSR_WRITE); 552 status = ((st00 & (1 << 4)) != 0) ? 553 connector_status_connected : 554 connector_status_disconnected; 555 556 I915_WRITE(pipeconf_reg, pipeconf); 557 } else { 558 bool restore_vblank = false; 559 int count, detect; 560 561 /* 562 * If there isn't any border, add some. 563 * Yes, this will flicker 564 */ 565 if (vblank_start <= vactive && vblank_end >= vtotal) { 566 uint32_t vsync = I915_READ(vsync_reg); 567 uint32_t vsync_start = (vsync & 0xffff) + 1; 568 569 vblank_start = vsync_start; 570 I915_WRITE(vblank_reg, 571 (vblank_start - 1) | 572 ((vblank_end - 1) << 16)); 573 restore_vblank = true; 574 } 575 /* sample in the vertical border, selecting the larger one */ 576 if (vblank_start - vactive >= vtotal - vblank_end) 577 vsample = (vblank_start + vactive) >> 1; 578 else 579 vsample = (vtotal + vblank_end) >> 1; 580 581 /* 582 * Wait for the border to be displayed 583 */ 584 while (I915_READ(pipe_dsl_reg) >= vactive) 585 ; 586 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 587 ; 588 /* 589 * Watch ST00 for an entire scanline 590 */ 591 detect = 0; 592 count = 0; 593 do { 594 count++; 595 /* Read the ST00 VGA status register */ 596 st00 = I915_READ8(_VGA_MSR_WRITE); 597 if (st00 & (1 << 4)) 598 detect++; 599 } while ((I915_READ(pipe_dsl_reg) == dsl)); 600 601 /* restore vblank if necessary */ 602 if (restore_vblank) 603 I915_WRITE(vblank_reg, vblank); 604 /* 605 * If more than 3/4 of the scanline detected a monitor, 606 * then it is assumed to be present. This works even on i830, 607 * where there isn't any way to force the border color across 608 * the screen 609 */ 610 status = detect * 4 > count * 3 ? 611 connector_status_connected : 612 connector_status_disconnected; 613 } 614 615 /* Restore previous settings */ 616 I915_WRITE(bclrpat_reg, save_bclrpat); 617 618 return status; 619 } 620 621 static enum drm_connector_status 622 intel_crt_detect(struct drm_connector *connector, bool force) 623 { 624 struct drm_device *dev = connector->dev; 625 struct drm_i915_private *dev_priv = dev->dev_private; 626 struct intel_crt *crt = intel_attached_crt(connector); 627 struct intel_encoder *intel_encoder = &crt->base; 628 enum intel_display_power_domain power_domain; 629 enum drm_connector_status status; 630 struct intel_load_detect_pipe tmp; 631 struct drm_modeset_acquire_ctx ctx; 632 633 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 634 connector->base.id, connector->name, 635 force); 636 637 power_domain = intel_display_port_power_domain(intel_encoder); 638 intel_display_power_get(dev_priv, power_domain); 639 640 if (I915_HAS_HOTPLUG(dev)) { 641 /* We can not rely on the HPD pin always being correctly wired 642 * up, for example many KVM do not pass it through, and so 643 * only trust an assertion that the monitor is connected. 644 */ 645 if (intel_crt_detect_hotplug(connector)) { 646 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 647 status = connector_status_connected; 648 goto out; 649 } else 650 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 651 } 652 653 if (intel_crt_detect_ddc(connector)) { 654 status = connector_status_connected; 655 goto out; 656 } 657 658 /* Load detection is broken on HPD capable machines. Whoever wants a 659 * broken monitor (without edid) to work behind a broken kvm (that fails 660 * to have the right resistors for HP detection) needs to fix this up. 661 * For now just bail out. */ 662 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 663 status = connector_status_disconnected; 664 goto out; 665 } 666 667 if (!force) { 668 status = connector->status; 669 goto out; 670 } 671 672 drm_modeset_acquire_init(&ctx, 0); 673 674 /* for pre-945g platforms use load detect */ 675 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 676 if (intel_crt_detect_ddc(connector)) 677 status = connector_status_connected; 678 else if (INTEL_INFO(dev)->gen < 4) 679 status = intel_crt_load_detect(crt, 680 to_intel_crtc(connector->state->crtc)->pipe); 681 else if (i915.load_detect_test) 682 status = connector_status_disconnected; 683 else 684 status = connector_status_unknown; 685 intel_release_load_detect_pipe(connector, &tmp, &ctx); 686 } else 687 status = connector_status_unknown; 688 689 drm_modeset_drop_locks(&ctx); 690 drm_modeset_acquire_fini(&ctx); 691 692 out: 693 intel_display_power_put(dev_priv, power_domain); 694 return status; 695 } 696 697 static void intel_crt_destroy(struct drm_connector *connector) 698 { 699 drm_connector_cleanup(connector); 700 kfree(connector); 701 } 702 703 static int intel_crt_get_modes(struct drm_connector *connector) 704 { 705 struct drm_device *dev = connector->dev; 706 struct drm_i915_private *dev_priv = dev->dev_private; 707 struct intel_crt *crt = intel_attached_crt(connector); 708 struct intel_encoder *intel_encoder = &crt->base; 709 enum intel_display_power_domain power_domain; 710 int ret; 711 struct i2c_adapter *i2c; 712 713 power_domain = intel_display_port_power_domain(intel_encoder); 714 intel_display_power_get(dev_priv, power_domain); 715 716 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 717 ret = intel_crt_ddc_get_modes(connector, i2c); 718 if (ret || !IS_G4X(dev)) 719 goto out; 720 721 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 722 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 723 ret = intel_crt_ddc_get_modes(connector, i2c); 724 725 out: 726 intel_display_power_put(dev_priv, power_domain); 727 728 return ret; 729 } 730 731 static int intel_crt_set_property(struct drm_connector *connector, 732 struct drm_property *property, 733 uint64_t value) 734 { 735 return 0; 736 } 737 738 void intel_crt_reset(struct drm_encoder *encoder) 739 { 740 struct drm_device *dev = encoder->dev; 741 struct drm_i915_private *dev_priv = dev->dev_private; 742 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 743 744 if (INTEL_INFO(dev)->gen >= 5) { 745 u32 adpa; 746 747 adpa = I915_READ(crt->adpa_reg); 748 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 749 adpa |= ADPA_HOTPLUG_BITS; 750 I915_WRITE(crt->adpa_reg, adpa); 751 POSTING_READ(crt->adpa_reg); 752 753 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 754 crt->force_hotplug_required = 1; 755 } 756 757 } 758 759 /* 760 * Routines for controlling stuff on the analog port 761 */ 762 763 static const struct drm_connector_funcs intel_crt_connector_funcs = { 764 .dpms = drm_atomic_helper_connector_dpms, 765 .detect = intel_crt_detect, 766 .fill_modes = drm_helper_probe_single_connector_modes, 767 .late_register = intel_connector_register, 768 .early_unregister = intel_connector_unregister, 769 .destroy = intel_crt_destroy, 770 .set_property = intel_crt_set_property, 771 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 772 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 773 .atomic_get_property = intel_connector_atomic_get_property, 774 }; 775 776 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 777 .mode_valid = intel_crt_mode_valid, 778 .get_modes = intel_crt_get_modes, 779 }; 780 781 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 782 .reset = intel_crt_reset, 783 .destroy = intel_encoder_destroy, 784 }; 785 786 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 787 { 788 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 789 return 1; 790 } 791 792 static const struct dmi_system_id intel_no_crt[] = { 793 { 794 .callback = intel_no_crt_dmi_callback, 795 .ident = "ACER ZGB", 796 .matches = { 797 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 798 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 799 }, 800 }, 801 { 802 .callback = intel_no_crt_dmi_callback, 803 .ident = "DELL XPS 8700", 804 .matches = { 805 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 806 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 807 }, 808 }, 809 { } 810 }; 811 812 void intel_crt_init(struct drm_device *dev) 813 { 814 struct drm_connector *connector; 815 struct intel_crt *crt; 816 struct intel_connector *intel_connector; 817 struct drm_i915_private *dev_priv = dev->dev_private; 818 i915_reg_t adpa_reg; 819 u32 adpa; 820 821 /* Skip machines without VGA that falsely report hotplug events */ 822 if (dmi_check_system(intel_no_crt)) 823 return; 824 825 if (HAS_PCH_SPLIT(dev)) 826 adpa_reg = PCH_ADPA; 827 else if (IS_VALLEYVIEW(dev)) 828 adpa_reg = VLV_ADPA; 829 else 830 adpa_reg = ADPA; 831 832 adpa = I915_READ(adpa_reg); 833 if ((adpa & ADPA_DAC_ENABLE) == 0) { 834 /* 835 * On some machines (some IVB at least) CRT can be 836 * fused off, but there's no known fuse bit to 837 * indicate that. On these machine the ADPA register 838 * works normally, except the DAC enable bit won't 839 * take. So the only way to tell is attempt to enable 840 * it and see what happens. 841 */ 842 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 843 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 844 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 845 return; 846 I915_WRITE(adpa_reg, adpa); 847 } 848 849 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 850 if (!crt) 851 return; 852 853 intel_connector = intel_connector_alloc(); 854 if (!intel_connector) { 855 kfree(crt); 856 return; 857 } 858 859 connector = &intel_connector->base; 860 crt->connector = intel_connector; 861 drm_connector_init(dev, &intel_connector->base, 862 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 863 864 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 865 DRM_MODE_ENCODER_DAC, "CRT"); 866 867 intel_connector_attach_encoder(intel_connector, &crt->base); 868 869 crt->base.type = INTEL_OUTPUT_ANALOG; 870 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 871 if (IS_I830(dev)) 872 crt->base.crtc_mask = (1 << 0); 873 else 874 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 875 876 if (IS_GEN2(dev)) 877 connector->interlace_allowed = 0; 878 else 879 connector->interlace_allowed = 1; 880 connector->doublescan_allowed = 0; 881 882 crt->adpa_reg = adpa_reg; 883 884 crt->base.compute_config = intel_crt_compute_config; 885 if (HAS_PCH_SPLIT(dev)) { 886 crt->base.disable = pch_disable_crt; 887 crt->base.post_disable = pch_post_disable_crt; 888 } else { 889 crt->base.disable = intel_disable_crt; 890 } 891 crt->base.enable = intel_enable_crt; 892 if (I915_HAS_HOTPLUG(dev)) 893 crt->base.hpd_pin = HPD_CRT; 894 if (HAS_DDI(dev)) { 895 crt->base.get_config = hsw_crt_get_config; 896 crt->base.get_hw_state = intel_ddi_get_hw_state; 897 } else { 898 crt->base.get_config = intel_crt_get_config; 899 crt->base.get_hw_state = intel_crt_get_hw_state; 900 } 901 intel_connector->get_hw_state = intel_connector_get_hw_state; 902 903 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 904 905 if (!I915_HAS_HOTPLUG(dev)) 906 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 907 908 /* 909 * Configure the automatic hotplug detection stuff 910 */ 911 crt->force_hotplug_required = 0; 912 913 /* 914 * TODO: find a proper way to discover whether we need to set the the 915 * polarity and link reversal bits or not, instead of relying on the 916 * BIOS. 917 */ 918 if (HAS_PCH_LPT(dev)) { 919 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 920 FDI_RX_LINK_REVERSAL_OVERRIDE; 921 922 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 923 } 924 925 intel_crt_reset(&crt->base.base); 926 } 927