1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/drm_edid.h> 33 #include "intel_drv.h" 34 #include <drm/i915_drm.h> 35 #include "i915_drv.h" 36 37 /* Here's the desired hotplug mode */ 38 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 39 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 40 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 41 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 42 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 43 ADPA_CRT_HOTPLUG_ENABLE) 44 45 struct intel_crt { 46 struct intel_encoder base; 47 /* DPMS state is stored in the connector, which we need in the 48 * encoder's enable/disable callbacks */ 49 struct intel_connector *connector; 50 bool force_hotplug_required; 51 u32 adpa_reg; 52 }; 53 54 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 55 { 56 return container_of(encoder, struct intel_crt, base); 57 } 58 59 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 60 { 61 return intel_encoder_to_crt(intel_attached_encoder(connector)); 62 } 63 64 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 65 enum i915_pipe *pipe) 66 { 67 struct drm_device *dev = encoder->base.dev; 68 struct drm_i915_private *dev_priv = dev->dev_private; 69 struct intel_crt *crt = intel_encoder_to_crt(encoder); 70 enum intel_display_power_domain power_domain; 71 u32 tmp; 72 73 power_domain = intel_display_port_power_domain(encoder); 74 if (!intel_display_power_enabled(dev_priv, power_domain)) 75 return false; 76 77 tmp = I915_READ(crt->adpa_reg); 78 79 if (!(tmp & ADPA_DAC_ENABLE)) 80 return false; 81 82 if (HAS_PCH_CPT(dev)) 83 *pipe = PORT_TO_PIPE_CPT(tmp); 84 else 85 *pipe = PORT_TO_PIPE(tmp); 86 87 return true; 88 } 89 90 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 91 { 92 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 93 struct intel_crt *crt = intel_encoder_to_crt(encoder); 94 u32 tmp, flags = 0; 95 96 tmp = I915_READ(crt->adpa_reg); 97 98 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 99 flags |= DRM_MODE_FLAG_PHSYNC; 100 else 101 flags |= DRM_MODE_FLAG_NHSYNC; 102 103 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 104 flags |= DRM_MODE_FLAG_PVSYNC; 105 else 106 flags |= DRM_MODE_FLAG_NVSYNC; 107 108 return flags; 109 } 110 111 static void intel_crt_get_config(struct intel_encoder *encoder, 112 struct intel_crtc_config *pipe_config) 113 { 114 struct drm_device *dev = encoder->base.dev; 115 int dotclock; 116 117 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); 118 119 dotclock = pipe_config->port_clock; 120 121 if (HAS_PCH_SPLIT(dev)) 122 ironlake_check_encoder_dotclock(pipe_config, dotclock); 123 124 pipe_config->adjusted_mode.crtc_clock = dotclock; 125 } 126 127 static void hsw_crt_get_config(struct intel_encoder *encoder, 128 struct intel_crtc_config *pipe_config) 129 { 130 intel_ddi_get_config(encoder, pipe_config); 131 132 pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 133 DRM_MODE_FLAG_NHSYNC | 134 DRM_MODE_FLAG_PVSYNC | 135 DRM_MODE_FLAG_NVSYNC); 136 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); 137 } 138 139 static void hsw_crt_pre_enable(struct intel_encoder *encoder) 140 { 141 struct drm_device *dev = encoder->base.dev; 142 struct drm_i915_private *dev_priv = dev->dev_private; 143 144 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); 145 I915_WRITE(SPLL_CTL, 146 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); 147 POSTING_READ(SPLL_CTL); 148 udelay(20); 149 } 150 151 /* Note: The caller is required to filter out dpms modes not supported by the 152 * platform. */ 153 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 154 { 155 struct drm_device *dev = encoder->base.dev; 156 struct drm_i915_private *dev_priv = dev->dev_private; 157 struct intel_crt *crt = intel_encoder_to_crt(encoder); 158 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 159 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 160 u32 adpa; 161 162 if (INTEL_INFO(dev)->gen >= 5) 163 adpa = ADPA_HOTPLUG_BITS; 164 else 165 adpa = 0; 166 167 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 168 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 169 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 170 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 171 172 /* For CPT allow 3 pipe config, for others just use A or B */ 173 if (HAS_PCH_LPT(dev)) 174 ; /* Those bits don't exist here */ 175 else if (HAS_PCH_CPT(dev)) 176 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 177 else if (crtc->pipe == 0) 178 adpa |= ADPA_PIPE_A_SELECT; 179 else 180 adpa |= ADPA_PIPE_B_SELECT; 181 182 if (!HAS_PCH_SPLIT(dev)) 183 I915_WRITE(BCLRPAT(crtc->pipe), 0); 184 185 switch (mode) { 186 case DRM_MODE_DPMS_ON: 187 adpa |= ADPA_DAC_ENABLE; 188 break; 189 case DRM_MODE_DPMS_STANDBY: 190 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 191 break; 192 case DRM_MODE_DPMS_SUSPEND: 193 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 194 break; 195 case DRM_MODE_DPMS_OFF: 196 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 197 break; 198 } 199 200 I915_WRITE(crt->adpa_reg, adpa); 201 } 202 203 static void intel_disable_crt(struct intel_encoder *encoder) 204 { 205 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 206 } 207 208 209 static void hsw_crt_post_disable(struct intel_encoder *encoder) 210 { 211 struct drm_device *dev = encoder->base.dev; 212 struct drm_i915_private *dev_priv = dev->dev_private; 213 uint32_t val; 214 215 DRM_DEBUG_KMS("Disabling SPLL\n"); 216 val = I915_READ(SPLL_CTL); 217 WARN_ON(!(val & SPLL_PLL_ENABLE)); 218 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 219 POSTING_READ(SPLL_CTL); 220 } 221 222 static void intel_enable_crt(struct intel_encoder *encoder) 223 { 224 struct intel_crt *crt = intel_encoder_to_crt(encoder); 225 226 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 227 } 228 229 /* Special dpms function to support cloning between dvo/sdvo/crt. */ 230 static void intel_crt_dpms(struct drm_connector *connector, int mode) 231 { 232 struct drm_device *dev = connector->dev; 233 struct intel_encoder *encoder = intel_attached_encoder(connector); 234 struct drm_crtc *crtc; 235 int old_dpms; 236 237 /* PCH platforms and VLV only support on/off. */ 238 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) 239 mode = DRM_MODE_DPMS_OFF; 240 241 if (mode == connector->dpms) 242 return; 243 244 old_dpms = connector->dpms; 245 connector->dpms = mode; 246 247 /* Only need to change hw state when actually enabled */ 248 crtc = encoder->base.crtc; 249 if (!crtc) { 250 encoder->connectors_active = false; 251 return; 252 } 253 254 /* We need the pipe to run for anything but OFF. */ 255 if (mode == DRM_MODE_DPMS_OFF) 256 encoder->connectors_active = false; 257 else 258 encoder->connectors_active = true; 259 260 /* We call connector dpms manually below in case pipe dpms doesn't 261 * change due to cloning. */ 262 if (mode < old_dpms) { 263 /* From off to on, enable the pipe first. */ 264 intel_crtc_update_dpms(crtc); 265 266 intel_crt_set_dpms(encoder, mode); 267 } else { 268 intel_crt_set_dpms(encoder, mode); 269 270 intel_crtc_update_dpms(crtc); 271 } 272 273 intel_modeset_check_state(connector->dev); 274 } 275 276 static enum drm_mode_status 277 intel_crt_mode_valid(struct drm_connector *connector, 278 struct drm_display_mode *mode) 279 { 280 struct drm_device *dev = connector->dev; 281 282 int max_clock = 0; 283 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 284 return MODE_NO_DBLESCAN; 285 286 if (mode->clock < 25000) 287 return MODE_CLOCK_LOW; 288 289 if (IS_GEN2(dev)) 290 max_clock = 350000; 291 else 292 max_clock = 400000; 293 if (mode->clock > max_clock) 294 return MODE_CLOCK_HIGH; 295 296 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 297 if (HAS_PCH_LPT(dev) && 298 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 299 return MODE_CLOCK_HIGH; 300 301 return MODE_OK; 302 } 303 304 static bool intel_crt_compute_config(struct intel_encoder *encoder, 305 struct intel_crtc_config *pipe_config) 306 { 307 struct drm_device *dev = encoder->base.dev; 308 309 if (HAS_PCH_SPLIT(dev)) 310 pipe_config->has_pch_encoder = true; 311 312 /* LPT FDI RX only supports 8bpc. */ 313 if (HAS_PCH_LPT(dev)) 314 pipe_config->pipe_bpp = 24; 315 316 /* FDI must always be 2.7 GHz */ 317 if (HAS_DDI(dev)) { 318 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 319 pipe_config->port_clock = 135000 * 2; 320 } 321 322 return true; 323 } 324 325 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 326 { 327 struct drm_device *dev = connector->dev; 328 struct intel_crt *crt = intel_attached_crt(connector); 329 struct drm_i915_private *dev_priv = dev->dev_private; 330 u32 adpa; 331 bool ret; 332 333 /* The first time through, trigger an explicit detection cycle */ 334 if (crt->force_hotplug_required) { 335 bool turn_off_dac = HAS_PCH_SPLIT(dev); 336 u32 save_adpa; 337 338 crt->force_hotplug_required = 0; 339 340 save_adpa = adpa = I915_READ(crt->adpa_reg); 341 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 342 343 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 344 if (turn_off_dac) 345 adpa &= ~ADPA_DAC_ENABLE; 346 347 I915_WRITE(crt->adpa_reg, adpa); 348 349 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 350 1000)) 351 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 352 353 if (turn_off_dac) { 354 I915_WRITE(crt->adpa_reg, save_adpa); 355 POSTING_READ(crt->adpa_reg); 356 } 357 } 358 359 /* Check the status to see if both blue and green are on now */ 360 adpa = I915_READ(crt->adpa_reg); 361 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 362 ret = true; 363 else 364 ret = false; 365 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 366 367 return ret; 368 } 369 370 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 371 { 372 struct drm_device *dev = connector->dev; 373 struct intel_crt *crt = intel_attached_crt(connector); 374 struct drm_i915_private *dev_priv = dev->dev_private; 375 u32 adpa; 376 bool ret; 377 u32 save_adpa; 378 379 save_adpa = adpa = I915_READ(crt->adpa_reg); 380 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 381 382 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 383 384 I915_WRITE(crt->adpa_reg, adpa); 385 386 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 387 1000)) { 388 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 389 I915_WRITE(crt->adpa_reg, save_adpa); 390 } 391 392 /* Check the status to see if both blue and green are on now */ 393 adpa = I915_READ(crt->adpa_reg); 394 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 395 ret = true; 396 else 397 ret = false; 398 399 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 400 401 return ret; 402 } 403 404 /** 405 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 406 * 407 * Not for i915G/i915GM 408 * 409 * \return true if CRT is connected. 410 * \return false if CRT is disconnected. 411 */ 412 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 413 { 414 struct drm_device *dev = connector->dev; 415 struct drm_i915_private *dev_priv = dev->dev_private; 416 u32 hotplug_en, orig, stat; 417 bool ret = false; 418 int i, tries = 0; 419 420 if (HAS_PCH_SPLIT(dev)) 421 return intel_ironlake_crt_detect_hotplug(connector); 422 423 if (IS_VALLEYVIEW(dev)) 424 return valleyview_crt_detect_hotplug(connector); 425 426 /* 427 * On 4 series desktop, CRT detect sequence need to be done twice 428 * to get a reliable result. 429 */ 430 431 if (IS_G4X(dev) && !IS_GM45(dev)) 432 tries = 2; 433 else 434 tries = 1; 435 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 436 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 437 438 for (i = 0; i < tries ; i++) { 439 /* turn on the FORCE_DETECT */ 440 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 441 /* wait for FORCE_DETECT to go off */ 442 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 443 CRT_HOTPLUG_FORCE_DETECT) == 0, 444 1000)) 445 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 446 } 447 448 stat = I915_READ(PORT_HOTPLUG_STAT); 449 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 450 ret = true; 451 452 /* clear the interrupt we just generated, if any */ 453 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 454 455 /* and put the bits back */ 456 I915_WRITE(PORT_HOTPLUG_EN, orig); 457 458 return ret; 459 } 460 461 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 462 struct i2c_adapter *i2c) 463 { 464 struct edid *edid; 465 466 edid = drm_get_edid(connector, i2c); 467 468 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 469 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 470 intel_gmbus_force_bit(i2c, true); 471 edid = drm_get_edid(connector, i2c); 472 intel_gmbus_force_bit(i2c, false); 473 } 474 475 return edid; 476 } 477 478 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 479 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 480 struct i2c_adapter *adapter) 481 { 482 struct edid *edid; 483 int ret; 484 485 edid = intel_crt_get_edid(connector, adapter); 486 if (!edid) 487 return 0; 488 489 ret = intel_connector_update_modes(connector, edid); 490 kfree(edid); 491 492 return ret; 493 } 494 495 static bool intel_crt_detect_ddc(struct drm_connector *connector) 496 { 497 struct intel_crt *crt = intel_attached_crt(connector); 498 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 499 struct edid *edid; 500 struct i2c_adapter *i2c; 501 502 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 503 504 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 505 edid = intel_crt_get_edid(connector, i2c); 506 507 if (edid) { 508 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 509 510 /* 511 * This may be a DVI-I connector with a shared DDC 512 * link between analog and digital outputs, so we 513 * have to check the EDID input spec of the attached device. 514 */ 515 if (!is_digital) { 516 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 517 return true; 518 } 519 520 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 521 } else { 522 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 523 } 524 525 kfree(edid); 526 527 return false; 528 } 529 530 static enum drm_connector_status 531 intel_crt_load_detect(struct intel_crt *crt) 532 { 533 struct drm_device *dev = crt->base.base.dev; 534 struct drm_i915_private *dev_priv = dev->dev_private; 535 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 536 uint32_t save_bclrpat; 537 uint32_t save_vtotal; 538 uint32_t vtotal, vactive; 539 uint32_t vsample; 540 uint32_t vblank, vblank_start, vblank_end; 541 uint32_t dsl; 542 uint32_t bclrpat_reg; 543 uint32_t vtotal_reg; 544 uint32_t vblank_reg; 545 uint32_t vsync_reg; 546 uint32_t pipeconf_reg; 547 uint32_t pipe_dsl_reg; 548 uint8_t st00; 549 enum drm_connector_status status; 550 551 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 552 553 bclrpat_reg = BCLRPAT(pipe); 554 vtotal_reg = VTOTAL(pipe); 555 vblank_reg = VBLANK(pipe); 556 vsync_reg = VSYNC(pipe); 557 pipeconf_reg = PIPECONF(pipe); 558 pipe_dsl_reg = PIPEDSL(pipe); 559 560 save_bclrpat = I915_READ(bclrpat_reg); 561 save_vtotal = I915_READ(vtotal_reg); 562 vblank = I915_READ(vblank_reg); 563 564 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 565 vactive = (save_vtotal & 0x7ff) + 1; 566 567 vblank_start = (vblank & 0xfff) + 1; 568 vblank_end = ((vblank >> 16) & 0xfff) + 1; 569 570 /* Set the border color to purple. */ 571 I915_WRITE(bclrpat_reg, 0x500050); 572 573 if (!IS_GEN2(dev)) { 574 uint32_t pipeconf = I915_READ(pipeconf_reg); 575 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 576 POSTING_READ(pipeconf_reg); 577 /* Wait for next Vblank to substitue 578 * border color for Color info */ 579 intel_wait_for_vblank(dev, pipe); 580 st00 = I915_READ8(VGA_MSR_WRITE); 581 status = ((st00 & (1 << 4)) != 0) ? 582 connector_status_connected : 583 connector_status_disconnected; 584 585 I915_WRITE(pipeconf_reg, pipeconf); 586 } else { 587 bool restore_vblank = false; 588 int count, detect; 589 590 /* 591 * If there isn't any border, add some. 592 * Yes, this will flicker 593 */ 594 if (vblank_start <= vactive && vblank_end >= vtotal) { 595 uint32_t vsync = I915_READ(vsync_reg); 596 uint32_t vsync_start = (vsync & 0xffff) + 1; 597 598 vblank_start = vsync_start; 599 I915_WRITE(vblank_reg, 600 (vblank_start - 1) | 601 ((vblank_end - 1) << 16)); 602 restore_vblank = true; 603 } 604 /* sample in the vertical border, selecting the larger one */ 605 if (vblank_start - vactive >= vtotal - vblank_end) 606 vsample = (vblank_start + vactive) >> 1; 607 else 608 vsample = (vtotal + vblank_end) >> 1; 609 610 /* 611 * Wait for the border to be displayed 612 */ 613 while (I915_READ(pipe_dsl_reg) >= vactive) 614 ; 615 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 616 ; 617 /* 618 * Watch ST00 for an entire scanline 619 */ 620 detect = 0; 621 count = 0; 622 do { 623 count++; 624 /* Read the ST00 VGA status register */ 625 st00 = I915_READ8(VGA_MSR_WRITE); 626 if (st00 & (1 << 4)) 627 detect++; 628 } while ((I915_READ(pipe_dsl_reg) == dsl)); 629 630 /* restore vblank if necessary */ 631 if (restore_vblank) 632 I915_WRITE(vblank_reg, vblank); 633 /* 634 * If more than 3/4 of the scanline detected a monitor, 635 * then it is assumed to be present. This works even on i830, 636 * where there isn't any way to force the border color across 637 * the screen 638 */ 639 status = detect * 4 > count * 3 ? 640 connector_status_connected : 641 connector_status_disconnected; 642 } 643 644 /* Restore previous settings */ 645 I915_WRITE(bclrpat_reg, save_bclrpat); 646 647 return status; 648 } 649 650 static enum drm_connector_status 651 intel_crt_detect(struct drm_connector *connector, bool force) 652 { 653 struct drm_device *dev = connector->dev; 654 struct drm_i915_private *dev_priv = dev->dev_private; 655 struct intel_crt *crt = intel_attached_crt(connector); 656 struct intel_encoder *intel_encoder = &crt->base; 657 enum intel_display_power_domain power_domain; 658 enum drm_connector_status status; 659 struct intel_load_detect_pipe tmp; 660 struct drm_modeset_acquire_ctx ctx; 661 662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 663 connector->base.id, connector->name, 664 force); 665 666 power_domain = intel_display_port_power_domain(intel_encoder); 667 intel_display_power_get(dev_priv, power_domain); 668 669 if (I915_HAS_HOTPLUG(dev)) { 670 /* We can not rely on the HPD pin always being correctly wired 671 * up, for example many KVM do not pass it through, and so 672 * only trust an assertion that the monitor is connected. 673 */ 674 if (intel_crt_detect_hotplug(connector)) { 675 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 676 status = connector_status_connected; 677 goto out; 678 } else 679 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 680 } 681 682 if (intel_crt_detect_ddc(connector)) { 683 status = connector_status_connected; 684 goto out; 685 } 686 687 /* Load detection is broken on HPD capable machines. Whoever wants a 688 * broken monitor (without edid) to work behind a broken kvm (that fails 689 * to have the right resistors for HP detection) needs to fix this up. 690 * For now just bail out. */ 691 if (I915_HAS_HOTPLUG(dev)) { 692 status = connector_status_disconnected; 693 goto out; 694 } 695 696 if (!force) { 697 status = connector->status; 698 goto out; 699 } 700 701 drm_modeset_acquire_init(&ctx, 0); 702 703 /* for pre-945g platforms use load detect */ 704 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 705 if (intel_crt_detect_ddc(connector)) 706 status = connector_status_connected; 707 else 708 status = intel_crt_load_detect(crt); 709 intel_release_load_detect_pipe(connector, &tmp); 710 } else 711 status = connector_status_unknown; 712 713 drm_modeset_drop_locks(&ctx); 714 drm_modeset_acquire_fini(&ctx); 715 716 out: 717 intel_display_power_put(dev_priv, power_domain); 718 return status; 719 } 720 721 static void intel_crt_destroy(struct drm_connector *connector) 722 { 723 drm_connector_cleanup(connector); 724 kfree(connector); 725 } 726 727 static int intel_crt_get_modes(struct drm_connector *connector) 728 { 729 struct drm_device *dev = connector->dev; 730 struct drm_i915_private *dev_priv = dev->dev_private; 731 struct intel_crt *crt = intel_attached_crt(connector); 732 struct intel_encoder *intel_encoder = &crt->base; 733 enum intel_display_power_domain power_domain; 734 int ret; 735 struct i2c_adapter *i2c; 736 737 power_domain = intel_display_port_power_domain(intel_encoder); 738 intel_display_power_get(dev_priv, power_domain); 739 740 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 741 ret = intel_crt_ddc_get_modes(connector, i2c); 742 if (ret || !IS_G4X(dev)) 743 goto out; 744 745 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 746 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); 747 ret = intel_crt_ddc_get_modes(connector, i2c); 748 749 out: 750 intel_display_power_put(dev_priv, power_domain); 751 752 return ret; 753 } 754 755 static int intel_crt_set_property(struct drm_connector *connector, 756 struct drm_property *property, 757 uint64_t value) 758 { 759 return 0; 760 } 761 762 static void intel_crt_reset(struct drm_connector *connector) 763 { 764 struct drm_device *dev = connector->dev; 765 struct drm_i915_private *dev_priv = dev->dev_private; 766 struct intel_crt *crt = intel_attached_crt(connector); 767 768 if (INTEL_INFO(dev)->gen >= 5) { 769 u32 adpa; 770 771 adpa = I915_READ(crt->adpa_reg); 772 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 773 adpa |= ADPA_HOTPLUG_BITS; 774 I915_WRITE(crt->adpa_reg, adpa); 775 POSTING_READ(crt->adpa_reg); 776 777 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); 778 crt->force_hotplug_required = 1; 779 } 780 781 } 782 783 /* 784 * Routines for controlling stuff on the analog port 785 */ 786 787 static const struct drm_connector_funcs intel_crt_connector_funcs = { 788 .reset = intel_crt_reset, 789 .dpms = intel_crt_dpms, 790 .detect = intel_crt_detect, 791 .fill_modes = drm_helper_probe_single_connector_modes, 792 .destroy = intel_crt_destroy, 793 .set_property = intel_crt_set_property, 794 }; 795 796 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 797 .mode_valid = intel_crt_mode_valid, 798 .get_modes = intel_crt_get_modes, 799 .best_encoder = intel_best_encoder, 800 }; 801 802 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 803 .destroy = intel_encoder_destroy, 804 }; 805 806 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 807 { 808 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 809 return 1; 810 } 811 812 static const struct dmi_system_id intel_no_crt[] = { 813 { 814 .callback = intel_no_crt_dmi_callback, 815 .ident = "ACER ZGB", 816 .matches = { 817 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 818 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 819 }, 820 }, 821 { 822 .callback = intel_no_crt_dmi_callback, 823 .ident = "DELL XPS 8700", 824 .matches = { 825 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 826 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 827 }, 828 }, 829 { } 830 }; 831 832 void intel_crt_init(struct drm_device *dev) 833 { 834 struct drm_connector *connector; 835 struct intel_crt *crt; 836 struct intel_connector *intel_connector; 837 struct drm_i915_private *dev_priv = dev->dev_private; 838 839 /* Skip machines without VGA that falsely report hotplug events */ 840 if (dmi_check_system(intel_no_crt)) 841 return; 842 843 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 844 if (!crt) 845 return; 846 847 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 848 if (!intel_connector) { 849 kfree(crt); 850 return; 851 } 852 853 connector = &intel_connector->base; 854 crt->connector = intel_connector; 855 drm_connector_init(dev, &intel_connector->base, 856 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 857 858 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 859 DRM_MODE_ENCODER_DAC); 860 861 intel_connector_attach_encoder(intel_connector, &crt->base); 862 863 crt->base.type = INTEL_OUTPUT_ANALOG; 864 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 865 if (IS_I830(dev)) 866 crt->base.crtc_mask = (1 << 0); 867 else 868 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 869 870 if (IS_GEN2(dev)) 871 connector->interlace_allowed = 0; 872 else 873 connector->interlace_allowed = 1; 874 connector->doublescan_allowed = 0; 875 876 if (HAS_PCH_SPLIT(dev)) 877 crt->adpa_reg = PCH_ADPA; 878 else if (IS_VALLEYVIEW(dev)) 879 crt->adpa_reg = VLV_ADPA; 880 else 881 crt->adpa_reg = ADPA; 882 883 crt->base.compute_config = intel_crt_compute_config; 884 crt->base.disable = intel_disable_crt; 885 crt->base.enable = intel_enable_crt; 886 if (I915_HAS_HOTPLUG(dev)) 887 crt->base.hpd_pin = HPD_CRT; 888 if (HAS_DDI(dev)) { 889 crt->base.get_config = hsw_crt_get_config; 890 crt->base.get_hw_state = intel_ddi_get_hw_state; 891 crt->base.pre_enable = hsw_crt_pre_enable; 892 crt->base.post_disable = hsw_crt_post_disable; 893 } else { 894 crt->base.get_config = intel_crt_get_config; 895 crt->base.get_hw_state = intel_crt_get_hw_state; 896 } 897 intel_connector->get_hw_state = intel_connector_get_hw_state; 898 intel_connector->unregister = intel_connector_unregister; 899 900 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 901 902 drm_connector_register(connector); 903 904 if (!I915_HAS_HOTPLUG(dev)) 905 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 906 907 /* 908 * Configure the automatic hotplug detection stuff 909 */ 910 crt->force_hotplug_required = 0; 911 912 /* 913 * TODO: find a proper way to discover whether we need to set the the 914 * polarity and link reversal bits or not, instead of relying on the 915 * BIOS. 916 */ 917 if (HAS_PCH_LPT(dev)) { 918 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 919 FDI_RX_LINK_REVERSAL_OVERRIDE; 920 921 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; 922 } 923 924 intel_crt_reset(connector); 925 } 926