1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/firmware.h> 25 #include "i915_drv.h" 26 #include "i915_reg.h" 27 28 /** 29 * DOC: csr support for dmc 30 * 31 * Display Context Save and Restore (CSR) firmware support added from gen9 32 * onwards to drive newly added DMC (Display microcontroller) in display 33 * engine to save and restore the state of display engine when it enter into 34 * low-power state and comes back to normal. 35 * 36 * Firmware loading status will be one of the below states: FW_UNINITIALIZED, 37 * FW_LOADED, FW_FAILED. 38 * 39 * Once the firmware is written into the registers status will be moved from 40 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will 41 * be moved to FW_FAILED. 42 */ 43 44 #define I915_CSR_KBL "i915/kbl_dmc_ver1.bin" 45 MODULE_FIRMWARE(I915_CSR_KBL); 46 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) 47 48 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin" 49 MODULE_FIRMWARE(I915_CSR_SKL); 50 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23) 51 52 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin" 53 MODULE_FIRMWARE(I915_CSR_BXT); 54 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) 55 56 #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares" 57 58 59 60 61 #define CSR_MAX_FW_SIZE 0x2FFF 62 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF 63 64 struct intel_css_header { 65 /* 0x09 for DMC */ 66 uint32_t module_type; 67 68 /* Includes the DMC specific header in dwords */ 69 uint32_t header_len; 70 71 /* always value would be 0x10000 */ 72 uint32_t header_ver; 73 74 /* Not used */ 75 uint32_t module_id; 76 77 /* Not used */ 78 uint32_t module_vendor; 79 80 /* in YYYYMMDD format */ 81 uint32_t date; 82 83 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 84 uint32_t size; 85 86 /* Not used */ 87 uint32_t key_size; 88 89 /* Not used */ 90 uint32_t modulus_size; 91 92 /* Not used */ 93 uint32_t exponent_size; 94 95 /* Not used */ 96 uint32_t reserved1[12]; 97 98 /* Major Minor */ 99 uint32_t version; 100 101 /* Not used */ 102 uint32_t reserved2[8]; 103 104 /* Not used */ 105 uint32_t kernel_header_info; 106 } __packed; 107 108 struct intel_fw_info { 109 uint16_t reserved1; 110 111 /* Stepping (A, B, C, ..., *). * is a wildcard */ 112 char stepping; 113 114 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 115 char substepping; 116 117 uint32_t offset; 118 uint32_t reserved2; 119 } __packed; 120 121 struct intel_package_header { 122 /* DMC container header length in dwords */ 123 unsigned char header_len; 124 125 /* always value would be 0x01 */ 126 unsigned char header_ver; 127 128 unsigned char reserved[10]; 129 130 /* Number of valid entries in the FWInfo array below */ 131 uint32_t num_entries; 132 133 struct intel_fw_info fw_info[20]; 134 } __packed; 135 136 struct intel_dmc_header { 137 /* always value would be 0x40403E3E */ 138 uint32_t signature; 139 140 /* DMC binary header length */ 141 unsigned char header_len; 142 143 /* 0x01 */ 144 unsigned char header_ver; 145 146 /* Reserved */ 147 uint16_t dmcc_ver; 148 149 /* Major, Minor */ 150 uint32_t project; 151 152 /* Firmware program size (excluding header) in dwords */ 153 uint32_t fw_size; 154 155 /* Major Minor version */ 156 uint32_t fw_version; 157 158 /* Number of valid MMIO cycles present. */ 159 uint32_t mmio_count; 160 161 /* MMIO address */ 162 uint32_t mmioaddr[8]; 163 164 /* MMIO data */ 165 uint32_t mmiodata[8]; 166 167 /* FW filename */ 168 unsigned char dfile[32]; 169 170 uint32_t reserved1[2]; 171 } __packed; 172 173 struct stepping_info { 174 char stepping; 175 char substepping; 176 }; 177 178 static const struct stepping_info kbl_stepping_info[] = { 179 {'A', '0'}, {'B', '0'}, {'C', '0'}, 180 {'D', '0'}, {'E', '0'}, {'F', '0'}, 181 {'G', '0'}, {'H', '0'}, {'I', '0'}, 182 }; 183 184 static const struct stepping_info skl_stepping_info[] = { 185 {'A', '0'}, {'B', '0'}, {'C', '0'}, 186 {'D', '0'}, {'E', '0'}, {'F', '0'}, 187 {'G', '0'}, {'H', '0'}, {'I', '0'}, 188 {'J', '0'}, {'K', '0'} 189 }; 190 191 static const struct stepping_info bxt_stepping_info[] = { 192 {'A', '0'}, {'A', '1'}, {'A', '2'}, 193 {'B', '0'}, {'B', '1'}, {'B', '2'} 194 }; 195 196 static const struct stepping_info no_stepping_info = { '*', '*' }; 197 198 static const struct stepping_info * 199 intel_get_stepping_info(struct drm_i915_private *dev_priv) 200 { 201 const struct stepping_info *si; 202 unsigned int size; 203 204 if (IS_KABYLAKE(dev_priv)) { 205 size = ARRAY_SIZE(kbl_stepping_info); 206 si = kbl_stepping_info; 207 } else if (IS_SKYLAKE(dev_priv)) { 208 size = ARRAY_SIZE(skl_stepping_info); 209 si = skl_stepping_info; 210 } else if (IS_BROXTON(dev_priv)) { 211 size = ARRAY_SIZE(bxt_stepping_info); 212 si = bxt_stepping_info; 213 } else { 214 size = 0; 215 } 216 217 if (INTEL_REVID(dev_priv) < size) 218 return si + INTEL_REVID(dev_priv); 219 220 return &no_stepping_info; 221 } 222 223 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 224 { 225 uint32_t val, mask; 226 227 mask = DC_STATE_DEBUG_MASK_MEMORY_UP; 228 229 if (IS_BROXTON(dev_priv)) 230 mask |= DC_STATE_DEBUG_MASK_CORES; 231 232 /* The below bit doesn't need to be cleared ever afterwards */ 233 val = I915_READ(DC_STATE_DEBUG); 234 if ((val & mask) != mask) { 235 val |= mask; 236 I915_WRITE(DC_STATE_DEBUG, val); 237 POSTING_READ(DC_STATE_DEBUG); 238 } 239 } 240 241 /** 242 * intel_csr_load_program() - write the firmware from memory to register. 243 * @dev_priv: i915 drm device. 244 * 245 * CSR firmware is read from a .bin file and kept in internal memory one time. 246 * Everytime display comes back from low power state this function is called to 247 * copy the firmware from internal memory to registers. 248 */ 249 void intel_csr_load_program(struct drm_i915_private *dev_priv) 250 { 251 u32 *payload = dev_priv->csr.dmc_payload; 252 uint32_t i, fw_size; 253 254 if (!IS_GEN9(dev_priv)) { 255 DRM_ERROR("No CSR support available for this platform\n"); 256 return; 257 } 258 259 if (!dev_priv->csr.dmc_payload) { 260 DRM_ERROR("Tried to program CSR with empty payload\n"); 261 return; 262 } 263 264 fw_size = dev_priv->csr.dmc_fw_size; 265 for (i = 0; i < fw_size; i++) 266 I915_WRITE(CSR_PROGRAM(i), payload[i]); 267 268 for (i = 0; i < dev_priv->csr.mmio_count; i++) { 269 I915_WRITE(dev_priv->csr.mmioaddr[i], 270 dev_priv->csr.mmiodata[i]); 271 } 272 273 dev_priv->csr.dc_state = 0; 274 275 gen9_set_dc_state_debugmask(dev_priv); 276 } 277 278 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, 279 const struct firmware *fw) 280 { 281 const struct intel_css_header *css_header; 282 const struct intel_package_header *package_header; 283 const struct intel_dmc_header *dmc_header; 284 struct intel_csr *csr = &dev_priv->csr; 285 const struct stepping_info *si = intel_get_stepping_info(dev_priv); 286 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; 287 uint32_t i; 288 uint32_t *dmc_payload; 289 uint32_t required_min_version; 290 291 if (!fw) 292 return NULL; 293 294 /* Extract CSS Header information*/ 295 css_header = (const struct intel_css_header *)fw->data; 296 if (sizeof(struct intel_css_header) != 297 (css_header->header_len * 4)) { 298 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", 299 (css_header->header_len * 4)); 300 return NULL; 301 } 302 303 csr->version = css_header->version; 304 305 if (IS_KABYLAKE(dev_priv)) { 306 required_min_version = KBL_CSR_VERSION_REQUIRED; 307 } else if (IS_SKYLAKE(dev_priv)) { 308 required_min_version = SKL_CSR_VERSION_REQUIRED; 309 } else if (IS_BROXTON(dev_priv)) { 310 required_min_version = BXT_CSR_VERSION_REQUIRED; 311 } else { 312 MISSING_CASE(INTEL_REVID(dev_priv)); 313 required_min_version = 0; 314 } 315 316 if (csr->version < required_min_version) { 317 DRM_INFO("Refusing to load old DMC firmware v%u.%u," 318 " please upgrade to v%u.%u or later" 319 " [" FIRMWARE_URL "].\n", 320 CSR_VERSION_MAJOR(csr->version), 321 CSR_VERSION_MINOR(csr->version), 322 CSR_VERSION_MAJOR(required_min_version), 323 CSR_VERSION_MINOR(required_min_version)); 324 return NULL; 325 } 326 327 readcount += sizeof(struct intel_css_header); 328 329 /* Extract Package Header information*/ 330 package_header = (const struct intel_package_header *) 331 &fw->data[readcount]; 332 if (sizeof(struct intel_package_header) != 333 (package_header->header_len * 4)) { 334 DRM_ERROR("Firmware has wrong package header length %u bytes\n", 335 (package_header->header_len * 4)); 336 return NULL; 337 } 338 readcount += sizeof(struct intel_package_header); 339 340 /* Search for dmc_offset to find firware binary. */ 341 for (i = 0; i < package_header->num_entries; i++) { 342 if (package_header->fw_info[i].substepping == '*' && 343 si->stepping == package_header->fw_info[i].stepping) { 344 dmc_offset = package_header->fw_info[i].offset; 345 break; 346 } else if (si->stepping == package_header->fw_info[i].stepping && 347 si->substepping == package_header->fw_info[i].substepping) { 348 dmc_offset = package_header->fw_info[i].offset; 349 break; 350 } else if (package_header->fw_info[i].stepping == '*' && 351 package_header->fw_info[i].substepping == '*') 352 dmc_offset = package_header->fw_info[i].offset; 353 } 354 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { 355 DRM_ERROR("Firmware not supported for %c stepping\n", 356 si->stepping); 357 return NULL; 358 } 359 readcount += dmc_offset; 360 361 /* Extract dmc_header information. */ 362 dmc_header = (const struct intel_dmc_header *)&fw->data[readcount]; 363 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { 364 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", 365 (dmc_header->header_len)); 366 return NULL; 367 } 368 readcount += sizeof(struct intel_dmc_header); 369 370 /* Cache the dmc header info. */ 371 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { 372 DRM_ERROR("Firmware has wrong mmio count %u\n", 373 dmc_header->mmio_count); 374 return NULL; 375 } 376 csr->mmio_count = dmc_header->mmio_count; 377 for (i = 0; i < dmc_header->mmio_count; i++) { 378 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE || 379 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { 380 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", 381 dmc_header->mmioaddr[i]); 382 return NULL; 383 } 384 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); 385 csr->mmiodata[i] = dmc_header->mmiodata[i]; 386 } 387 388 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 389 nbytes = dmc_header->fw_size * 4; 390 if (nbytes > CSR_MAX_FW_SIZE) { 391 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); 392 return NULL; 393 } 394 csr->dmc_fw_size = dmc_header->fw_size; 395 396 dmc_payload = kmalloc(nbytes, M_DRM, M_WAITOK); 397 if (!dmc_payload) { 398 DRM_ERROR("Memory allocation failed for dmc payload\n"); 399 return NULL; 400 } 401 402 return memcpy(dmc_payload, &fw->data[readcount], nbytes); 403 } 404 405 static void csr_load_work_fn(struct work_struct *work) 406 { 407 struct drm_i915_private *dev_priv; 408 struct intel_csr *csr; 409 const struct firmware *fw; 410 int ret; 411 412 dev_priv = container_of(work, typeof(*dev_priv), csr.work); 413 csr = &dev_priv->csr; 414 415 ret = request_firmware(&fw, dev_priv->csr.fw_path, 416 &dev_priv->dev->pdev->dev); 417 if (fw) 418 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); 419 420 if (dev_priv->csr.dmc_payload) { 421 intel_csr_load_program(dev_priv); 422 423 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 424 425 DRM_INFO("Finished loading %s (v%u.%u)\n", 426 dev_priv->csr.fw_path, 427 CSR_VERSION_MAJOR(csr->version), 428 CSR_VERSION_MINOR(csr->version)); 429 } else { 430 DRM_ERROR( 431 "Failed to load DMC firmware" 432 " [" FIRMWARE_URL "]," 433 " disabling runtime power management.\n"); 434 } 435 436 release_firmware(fw); 437 } 438 439 /** 440 * intel_csr_ucode_init() - initialize the firmware loading. 441 * @dev_priv: i915 drm device. 442 * 443 * This function is called at the time of loading the display driver to read 444 * firmware from a .bin file and copied into a internal memory. 445 */ 446 void intel_csr_ucode_init(struct drm_i915_private *dev_priv) 447 { 448 struct intel_csr *csr = &dev_priv->csr; 449 450 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); 451 452 if (!HAS_CSR(dev_priv)) 453 return; 454 455 if (IS_KABYLAKE(dev_priv)) 456 csr->fw_path = I915_CSR_KBL; 457 else if (IS_SKYLAKE(dev_priv)) 458 csr->fw_path = I915_CSR_SKL; 459 else if (IS_BROXTON(dev_priv)) 460 csr->fw_path = I915_CSR_BXT; 461 else { 462 DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); 463 return; 464 } 465 466 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); 467 468 /* 469 * Obtain a runtime pm reference, until CSR is loaded, 470 * to avoid entering runtime-suspend. 471 */ 472 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 473 474 schedule_work(&dev_priv->csr.work); 475 } 476 477 /** 478 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend 479 * @dev_priv: i915 drm device 480 * 481 * Prepare the DMC firmware before entering system suspend. This includes 482 * flushing pending work items and releasing any resources acquired during 483 * init. 484 */ 485 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) 486 { 487 if (!HAS_CSR(dev_priv)) 488 return; 489 490 flush_work(&dev_priv->csr.work); 491 492 /* Drop the reference held in case DMC isn't loaded. */ 493 if (!dev_priv->csr.dmc_payload) 494 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 495 } 496 497 /** 498 * intel_csr_ucode_resume() - init CSR firmware during system resume 499 * @dev_priv: i915 drm device 500 * 501 * Reinitialize the DMC firmware during system resume, reacquiring any 502 * resources released in intel_csr_ucode_suspend(). 503 */ 504 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) 505 { 506 if (!HAS_CSR(dev_priv)) 507 return; 508 509 /* 510 * Reacquire the reference to keep RPM disabled in case DMC isn't 511 * loaded. 512 */ 513 if (!dev_priv->csr.dmc_payload) 514 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 515 } 516 517 /** 518 * intel_csr_ucode_fini() - unload the CSR firmware. 519 * @dev_priv: i915 drm device. 520 * 521 * Firmmware unloading includes freeing the internal memory and reset the 522 * firmware loading status. 523 */ 524 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) 525 { 526 if (!HAS_CSR(dev_priv)) 527 return; 528 529 intel_csr_ucode_suspend(dev_priv); 530 531 kfree(dev_priv->csr.dmc_payload); 532 } 533