1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/firmware.h> 25 #include "i915_drv.h" 26 #include "i915_reg.h" 27 28 /** 29 * DOC: csr support for dmc 30 * 31 * Display Context Save and Restore (CSR) firmware support added from gen9 32 * onwards to drive newly added DMC (Display microcontroller) in display 33 * engine to save and restore the state of display engine when it enter into 34 * low-power state and comes back to normal. 35 * 36 * Firmware loading status will be one of the below states: FW_UNINITIALIZED, 37 * FW_LOADED, FW_FAILED. 38 * 39 * Once the firmware is written into the registers status will be moved from 40 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will 41 * be moved to FW_FAILED. 42 */ 43 44 #define I915_CSR_SKL "i915/skl_dmc_ver1.bin" 45 #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin" 46 47 MODULE_FIRMWARE(I915_CSR_SKL); 48 MODULE_FIRMWARE(I915_CSR_BXT); 49 50 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23) 51 52 #define CSR_MAX_FW_SIZE 0x2FFF 53 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF 54 55 struct intel_css_header { 56 /* 0x09 for DMC */ 57 uint32_t module_type; 58 59 /* Includes the DMC specific header in dwords */ 60 uint32_t header_len; 61 62 /* always value would be 0x10000 */ 63 uint32_t header_ver; 64 65 /* Not used */ 66 uint32_t module_id; 67 68 /* Not used */ 69 uint32_t module_vendor; 70 71 /* in YYYYMMDD format */ 72 uint32_t date; 73 74 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 75 uint32_t size; 76 77 /* Not used */ 78 uint32_t key_size; 79 80 /* Not used */ 81 uint32_t modulus_size; 82 83 /* Not used */ 84 uint32_t exponent_size; 85 86 /* Not used */ 87 uint32_t reserved1[12]; 88 89 /* Major Minor */ 90 uint32_t version; 91 92 /* Not used */ 93 uint32_t reserved2[8]; 94 95 /* Not used */ 96 uint32_t kernel_header_info; 97 } __packed; 98 99 struct intel_fw_info { 100 uint16_t reserved1; 101 102 /* Stepping (A, B, C, ..., *). * is a wildcard */ 103 char stepping; 104 105 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 106 char substepping; 107 108 uint32_t offset; 109 uint32_t reserved2; 110 } __packed; 111 112 struct intel_package_header { 113 /* DMC container header length in dwords */ 114 unsigned char header_len; 115 116 /* always value would be 0x01 */ 117 unsigned char header_ver; 118 119 unsigned char reserved[10]; 120 121 /* Number of valid entries in the FWInfo array below */ 122 uint32_t num_entries; 123 124 struct intel_fw_info fw_info[20]; 125 } __packed; 126 127 struct intel_dmc_header { 128 /* always value would be 0x40403E3E */ 129 uint32_t signature; 130 131 /* DMC binary header length */ 132 unsigned char header_len; 133 134 /* 0x01 */ 135 unsigned char header_ver; 136 137 /* Reserved */ 138 uint16_t dmcc_ver; 139 140 /* Major, Minor */ 141 uint32_t project; 142 143 /* Firmware program size (excluding header) in dwords */ 144 uint32_t fw_size; 145 146 /* Major Minor version */ 147 uint32_t fw_version; 148 149 /* Number of valid MMIO cycles present. */ 150 uint32_t mmio_count; 151 152 /* MMIO address */ 153 uint32_t mmioaddr[8]; 154 155 /* MMIO data */ 156 uint32_t mmiodata[8]; 157 158 /* FW filename */ 159 unsigned char dfile[32]; 160 161 uint32_t reserved1[2]; 162 } __packed; 163 164 struct stepping_info { 165 char stepping; 166 char substepping; 167 }; 168 169 /* 170 * Kabylake derivated from Skylake H0, so SKL H0 171 * is the right firmware for KBL A0 (revid 0). 172 */ 173 static const struct stepping_info kbl_stepping_info[] = { 174 {'H', '0'}, {'I', '0'} 175 }; 176 177 static const struct stepping_info skl_stepping_info[] = { 178 {'A', '0'}, {'B', '0'}, {'C', '0'}, 179 {'D', '0'}, {'E', '0'}, {'F', '0'}, 180 {'G', '0'}, {'H', '0'}, {'I', '0'} 181 }; 182 183 static const struct stepping_info bxt_stepping_info[] = { 184 {'A', '0'}, {'A', '1'}, {'A', '2'}, 185 {'B', '0'}, {'B', '1'}, {'B', '2'} 186 }; 187 188 static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev) 189 { 190 const struct stepping_info *si; 191 unsigned int size; 192 193 if (IS_KABYLAKE(dev)) { 194 size = ARRAY_SIZE(kbl_stepping_info); 195 si = kbl_stepping_info; 196 } else if (IS_SKYLAKE(dev)) { 197 size = ARRAY_SIZE(skl_stepping_info); 198 si = skl_stepping_info; 199 } else if (IS_BROXTON(dev)) { 200 size = ARRAY_SIZE(bxt_stepping_info); 201 si = bxt_stepping_info; 202 } else { 203 return NULL; 204 } 205 206 if (INTEL_REVID(dev) < size) 207 return si + INTEL_REVID(dev); 208 209 return NULL; 210 } 211 212 /** 213 * intel_csr_load_program() - write the firmware from memory to register. 214 * @dev_priv: i915 drm device. 215 * 216 * CSR firmware is read from a .bin file and kept in internal memory one time. 217 * Everytime display comes back from low power state this function is called to 218 * copy the firmware from internal memory to registers. 219 */ 220 void intel_csr_load_program(struct drm_i915_private *dev_priv) 221 { 222 u32 *payload = dev_priv->csr.dmc_payload; 223 uint32_t i, fw_size; 224 225 if (!IS_GEN9(dev_priv)) { 226 DRM_ERROR("No CSR support available for this platform\n"); 227 return; 228 } 229 230 if (!dev_priv->csr.dmc_payload) { 231 DRM_ERROR("Tried to program CSR with empty payload\n"); 232 return; 233 } 234 235 fw_size = dev_priv->csr.dmc_fw_size; 236 for (i = 0; i < fw_size; i++) 237 I915_WRITE(CSR_PROGRAM(i), payload[i]); 238 239 for (i = 0; i < dev_priv->csr.mmio_count; i++) { 240 I915_WRITE(dev_priv->csr.mmioaddr[i], 241 dev_priv->csr.mmiodata[i]); 242 } 243 244 dev_priv->csr.dc_state = 0; 245 } 246 247 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, 248 const struct firmware *fw) 249 { 250 struct drm_device *dev = dev_priv->dev; 251 const struct intel_css_header *css_header; 252 const struct intel_package_header *package_header; 253 const struct intel_dmc_header *dmc_header; 254 struct intel_csr *csr = &dev_priv->csr; 255 const struct stepping_info *stepping_info = intel_get_stepping_info(dev); 256 char stepping, substepping; 257 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; 258 uint32_t i; 259 uint32_t *dmc_payload; 260 261 if (!fw) 262 return NULL; 263 264 if (!stepping_info) { 265 DRM_ERROR("Unknown stepping info, firmware loading failed\n"); 266 return NULL; 267 } 268 269 stepping = stepping_info->stepping; 270 substepping = stepping_info->substepping; 271 272 /* Extract CSS Header information*/ 273 css_header = (const struct intel_css_header *)fw->data; 274 if (sizeof(struct intel_css_header) != 275 (css_header->header_len * 4)) { 276 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", 277 (css_header->header_len * 4)); 278 return NULL; 279 } 280 281 csr->version = css_header->version; 282 283 if (IS_SKYLAKE(dev) && csr->version < SKL_CSR_VERSION_REQUIRED) { 284 DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u," 285 " please upgrade to v%u.%u or later" 286 " [https://01.org/linuxgraphics/intel-linux-graphics-firmwares].\n", 287 CSR_VERSION_MAJOR(csr->version), 288 CSR_VERSION_MINOR(csr->version), 289 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED), 290 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED)); 291 return NULL; 292 } 293 294 readcount += sizeof(struct intel_css_header); 295 296 /* Extract Package Header information*/ 297 package_header = (const struct intel_package_header *) 298 &fw->data[readcount]; 299 if (sizeof(struct intel_package_header) != 300 (package_header->header_len * 4)) { 301 DRM_ERROR("Firmware has wrong package header length %u bytes\n", 302 (package_header->header_len * 4)); 303 return NULL; 304 } 305 readcount += sizeof(struct intel_package_header); 306 307 /* Search for dmc_offset to find firware binary. */ 308 for (i = 0; i < package_header->num_entries; i++) { 309 if (package_header->fw_info[i].substepping == '*' && 310 stepping == package_header->fw_info[i].stepping) { 311 dmc_offset = package_header->fw_info[i].offset; 312 break; 313 } else if (stepping == package_header->fw_info[i].stepping && 314 substepping == package_header->fw_info[i].substepping) { 315 dmc_offset = package_header->fw_info[i].offset; 316 break; 317 } else if (package_header->fw_info[i].stepping == '*' && 318 package_header->fw_info[i].substepping == '*') 319 dmc_offset = package_header->fw_info[i].offset; 320 } 321 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { 322 DRM_ERROR("Firmware not supported for %c stepping\n", stepping); 323 return NULL; 324 } 325 readcount += dmc_offset; 326 327 /* Extract dmc_header information. */ 328 dmc_header = (const struct intel_dmc_header *)&fw->data[readcount]; 329 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { 330 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", 331 (dmc_header->header_len)); 332 return NULL; 333 } 334 readcount += sizeof(struct intel_dmc_header); 335 336 /* Cache the dmc header info. */ 337 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { 338 DRM_ERROR("Firmware has wrong mmio count %u\n", 339 dmc_header->mmio_count); 340 return NULL; 341 } 342 csr->mmio_count = dmc_header->mmio_count; 343 for (i = 0; i < dmc_header->mmio_count; i++) { 344 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE || 345 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { 346 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", 347 dmc_header->mmioaddr[i]); 348 return NULL; 349 } 350 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); 351 csr->mmiodata[i] = dmc_header->mmiodata[i]; 352 } 353 354 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 355 nbytes = dmc_header->fw_size * 4; 356 if (nbytes > CSR_MAX_FW_SIZE) { 357 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); 358 return NULL; 359 } 360 csr->dmc_fw_size = dmc_header->fw_size; 361 362 dmc_payload = kmalloc(nbytes, M_DRM, M_WAITOK); 363 if (!dmc_payload) { 364 DRM_ERROR("Memory allocation failed for dmc payload\n"); 365 return NULL; 366 } 367 368 memcpy(dmc_payload, &fw->data[readcount], nbytes); 369 370 return dmc_payload; 371 } 372 373 static void csr_load_work_fn(struct work_struct *work) 374 { 375 struct drm_i915_private *dev_priv; 376 struct intel_csr *csr; 377 const struct firmware *fw; 378 int ret; 379 380 dev_priv = container_of(work, typeof(*dev_priv), csr.work); 381 csr = &dev_priv->csr; 382 383 ret = request_firmware(&fw, dev_priv->csr.fw_path, 384 &dev_priv->dev->pdev->dev); 385 if (!fw) 386 goto out; 387 388 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); 389 if (!dev_priv->csr.dmc_payload) 390 goto out; 391 392 /* load csr program during system boot, as needed for DC states */ 393 intel_csr_load_program(dev_priv); 394 395 out: 396 if (dev_priv->csr.dmc_payload) { 397 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 398 399 DRM_INFO("Finished loading %s (v%u.%u)\n", 400 dev_priv->csr.fw_path, 401 CSR_VERSION_MAJOR(csr->version), 402 CSR_VERSION_MINOR(csr->version)); 403 } else { 404 DRM_ERROR("Failed to load DMC firmware, disabling rpm\n"); 405 } 406 407 release_firmware(fw); 408 } 409 410 /** 411 * intel_csr_ucode_init() - initialize the firmware loading. 412 * @dev_priv: i915 drm device. 413 * 414 * This function is called at the time of loading the display driver to read 415 * firmware from a .bin file and copied into a internal memory. 416 */ 417 void intel_csr_ucode_init(struct drm_i915_private *dev_priv) 418 { 419 struct intel_csr *csr = &dev_priv->csr; 420 421 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); 422 423 if (!HAS_CSR(dev_priv)) 424 return; 425 426 if (IS_SKYLAKE(dev_priv)) 427 csr->fw_path = I915_CSR_SKL; 428 else if (IS_BROXTON(dev_priv)) 429 csr->fw_path = I915_CSR_BXT; 430 else { 431 DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); 432 return; 433 } 434 435 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); 436 437 /* 438 * Obtain a runtime pm reference, until CSR is loaded, 439 * to avoid entering runtime-suspend. 440 */ 441 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 442 443 schedule_work(&dev_priv->csr.work); 444 } 445 446 /** 447 * intel_csr_ucode_fini() - unload the CSR firmware. 448 * @dev_priv: i915 drm device. 449 * 450 * Firmmware unloading includes freeing the internal momory and reset the 451 * firmware loading status. 452 */ 453 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) 454 { 455 if (!HAS_CSR(dev_priv)) 456 return; 457 458 flush_work(&dev_priv->csr.work); 459 460 kfree(dev_priv->csr.dmc_payload); 461 } 462