1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/firmware.h> 25 #include "i915_drv.h" 26 #include "i915_reg.h" 27 28 /** 29 * DOC: csr support for dmc 30 * 31 * Display Context Save and Restore (CSR) firmware support added from gen9 32 * onwards to drive newly added DMC (Display microcontroller) in display 33 * engine to save and restore the state of display engine when it enter into 34 * low-power state and comes back to normal. 35 */ 36 37 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" 38 MODULE_FIRMWARE(I915_CSR_KBL); 39 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) 40 41 #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" 42 MODULE_FIRMWARE(I915_CSR_SKL); 43 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26) 44 45 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin" 46 MODULE_FIRMWARE(I915_CSR_BXT); 47 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) 48 49 #define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares" 50 51 52 53 54 #define CSR_MAX_FW_SIZE 0x2FFF 55 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF 56 57 struct intel_css_header { 58 /* 0x09 for DMC */ 59 uint32_t module_type; 60 61 /* Includes the DMC specific header in dwords */ 62 uint32_t header_len; 63 64 /* always value would be 0x10000 */ 65 uint32_t header_ver; 66 67 /* Not used */ 68 uint32_t module_id; 69 70 /* Not used */ 71 uint32_t module_vendor; 72 73 /* in YYYYMMDD format */ 74 uint32_t date; 75 76 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 77 uint32_t size; 78 79 /* Not used */ 80 uint32_t key_size; 81 82 /* Not used */ 83 uint32_t modulus_size; 84 85 /* Not used */ 86 uint32_t exponent_size; 87 88 /* Not used */ 89 uint32_t reserved1[12]; 90 91 /* Major Minor */ 92 uint32_t version; 93 94 /* Not used */ 95 uint32_t reserved2[8]; 96 97 /* Not used */ 98 uint32_t kernel_header_info; 99 } __packed; 100 101 struct intel_fw_info { 102 uint16_t reserved1; 103 104 /* Stepping (A, B, C, ..., *). * is a wildcard */ 105 char stepping; 106 107 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 108 char substepping; 109 110 uint32_t offset; 111 uint32_t reserved2; 112 } __packed; 113 114 struct intel_package_header { 115 /* DMC container header length in dwords */ 116 unsigned char header_len; 117 118 /* always value would be 0x01 */ 119 unsigned char header_ver; 120 121 unsigned char reserved[10]; 122 123 /* Number of valid entries in the FWInfo array below */ 124 uint32_t num_entries; 125 126 struct intel_fw_info fw_info[20]; 127 } __packed; 128 129 struct intel_dmc_header { 130 /* always value would be 0x40403E3E */ 131 uint32_t signature; 132 133 /* DMC binary header length */ 134 unsigned char header_len; 135 136 /* 0x01 */ 137 unsigned char header_ver; 138 139 /* Reserved */ 140 uint16_t dmcc_ver; 141 142 /* Major, Minor */ 143 uint32_t project; 144 145 /* Firmware program size (excluding header) in dwords */ 146 uint32_t fw_size; 147 148 /* Major Minor version */ 149 uint32_t fw_version; 150 151 /* Number of valid MMIO cycles present. */ 152 uint32_t mmio_count; 153 154 /* MMIO address */ 155 uint32_t mmioaddr[8]; 156 157 /* MMIO data */ 158 uint32_t mmiodata[8]; 159 160 /* FW filename */ 161 unsigned char dfile[32]; 162 163 uint32_t reserved1[2]; 164 } __packed; 165 166 struct stepping_info { 167 char stepping; 168 char substepping; 169 }; 170 171 static const struct stepping_info kbl_stepping_info[] = { 172 {'A', '0'}, {'B', '0'}, {'C', '0'}, 173 {'D', '0'}, {'E', '0'}, {'F', '0'}, 174 {'G', '0'}, {'H', '0'}, {'I', '0'}, 175 }; 176 177 static const struct stepping_info skl_stepping_info[] = { 178 {'A', '0'}, {'B', '0'}, {'C', '0'}, 179 {'D', '0'}, {'E', '0'}, {'F', '0'}, 180 {'G', '0'}, {'H', '0'}, {'I', '0'}, 181 {'J', '0'}, {'K', '0'} 182 }; 183 184 static const struct stepping_info bxt_stepping_info[] = { 185 {'A', '0'}, {'A', '1'}, {'A', '2'}, 186 {'B', '0'}, {'B', '1'}, {'B', '2'} 187 }; 188 189 static const struct stepping_info no_stepping_info = { '*', '*' }; 190 191 static const struct stepping_info * 192 intel_get_stepping_info(struct drm_i915_private *dev_priv) 193 { 194 const struct stepping_info *si; 195 unsigned int size; 196 197 if (IS_KABYLAKE(dev_priv)) { 198 size = ARRAY_SIZE(kbl_stepping_info); 199 si = kbl_stepping_info; 200 } else if (IS_SKYLAKE(dev_priv)) { 201 size = ARRAY_SIZE(skl_stepping_info); 202 si = skl_stepping_info; 203 } else if (IS_BROXTON(dev_priv)) { 204 size = ARRAY_SIZE(bxt_stepping_info); 205 si = bxt_stepping_info; 206 } else { 207 size = 0; 208 } 209 210 if (INTEL_REVID(dev_priv) < size) 211 return si + INTEL_REVID(dev_priv); 212 213 return &no_stepping_info; 214 } 215 216 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 217 { 218 uint32_t val, mask; 219 220 mask = DC_STATE_DEBUG_MASK_MEMORY_UP; 221 222 if (IS_BROXTON(dev_priv)) 223 mask |= DC_STATE_DEBUG_MASK_CORES; 224 225 /* The below bit doesn't need to be cleared ever afterwards */ 226 val = I915_READ(DC_STATE_DEBUG); 227 if ((val & mask) != mask) { 228 val |= mask; 229 I915_WRITE(DC_STATE_DEBUG, val); 230 POSTING_READ(DC_STATE_DEBUG); 231 } 232 } 233 234 /** 235 * intel_csr_load_program() - write the firmware from memory to register. 236 * @dev_priv: i915 drm device. 237 * 238 * CSR firmware is read from a .bin file and kept in internal memory one time. 239 * Everytime display comes back from low power state this function is called to 240 * copy the firmware from internal memory to registers. 241 */ 242 void intel_csr_load_program(struct drm_i915_private *dev_priv) 243 { 244 u32 *payload = dev_priv->csr.dmc_payload; 245 uint32_t i, fw_size; 246 247 if (!IS_GEN9(dev_priv)) { 248 DRM_ERROR("No CSR support available for this platform\n"); 249 return; 250 } 251 252 if (!dev_priv->csr.dmc_payload) { 253 DRM_ERROR("Tried to program CSR with empty payload\n"); 254 return; 255 } 256 257 fw_size = dev_priv->csr.dmc_fw_size; 258 for (i = 0; i < fw_size; i++) 259 I915_WRITE(CSR_PROGRAM(i), payload[i]); 260 261 for (i = 0; i < dev_priv->csr.mmio_count; i++) { 262 I915_WRITE(dev_priv->csr.mmioaddr[i], 263 dev_priv->csr.mmiodata[i]); 264 } 265 266 dev_priv->csr.dc_state = 0; 267 268 gen9_set_dc_state_debugmask(dev_priv); 269 } 270 271 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, 272 const struct firmware *fw) 273 { 274 const struct intel_css_header *css_header; 275 const struct intel_package_header *package_header; 276 const struct intel_dmc_header *dmc_header; 277 struct intel_csr *csr = &dev_priv->csr; 278 const struct stepping_info *si = intel_get_stepping_info(dev_priv); 279 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; 280 uint32_t i; 281 uint32_t *dmc_payload; 282 uint32_t required_version; 283 284 if (!fw) 285 return NULL; 286 287 /* Extract CSS Header information*/ 288 css_header = (const struct intel_css_header *)fw->data; 289 if (sizeof(struct intel_css_header) != 290 (css_header->header_len * 4)) { 291 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", 292 (css_header->header_len * 4)); 293 return NULL; 294 } 295 296 csr->version = css_header->version; 297 298 if (IS_KABYLAKE(dev_priv)) { 299 required_version = KBL_CSR_VERSION_REQUIRED; 300 } else if (IS_SKYLAKE(dev_priv)) { 301 required_version = SKL_CSR_VERSION_REQUIRED; 302 } else if (IS_BROXTON(dev_priv)) { 303 required_version = BXT_CSR_VERSION_REQUIRED; 304 } else { 305 MISSING_CASE(INTEL_REVID(dev_priv)); 306 required_version = 0; 307 } 308 309 if (csr->version != required_version) { 310 DRM_INFO("Refusing to load DMC firmware v%u.%u," 311 " please use v%u.%u [" FIRMWARE_URL "].\n", 312 CSR_VERSION_MAJOR(csr->version), 313 CSR_VERSION_MINOR(csr->version), 314 CSR_VERSION_MAJOR(required_version), 315 CSR_VERSION_MINOR(required_version)); 316 return NULL; 317 } 318 319 readcount += sizeof(struct intel_css_header); 320 321 /* Extract Package Header information*/ 322 package_header = (const struct intel_package_header *) 323 &fw->data[readcount]; 324 if (sizeof(struct intel_package_header) != 325 (package_header->header_len * 4)) { 326 DRM_ERROR("Firmware has wrong package header length %u bytes\n", 327 (package_header->header_len * 4)); 328 return NULL; 329 } 330 readcount += sizeof(struct intel_package_header); 331 332 /* Search for dmc_offset to find firware binary. */ 333 for (i = 0; i < package_header->num_entries; i++) { 334 if (package_header->fw_info[i].substepping == '*' && 335 si->stepping == package_header->fw_info[i].stepping) { 336 dmc_offset = package_header->fw_info[i].offset; 337 break; 338 } else if (si->stepping == package_header->fw_info[i].stepping && 339 si->substepping == package_header->fw_info[i].substepping) { 340 dmc_offset = package_header->fw_info[i].offset; 341 break; 342 } else if (package_header->fw_info[i].stepping == '*' && 343 package_header->fw_info[i].substepping == '*') 344 dmc_offset = package_header->fw_info[i].offset; 345 } 346 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { 347 DRM_ERROR("Firmware not supported for %c stepping\n", 348 si->stepping); 349 return NULL; 350 } 351 readcount += dmc_offset; 352 353 /* Extract dmc_header information. */ 354 dmc_header = (const struct intel_dmc_header *)&fw->data[readcount]; 355 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { 356 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", 357 (dmc_header->header_len)); 358 return NULL; 359 } 360 readcount += sizeof(struct intel_dmc_header); 361 362 /* Cache the dmc header info. */ 363 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { 364 DRM_ERROR("Firmware has wrong mmio count %u\n", 365 dmc_header->mmio_count); 366 return NULL; 367 } 368 csr->mmio_count = dmc_header->mmio_count; 369 for (i = 0; i < dmc_header->mmio_count; i++) { 370 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE || 371 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { 372 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", 373 dmc_header->mmioaddr[i]); 374 return NULL; 375 } 376 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); 377 csr->mmiodata[i] = dmc_header->mmiodata[i]; 378 } 379 380 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 381 nbytes = dmc_header->fw_size * 4; 382 if (nbytes > CSR_MAX_FW_SIZE) { 383 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); 384 return NULL; 385 } 386 csr->dmc_fw_size = dmc_header->fw_size; 387 388 dmc_payload = kmalloc(nbytes, M_DRM, M_WAITOK); 389 if (!dmc_payload) { 390 DRM_ERROR("Memory allocation failed for dmc payload\n"); 391 return NULL; 392 } 393 394 return memcpy(dmc_payload, &fw->data[readcount], nbytes); 395 } 396 397 static void csr_load_work_fn(struct work_struct *work) 398 { 399 struct drm_i915_private *dev_priv; 400 struct intel_csr *csr; 401 const struct firmware *fw; 402 int ret; 403 404 dev_priv = container_of(work, typeof(*dev_priv), csr.work); 405 csr = &dev_priv->csr; 406 407 ret = request_firmware(&fw, dev_priv->csr.fw_path, 408 &dev_priv->drm.pdev->dev); 409 if (fw) 410 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); 411 412 if (dev_priv->csr.dmc_payload) { 413 intel_csr_load_program(dev_priv); 414 415 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 416 417 DRM_INFO("Finished loading %s (v%u.%u)\n", 418 dev_priv->csr.fw_path, 419 CSR_VERSION_MAJOR(csr->version), 420 CSR_VERSION_MINOR(csr->version)); 421 } else { 422 DRM_ERROR( 423 "Failed to load DMC firmware" 424 " [" FIRMWARE_URL "]," 425 " disabling runtime power management.\n"); 426 } 427 428 release_firmware(fw); 429 } 430 431 /** 432 * intel_csr_ucode_init() - initialize the firmware loading. 433 * @dev_priv: i915 drm device. 434 * 435 * This function is called at the time of loading the display driver to read 436 * firmware from a .bin file and copied into a internal memory. 437 */ 438 void intel_csr_ucode_init(struct drm_i915_private *dev_priv) 439 { 440 struct intel_csr *csr = &dev_priv->csr; 441 442 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); 443 444 if (!HAS_CSR(dev_priv)) 445 return; 446 447 if (IS_KABYLAKE(dev_priv)) 448 csr->fw_path = I915_CSR_KBL; 449 else if (IS_SKYLAKE(dev_priv)) 450 csr->fw_path = I915_CSR_SKL; 451 else if (IS_BROXTON(dev_priv)) 452 csr->fw_path = I915_CSR_BXT; 453 else { 454 DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); 455 return; 456 } 457 458 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); 459 460 /* 461 * Obtain a runtime pm reference, until CSR is loaded, 462 * to avoid entering runtime-suspend. 463 */ 464 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 465 466 schedule_work(&dev_priv->csr.work); 467 } 468 469 /** 470 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend 471 * @dev_priv: i915 drm device 472 * 473 * Prepare the DMC firmware before entering system suspend. This includes 474 * flushing pending work items and releasing any resources acquired during 475 * init. 476 */ 477 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) 478 { 479 if (!HAS_CSR(dev_priv)) 480 return; 481 482 flush_work(&dev_priv->csr.work); 483 484 /* Drop the reference held in case DMC isn't loaded. */ 485 if (!dev_priv->csr.dmc_payload) 486 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 487 } 488 489 /** 490 * intel_csr_ucode_resume() - init CSR firmware during system resume 491 * @dev_priv: i915 drm device 492 * 493 * Reinitialize the DMC firmware during system resume, reacquiring any 494 * resources released in intel_csr_ucode_suspend(). 495 */ 496 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) 497 { 498 if (!HAS_CSR(dev_priv)) 499 return; 500 501 /* 502 * Reacquire the reference to keep RPM disabled in case DMC isn't 503 * loaded. 504 */ 505 if (!dev_priv->csr.dmc_payload) 506 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 507 } 508 509 /** 510 * intel_csr_ucode_fini() - unload the CSR firmware. 511 * @dev_priv: i915 drm device. 512 * 513 * Firmmware unloading includes freeing the internal memory and reset the 514 * firmware loading status. 515 */ 516 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) 517 { 518 if (!HAS_CSR(dev_priv)) 519 return; 520 521 intel_csr_ucode_suspend(dev_priv); 522 523 kfree(dev_priv->csr.dmc_payload); 524 } 525