119df918dSFrançois Tigeot /*
219df918dSFrançois Tigeot * Copyright © 2012 Intel Corporation
319df918dSFrançois Tigeot *
419df918dSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a
519df918dSFrançois Tigeot * copy of this software and associated documentation files (the "Software"),
619df918dSFrançois Tigeot * to deal in the Software without restriction, including without limitation
719df918dSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense,
819df918dSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the
919df918dSFrançois Tigeot * Software is furnished to do so, subject to the following conditions:
1019df918dSFrançois Tigeot *
1119df918dSFrançois Tigeot * The above copyright notice and this permission notice (including the next
1219df918dSFrançois Tigeot * paragraph) shall be included in all copies or substantial portions of the
1319df918dSFrançois Tigeot * Software.
1419df918dSFrançois Tigeot *
1519df918dSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1619df918dSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1719df918dSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1819df918dSFrançois Tigeot * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1919df918dSFrançois Tigeot * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2019df918dSFrançois Tigeot * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2119df918dSFrançois Tigeot * IN THE SOFTWARE.
2219df918dSFrançois Tigeot *
2319df918dSFrançois Tigeot * Authors:
2419df918dSFrançois Tigeot * Eugeni Dodonov <eugeni.dodonov@intel.com>
2519df918dSFrançois Tigeot *
2619df918dSFrançois Tigeot */
2719df918dSFrançois Tigeot
2819df918dSFrançois Tigeot #include "i915_drv.h"
2919df918dSFrançois Tigeot #include "intel_drv.h"
301b13d190SFrançois Tigeot
311b13d190SFrançois Tigeot struct ddi_buf_trans {
321b13d190SFrançois Tigeot u32 trans1; /* balance leg enable, de-emph level */
331b13d190SFrançois Tigeot u32 trans2; /* vref sel, vswing */
34a05eeebfSFrançois Tigeot u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
351b13d190SFrançois Tigeot };
3619df918dSFrançois Tigeot
37a85cb24fSFrançois Tigeot static const u8 index_to_dp_signal_levels[] = {
38a85cb24fSFrançois Tigeot [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
39a85cb24fSFrançois Tigeot [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
40a85cb24fSFrançois Tigeot [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
41a85cb24fSFrançois Tigeot [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
42a85cb24fSFrançois Tigeot [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
43a85cb24fSFrançois Tigeot [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
44a85cb24fSFrançois Tigeot [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
45a85cb24fSFrançois Tigeot [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
46a85cb24fSFrançois Tigeot [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
47a85cb24fSFrançois Tigeot [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
48a85cb24fSFrançois Tigeot };
49a85cb24fSFrançois Tigeot
5019df918dSFrançois Tigeot /* HDMI/DVI modes ignore everything but the last 2 items. So we share
5119df918dSFrançois Tigeot * them for both DP and FDI transports, allowing those ports to
5219df918dSFrançois Tigeot * automatically adapt to HDMI connections as well
5319df918dSFrançois Tigeot */
541b13d190SFrançois Tigeot static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
55a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0006000E, 0x0 },
56a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x0005000A, 0x0 },
57a05eeebfSFrançois Tigeot { 0x00C30FFF, 0x00040006, 0x0 },
58a05eeebfSFrançois Tigeot { 0x80AAAFFF, 0x000B0000, 0x0 },
59a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0005000A, 0x0 },
60a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x000C0004, 0x0 },
61a05eeebfSFrançois Tigeot { 0x80C30FFF, 0x000B0000, 0x0 },
62a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00040006, 0x0 },
63a05eeebfSFrançois Tigeot { 0x80D75FFF, 0x000B0000, 0x0 },
6419df918dSFrançois Tigeot };
6519df918dSFrançois Tigeot
661b13d190SFrançois Tigeot static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
67a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0007000E, 0x0 },
68a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x000F000A, 0x0 },
69a05eeebfSFrançois Tigeot { 0x00C30FFF, 0x00060006, 0x0 },
70a05eeebfSFrançois Tigeot { 0x00AAAFFF, 0x001E0000, 0x0 },
71a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x000F000A, 0x0 },
72a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x00160004, 0x0 },
73a05eeebfSFrançois Tigeot { 0x00C30FFF, 0x001E0000, 0x0 },
74a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00060006, 0x0 },
75a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x001E0000, 0x0 },
7619df918dSFrançois Tigeot };
7719df918dSFrançois Tigeot
781b13d190SFrançois Tigeot static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
791b13d190SFrançois Tigeot /* Idx NT mV d T mV d db */
80a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
81a05eeebfSFrançois Tigeot { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
82a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
83a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
84a05eeebfSFrançois Tigeot { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
85a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
86a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
87a05eeebfSFrançois Tigeot { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
88a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
89a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
90a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
91a05eeebfSFrançois Tigeot { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
929edbd4a0SFrançois Tigeot };
939edbd4a0SFrançois Tigeot
941b13d190SFrançois Tigeot static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
95a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00000012, 0x0 },
96a05eeebfSFrançois Tigeot { 0x00EBAFFF, 0x00020011, 0x0 },
97a05eeebfSFrançois Tigeot { 0x00C71FFF, 0x0006000F, 0x0 },
98a05eeebfSFrançois Tigeot { 0x00AAAFFF, 0x000E000A, 0x0 },
99a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00020011, 0x0 },
100a05eeebfSFrançois Tigeot { 0x00DB6FFF, 0x0005000F, 0x0 },
101a05eeebfSFrançois Tigeot { 0x00BEEFFF, 0x000A000C, 0x0 },
102a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0005000F, 0x0 },
103a05eeebfSFrançois Tigeot { 0x00DB6FFF, 0x000A000C, 0x0 },
1049edbd4a0SFrançois Tigeot };
1059edbd4a0SFrançois Tigeot
1061b13d190SFrançois Tigeot static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
107a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0007000E, 0x0 },
108a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x000E000A, 0x0 },
109a05eeebfSFrançois Tigeot { 0x00BEFFFF, 0x00140006, 0x0 },
110a05eeebfSFrançois Tigeot { 0x80B2CFFF, 0x001B0002, 0x0 },
111a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x000E000A, 0x0 },
112a05eeebfSFrançois Tigeot { 0x00DB6FFF, 0x00160005, 0x0 },
113a05eeebfSFrançois Tigeot { 0x80C71FFF, 0x001A0002, 0x0 },
114a05eeebfSFrançois Tigeot { 0x00F7DFFF, 0x00180004, 0x0 },
115a05eeebfSFrançois Tigeot { 0x80D75FFF, 0x001B0002, 0x0 },
1169edbd4a0SFrançois Tigeot };
1179edbd4a0SFrançois Tigeot
1181b13d190SFrançois Tigeot static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
119a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0001000E, 0x0 },
120a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x0004000A, 0x0 },
121a05eeebfSFrançois Tigeot { 0x00C30FFF, 0x00070006, 0x0 },
122a05eeebfSFrançois Tigeot { 0x00AAAFFF, 0x000C0000, 0x0 },
123a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0004000A, 0x0 },
124a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x00090004, 0x0 },
125a05eeebfSFrançois Tigeot { 0x00C30FFF, 0x000C0000, 0x0 },
126a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00070006, 0x0 },
127a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x000C0000, 0x0 },
1281b13d190SFrançois Tigeot };
1291b13d190SFrançois Tigeot
1301b13d190SFrançois Tigeot static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
1311b13d190SFrançois Tigeot /* Idx NT mV d T mV df db */
132a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
133a05eeebfSFrançois Tigeot { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
134a05eeebfSFrançois Tigeot { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
135a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
136a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
137a05eeebfSFrançois Tigeot { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
138a05eeebfSFrançois Tigeot { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
139a05eeebfSFrançois Tigeot { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
140a05eeebfSFrançois Tigeot { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
141a05eeebfSFrançois Tigeot { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
1429edbd4a0SFrançois Tigeot };
1439edbd4a0SFrançois Tigeot
144a05eeebfSFrançois Tigeot /* Skylake H and S */
1452c9916cdSFrançois Tigeot static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
146a05eeebfSFrançois Tigeot { 0x00002016, 0x000000A0, 0x0 },
147a05eeebfSFrançois Tigeot { 0x00005012, 0x0000009B, 0x0 },
148a05eeebfSFrançois Tigeot { 0x00007011, 0x00000088, 0x0 },
149c0e85e96SFrançois Tigeot { 0x80009010, 0x000000C0, 0x1 },
150a05eeebfSFrançois Tigeot { 0x00002016, 0x0000009B, 0x0 },
151a05eeebfSFrançois Tigeot { 0x00005012, 0x00000088, 0x0 },
152c0e85e96SFrançois Tigeot { 0x80007011, 0x000000C0, 0x1 },
153a05eeebfSFrançois Tigeot { 0x00002016, 0x000000DF, 0x0 },
154c0e85e96SFrançois Tigeot { 0x80005012, 0x000000C0, 0x1 },
1552c9916cdSFrançois Tigeot };
1562c9916cdSFrançois Tigeot
157a05eeebfSFrançois Tigeot /* Skylake U */
158a05eeebfSFrançois Tigeot static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
159a05eeebfSFrançois Tigeot { 0x0000201B, 0x000000A2, 0x0 },
160a05eeebfSFrançois Tigeot { 0x00005012, 0x00000088, 0x0 },
1618621f407SFrançois Tigeot { 0x80007011, 0x000000CD, 0x1 },
162c0e85e96SFrançois Tigeot { 0x80009010, 0x000000C0, 0x1 },
163a05eeebfSFrançois Tigeot { 0x0000201B, 0x0000009D, 0x0 },
164c0e85e96SFrançois Tigeot { 0x80005012, 0x000000C0, 0x1 },
165c0e85e96SFrançois Tigeot { 0x80007011, 0x000000C0, 0x1 },
166a05eeebfSFrançois Tigeot { 0x00002016, 0x00000088, 0x0 },
167c0e85e96SFrançois Tigeot { 0x80005012, 0x000000C0, 0x1 },
168a05eeebfSFrançois Tigeot };
169a05eeebfSFrançois Tigeot
170a05eeebfSFrançois Tigeot /* Skylake Y */
171a05eeebfSFrançois Tigeot static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
172a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A2, 0x0 },
173a05eeebfSFrançois Tigeot { 0x00005012, 0x00000088, 0x0 },
1748621f407SFrançois Tigeot { 0x80007011, 0x000000CD, 0x3 },
175c0e85e96SFrançois Tigeot { 0x80009010, 0x000000C0, 0x3 },
176a05eeebfSFrançois Tigeot { 0x00000018, 0x0000009D, 0x0 },
177c0e85e96SFrançois Tigeot { 0x80005012, 0x000000C0, 0x3 },
178c0e85e96SFrançois Tigeot { 0x80007011, 0x000000C0, 0x3 },
179a05eeebfSFrançois Tigeot { 0x00000018, 0x00000088, 0x0 },
180c0e85e96SFrançois Tigeot { 0x80005012, 0x000000C0, 0x3 },
181a05eeebfSFrançois Tigeot };
182a05eeebfSFrançois Tigeot
1831e12ee3bSFrançois Tigeot /* Kabylake H and S */
1841e12ee3bSFrançois Tigeot static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
1851e12ee3bSFrançois Tigeot { 0x00002016, 0x000000A0, 0x0 },
1861e12ee3bSFrançois Tigeot { 0x00005012, 0x0000009B, 0x0 },
1871e12ee3bSFrançois Tigeot { 0x00007011, 0x00000088, 0x0 },
1881e12ee3bSFrançois Tigeot { 0x80009010, 0x000000C0, 0x1 },
1891e12ee3bSFrançois Tigeot { 0x00002016, 0x0000009B, 0x0 },
1901e12ee3bSFrançois Tigeot { 0x00005012, 0x00000088, 0x0 },
1911e12ee3bSFrançois Tigeot { 0x80007011, 0x000000C0, 0x1 },
1921e12ee3bSFrançois Tigeot { 0x00002016, 0x00000097, 0x0 },
1931e12ee3bSFrançois Tigeot { 0x80005012, 0x000000C0, 0x1 },
1941e12ee3bSFrançois Tigeot };
1951e12ee3bSFrançois Tigeot
1961e12ee3bSFrançois Tigeot /* Kabylake U */
1971e12ee3bSFrançois Tigeot static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
1981e12ee3bSFrançois Tigeot { 0x0000201B, 0x000000A1, 0x0 },
1991e12ee3bSFrançois Tigeot { 0x00005012, 0x00000088, 0x0 },
2001e12ee3bSFrançois Tigeot { 0x80007011, 0x000000CD, 0x3 },
2011e12ee3bSFrançois Tigeot { 0x80009010, 0x000000C0, 0x3 },
2021e12ee3bSFrançois Tigeot { 0x0000201B, 0x0000009D, 0x0 },
2031e12ee3bSFrançois Tigeot { 0x80005012, 0x000000C0, 0x3 },
2041e12ee3bSFrançois Tigeot { 0x80007011, 0x000000C0, 0x3 },
2051e12ee3bSFrançois Tigeot { 0x00002016, 0x0000004F, 0x0 },
2061e12ee3bSFrançois Tigeot { 0x80005012, 0x000000C0, 0x3 },
2071e12ee3bSFrançois Tigeot };
2081e12ee3bSFrançois Tigeot
2091e12ee3bSFrançois Tigeot /* Kabylake Y */
2101e12ee3bSFrançois Tigeot static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
2111e12ee3bSFrançois Tigeot { 0x00001017, 0x000000A1, 0x0 },
2121e12ee3bSFrançois Tigeot { 0x00005012, 0x00000088, 0x0 },
2131e12ee3bSFrançois Tigeot { 0x80007011, 0x000000CD, 0x3 },
2141e12ee3bSFrançois Tigeot { 0x8000800F, 0x000000C0, 0x3 },
2151e12ee3bSFrançois Tigeot { 0x00001017, 0x0000009D, 0x0 },
2161e12ee3bSFrançois Tigeot { 0x80005012, 0x000000C0, 0x3 },
2171e12ee3bSFrançois Tigeot { 0x80007011, 0x000000C0, 0x3 },
2181e12ee3bSFrançois Tigeot { 0x00001017, 0x0000004C, 0x0 },
2191e12ee3bSFrançois Tigeot { 0x80005012, 0x000000C0, 0x3 },
2201e12ee3bSFrançois Tigeot };
2211e12ee3bSFrançois Tigeot
222a05eeebfSFrançois Tigeot /*
2231e12ee3bSFrançois Tigeot * Skylake/Kabylake H and S
224a05eeebfSFrançois Tigeot * eDP 1.4 low vswing translation parameters
225a05eeebfSFrançois Tigeot */
226477eb7f9SFrançois Tigeot static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
227a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A8, 0x0 },
228a05eeebfSFrançois Tigeot { 0x00004013, 0x000000A9, 0x0 },
229a05eeebfSFrançois Tigeot { 0x00007011, 0x000000A2, 0x0 },
230a05eeebfSFrançois Tigeot { 0x00009010, 0x0000009C, 0x0 },
231a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A9, 0x0 },
232a05eeebfSFrançois Tigeot { 0x00006013, 0x000000A2, 0x0 },
233a05eeebfSFrançois Tigeot { 0x00007011, 0x000000A6, 0x0 },
234a05eeebfSFrançois Tigeot { 0x00000018, 0x000000AB, 0x0 },
235a05eeebfSFrançois Tigeot { 0x00007013, 0x0000009F, 0x0 },
236a05eeebfSFrançois Tigeot { 0x00000018, 0x000000DF, 0x0 },
237477eb7f9SFrançois Tigeot };
238477eb7f9SFrançois Tigeot
239a05eeebfSFrançois Tigeot /*
2401e12ee3bSFrançois Tigeot * Skylake/Kabylake U
241a05eeebfSFrançois Tigeot * eDP 1.4 low vswing translation parameters
242a05eeebfSFrançois Tigeot */
243a05eeebfSFrançois Tigeot static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
244a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A8, 0x0 },
245a05eeebfSFrançois Tigeot { 0x00004013, 0x000000A9, 0x0 },
246a05eeebfSFrançois Tigeot { 0x00007011, 0x000000A2, 0x0 },
247a05eeebfSFrançois Tigeot { 0x00009010, 0x0000009C, 0x0 },
248a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A9, 0x0 },
249a05eeebfSFrançois Tigeot { 0x00006013, 0x000000A2, 0x0 },
250a05eeebfSFrançois Tigeot { 0x00007011, 0x000000A6, 0x0 },
251a05eeebfSFrançois Tigeot { 0x00002016, 0x000000AB, 0x0 },
252a05eeebfSFrançois Tigeot { 0x00005013, 0x0000009F, 0x0 },
253a05eeebfSFrançois Tigeot { 0x00000018, 0x000000DF, 0x0 },
254a05eeebfSFrançois Tigeot };
255477eb7f9SFrançois Tigeot
256a05eeebfSFrançois Tigeot /*
2571e12ee3bSFrançois Tigeot * Skylake/Kabylake Y
258a05eeebfSFrançois Tigeot * eDP 1.4 low vswing translation parameters
259a05eeebfSFrançois Tigeot */
260a05eeebfSFrançois Tigeot static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
261a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A8, 0x0 },
262a05eeebfSFrançois Tigeot { 0x00004013, 0x000000AB, 0x0 },
263a05eeebfSFrançois Tigeot { 0x00007011, 0x000000A4, 0x0 },
264a05eeebfSFrançois Tigeot { 0x00009010, 0x000000DF, 0x0 },
265a05eeebfSFrançois Tigeot { 0x00000018, 0x000000AA, 0x0 },
266a05eeebfSFrançois Tigeot { 0x00006013, 0x000000A4, 0x0 },
267a05eeebfSFrançois Tigeot { 0x00007011, 0x0000009D, 0x0 },
268a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A0, 0x0 },
269a05eeebfSFrançois Tigeot { 0x00006012, 0x000000DF, 0x0 },
270a05eeebfSFrançois Tigeot { 0x00000018, 0x0000008A, 0x0 },
271a05eeebfSFrançois Tigeot };
272a05eeebfSFrançois Tigeot
2731e12ee3bSFrançois Tigeot /* Skylake/Kabylake U, H and S */
2742c9916cdSFrançois Tigeot static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
275a05eeebfSFrançois Tigeot { 0x00000018, 0x000000AC, 0x0 },
276a05eeebfSFrançois Tigeot { 0x00005012, 0x0000009D, 0x0 },
277a05eeebfSFrançois Tigeot { 0x00007011, 0x00000088, 0x0 },
278a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A1, 0x0 },
279a05eeebfSFrançois Tigeot { 0x00000018, 0x00000098, 0x0 },
280a05eeebfSFrançois Tigeot { 0x00004013, 0x00000088, 0x0 },
281c0e85e96SFrançois Tigeot { 0x80006012, 0x000000CD, 0x1 },
282a05eeebfSFrançois Tigeot { 0x00000018, 0x000000DF, 0x0 },
283c0e85e96SFrançois Tigeot { 0x80003015, 0x000000CD, 0x1 }, /* Default */
284c0e85e96SFrançois Tigeot { 0x80003015, 0x000000C0, 0x1 },
285c0e85e96SFrançois Tigeot { 0x80000018, 0x000000C0, 0x1 },
286a05eeebfSFrançois Tigeot };
287a05eeebfSFrançois Tigeot
2881e12ee3bSFrançois Tigeot /* Skylake/Kabylake Y */
289a05eeebfSFrançois Tigeot static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
290a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A1, 0x0 },
291a05eeebfSFrançois Tigeot { 0x00005012, 0x000000DF, 0x0 },
292c0e85e96SFrançois Tigeot { 0x80007011, 0x000000CB, 0x3 },
293a05eeebfSFrançois Tigeot { 0x00000018, 0x000000A4, 0x0 },
294a05eeebfSFrançois Tigeot { 0x00000018, 0x0000009D, 0x0 },
295a05eeebfSFrançois Tigeot { 0x00004013, 0x00000080, 0x0 },
296c0e85e96SFrançois Tigeot { 0x80006013, 0x000000C0, 0x3 },
297a05eeebfSFrançois Tigeot { 0x00000018, 0x0000008A, 0x0 },
298c0e85e96SFrançois Tigeot { 0x80003015, 0x000000C0, 0x3 }, /* Default */
299c0e85e96SFrançois Tigeot { 0x80003015, 0x000000C0, 0x3 },
300c0e85e96SFrançois Tigeot { 0x80000018, 0x000000C0, 0x3 },
3012c9916cdSFrançois Tigeot };
3022c9916cdSFrançois Tigeot
30319c468b4SFrançois Tigeot struct bxt_ddi_buf_trans {
304*3f2dd94aSFrançois Tigeot u8 margin; /* swing value */
305*3f2dd94aSFrançois Tigeot u8 scale; /* scale value */
306*3f2dd94aSFrançois Tigeot u8 enable; /* scale enable */
307*3f2dd94aSFrançois Tigeot u8 deemphasis;
30819c468b4SFrançois Tigeot };
30919c468b4SFrançois Tigeot
31019c468b4SFrançois Tigeot static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
31119c468b4SFrançois Tigeot /* Idx NT mV diff db */
312*3f2dd94aSFrançois Tigeot { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
313*3f2dd94aSFrançois Tigeot { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
314*3f2dd94aSFrançois Tigeot { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
315*3f2dd94aSFrançois Tigeot { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
316*3f2dd94aSFrançois Tigeot { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
317*3f2dd94aSFrançois Tigeot { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
318*3f2dd94aSFrançois Tigeot { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
319*3f2dd94aSFrançois Tigeot { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
320*3f2dd94aSFrançois Tigeot { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
321*3f2dd94aSFrançois Tigeot { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
32219c468b4SFrançois Tigeot };
32319c468b4SFrançois Tigeot
324352ff8bdSFrançois Tigeot static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
325352ff8bdSFrançois Tigeot /* Idx NT mV diff db */
326*3f2dd94aSFrançois Tigeot { 26, 0, 0, 128, }, /* 0: 200 0 */
327*3f2dd94aSFrançois Tigeot { 38, 0, 0, 112, }, /* 1: 200 1.5 */
328*3f2dd94aSFrançois Tigeot { 48, 0, 0, 96, }, /* 2: 200 4 */
329*3f2dd94aSFrançois Tigeot { 54, 0, 0, 69, }, /* 3: 200 6 */
330*3f2dd94aSFrançois Tigeot { 32, 0, 0, 128, }, /* 4: 250 0 */
331*3f2dd94aSFrançois Tigeot { 48, 0, 0, 104, }, /* 5: 250 1.5 */
332*3f2dd94aSFrançois Tigeot { 54, 0, 0, 85, }, /* 6: 250 4 */
333*3f2dd94aSFrançois Tigeot { 43, 0, 0, 128, }, /* 7: 300 0 */
334*3f2dd94aSFrançois Tigeot { 54, 0, 0, 101, }, /* 8: 300 1.5 */
335*3f2dd94aSFrançois Tigeot { 48, 0, 0, 128, }, /* 9: 300 0 */
336352ff8bdSFrançois Tigeot };
337352ff8bdSFrançois Tigeot
33819c468b4SFrançois Tigeot /* BSpec has 2 recommended values - entries 0 and 8.
33919c468b4SFrançois Tigeot * Using the entry with higher vswing.
34019c468b4SFrançois Tigeot */
34119c468b4SFrançois Tigeot static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
34219c468b4SFrançois Tigeot /* Idx NT mV diff db */
343*3f2dd94aSFrançois Tigeot { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
344*3f2dd94aSFrançois Tigeot { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
345*3f2dd94aSFrançois Tigeot { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
346*3f2dd94aSFrançois Tigeot { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
347*3f2dd94aSFrançois Tigeot { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
348*3f2dd94aSFrançois Tigeot { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
349*3f2dd94aSFrançois Tigeot { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
350*3f2dd94aSFrançois Tigeot { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
351*3f2dd94aSFrançois Tigeot { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
352*3f2dd94aSFrançois Tigeot { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
353*3f2dd94aSFrançois Tigeot };
354*3f2dd94aSFrançois Tigeot
355*3f2dd94aSFrançois Tigeot struct cnl_ddi_buf_trans {
356*3f2dd94aSFrançois Tigeot u8 dw2_swing_sel;
357*3f2dd94aSFrançois Tigeot u8 dw7_n_scalar;
358*3f2dd94aSFrançois Tigeot u8 dw4_cursor_coeff;
359*3f2dd94aSFrançois Tigeot u8 dw4_post_cursor_2;
360*3f2dd94aSFrançois Tigeot u8 dw4_post_cursor_1;
361*3f2dd94aSFrançois Tigeot };
362*3f2dd94aSFrançois Tigeot
363*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 0.85V for DP */
364*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
365*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
366*3f2dd94aSFrançois Tigeot { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
367*3f2dd94aSFrançois Tigeot { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
368*3f2dd94aSFrançois Tigeot { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
369*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
370*3f2dd94aSFrançois Tigeot { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
371*3f2dd94aSFrançois Tigeot { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
372*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
373*3f2dd94aSFrançois Tigeot { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
374*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
375*3f2dd94aSFrançois Tigeot { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
376*3f2dd94aSFrançois Tigeot };
377*3f2dd94aSFrançois Tigeot
378*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 0.85V for HDMI */
379*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
380*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
381*3f2dd94aSFrançois Tigeot { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
382*3f2dd94aSFrançois Tigeot { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
383*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
384*3f2dd94aSFrançois Tigeot { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
385*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
386*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
387*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
388*3f2dd94aSFrançois Tigeot };
389*3f2dd94aSFrançois Tigeot
390*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 0.85V for eDP */
391*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
392*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
393*3f2dd94aSFrançois Tigeot { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
394*3f2dd94aSFrançois Tigeot { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
395*3f2dd94aSFrançois Tigeot { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
396*3f2dd94aSFrançois Tigeot { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
397*3f2dd94aSFrançois Tigeot { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
398*3f2dd94aSFrançois Tigeot { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
399*3f2dd94aSFrançois Tigeot { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
400*3f2dd94aSFrançois Tigeot { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
401*3f2dd94aSFrançois Tigeot { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
402*3f2dd94aSFrançois Tigeot };
403*3f2dd94aSFrançois Tigeot
404*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 0.95V for DP */
405*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
406*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
407*3f2dd94aSFrançois Tigeot { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
408*3f2dd94aSFrançois Tigeot { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
409*3f2dd94aSFrançois Tigeot { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
410*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
411*3f2dd94aSFrançois Tigeot { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
412*3f2dd94aSFrançois Tigeot { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
413*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
414*3f2dd94aSFrançois Tigeot { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
415*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
416*3f2dd94aSFrançois Tigeot { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
417*3f2dd94aSFrançois Tigeot };
418*3f2dd94aSFrançois Tigeot
419*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 0.95V for HDMI */
420*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
421*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
422*3f2dd94aSFrançois Tigeot { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
423*3f2dd94aSFrançois Tigeot { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
424*3f2dd94aSFrançois Tigeot { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
425*3f2dd94aSFrançois Tigeot { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
426*3f2dd94aSFrançois Tigeot { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
427*3f2dd94aSFrançois Tigeot { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
428*3f2dd94aSFrançois Tigeot { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
429*3f2dd94aSFrançois Tigeot { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
430*3f2dd94aSFrançois Tigeot { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
431*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
432*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
433*3f2dd94aSFrançois Tigeot };
434*3f2dd94aSFrançois Tigeot
435*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 0.95V for eDP */
436*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
437*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
438*3f2dd94aSFrançois Tigeot { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
439*3f2dd94aSFrançois Tigeot { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
440*3f2dd94aSFrançois Tigeot { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
441*3f2dd94aSFrançois Tigeot { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
442*3f2dd94aSFrançois Tigeot { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
443*3f2dd94aSFrançois Tigeot { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
444*3f2dd94aSFrançois Tigeot { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
445*3f2dd94aSFrançois Tigeot { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
446*3f2dd94aSFrançois Tigeot { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
447*3f2dd94aSFrançois Tigeot { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
448*3f2dd94aSFrançois Tigeot };
449*3f2dd94aSFrançois Tigeot
450*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 1.05V for DP */
451*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
452*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
453*3f2dd94aSFrançois Tigeot { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
454*3f2dd94aSFrançois Tigeot { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
455*3f2dd94aSFrançois Tigeot { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
456*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
457*3f2dd94aSFrançois Tigeot { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
458*3f2dd94aSFrançois Tigeot { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
459*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
460*3f2dd94aSFrançois Tigeot { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
461*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
462*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
463*3f2dd94aSFrançois Tigeot };
464*3f2dd94aSFrançois Tigeot
465*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 1.05V for HDMI */
466*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
467*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
468*3f2dd94aSFrançois Tigeot { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
469*3f2dd94aSFrançois Tigeot { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
470*3f2dd94aSFrançois Tigeot { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
471*3f2dd94aSFrançois Tigeot { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
472*3f2dd94aSFrançois Tigeot { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
473*3f2dd94aSFrançois Tigeot { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
474*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
475*3f2dd94aSFrançois Tigeot { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
476*3f2dd94aSFrançois Tigeot { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
477*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
478*3f2dd94aSFrançois Tigeot { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
479*3f2dd94aSFrançois Tigeot };
480*3f2dd94aSFrançois Tigeot
481*3f2dd94aSFrançois Tigeot /* Voltage Swing Programming for VccIO 1.05V for eDP */
482*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
483*3f2dd94aSFrançois Tigeot /* NT mV Trans mV db */
484*3f2dd94aSFrançois Tigeot { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
485*3f2dd94aSFrançois Tigeot { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
486*3f2dd94aSFrançois Tigeot { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
487*3f2dd94aSFrançois Tigeot { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
488*3f2dd94aSFrançois Tigeot { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
489*3f2dd94aSFrançois Tigeot { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
490*3f2dd94aSFrançois Tigeot { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
491*3f2dd94aSFrançois Tigeot { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
492*3f2dd94aSFrançois Tigeot { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
49319c468b4SFrançois Tigeot };
49419c468b4SFrançois Tigeot
intel_ddi_get_encoder_port(struct intel_encoder * encoder)49571f41f3eSFrançois Tigeot enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
49619df918dSFrançois Tigeot {
49771f41f3eSFrançois Tigeot switch (encoder->type) {
498352ff8bdSFrançois Tigeot case INTEL_OUTPUT_DP_MST:
49971f41f3eSFrançois Tigeot return enc_to_mst(&encoder->base)->primary->port;
500303bf270SFrançois Tigeot case INTEL_OUTPUT_DP:
501352ff8bdSFrançois Tigeot case INTEL_OUTPUT_EDP:
502352ff8bdSFrançois Tigeot case INTEL_OUTPUT_HDMI:
503352ff8bdSFrançois Tigeot case INTEL_OUTPUT_UNKNOWN:
50471f41f3eSFrançois Tigeot return enc_to_dig_port(&encoder->base)->port;
505352ff8bdSFrançois Tigeot case INTEL_OUTPUT_ANALOG:
50671f41f3eSFrançois Tigeot return PORT_E;
50771f41f3eSFrançois Tigeot default:
50871f41f3eSFrançois Tigeot MISSING_CASE(encoder->type);
50971f41f3eSFrançois Tigeot return PORT_A;
51019df918dSFrançois Tigeot }
51119df918dSFrançois Tigeot }
51219df918dSFrançois Tigeot
51371f41f3eSFrançois Tigeot static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)51471f41f3eSFrançois Tigeot bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
51519c468b4SFrançois Tigeot {
51671f41f3eSFrançois Tigeot if (dev_priv->vbt.edp.low_vswing) {
51771f41f3eSFrançois Tigeot *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
51871f41f3eSFrançois Tigeot return bdw_ddi_translations_edp;
51971f41f3eSFrançois Tigeot } else {
52071f41f3eSFrançois Tigeot *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
52171f41f3eSFrançois Tigeot return bdw_ddi_translations_dp;
52271f41f3eSFrançois Tigeot }
52319c468b4SFrançois Tigeot }
52419c468b4SFrançois Tigeot
525c0e85e96SFrançois Tigeot static const struct ddi_buf_trans *
skl_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)526c0e85e96SFrançois Tigeot skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
52719c468b4SFrançois Tigeot {
5281e12ee3bSFrançois Tigeot if (IS_SKL_ULX(dev_priv)) {
529a05eeebfSFrançois Tigeot *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
530c0e85e96SFrançois Tigeot return skl_y_ddi_translations_dp;
5311e12ee3bSFrançois Tigeot } else if (IS_SKL_ULT(dev_priv)) {
532a05eeebfSFrançois Tigeot *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
533c0e85e96SFrançois Tigeot return skl_u_ddi_translations_dp;
534a05eeebfSFrançois Tigeot } else {
535a05eeebfSFrançois Tigeot *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
536c0e85e96SFrançois Tigeot return skl_ddi_translations_dp;
537a05eeebfSFrançois Tigeot }
538a05eeebfSFrançois Tigeot }
539a05eeebfSFrançois Tigeot
540a05eeebfSFrançois Tigeot static const struct ddi_buf_trans *
kbl_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)5411e12ee3bSFrançois Tigeot kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
5421e12ee3bSFrançois Tigeot {
5431e12ee3bSFrançois Tigeot if (IS_KBL_ULX(dev_priv)) {
5441e12ee3bSFrançois Tigeot *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
5451e12ee3bSFrançois Tigeot return kbl_y_ddi_translations_dp;
546*3f2dd94aSFrançois Tigeot } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
5471e12ee3bSFrançois Tigeot *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
5481e12ee3bSFrançois Tigeot return kbl_u_ddi_translations_dp;
5491e12ee3bSFrançois Tigeot } else {
5501e12ee3bSFrançois Tigeot *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
5511e12ee3bSFrançois Tigeot return kbl_ddi_translations_dp;
5521e12ee3bSFrançois Tigeot }
5531e12ee3bSFrançois Tigeot }
5541e12ee3bSFrançois Tigeot
5551e12ee3bSFrançois Tigeot static const struct ddi_buf_trans *
skl_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)556c0e85e96SFrançois Tigeot skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
557a05eeebfSFrançois Tigeot {
5588621f407SFrançois Tigeot if (dev_priv->vbt.edp.low_vswing) {
559c0e85e96SFrançois Tigeot if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
560c0e85e96SFrançois Tigeot *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
561c0e85e96SFrançois Tigeot return skl_y_ddi_translations_edp;
562*3f2dd94aSFrançois Tigeot } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
563*3f2dd94aSFrançois Tigeot IS_CFL_ULT(dev_priv)) {
564c0e85e96SFrançois Tigeot *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
565c0e85e96SFrançois Tigeot return skl_u_ddi_translations_edp;
566a05eeebfSFrançois Tigeot } else {
567c0e85e96SFrançois Tigeot *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
568c0e85e96SFrançois Tigeot return skl_ddi_translations_edp;
569c0e85e96SFrançois Tigeot }
570a05eeebfSFrançois Tigeot }
571a05eeebfSFrançois Tigeot
572*3f2dd94aSFrançois Tigeot if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
5731e12ee3bSFrançois Tigeot return kbl_get_buf_trans_dp(dev_priv, n_entries);
5741e12ee3bSFrançois Tigeot else
575c0e85e96SFrançois Tigeot return skl_get_buf_trans_dp(dev_priv, n_entries);
576c0e85e96SFrançois Tigeot }
577c0e85e96SFrançois Tigeot
578c0e85e96SFrançois Tigeot static const struct ddi_buf_trans *
skl_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)579c0e85e96SFrançois Tigeot skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
580c0e85e96SFrançois Tigeot {
581c0e85e96SFrançois Tigeot if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
582c0e85e96SFrançois Tigeot *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
583c0e85e96SFrançois Tigeot return skl_y_ddi_translations_hdmi;
584c0e85e96SFrançois Tigeot } else {
585c0e85e96SFrançois Tigeot *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
586c0e85e96SFrançois Tigeot return skl_ddi_translations_hdmi;
587c0e85e96SFrançois Tigeot }
588a05eeebfSFrançois Tigeot }
589a05eeebfSFrançois Tigeot
skl_buf_trans_num_entries(enum port port,int n_entries)590*3f2dd94aSFrançois Tigeot static int skl_buf_trans_num_entries(enum port port, int n_entries)
5918621f407SFrançois Tigeot {
592*3f2dd94aSFrançois Tigeot /* Only DDIA and DDIE can select the 10th register with DP */
593*3f2dd94aSFrançois Tigeot if (port == PORT_A || port == PORT_E)
594*3f2dd94aSFrançois Tigeot return min(n_entries, 10);
595*3f2dd94aSFrançois Tigeot else
596*3f2dd94aSFrançois Tigeot return min(n_entries, 9);
5978621f407SFrançois Tigeot }
5988621f407SFrançois Tigeot
599a85cb24fSFrançois Tigeot static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_dp(struct drm_i915_private * dev_priv,enum port port,int * n_entries)600a85cb24fSFrançois Tigeot intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
601*3f2dd94aSFrançois Tigeot enum port port, int *n_entries)
602a85cb24fSFrançois Tigeot {
603*3f2dd94aSFrançois Tigeot if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
604*3f2dd94aSFrançois Tigeot const struct ddi_buf_trans *ddi_translations =
605*3f2dd94aSFrançois Tigeot kbl_get_buf_trans_dp(dev_priv, n_entries);
606*3f2dd94aSFrançois Tigeot *n_entries = skl_buf_trans_num_entries(port, *n_entries);
607*3f2dd94aSFrançois Tigeot return ddi_translations;
608a85cb24fSFrançois Tigeot } else if (IS_SKYLAKE(dev_priv)) {
609*3f2dd94aSFrançois Tigeot const struct ddi_buf_trans *ddi_translations =
610*3f2dd94aSFrançois Tigeot skl_get_buf_trans_dp(dev_priv, n_entries);
611*3f2dd94aSFrançois Tigeot *n_entries = skl_buf_trans_num_entries(port, *n_entries);
612*3f2dd94aSFrançois Tigeot return ddi_translations;
613a85cb24fSFrançois Tigeot } else if (IS_BROADWELL(dev_priv)) {
614a85cb24fSFrançois Tigeot *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
615a85cb24fSFrançois Tigeot return bdw_ddi_translations_dp;
616a85cb24fSFrançois Tigeot } else if (IS_HASWELL(dev_priv)) {
617a85cb24fSFrançois Tigeot *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
618a85cb24fSFrançois Tigeot return hsw_ddi_translations_dp;
619a85cb24fSFrançois Tigeot }
620a85cb24fSFrançois Tigeot
621a85cb24fSFrançois Tigeot *n_entries = 0;
622a85cb24fSFrançois Tigeot return NULL;
623a85cb24fSFrançois Tigeot }
624a85cb24fSFrançois Tigeot
625a85cb24fSFrançois Tigeot static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_edp(struct drm_i915_private * dev_priv,enum port port,int * n_entries)626a85cb24fSFrançois Tigeot intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
627*3f2dd94aSFrançois Tigeot enum port port, int *n_entries)
628a85cb24fSFrançois Tigeot {
629*3f2dd94aSFrançois Tigeot if (IS_GEN9_BC(dev_priv)) {
630*3f2dd94aSFrançois Tigeot const struct ddi_buf_trans *ddi_translations =
631*3f2dd94aSFrançois Tigeot skl_get_buf_trans_edp(dev_priv, n_entries);
632*3f2dd94aSFrançois Tigeot *n_entries = skl_buf_trans_num_entries(port, *n_entries);
633*3f2dd94aSFrançois Tigeot return ddi_translations;
634a85cb24fSFrançois Tigeot } else if (IS_BROADWELL(dev_priv)) {
635a85cb24fSFrançois Tigeot return bdw_get_buf_trans_edp(dev_priv, n_entries);
636a85cb24fSFrançois Tigeot } else if (IS_HASWELL(dev_priv)) {
637a85cb24fSFrançois Tigeot *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
638a85cb24fSFrançois Tigeot return hsw_ddi_translations_dp;
639a85cb24fSFrançois Tigeot }
640a85cb24fSFrançois Tigeot
641a85cb24fSFrançois Tigeot *n_entries = 0;
642a85cb24fSFrançois Tigeot return NULL;
643a85cb24fSFrançois Tigeot }
644a85cb24fSFrançois Tigeot
645a85cb24fSFrançois Tigeot static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_fdi(struct drm_i915_private * dev_priv,int * n_entries)646a85cb24fSFrançois Tigeot intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
647a85cb24fSFrançois Tigeot int *n_entries)
648a85cb24fSFrançois Tigeot {
649a85cb24fSFrançois Tigeot if (IS_BROADWELL(dev_priv)) {
650*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
651*3f2dd94aSFrançois Tigeot return bdw_ddi_translations_fdi;
652a85cb24fSFrançois Tigeot } else if (IS_HASWELL(dev_priv)) {
653a85cb24fSFrançois Tigeot *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
654a85cb24fSFrançois Tigeot return hsw_ddi_translations_fdi;
655a85cb24fSFrançois Tigeot }
656a85cb24fSFrançois Tigeot
657a85cb24fSFrançois Tigeot *n_entries = 0;
658a85cb24fSFrançois Tigeot return NULL;
659a85cb24fSFrançois Tigeot }
660a85cb24fSFrançois Tigeot
661*3f2dd94aSFrançois Tigeot static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)662*3f2dd94aSFrançois Tigeot intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
663*3f2dd94aSFrançois Tigeot int *n_entries)
664*3f2dd94aSFrançois Tigeot {
665*3f2dd94aSFrançois Tigeot if (IS_GEN9_BC(dev_priv)) {
666*3f2dd94aSFrançois Tigeot return skl_get_buf_trans_hdmi(dev_priv, n_entries);
667*3f2dd94aSFrançois Tigeot } else if (IS_BROADWELL(dev_priv)) {
668*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
669*3f2dd94aSFrançois Tigeot return bdw_ddi_translations_hdmi;
670*3f2dd94aSFrançois Tigeot } else if (IS_HASWELL(dev_priv)) {
671*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
672*3f2dd94aSFrançois Tigeot return hsw_ddi_translations_hdmi;
673*3f2dd94aSFrançois Tigeot }
674*3f2dd94aSFrançois Tigeot
675*3f2dd94aSFrançois Tigeot *n_entries = 0;
676*3f2dd94aSFrançois Tigeot return NULL;
677*3f2dd94aSFrançois Tigeot }
678*3f2dd94aSFrançois Tigeot
679*3f2dd94aSFrançois Tigeot static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)680*3f2dd94aSFrançois Tigeot bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
681*3f2dd94aSFrançois Tigeot {
682*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
683*3f2dd94aSFrançois Tigeot return bxt_ddi_translations_dp;
684*3f2dd94aSFrançois Tigeot }
685*3f2dd94aSFrançois Tigeot
686*3f2dd94aSFrançois Tigeot static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)687*3f2dd94aSFrançois Tigeot bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
688*3f2dd94aSFrançois Tigeot {
689*3f2dd94aSFrançois Tigeot if (dev_priv->vbt.edp.low_vswing) {
690*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
691*3f2dd94aSFrançois Tigeot return bxt_ddi_translations_edp;
692*3f2dd94aSFrançois Tigeot }
693*3f2dd94aSFrançois Tigeot
694*3f2dd94aSFrançois Tigeot return bxt_get_buf_trans_dp(dev_priv, n_entries);
695*3f2dd94aSFrançois Tigeot }
696*3f2dd94aSFrançois Tigeot
697*3f2dd94aSFrançois Tigeot static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)698*3f2dd94aSFrançois Tigeot bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
699*3f2dd94aSFrançois Tigeot {
700*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
701*3f2dd94aSFrançois Tigeot return bxt_ddi_translations_hdmi;
702*3f2dd94aSFrançois Tigeot }
703*3f2dd94aSFrançois Tigeot
704*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)705*3f2dd94aSFrançois Tigeot cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
706*3f2dd94aSFrançois Tigeot {
707*3f2dd94aSFrançois Tigeot u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
708*3f2dd94aSFrançois Tigeot
709*3f2dd94aSFrançois Tigeot if (voltage == VOLTAGE_INFO_0_85V) {
710*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
711*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_hdmi_0_85V;
712*3f2dd94aSFrançois Tigeot } else if (voltage == VOLTAGE_INFO_0_95V) {
713*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
714*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_hdmi_0_95V;
715*3f2dd94aSFrançois Tigeot } else if (voltage == VOLTAGE_INFO_1_05V) {
716*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
717*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_hdmi_1_05V;
718*3f2dd94aSFrançois Tigeot } else {
719*3f2dd94aSFrançois Tigeot *n_entries = 1; /* shut up gcc */
720*3f2dd94aSFrançois Tigeot MISSING_CASE(voltage);
721*3f2dd94aSFrançois Tigeot }
722*3f2dd94aSFrançois Tigeot return NULL;
723*3f2dd94aSFrançois Tigeot }
724*3f2dd94aSFrançois Tigeot
725*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)726*3f2dd94aSFrançois Tigeot cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
727*3f2dd94aSFrançois Tigeot {
728*3f2dd94aSFrançois Tigeot u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
729*3f2dd94aSFrançois Tigeot
730*3f2dd94aSFrançois Tigeot if (voltage == VOLTAGE_INFO_0_85V) {
731*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
732*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_dp_0_85V;
733*3f2dd94aSFrançois Tigeot } else if (voltage == VOLTAGE_INFO_0_95V) {
734*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
735*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_dp_0_95V;
736*3f2dd94aSFrançois Tigeot } else if (voltage == VOLTAGE_INFO_1_05V) {
737*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
738*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_dp_1_05V;
739*3f2dd94aSFrançois Tigeot } else {
740*3f2dd94aSFrançois Tigeot *n_entries = 1; /* shut up gcc */
741*3f2dd94aSFrançois Tigeot MISSING_CASE(voltage);
742*3f2dd94aSFrançois Tigeot }
743*3f2dd94aSFrançois Tigeot return NULL;
744*3f2dd94aSFrançois Tigeot }
745*3f2dd94aSFrançois Tigeot
746*3f2dd94aSFrançois Tigeot static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)747*3f2dd94aSFrançois Tigeot cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
748*3f2dd94aSFrançois Tigeot {
749*3f2dd94aSFrançois Tigeot u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
750*3f2dd94aSFrançois Tigeot
751*3f2dd94aSFrançois Tigeot if (dev_priv->vbt.edp.low_vswing) {
752*3f2dd94aSFrançois Tigeot if (voltage == VOLTAGE_INFO_0_85V) {
753*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
754*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_edp_0_85V;
755*3f2dd94aSFrançois Tigeot } else if (voltage == VOLTAGE_INFO_0_95V) {
756*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
757*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_edp_0_95V;
758*3f2dd94aSFrançois Tigeot } else if (voltage == VOLTAGE_INFO_1_05V) {
759*3f2dd94aSFrançois Tigeot *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
760*3f2dd94aSFrançois Tigeot return cnl_ddi_translations_edp_1_05V;
761*3f2dd94aSFrançois Tigeot } else {
762*3f2dd94aSFrançois Tigeot *n_entries = 1; /* shut up gcc */
763*3f2dd94aSFrançois Tigeot MISSING_CASE(voltage);
764*3f2dd94aSFrançois Tigeot }
765*3f2dd94aSFrançois Tigeot return NULL;
766*3f2dd94aSFrançois Tigeot } else {
767*3f2dd94aSFrançois Tigeot return cnl_get_buf_trans_dp(dev_priv, n_entries);
768*3f2dd94aSFrançois Tigeot }
769*3f2dd94aSFrançois Tigeot }
770*3f2dd94aSFrançois Tigeot
intel_ddi_hdmi_level(struct drm_i915_private * dev_priv,enum port port)771*3f2dd94aSFrançois Tigeot static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
772*3f2dd94aSFrançois Tigeot {
773*3f2dd94aSFrançois Tigeot int n_entries, level, default_entry;
774*3f2dd94aSFrançois Tigeot
775*3f2dd94aSFrançois Tigeot level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
776*3f2dd94aSFrançois Tigeot
777*3f2dd94aSFrançois Tigeot if (IS_CANNONLAKE(dev_priv)) {
778*3f2dd94aSFrançois Tigeot cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
779*3f2dd94aSFrançois Tigeot default_entry = n_entries - 1;
780*3f2dd94aSFrançois Tigeot } else if (IS_GEN9_LP(dev_priv)) {
781*3f2dd94aSFrançois Tigeot bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
782*3f2dd94aSFrançois Tigeot default_entry = n_entries - 1;
783*3f2dd94aSFrançois Tigeot } else if (IS_GEN9_BC(dev_priv)) {
784*3f2dd94aSFrançois Tigeot intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
785*3f2dd94aSFrançois Tigeot default_entry = 8;
786*3f2dd94aSFrançois Tigeot } else if (IS_BROADWELL(dev_priv)) {
787*3f2dd94aSFrançois Tigeot intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
788*3f2dd94aSFrançois Tigeot default_entry = 7;
789*3f2dd94aSFrançois Tigeot } else if (IS_HASWELL(dev_priv)) {
790*3f2dd94aSFrançois Tigeot intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
791*3f2dd94aSFrançois Tigeot default_entry = 6;
792*3f2dd94aSFrançois Tigeot } else {
793*3f2dd94aSFrançois Tigeot WARN(1, "ddi translation table missing\n");
794*3f2dd94aSFrançois Tigeot return 0;
795*3f2dd94aSFrançois Tigeot }
796*3f2dd94aSFrançois Tigeot
797*3f2dd94aSFrançois Tigeot /* Choose a good default if VBT is badly populated */
798*3f2dd94aSFrançois Tigeot if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
799*3f2dd94aSFrançois Tigeot level = default_entry;
800*3f2dd94aSFrançois Tigeot
801*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(n_entries == 0))
802*3f2dd94aSFrançois Tigeot return 0;
803*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(level >= n_entries))
804*3f2dd94aSFrançois Tigeot level = n_entries - 1;
805*3f2dd94aSFrançois Tigeot
806*3f2dd94aSFrançois Tigeot return level;
807*3f2dd94aSFrançois Tigeot }
808*3f2dd94aSFrançois Tigeot
8099edbd4a0SFrançois Tigeot /*
8109edbd4a0SFrançois Tigeot * Starting with Haswell, DDI port buffers must be programmed with correct
81171f41f3eSFrançois Tigeot * values in advance. This function programs the correct values for
81271f41f3eSFrançois Tigeot * DP/eDP/FDI use cases.
81319df918dSFrançois Tigeot */
intel_prepare_dp_ddi_buffers(struct intel_encoder * encoder)814a85cb24fSFrançois Tigeot static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
81519df918dSFrançois Tigeot {
816c0e85e96SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
817a05eeebfSFrançois Tigeot u32 iboost_bit = 0;
818a85cb24fSFrançois Tigeot int i, n_entries;
81971f41f3eSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
8201b13d190SFrançois Tigeot const struct ddi_buf_trans *ddi_translations;
82119df918dSFrançois Tigeot
822a85cb24fSFrançois Tigeot switch (encoder->type) {
823a85cb24fSFrançois Tigeot case INTEL_OUTPUT_EDP:
824*3f2dd94aSFrançois Tigeot ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
825a85cb24fSFrançois Tigeot &n_entries);
826a85cb24fSFrançois Tigeot break;
827a85cb24fSFrançois Tigeot case INTEL_OUTPUT_DP:
828*3f2dd94aSFrançois Tigeot ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
829a85cb24fSFrançois Tigeot &n_entries);
830a85cb24fSFrançois Tigeot break;
831a85cb24fSFrançois Tigeot case INTEL_OUTPUT_ANALOG:
832a85cb24fSFrançois Tigeot ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
833a85cb24fSFrançois Tigeot &n_entries);
834a85cb24fSFrançois Tigeot break;
835a85cb24fSFrançois Tigeot default:
836a85cb24fSFrançois Tigeot MISSING_CASE(encoder->type);
837a85cb24fSFrançois Tigeot return;
8389edbd4a0SFrançois Tigeot }
83919df918dSFrançois Tigeot
8401e12ee3bSFrançois Tigeot /* If we're boosting the current, set bit 31 of trans1 */
841*3f2dd94aSFrançois Tigeot if (IS_GEN9_BC(dev_priv) &&
842*3f2dd94aSFrançois Tigeot dev_priv->vbt.ddi_port_info[port].dp_boost_level)
8431e12ee3bSFrançois Tigeot iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
8441e12ee3bSFrançois Tigeot
845a85cb24fSFrançois Tigeot for (i = 0; i < n_entries; i++) {
846352ff8bdSFrançois Tigeot I915_WRITE(DDI_BUF_TRANS_LO(port, i),
847352ff8bdSFrançois Tigeot ddi_translations[i].trans1 | iboost_bit);
848352ff8bdSFrançois Tigeot I915_WRITE(DDI_BUF_TRANS_HI(port, i),
849352ff8bdSFrançois Tigeot ddi_translations[i].trans2);
85019df918dSFrançois Tigeot }
85171f41f3eSFrançois Tigeot }
8521b13d190SFrançois Tigeot
85371f41f3eSFrançois Tigeot /*
85471f41f3eSFrançois Tigeot * Starting with Haswell, DDI port buffers must be programmed with correct
85571f41f3eSFrançois Tigeot * values in advance. This function programs the correct values for
85671f41f3eSFrançois Tigeot * HDMI/DVI use cases.
85771f41f3eSFrançois Tigeot */
intel_prepare_hdmi_ddi_buffers(struct intel_encoder * encoder,int level)858*3f2dd94aSFrançois Tigeot static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
859*3f2dd94aSFrançois Tigeot int level)
86071f41f3eSFrançois Tigeot {
86171f41f3eSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
86271f41f3eSFrançois Tigeot u32 iboost_bit = 0;
863*3f2dd94aSFrançois Tigeot int n_entries;
86471f41f3eSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
865*3f2dd94aSFrançois Tigeot const struct ddi_buf_trans *ddi_translations;
86671f41f3eSFrançois Tigeot
867*3f2dd94aSFrançois Tigeot ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
868*3f2dd94aSFrançois Tigeot
869*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(!ddi_translations))
87019c468b4SFrançois Tigeot return;
871*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(level >= n_entries))
872*3f2dd94aSFrançois Tigeot level = n_entries - 1;
87371f41f3eSFrançois Tigeot
87471f41f3eSFrançois Tigeot /* If we're boosting the current, set bit 31 of trans1 */
875*3f2dd94aSFrançois Tigeot if (IS_GEN9_BC(dev_priv) &&
876*3f2dd94aSFrançois Tigeot dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
87771f41f3eSFrançois Tigeot iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
87871f41f3eSFrançois Tigeot
8799edbd4a0SFrançois Tigeot /* Entry 9 is for HDMI: */
88071f41f3eSFrançois Tigeot I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
881*3f2dd94aSFrançois Tigeot ddi_translations[level].trans1 | iboost_bit);
88271f41f3eSFrançois Tigeot I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
883*3f2dd94aSFrançois Tigeot ddi_translations[level].trans2);
88419df918dSFrançois Tigeot }
88519df918dSFrançois Tigeot
intel_wait_ddi_buf_idle(struct drm_i915_private * dev_priv,enum port port)88619df918dSFrançois Tigeot static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
88719df918dSFrançois Tigeot enum port port)
88819df918dSFrançois Tigeot {
889aee94f86SFrançois Tigeot i915_reg_t reg = DDI_BUF_CTL(port);
89019df918dSFrançois Tigeot int i;
89119df918dSFrançois Tigeot
89219c468b4SFrançois Tigeot for (i = 0; i < 16; i++) {
89319df918dSFrançois Tigeot udelay(1);
89419df918dSFrançois Tigeot if (I915_READ(reg) & DDI_BUF_IS_IDLE)
89519df918dSFrançois Tigeot return;
89619df918dSFrançois Tigeot }
89719df918dSFrançois Tigeot DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
89819df918dSFrançois Tigeot }
89919df918dSFrançois Tigeot
hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll * pll)900*3f2dd94aSFrançois Tigeot static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
9011e12ee3bSFrançois Tigeot {
9021e12ee3bSFrançois Tigeot switch (pll->id) {
9031e12ee3bSFrançois Tigeot case DPLL_ID_WRPLL1:
9041e12ee3bSFrançois Tigeot return PORT_CLK_SEL_WRPLL1;
9051e12ee3bSFrançois Tigeot case DPLL_ID_WRPLL2:
9061e12ee3bSFrançois Tigeot return PORT_CLK_SEL_WRPLL2;
9071e12ee3bSFrançois Tigeot case DPLL_ID_SPLL:
9081e12ee3bSFrançois Tigeot return PORT_CLK_SEL_SPLL;
9091e12ee3bSFrançois Tigeot case DPLL_ID_LCPLL_810:
9101e12ee3bSFrançois Tigeot return PORT_CLK_SEL_LCPLL_810;
9111e12ee3bSFrançois Tigeot case DPLL_ID_LCPLL_1350:
9121e12ee3bSFrançois Tigeot return PORT_CLK_SEL_LCPLL_1350;
9131e12ee3bSFrançois Tigeot case DPLL_ID_LCPLL_2700:
9141e12ee3bSFrançois Tigeot return PORT_CLK_SEL_LCPLL_2700;
9151e12ee3bSFrançois Tigeot default:
9161e12ee3bSFrançois Tigeot MISSING_CASE(pll->id);
9171e12ee3bSFrançois Tigeot return PORT_CLK_SEL_NONE;
9181e12ee3bSFrançois Tigeot }
9191e12ee3bSFrançois Tigeot }
9201e12ee3bSFrançois Tigeot
92119df918dSFrançois Tigeot /* Starting with Haswell, different DDI ports can work in FDI mode for
92219df918dSFrançois Tigeot * connection to the PCH-located connectors. For this, it is necessary to train
92319df918dSFrançois Tigeot * both the DDI port and PCH receiver for the desired DDI buffer settings.
92419df918dSFrançois Tigeot *
92519df918dSFrançois Tigeot * The recommended port to work in FDI mode is DDI E, which we use here. Also,
92619df918dSFrançois Tigeot * please note that when FDI mode is active on DDI E, it shares 2 lines with
92719df918dSFrançois Tigeot * DDI A (which is used for eDP)
92819df918dSFrançois Tigeot */
92919df918dSFrançois Tigeot
hsw_fdi_link_train(struct intel_crtc * crtc,const struct intel_crtc_state * crtc_state)930a85cb24fSFrançois Tigeot void hsw_fdi_link_train(struct intel_crtc *crtc,
931a85cb24fSFrançois Tigeot const struct intel_crtc_state *crtc_state)
93219df918dSFrançois Tigeot {
933a85cb24fSFrançois Tigeot struct drm_device *dev = crtc->base.dev;
934303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
935c0e85e96SFrançois Tigeot struct intel_encoder *encoder;
9361e12ee3bSFrançois Tigeot u32 temp, i, rx_ctl_val, ddi_pll_sel;
93719df918dSFrançois Tigeot
938a85cb24fSFrançois Tigeot for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
939c0e85e96SFrançois Tigeot WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
94071f41f3eSFrançois Tigeot intel_prepare_dp_ddi_buffers(encoder);
941c0e85e96SFrançois Tigeot }
942c0e85e96SFrançois Tigeot
94319df918dSFrançois Tigeot /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
94419df918dSFrançois Tigeot * mode set "sequence for CRT port" document:
94519df918dSFrançois Tigeot * - TP1 to TP2 time with the default value
94619df918dSFrançois Tigeot * - FDI delay to 90h
9475d0b1887SFrançois Tigeot *
9485d0b1887SFrançois Tigeot * WaFDIAutoLinkSetTimingOverrride:hsw
94919df918dSFrançois Tigeot */
950352ff8bdSFrançois Tigeot I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
95119df918dSFrançois Tigeot FDI_RX_PWRDN_LANE0_VAL(2) |
95219df918dSFrançois Tigeot FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
95319df918dSFrançois Tigeot
95419df918dSFrançois Tigeot /* Enable the PCH Receiver FDI PLL */
95519df918dSFrançois Tigeot rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
9565d0b1887SFrançois Tigeot FDI_RX_PLL_ENABLE |
957a85cb24fSFrançois Tigeot FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
958352ff8bdSFrançois Tigeot I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
959352ff8bdSFrançois Tigeot POSTING_READ(FDI_RX_CTL(PIPE_A));
96019df918dSFrançois Tigeot udelay(220);
96119df918dSFrançois Tigeot
96219df918dSFrançois Tigeot /* Switch from Rawclk to PCDclk */
96319df918dSFrançois Tigeot rx_ctl_val |= FDI_PCDCLK;
964352ff8bdSFrançois Tigeot I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
96519df918dSFrançois Tigeot
96619df918dSFrançois Tigeot /* Configure Port Clock Select */
967a85cb24fSFrançois Tigeot ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
9681e12ee3bSFrançois Tigeot I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
9691e12ee3bSFrançois Tigeot WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
97019df918dSFrançois Tigeot
97119df918dSFrançois Tigeot /* Start the training iterating through available voltages and emphasis,
97219df918dSFrançois Tigeot * testing each value twice. */
9731b13d190SFrançois Tigeot for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
97419df918dSFrançois Tigeot /* Configure DP_TP_CTL with auto-training */
97519df918dSFrançois Tigeot I915_WRITE(DP_TP_CTL(PORT_E),
97619df918dSFrançois Tigeot DP_TP_CTL_FDI_AUTOTRAIN |
97719df918dSFrançois Tigeot DP_TP_CTL_ENHANCED_FRAME_ENABLE |
97819df918dSFrançois Tigeot DP_TP_CTL_LINK_TRAIN_PAT1 |
97919df918dSFrançois Tigeot DP_TP_CTL_ENABLE);
98019df918dSFrançois Tigeot
98119df918dSFrançois Tigeot /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
98219df918dSFrançois Tigeot * DDI E does not support port reversal, the functionality is
98319df918dSFrançois Tigeot * achieved on the PCH side in FDI_RX_CTL, so no need to set the
98419df918dSFrançois Tigeot * port reversal bit */
98519df918dSFrançois Tigeot I915_WRITE(DDI_BUF_CTL(PORT_E),
98619df918dSFrançois Tigeot DDI_BUF_CTL_ENABLE |
987a85cb24fSFrançois Tigeot ((crtc_state->fdi_lanes - 1) << 1) |
9881b13d190SFrançois Tigeot DDI_BUF_TRANS_SELECT(i / 2));
98919df918dSFrançois Tigeot POSTING_READ(DDI_BUF_CTL(PORT_E));
99019df918dSFrançois Tigeot
99119df918dSFrançois Tigeot udelay(600);
99219df918dSFrançois Tigeot
99319df918dSFrançois Tigeot /* Program PCH FDI Receiver TU */
994352ff8bdSFrançois Tigeot I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
99519df918dSFrançois Tigeot
99619df918dSFrançois Tigeot /* Enable PCH FDI Receiver with auto-training */
99719df918dSFrançois Tigeot rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
998352ff8bdSFrançois Tigeot I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
999352ff8bdSFrançois Tigeot POSTING_READ(FDI_RX_CTL(PIPE_A));
100019df918dSFrançois Tigeot
100119df918dSFrançois Tigeot /* Wait for FDI receiver lane calibration */
100219df918dSFrançois Tigeot udelay(30);
100319df918dSFrançois Tigeot
100419df918dSFrançois Tigeot /* Unset FDI_RX_MISC pwrdn lanes */
1005352ff8bdSFrançois Tigeot temp = I915_READ(FDI_RX_MISC(PIPE_A));
100619df918dSFrançois Tigeot temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1007352ff8bdSFrançois Tigeot I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1008352ff8bdSFrançois Tigeot POSTING_READ(FDI_RX_MISC(PIPE_A));
100919df918dSFrançois Tigeot
101019df918dSFrançois Tigeot /* Wait for FDI auto training time */
101119df918dSFrançois Tigeot udelay(5);
101219df918dSFrançois Tigeot
101319df918dSFrançois Tigeot temp = I915_READ(DP_TP_STATUS(PORT_E));
101419df918dSFrançois Tigeot if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
101519df918dSFrançois Tigeot DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1016aee94f86SFrançois Tigeot break;
1017aee94f86SFrançois Tigeot }
101819df918dSFrançois Tigeot
1019aee94f86SFrançois Tigeot /*
1020aee94f86SFrançois Tigeot * Leave things enabled even if we failed to train FDI.
1021aee94f86SFrançois Tigeot * Results in less fireworks from the state checker.
1022aee94f86SFrançois Tigeot */
1023aee94f86SFrançois Tigeot if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1024aee94f86SFrançois Tigeot DRM_ERROR("FDI link training failed!\n");
1025aee94f86SFrançois Tigeot break;
102619df918dSFrançois Tigeot }
102719df918dSFrançois Tigeot
10288621f407SFrançois Tigeot rx_ctl_val &= ~FDI_RX_ENABLE;
10298621f407SFrançois Tigeot I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
10308621f407SFrançois Tigeot POSTING_READ(FDI_RX_CTL(PIPE_A));
10318621f407SFrançois Tigeot
103219df918dSFrançois Tigeot temp = I915_READ(DDI_BUF_CTL(PORT_E));
103319df918dSFrançois Tigeot temp &= ~DDI_BUF_CTL_ENABLE;
103419df918dSFrançois Tigeot I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
103519df918dSFrançois Tigeot POSTING_READ(DDI_BUF_CTL(PORT_E));
103619df918dSFrançois Tigeot
103719df918dSFrançois Tigeot /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
103819df918dSFrançois Tigeot temp = I915_READ(DP_TP_CTL(PORT_E));
103919df918dSFrançois Tigeot temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
104019df918dSFrançois Tigeot temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
104119df918dSFrançois Tigeot I915_WRITE(DP_TP_CTL(PORT_E), temp);
104219df918dSFrançois Tigeot POSTING_READ(DP_TP_CTL(PORT_E));
104319df918dSFrançois Tigeot
104419df918dSFrançois Tigeot intel_wait_ddi_buf_idle(dev_priv, PORT_E);
104519df918dSFrançois Tigeot
104619df918dSFrançois Tigeot /* Reset FDI_RX_MISC pwrdn lanes */
1047352ff8bdSFrançois Tigeot temp = I915_READ(FDI_RX_MISC(PIPE_A));
104819df918dSFrançois Tigeot temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
104919df918dSFrançois Tigeot temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1050352ff8bdSFrançois Tigeot I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1051352ff8bdSFrançois Tigeot POSTING_READ(FDI_RX_MISC(PIPE_A));
105219df918dSFrançois Tigeot }
105319df918dSFrançois Tigeot
1054aee94f86SFrançois Tigeot /* Enable normal pixel sending for FDI */
1055aee94f86SFrançois Tigeot I915_WRITE(DP_TP_CTL(PORT_E),
1056aee94f86SFrançois Tigeot DP_TP_CTL_FDI_AUTOTRAIN |
1057aee94f86SFrançois Tigeot DP_TP_CTL_LINK_TRAIN_NORMAL |
1058aee94f86SFrançois Tigeot DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1059aee94f86SFrançois Tigeot DP_TP_CTL_ENABLE);
106019df918dSFrançois Tigeot }
106119df918dSFrançois Tigeot
intel_ddi_init_dp_buf_reg(struct intel_encoder * encoder)1062a85cb24fSFrançois Tigeot static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
10631b13d190SFrançois Tigeot {
10641b13d190SFrançois Tigeot struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
10651b13d190SFrançois Tigeot struct intel_digital_port *intel_dig_port =
10661b13d190SFrançois Tigeot enc_to_dig_port(&encoder->base);
10671b13d190SFrançois Tigeot
10681b13d190SFrançois Tigeot intel_dp->DP = intel_dig_port->saved_port_bits |
10691b13d190SFrançois Tigeot DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
10701b13d190SFrançois Tigeot intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
10711b13d190SFrançois Tigeot }
10721b13d190SFrançois Tigeot
107319df918dSFrançois Tigeot static struct intel_encoder *
intel_ddi_get_crtc_encoder(struct intel_crtc * crtc)1074a85cb24fSFrançois Tigeot intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
107519df918dSFrançois Tigeot {
1076a85cb24fSFrançois Tigeot struct drm_device *dev = crtc->base.dev;
1077a85cb24fSFrançois Tigeot struct intel_encoder *encoder, *ret = NULL;
107819df918dSFrançois Tigeot int num_encoders = 0;
107919df918dSFrançois Tigeot
1080a85cb24fSFrançois Tigeot for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1081a85cb24fSFrançois Tigeot ret = encoder;
108219df918dSFrançois Tigeot num_encoders++;
108319df918dSFrançois Tigeot }
108419df918dSFrançois Tigeot
108519df918dSFrançois Tigeot if (num_encoders != 1)
10865d0b1887SFrançois Tigeot WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1087a85cb24fSFrançois Tigeot pipe_name(crtc->pipe));
108819df918dSFrançois Tigeot
108919df918dSFrançois Tigeot BUG_ON(ret == NULL);
109019df918dSFrançois Tigeot return ret;
109119df918dSFrançois Tigeot }
109219df918dSFrançois Tigeot
1093a85cb24fSFrançois Tigeot /* Finds the only possible encoder associated with the given CRTC. */
109419c468b4SFrançois Tigeot struct intel_encoder *
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state * crtc_state)1095477eb7f9SFrançois Tigeot intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
10962c9916cdSFrançois Tigeot {
1097477eb7f9SFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1098477eb7f9SFrançois Tigeot struct intel_encoder *ret = NULL;
1099477eb7f9SFrançois Tigeot struct drm_atomic_state *state;
110019c468b4SFrançois Tigeot struct drm_connector *connector;
110119c468b4SFrançois Tigeot struct drm_connector_state *connector_state;
11022c9916cdSFrançois Tigeot int num_encoders = 0;
1103477eb7f9SFrançois Tigeot int i;
11042c9916cdSFrançois Tigeot
1105477eb7f9SFrançois Tigeot state = crtc_state->base.state;
1106477eb7f9SFrançois Tigeot
1107a85cb24fSFrançois Tigeot for_each_new_connector_in_state(state, connector, connector_state, i) {
110819c468b4SFrançois Tigeot if (connector_state->crtc != crtc_state->base.crtc)
1109477eb7f9SFrançois Tigeot continue;
1110477eb7f9SFrançois Tigeot
111119c468b4SFrançois Tigeot ret = to_intel_encoder(connector_state->best_encoder);
11122c9916cdSFrançois Tigeot num_encoders++;
11132c9916cdSFrançois Tigeot }
11142c9916cdSFrançois Tigeot
11152c9916cdSFrançois Tigeot WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
11162c9916cdSFrançois Tigeot pipe_name(crtc->pipe));
11172c9916cdSFrançois Tigeot
11182c9916cdSFrançois Tigeot BUG_ON(ret == NULL);
11192c9916cdSFrançois Tigeot return ret;
11202c9916cdSFrançois Tigeot }
11212c9916cdSFrançois Tigeot
11225d0b1887SFrançois Tigeot #define LC_FREQ 2700
11235d0b1887SFrançois Tigeot
hsw_ddi_calc_wrpll_link(struct drm_i915_private * dev_priv,i915_reg_t reg)1124aee94f86SFrançois Tigeot static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1125aee94f86SFrançois Tigeot i915_reg_t reg)
1126ba55f2f5SFrançois Tigeot {
1127ba55f2f5SFrançois Tigeot int refclk = LC_FREQ;
1128ba55f2f5SFrançois Tigeot int n, p, r;
1129ba55f2f5SFrançois Tigeot u32 wrpll;
1130ba55f2f5SFrançois Tigeot
1131ba55f2f5SFrançois Tigeot wrpll = I915_READ(reg);
113224edb884SFrançois Tigeot switch (wrpll & WRPLL_PLL_REF_MASK) {
113324edb884SFrançois Tigeot case WRPLL_PLL_SSC:
113424edb884SFrançois Tigeot case WRPLL_PLL_NON_SSC:
1135ba55f2f5SFrançois Tigeot /*
1136ba55f2f5SFrançois Tigeot * We could calculate spread here, but our checking
1137ba55f2f5SFrançois Tigeot * code only cares about 5% accuracy, and spread is a max of
1138ba55f2f5SFrançois Tigeot * 0.5% downspread.
1139ba55f2f5SFrançois Tigeot */
1140ba55f2f5SFrançois Tigeot refclk = 135;
1141ba55f2f5SFrançois Tigeot break;
114224edb884SFrançois Tigeot case WRPLL_PLL_LCPLL:
1143ba55f2f5SFrançois Tigeot refclk = LC_FREQ;
1144ba55f2f5SFrançois Tigeot break;
1145ba55f2f5SFrançois Tigeot default:
1146ba55f2f5SFrançois Tigeot WARN(1, "bad wrpll refclk\n");
1147ba55f2f5SFrançois Tigeot return 0;
1148ba55f2f5SFrançois Tigeot }
1149ba55f2f5SFrançois Tigeot
1150ba55f2f5SFrançois Tigeot r = wrpll & WRPLL_DIVIDER_REF_MASK;
1151ba55f2f5SFrançois Tigeot p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1152ba55f2f5SFrançois Tigeot n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1153ba55f2f5SFrançois Tigeot
1154ba55f2f5SFrançois Tigeot /* Convert to KHz, p & r have a fixed point portion */
1155ba55f2f5SFrançois Tigeot return (refclk * n * 100) / (p * r);
1156ba55f2f5SFrançois Tigeot }
1157ba55f2f5SFrançois Tigeot
skl_calc_wrpll_link(struct drm_i915_private * dev_priv,enum intel_dpll_id pll_id)11582c9916cdSFrançois Tigeot static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1159*3f2dd94aSFrançois Tigeot enum intel_dpll_id pll_id)
11602c9916cdSFrançois Tigeot {
1161aee94f86SFrançois Tigeot i915_reg_t cfgcr1_reg, cfgcr2_reg;
11622c9916cdSFrançois Tigeot uint32_t cfgcr1_val, cfgcr2_val;
11632c9916cdSFrançois Tigeot uint32_t p0, p1, p2, dco_freq;
11642c9916cdSFrançois Tigeot
1165*3f2dd94aSFrançois Tigeot cfgcr1_reg = DPLL_CFGCR1(pll_id);
1166*3f2dd94aSFrançois Tigeot cfgcr2_reg = DPLL_CFGCR2(pll_id);
11672c9916cdSFrançois Tigeot
11682c9916cdSFrançois Tigeot cfgcr1_val = I915_READ(cfgcr1_reg);
11692c9916cdSFrançois Tigeot cfgcr2_val = I915_READ(cfgcr2_reg);
11702c9916cdSFrançois Tigeot
11712c9916cdSFrançois Tigeot p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
11722c9916cdSFrançois Tigeot p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
11732c9916cdSFrançois Tigeot
11742c9916cdSFrançois Tigeot if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
11752c9916cdSFrançois Tigeot p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
11762c9916cdSFrançois Tigeot else
11772c9916cdSFrançois Tigeot p1 = 1;
11782c9916cdSFrançois Tigeot
11792c9916cdSFrançois Tigeot
11802c9916cdSFrançois Tigeot switch (p0) {
11812c9916cdSFrançois Tigeot case DPLL_CFGCR2_PDIV_1:
11822c9916cdSFrançois Tigeot p0 = 1;
11832c9916cdSFrançois Tigeot break;
11842c9916cdSFrançois Tigeot case DPLL_CFGCR2_PDIV_2:
11852c9916cdSFrançois Tigeot p0 = 2;
11862c9916cdSFrançois Tigeot break;
11872c9916cdSFrançois Tigeot case DPLL_CFGCR2_PDIV_3:
11882c9916cdSFrançois Tigeot p0 = 3;
11892c9916cdSFrançois Tigeot break;
11902c9916cdSFrançois Tigeot case DPLL_CFGCR2_PDIV_7:
11912c9916cdSFrançois Tigeot p0 = 7;
11922c9916cdSFrançois Tigeot break;
11932c9916cdSFrançois Tigeot }
11942c9916cdSFrançois Tigeot
11952c9916cdSFrançois Tigeot switch (p2) {
11962c9916cdSFrançois Tigeot case DPLL_CFGCR2_KDIV_5:
11972c9916cdSFrançois Tigeot p2 = 5;
11982c9916cdSFrançois Tigeot break;
11992c9916cdSFrançois Tigeot case DPLL_CFGCR2_KDIV_2:
12002c9916cdSFrançois Tigeot p2 = 2;
12012c9916cdSFrançois Tigeot break;
12022c9916cdSFrançois Tigeot case DPLL_CFGCR2_KDIV_3:
12032c9916cdSFrançois Tigeot p2 = 3;
12042c9916cdSFrançois Tigeot break;
12052c9916cdSFrançois Tigeot case DPLL_CFGCR2_KDIV_1:
12062c9916cdSFrançois Tigeot p2 = 1;
12072c9916cdSFrançois Tigeot break;
12082c9916cdSFrançois Tigeot }
12092c9916cdSFrançois Tigeot
12102c9916cdSFrançois Tigeot dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
12112c9916cdSFrançois Tigeot
12122c9916cdSFrançois Tigeot dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
12132c9916cdSFrançois Tigeot 1000) / 0x8000;
12142c9916cdSFrançois Tigeot
12152c9916cdSFrançois Tigeot return dco_freq / (p0 * p1 * p2 * 5);
12162c9916cdSFrançois Tigeot }
12172c9916cdSFrançois Tigeot
cnl_calc_wrpll_link(struct drm_i915_private * dev_priv,enum intel_dpll_id pll_id)1218*3f2dd94aSFrançois Tigeot static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1219*3f2dd94aSFrançois Tigeot enum intel_dpll_id pll_id)
1220*3f2dd94aSFrançois Tigeot {
1221*3f2dd94aSFrançois Tigeot uint32_t cfgcr0, cfgcr1;
1222*3f2dd94aSFrançois Tigeot uint32_t p0, p1, p2, dco_freq, ref_clock;
1223*3f2dd94aSFrançois Tigeot
1224*3f2dd94aSFrançois Tigeot cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1225*3f2dd94aSFrançois Tigeot cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1226*3f2dd94aSFrançois Tigeot
1227*3f2dd94aSFrançois Tigeot p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1228*3f2dd94aSFrançois Tigeot p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1229*3f2dd94aSFrançois Tigeot
1230*3f2dd94aSFrançois Tigeot if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1231*3f2dd94aSFrançois Tigeot p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1232*3f2dd94aSFrançois Tigeot DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1233*3f2dd94aSFrançois Tigeot else
1234*3f2dd94aSFrançois Tigeot p1 = 1;
1235*3f2dd94aSFrançois Tigeot
1236*3f2dd94aSFrançois Tigeot
1237*3f2dd94aSFrançois Tigeot switch (p0) {
1238*3f2dd94aSFrançois Tigeot case DPLL_CFGCR1_PDIV_2:
1239*3f2dd94aSFrançois Tigeot p0 = 2;
1240*3f2dd94aSFrançois Tigeot break;
1241*3f2dd94aSFrançois Tigeot case DPLL_CFGCR1_PDIV_3:
1242*3f2dd94aSFrançois Tigeot p0 = 3;
1243*3f2dd94aSFrançois Tigeot break;
1244*3f2dd94aSFrançois Tigeot case DPLL_CFGCR1_PDIV_5:
1245*3f2dd94aSFrançois Tigeot p0 = 5;
1246*3f2dd94aSFrançois Tigeot break;
1247*3f2dd94aSFrançois Tigeot case DPLL_CFGCR1_PDIV_7:
1248*3f2dd94aSFrançois Tigeot p0 = 7;
1249*3f2dd94aSFrançois Tigeot break;
1250*3f2dd94aSFrançois Tigeot }
1251*3f2dd94aSFrançois Tigeot
1252*3f2dd94aSFrançois Tigeot switch (p2) {
1253*3f2dd94aSFrançois Tigeot case DPLL_CFGCR1_KDIV_1:
1254*3f2dd94aSFrançois Tigeot p2 = 1;
1255*3f2dd94aSFrançois Tigeot break;
1256*3f2dd94aSFrançois Tigeot case DPLL_CFGCR1_KDIV_2:
1257*3f2dd94aSFrançois Tigeot p2 = 2;
1258*3f2dd94aSFrançois Tigeot break;
1259*3f2dd94aSFrançois Tigeot case DPLL_CFGCR1_KDIV_4:
1260*3f2dd94aSFrançois Tigeot p2 = 4;
1261*3f2dd94aSFrançois Tigeot break;
1262*3f2dd94aSFrançois Tigeot }
1263*3f2dd94aSFrançois Tigeot
1264*3f2dd94aSFrançois Tigeot ref_clock = dev_priv->cdclk.hw.ref;
1265*3f2dd94aSFrançois Tigeot
1266*3f2dd94aSFrançois Tigeot dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1267*3f2dd94aSFrançois Tigeot
1268*3f2dd94aSFrançois Tigeot dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1269*3f2dd94aSFrançois Tigeot DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1270*3f2dd94aSFrançois Tigeot
1271*3f2dd94aSFrançois Tigeot if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1272*3f2dd94aSFrançois Tigeot return 0;
1273*3f2dd94aSFrançois Tigeot
1274*3f2dd94aSFrançois Tigeot return dco_freq / (p0 * p1 * p2 * 5);
1275*3f2dd94aSFrançois Tigeot }
1276*3f2dd94aSFrançois Tigeot
ddi_dotclock_get(struct intel_crtc_state * pipe_config)1277a05eeebfSFrançois Tigeot static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1278a05eeebfSFrançois Tigeot {
1279a05eeebfSFrançois Tigeot int dotclock;
1280a05eeebfSFrançois Tigeot
1281a05eeebfSFrançois Tigeot if (pipe_config->has_pch_encoder)
1282a05eeebfSFrançois Tigeot dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1283a05eeebfSFrançois Tigeot &pipe_config->fdi_m_n);
1284303bf270SFrançois Tigeot else if (intel_crtc_has_dp_encoder(pipe_config))
1285a05eeebfSFrançois Tigeot dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1286a05eeebfSFrançois Tigeot &pipe_config->dp_m_n);
1287a05eeebfSFrançois Tigeot else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1288a05eeebfSFrançois Tigeot dotclock = pipe_config->port_clock * 2 / 3;
1289a05eeebfSFrançois Tigeot else
1290a05eeebfSFrançois Tigeot dotclock = pipe_config->port_clock;
1291a05eeebfSFrançois Tigeot
1292*3f2dd94aSFrançois Tigeot if (pipe_config->ycbcr420)
1293*3f2dd94aSFrançois Tigeot dotclock *= 2;
1294*3f2dd94aSFrançois Tigeot
1295a05eeebfSFrançois Tigeot if (pipe_config->pixel_multiplier)
1296a05eeebfSFrançois Tigeot dotclock /= pipe_config->pixel_multiplier;
1297a05eeebfSFrançois Tigeot
1298a05eeebfSFrançois Tigeot pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1299a05eeebfSFrançois Tigeot }
13002c9916cdSFrançois Tigeot
cnl_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1301*3f2dd94aSFrançois Tigeot static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1302*3f2dd94aSFrançois Tigeot struct intel_crtc_state *pipe_config)
1303*3f2dd94aSFrançois Tigeot {
1304*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1305*3f2dd94aSFrançois Tigeot int link_clock = 0;
1306*3f2dd94aSFrançois Tigeot uint32_t cfgcr0;
1307*3f2dd94aSFrançois Tigeot enum intel_dpll_id pll_id;
1308*3f2dd94aSFrançois Tigeot
1309*3f2dd94aSFrançois Tigeot pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1310*3f2dd94aSFrançois Tigeot
1311*3f2dd94aSFrançois Tigeot cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1312*3f2dd94aSFrançois Tigeot
1313*3f2dd94aSFrançois Tigeot if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1314*3f2dd94aSFrançois Tigeot link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1315*3f2dd94aSFrançois Tigeot } else {
1316*3f2dd94aSFrançois Tigeot link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1317*3f2dd94aSFrançois Tigeot
1318*3f2dd94aSFrançois Tigeot switch (link_clock) {
1319*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_810:
1320*3f2dd94aSFrançois Tigeot link_clock = 81000;
1321*3f2dd94aSFrançois Tigeot break;
1322*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_1080:
1323*3f2dd94aSFrançois Tigeot link_clock = 108000;
1324*3f2dd94aSFrançois Tigeot break;
1325*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_1350:
1326*3f2dd94aSFrançois Tigeot link_clock = 135000;
1327*3f2dd94aSFrançois Tigeot break;
1328*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_1620:
1329*3f2dd94aSFrançois Tigeot link_clock = 162000;
1330*3f2dd94aSFrançois Tigeot break;
1331*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_2160:
1332*3f2dd94aSFrançois Tigeot link_clock = 216000;
1333*3f2dd94aSFrançois Tigeot break;
1334*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_2700:
1335*3f2dd94aSFrançois Tigeot link_clock = 270000;
1336*3f2dd94aSFrançois Tigeot break;
1337*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_3240:
1338*3f2dd94aSFrançois Tigeot link_clock = 324000;
1339*3f2dd94aSFrançois Tigeot break;
1340*3f2dd94aSFrançois Tigeot case DPLL_CFGCR0_LINK_RATE_4050:
1341*3f2dd94aSFrançois Tigeot link_clock = 405000;
1342*3f2dd94aSFrançois Tigeot break;
1343*3f2dd94aSFrançois Tigeot default:
1344*3f2dd94aSFrançois Tigeot WARN(1, "Unsupported link rate\n");
1345*3f2dd94aSFrançois Tigeot break;
1346*3f2dd94aSFrançois Tigeot }
1347*3f2dd94aSFrançois Tigeot link_clock *= 2;
1348*3f2dd94aSFrançois Tigeot }
1349*3f2dd94aSFrançois Tigeot
1350*3f2dd94aSFrançois Tigeot pipe_config->port_clock = link_clock;
1351*3f2dd94aSFrançois Tigeot
1352*3f2dd94aSFrançois Tigeot ddi_dotclock_get(pipe_config);
1353*3f2dd94aSFrançois Tigeot }
1354*3f2dd94aSFrançois Tigeot
skl_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)13552c9916cdSFrançois Tigeot static void skl_ddi_clock_get(struct intel_encoder *encoder,
13562c9916cdSFrançois Tigeot struct intel_crtc_state *pipe_config)
13572c9916cdSFrançois Tigeot {
1358303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
13592c9916cdSFrançois Tigeot int link_clock = 0;
1360*3f2dd94aSFrançois Tigeot uint32_t dpll_ctl1;
1361*3f2dd94aSFrançois Tigeot enum intel_dpll_id pll_id;
13622c9916cdSFrançois Tigeot
1363*3f2dd94aSFrançois Tigeot pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
13642c9916cdSFrançois Tigeot
13652c9916cdSFrançois Tigeot dpll_ctl1 = I915_READ(DPLL_CTRL1);
13662c9916cdSFrançois Tigeot
1367*3f2dd94aSFrançois Tigeot if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1368*3f2dd94aSFrançois Tigeot link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
13692c9916cdSFrançois Tigeot } else {
1370*3f2dd94aSFrançois Tigeot link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1371*3f2dd94aSFrançois Tigeot link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
13722c9916cdSFrançois Tigeot
13732c9916cdSFrançois Tigeot switch (link_clock) {
137419c468b4SFrançois Tigeot case DPLL_CTRL1_LINK_RATE_810:
13752c9916cdSFrançois Tigeot link_clock = 81000;
13762c9916cdSFrançois Tigeot break;
137719c468b4SFrançois Tigeot case DPLL_CTRL1_LINK_RATE_1080:
1378477eb7f9SFrançois Tigeot link_clock = 108000;
1379477eb7f9SFrançois Tigeot break;
138019c468b4SFrançois Tigeot case DPLL_CTRL1_LINK_RATE_1350:
13812c9916cdSFrançois Tigeot link_clock = 135000;
13822c9916cdSFrançois Tigeot break;
138319c468b4SFrançois Tigeot case DPLL_CTRL1_LINK_RATE_1620:
1384477eb7f9SFrançois Tigeot link_clock = 162000;
1385477eb7f9SFrançois Tigeot break;
138619c468b4SFrançois Tigeot case DPLL_CTRL1_LINK_RATE_2160:
1387477eb7f9SFrançois Tigeot link_clock = 216000;
1388477eb7f9SFrançois Tigeot break;
138919c468b4SFrançois Tigeot case DPLL_CTRL1_LINK_RATE_2700:
13902c9916cdSFrançois Tigeot link_clock = 270000;
13912c9916cdSFrançois Tigeot break;
13922c9916cdSFrançois Tigeot default:
13932c9916cdSFrançois Tigeot WARN(1, "Unsupported link rate\n");
13942c9916cdSFrançois Tigeot break;
13952c9916cdSFrançois Tigeot }
13962c9916cdSFrançois Tigeot link_clock *= 2;
13972c9916cdSFrançois Tigeot }
13982c9916cdSFrançois Tigeot
13992c9916cdSFrançois Tigeot pipe_config->port_clock = link_clock;
14002c9916cdSFrançois Tigeot
1401a05eeebfSFrançois Tigeot ddi_dotclock_get(pipe_config);
14022c9916cdSFrançois Tigeot }
14032c9916cdSFrançois Tigeot
hsw_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)14041b13d190SFrançois Tigeot static void hsw_ddi_clock_get(struct intel_encoder *encoder,
14052c9916cdSFrançois Tigeot struct intel_crtc_state *pipe_config)
1406ba55f2f5SFrançois Tigeot {
1407303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1408ba55f2f5SFrançois Tigeot int link_clock = 0;
1409ba55f2f5SFrançois Tigeot u32 val, pll;
1410ba55f2f5SFrançois Tigeot
14111e12ee3bSFrançois Tigeot val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1412ba55f2f5SFrançois Tigeot switch (val & PORT_CLK_SEL_MASK) {
1413ba55f2f5SFrançois Tigeot case PORT_CLK_SEL_LCPLL_810:
1414ba55f2f5SFrançois Tigeot link_clock = 81000;
1415ba55f2f5SFrançois Tigeot break;
1416ba55f2f5SFrançois Tigeot case PORT_CLK_SEL_LCPLL_1350:
1417ba55f2f5SFrançois Tigeot link_clock = 135000;
1418ba55f2f5SFrançois Tigeot break;
1419ba55f2f5SFrançois Tigeot case PORT_CLK_SEL_LCPLL_2700:
1420ba55f2f5SFrançois Tigeot link_clock = 270000;
1421ba55f2f5SFrançois Tigeot break;
1422ba55f2f5SFrançois Tigeot case PORT_CLK_SEL_WRPLL1:
1423aee94f86SFrançois Tigeot link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1424ba55f2f5SFrançois Tigeot break;
1425ba55f2f5SFrançois Tigeot case PORT_CLK_SEL_WRPLL2:
1426aee94f86SFrançois Tigeot link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1427ba55f2f5SFrançois Tigeot break;
1428ba55f2f5SFrançois Tigeot case PORT_CLK_SEL_SPLL:
1429ba55f2f5SFrançois Tigeot pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1430ba55f2f5SFrançois Tigeot if (pll == SPLL_PLL_FREQ_810MHz)
1431ba55f2f5SFrançois Tigeot link_clock = 81000;
1432ba55f2f5SFrançois Tigeot else if (pll == SPLL_PLL_FREQ_1350MHz)
1433ba55f2f5SFrançois Tigeot link_clock = 135000;
1434ba55f2f5SFrançois Tigeot else if (pll == SPLL_PLL_FREQ_2700MHz)
1435ba55f2f5SFrançois Tigeot link_clock = 270000;
1436ba55f2f5SFrançois Tigeot else {
1437ba55f2f5SFrançois Tigeot WARN(1, "bad spll freq\n");
1438ba55f2f5SFrançois Tigeot return;
1439ba55f2f5SFrançois Tigeot }
1440ba55f2f5SFrançois Tigeot break;
1441ba55f2f5SFrançois Tigeot default:
1442ba55f2f5SFrançois Tigeot WARN(1, "bad port clock sel\n");
1443ba55f2f5SFrançois Tigeot return;
1444ba55f2f5SFrançois Tigeot }
1445ba55f2f5SFrançois Tigeot
1446ba55f2f5SFrançois Tigeot pipe_config->port_clock = link_clock * 2;
1447ba55f2f5SFrançois Tigeot
1448a05eeebfSFrançois Tigeot ddi_dotclock_get(pipe_config);
1449ba55f2f5SFrançois Tigeot }
1450ba55f2f5SFrançois Tigeot
bxt_calc_pll_link(struct drm_i915_private * dev_priv,enum intel_dpll_id pll_id)145119c468b4SFrançois Tigeot static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1452*3f2dd94aSFrançois Tigeot enum intel_dpll_id pll_id)
145319c468b4SFrançois Tigeot {
1454a05eeebfSFrançois Tigeot struct intel_shared_dpll *pll;
1455a05eeebfSFrançois Tigeot struct intel_dpll_hw_state *state;
14561487f786SFrançois Tigeot struct dpll clock;
1457a05eeebfSFrançois Tigeot
1458a05eeebfSFrançois Tigeot /* For DDI ports we always use a shared PLL. */
1459*3f2dd94aSFrançois Tigeot if (WARN_ON(pll_id == DPLL_ID_PRIVATE))
146019c468b4SFrançois Tigeot return 0;
1461a05eeebfSFrançois Tigeot
1462*3f2dd94aSFrançois Tigeot pll = &dev_priv->shared_dplls[pll_id];
1463a85cb24fSFrançois Tigeot state = &pll->state.hw_state;
1464a05eeebfSFrançois Tigeot
1465a05eeebfSFrançois Tigeot clock.m1 = 2;
1466a05eeebfSFrançois Tigeot clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1467a05eeebfSFrançois Tigeot if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1468a05eeebfSFrançois Tigeot clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1469a05eeebfSFrançois Tigeot clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1470a05eeebfSFrançois Tigeot clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1471a05eeebfSFrançois Tigeot clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1472a05eeebfSFrançois Tigeot
1473a05eeebfSFrançois Tigeot return chv_calc_dpll_params(100000, &clock);
147419c468b4SFrançois Tigeot }
147519c468b4SFrançois Tigeot
bxt_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)147619c468b4SFrançois Tigeot static void bxt_ddi_clock_get(struct intel_encoder *encoder,
147719c468b4SFrançois Tigeot struct intel_crtc_state *pipe_config)
147819c468b4SFrançois Tigeot {
1479303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
148019c468b4SFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
1481*3f2dd94aSFrançois Tigeot enum intel_dpll_id pll_id = port;
148219c468b4SFrançois Tigeot
1483*3f2dd94aSFrançois Tigeot pipe_config->port_clock = bxt_calc_pll_link(dev_priv, pll_id);
148419c468b4SFrançois Tigeot
1485a05eeebfSFrançois Tigeot ddi_dotclock_get(pipe_config);
148619c468b4SFrançois Tigeot }
148719c468b4SFrançois Tigeot
intel_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)14881b13d190SFrançois Tigeot void intel_ddi_clock_get(struct intel_encoder *encoder,
14892c9916cdSFrançois Tigeot struct intel_crtc_state *pipe_config)
14901b13d190SFrançois Tigeot {
14911e12ee3bSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
14922c9916cdSFrançois Tigeot
14931e12ee3bSFrançois Tigeot if (INTEL_GEN(dev_priv) <= 8)
14941b13d190SFrançois Tigeot hsw_ddi_clock_get(encoder, pipe_config);
1495a85cb24fSFrançois Tigeot else if (IS_GEN9_BC(dev_priv))
14962c9916cdSFrançois Tigeot skl_ddi_clock_get(encoder, pipe_config);
1497a85cb24fSFrançois Tigeot else if (IS_GEN9_LP(dev_priv))
149819c468b4SFrançois Tigeot bxt_ddi_clock_get(encoder, pipe_config);
1499*3f2dd94aSFrançois Tigeot else if (IS_CANNONLAKE(dev_priv))
1500*3f2dd94aSFrançois Tigeot cnl_ddi_clock_get(encoder, pipe_config);
15011b13d190SFrançois Tigeot }
15021b13d190SFrançois Tigeot
intel_ddi_set_pipe_settings(const struct intel_crtc_state * crtc_state)1503a85cb24fSFrançois Tigeot void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
150419df918dSFrançois Tigeot {
1505a85cb24fSFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1506a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1507a85cb24fSFrançois Tigeot struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1508a85cb24fSFrançois Tigeot enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1509a85cb24fSFrançois Tigeot int type = encoder->type;
151019df918dSFrançois Tigeot uint32_t temp;
151119df918dSFrançois Tigeot
1512303bf270SFrançois Tigeot if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
15138621f407SFrançois Tigeot WARN_ON(transcoder_is_dsi(cpu_transcoder));
15148621f407SFrançois Tigeot
151519df918dSFrançois Tigeot temp = TRANS_MSA_SYNC_CLK;
1516a85cb24fSFrançois Tigeot switch (crtc_state->pipe_bpp) {
151719df918dSFrançois Tigeot case 18:
151819df918dSFrançois Tigeot temp |= TRANS_MSA_6_BPC;
151919df918dSFrançois Tigeot break;
152019df918dSFrançois Tigeot case 24:
152119df918dSFrançois Tigeot temp |= TRANS_MSA_8_BPC;
152219df918dSFrançois Tigeot break;
152319df918dSFrançois Tigeot case 30:
152419df918dSFrançois Tigeot temp |= TRANS_MSA_10_BPC;
152519df918dSFrançois Tigeot break;
152619df918dSFrançois Tigeot case 36:
152719df918dSFrançois Tigeot temp |= TRANS_MSA_12_BPC;
152819df918dSFrançois Tigeot break;
152919df918dSFrançois Tigeot default:
15308e26cdf6SFrançois Tigeot BUG();
153119df918dSFrançois Tigeot }
153219df918dSFrançois Tigeot I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
153319df918dSFrançois Tigeot }
153419df918dSFrançois Tigeot }
153519df918dSFrançois Tigeot
intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state * crtc_state,bool state)1536a85cb24fSFrançois Tigeot void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1537a85cb24fSFrançois Tigeot bool state)
15381b13d190SFrançois Tigeot {
1539a85cb24fSFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1540a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1541a85cb24fSFrançois Tigeot enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
15421b13d190SFrançois Tigeot uint32_t temp;
15431b13d190SFrançois Tigeot temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
15441b13d190SFrançois Tigeot if (state == true)
15451b13d190SFrançois Tigeot temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
15461b13d190SFrançois Tigeot else
15471b13d190SFrançois Tigeot temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
15481b13d190SFrançois Tigeot I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
15491b13d190SFrançois Tigeot }
15501b13d190SFrançois Tigeot
intel_ddi_enable_transcoder_func(const struct intel_crtc_state * crtc_state)1551a85cb24fSFrançois Tigeot void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
155219df918dSFrançois Tigeot {
1553a85cb24fSFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1554a85cb24fSFrançois Tigeot struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1555a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1556a85cb24fSFrançois Tigeot enum i915_pipe pipe = crtc->pipe;
1557a85cb24fSFrançois Tigeot enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1558a85cb24fSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
1559a85cb24fSFrançois Tigeot int type = encoder->type;
156019df918dSFrançois Tigeot uint32_t temp;
156119df918dSFrançois Tigeot
156219df918dSFrançois Tigeot /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
156319df918dSFrançois Tigeot temp = TRANS_DDI_FUNC_ENABLE;
156419df918dSFrançois Tigeot temp |= TRANS_DDI_SELECT_PORT(port);
156519df918dSFrançois Tigeot
1566a85cb24fSFrançois Tigeot switch (crtc_state->pipe_bpp) {
156719df918dSFrançois Tigeot case 18:
156819df918dSFrançois Tigeot temp |= TRANS_DDI_BPC_6;
156919df918dSFrançois Tigeot break;
157019df918dSFrançois Tigeot case 24:
157119df918dSFrançois Tigeot temp |= TRANS_DDI_BPC_8;
157219df918dSFrançois Tigeot break;
157319df918dSFrançois Tigeot case 30:
157419df918dSFrançois Tigeot temp |= TRANS_DDI_BPC_10;
157519df918dSFrançois Tigeot break;
157619df918dSFrançois Tigeot case 36:
157719df918dSFrançois Tigeot temp |= TRANS_DDI_BPC_12;
157819df918dSFrançois Tigeot break;
157919df918dSFrançois Tigeot default:
15808e26cdf6SFrançois Tigeot BUG();
158119df918dSFrançois Tigeot }
158219df918dSFrançois Tigeot
1583a85cb24fSFrançois Tigeot if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
158419df918dSFrançois Tigeot temp |= TRANS_DDI_PVSYNC;
1585a85cb24fSFrançois Tigeot if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
158619df918dSFrançois Tigeot temp |= TRANS_DDI_PHSYNC;
158719df918dSFrançois Tigeot
158819df918dSFrançois Tigeot if (cpu_transcoder == TRANSCODER_EDP) {
158919df918dSFrançois Tigeot switch (pipe) {
159019df918dSFrançois Tigeot case PIPE_A:
15919edbd4a0SFrançois Tigeot /* On Haswell, can only use the always-on power well for
15929edbd4a0SFrançois Tigeot * eDP when not using the panel fitter, and when not
15939edbd4a0SFrançois Tigeot * using motion blur mitigation (which we don't
15949edbd4a0SFrançois Tigeot * support). */
15951e12ee3bSFrançois Tigeot if (IS_HASWELL(dev_priv) &&
1596a85cb24fSFrançois Tigeot (crtc_state->pch_pfit.enabled ||
1597a85cb24fSFrançois Tigeot crtc_state->pch_pfit.force_thru))
159819df918dSFrançois Tigeot temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1599a2fdbec6SFrançois Tigeot else
1600a2fdbec6SFrançois Tigeot temp |= TRANS_DDI_EDP_INPUT_A_ON;
160119df918dSFrançois Tigeot break;
160219df918dSFrançois Tigeot case PIPE_B:
160319df918dSFrançois Tigeot temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
160419df918dSFrançois Tigeot break;
160519df918dSFrançois Tigeot case PIPE_C:
160619df918dSFrançois Tigeot temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
160719df918dSFrançois Tigeot break;
160819df918dSFrançois Tigeot default:
160919df918dSFrançois Tigeot BUG();
161019df918dSFrançois Tigeot break;
161119df918dSFrançois Tigeot }
161219df918dSFrançois Tigeot }
161319df918dSFrançois Tigeot
161419df918dSFrançois Tigeot if (type == INTEL_OUTPUT_HDMI) {
1615a85cb24fSFrançois Tigeot if (crtc_state->has_hdmi_sink)
161619df918dSFrançois Tigeot temp |= TRANS_DDI_MODE_SELECT_HDMI;
161719df918dSFrançois Tigeot else
161819df918dSFrançois Tigeot temp |= TRANS_DDI_MODE_SELECT_DVI;
1619a85cb24fSFrançois Tigeot
1620a85cb24fSFrançois Tigeot if (crtc_state->hdmi_scrambling)
1621a85cb24fSFrançois Tigeot temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1622a85cb24fSFrançois Tigeot if (crtc_state->hdmi_high_tmds_clock_ratio)
1623a85cb24fSFrançois Tigeot temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
162419df918dSFrançois Tigeot } else if (type == INTEL_OUTPUT_ANALOG) {
162519df918dSFrançois Tigeot temp |= TRANS_DDI_MODE_SELECT_FDI;
1626a85cb24fSFrançois Tigeot temp |= (crtc_state->fdi_lanes - 1) << 1;
1627303bf270SFrançois Tigeot } else if (type == INTEL_OUTPUT_DP ||
162819df918dSFrançois Tigeot type == INTEL_OUTPUT_EDP) {
16292c9916cdSFrançois Tigeot temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1630a85cb24fSFrançois Tigeot temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
16312c9916cdSFrançois Tigeot } else if (type == INTEL_OUTPUT_DP_MST) {
16322c9916cdSFrançois Tigeot temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1633a85cb24fSFrançois Tigeot temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
163419df918dSFrançois Tigeot } else {
16355d0b1887SFrançois Tigeot WARN(1, "Invalid encoder type %d for pipe %c\n",
1636a85cb24fSFrançois Tigeot encoder->type, pipe_name(pipe));
163719df918dSFrançois Tigeot }
163819df918dSFrançois Tigeot
163919df918dSFrançois Tigeot I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
164019df918dSFrançois Tigeot }
164119df918dSFrançois Tigeot
intel_ddi_disable_transcoder_func(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)164219df918dSFrançois Tigeot void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
164319df918dSFrançois Tigeot enum transcoder cpu_transcoder)
164419df918dSFrançois Tigeot {
1645aee94f86SFrançois Tigeot i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
164619df918dSFrançois Tigeot uint32_t val = I915_READ(reg);
164719df918dSFrançois Tigeot
16482c9916cdSFrançois Tigeot val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
164919df918dSFrançois Tigeot val |= TRANS_DDI_PORT_NONE;
165019df918dSFrançois Tigeot I915_WRITE(reg, val);
165119df918dSFrançois Tigeot }
165219df918dSFrançois Tigeot
intel_ddi_connector_get_hw_state(struct intel_connector * intel_connector)165319df918dSFrançois Tigeot bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
165419df918dSFrançois Tigeot {
165519df918dSFrançois Tigeot struct drm_device *dev = intel_connector->base.dev;
1656303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
1657a85cb24fSFrançois Tigeot struct intel_encoder *encoder = intel_connector->encoder;
165819df918dSFrançois Tigeot int type = intel_connector->base.connector_type;
1659a85cb24fSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
166019df918dSFrançois Tigeot enum i915_pipe pipe = 0;
166119df918dSFrançois Tigeot enum transcoder cpu_transcoder;
166219df918dSFrançois Tigeot uint32_t tmp;
1663aee94f86SFrançois Tigeot bool ret;
166419df918dSFrançois Tigeot
1665a85cb24fSFrançois Tigeot if (!intel_display_power_get_if_enabled(dev_priv,
1666a85cb24fSFrançois Tigeot encoder->power_domain))
1667ba55f2f5SFrançois Tigeot return false;
1668ba55f2f5SFrançois Tigeot
1669a85cb24fSFrançois Tigeot if (!encoder->get_hw_state(encoder, &pipe)) {
1670aee94f86SFrançois Tigeot ret = false;
1671aee94f86SFrançois Tigeot goto out;
1672aee94f86SFrançois Tigeot }
167319df918dSFrançois Tigeot
167419df918dSFrançois Tigeot if (port == PORT_A)
167519df918dSFrançois Tigeot cpu_transcoder = TRANSCODER_EDP;
167619df918dSFrançois Tigeot else
1677a2fdbec6SFrançois Tigeot cpu_transcoder = (enum transcoder) pipe;
167819df918dSFrançois Tigeot
167919df918dSFrançois Tigeot tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
168019df918dSFrançois Tigeot
168119df918dSFrançois Tigeot switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
168219df918dSFrançois Tigeot case TRANS_DDI_MODE_SELECT_HDMI:
168319df918dSFrançois Tigeot case TRANS_DDI_MODE_SELECT_DVI:
1684aee94f86SFrançois Tigeot ret = type == DRM_MODE_CONNECTOR_HDMIA;
1685aee94f86SFrançois Tigeot break;
168619df918dSFrançois Tigeot
168719df918dSFrançois Tigeot case TRANS_DDI_MODE_SELECT_DP_SST:
1688aee94f86SFrançois Tigeot ret = type == DRM_MODE_CONNECTOR_eDP ||
1689aee94f86SFrançois Tigeot type == DRM_MODE_CONNECTOR_DisplayPort;
1690aee94f86SFrançois Tigeot break;
1691aee94f86SFrançois Tigeot
16922c9916cdSFrançois Tigeot case TRANS_DDI_MODE_SELECT_DP_MST:
16932c9916cdSFrançois Tigeot /* if the transcoder is in MST state then
16942c9916cdSFrançois Tigeot * connector isn't connected */
1695aee94f86SFrançois Tigeot ret = false;
1696aee94f86SFrançois Tigeot break;
169719df918dSFrançois Tigeot
169819df918dSFrançois Tigeot case TRANS_DDI_MODE_SELECT_FDI:
1699aee94f86SFrançois Tigeot ret = type == DRM_MODE_CONNECTOR_VGA;
1700aee94f86SFrançois Tigeot break;
170119df918dSFrançois Tigeot
170219df918dSFrançois Tigeot default:
1703aee94f86SFrançois Tigeot ret = false;
1704aee94f86SFrançois Tigeot break;
170519df918dSFrançois Tigeot }
1706aee94f86SFrançois Tigeot
1707aee94f86SFrançois Tigeot out:
1708a85cb24fSFrançois Tigeot intel_display_power_put(dev_priv, encoder->power_domain);
1709aee94f86SFrançois Tigeot
1710aee94f86SFrançois Tigeot return ret;
171119df918dSFrançois Tigeot }
171219df918dSFrançois Tigeot
intel_ddi_get_hw_state(struct intel_encoder * encoder,enum i915_pipe * pipe)171319df918dSFrançois Tigeot bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
171419df918dSFrançois Tigeot enum i915_pipe *pipe)
171519df918dSFrançois Tigeot {
171619df918dSFrançois Tigeot struct drm_device *dev = encoder->base.dev;
1717303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dev);
171819df918dSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
171919df918dSFrançois Tigeot u32 tmp;
172019df918dSFrançois Tigeot int i;
1721aee94f86SFrançois Tigeot bool ret;
172219df918dSFrançois Tigeot
1723a85cb24fSFrançois Tigeot if (!intel_display_power_get_if_enabled(dev_priv,
1724a85cb24fSFrançois Tigeot encoder->power_domain))
1725ba55f2f5SFrançois Tigeot return false;
1726ba55f2f5SFrançois Tigeot
1727aee94f86SFrançois Tigeot ret = false;
1728aee94f86SFrançois Tigeot
172919df918dSFrançois Tigeot tmp = I915_READ(DDI_BUF_CTL(port));
173019df918dSFrançois Tigeot
173119df918dSFrançois Tigeot if (!(tmp & DDI_BUF_CTL_ENABLE))
1732aee94f86SFrançois Tigeot goto out;
173319df918dSFrançois Tigeot
173419df918dSFrançois Tigeot if (port == PORT_A) {
173519df918dSFrançois Tigeot tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
173619df918dSFrançois Tigeot
173719df918dSFrançois Tigeot switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
173819df918dSFrançois Tigeot case TRANS_DDI_EDP_INPUT_A_ON:
173919df918dSFrançois Tigeot case TRANS_DDI_EDP_INPUT_A_ONOFF:
174019df918dSFrançois Tigeot *pipe = PIPE_A;
174119df918dSFrançois Tigeot break;
174219df918dSFrançois Tigeot case TRANS_DDI_EDP_INPUT_B_ONOFF:
174319df918dSFrançois Tigeot *pipe = PIPE_B;
174419df918dSFrançois Tigeot break;
174519df918dSFrançois Tigeot case TRANS_DDI_EDP_INPUT_C_ONOFF:
174619df918dSFrançois Tigeot *pipe = PIPE_C;
174719df918dSFrançois Tigeot break;
174819df918dSFrançois Tigeot }
174919df918dSFrançois Tigeot
1750aee94f86SFrançois Tigeot ret = true;
1751aee94f86SFrançois Tigeot
1752aee94f86SFrançois Tigeot goto out;
1753aee94f86SFrançois Tigeot }
1754aee94f86SFrançois Tigeot
175519df918dSFrançois Tigeot for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
175619df918dSFrançois Tigeot tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
175719df918dSFrançois Tigeot
1758aee94f86SFrançois Tigeot if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1759aee94f86SFrançois Tigeot if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1760aee94f86SFrançois Tigeot TRANS_DDI_MODE_SELECT_DP_MST)
1761aee94f86SFrançois Tigeot goto out;
17622c9916cdSFrançois Tigeot
176319df918dSFrançois Tigeot *pipe = i;
1764aee94f86SFrançois Tigeot ret = true;
1765aee94f86SFrançois Tigeot
1766aee94f86SFrançois Tigeot goto out;
176719df918dSFrançois Tigeot }
176819df918dSFrançois Tigeot }
176919df918dSFrançois Tigeot
17705d0b1887SFrançois Tigeot DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
177119df918dSFrançois Tigeot
1772aee94f86SFrançois Tigeot out:
1773a85cb24fSFrançois Tigeot if (ret && IS_GEN9_LP(dev_priv)) {
17741487f786SFrançois Tigeot tmp = I915_READ(BXT_PHY_CTL(port));
1775*3f2dd94aSFrançois Tigeot if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
1776*3f2dd94aSFrançois Tigeot BXT_PHY_LANE_POWERDOWN_ACK |
17771487f786SFrançois Tigeot BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
17781487f786SFrançois Tigeot DRM_ERROR("Port %c enabled but PHY powered down? "
17791487f786SFrançois Tigeot "(PHY_CTL %08x)\n", port_name(port), tmp);
17801487f786SFrançois Tigeot }
17811487f786SFrançois Tigeot
1782a85cb24fSFrançois Tigeot intel_display_power_put(dev_priv, encoder->power_domain);
1783aee94f86SFrançois Tigeot
1784aee94f86SFrançois Tigeot return ret;
178519df918dSFrançois Tigeot }
178619df918dSFrançois Tigeot
intel_ddi_get_power_domains(struct intel_encoder * encoder)1787a85cb24fSFrançois Tigeot static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
178819df918dSFrançois Tigeot {
1789a85cb24fSFrançois Tigeot struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1790a85cb24fSFrançois Tigeot enum i915_pipe pipe;
1791a85cb24fSFrançois Tigeot
1792a85cb24fSFrançois Tigeot if (intel_ddi_get_hw_state(encoder, &pipe))
1793a85cb24fSFrançois Tigeot return BIT_ULL(dig_port->ddi_io_power_domain);
1794a85cb24fSFrançois Tigeot
1795a85cb24fSFrançois Tigeot return 0;
1796a85cb24fSFrançois Tigeot }
1797a85cb24fSFrançois Tigeot
intel_ddi_enable_pipe_clock(const struct intel_crtc_state * crtc_state)1798a85cb24fSFrançois Tigeot void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1799a85cb24fSFrançois Tigeot {
1800a85cb24fSFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1801a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802a85cb24fSFrançois Tigeot struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1803a85cb24fSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
1804a85cb24fSFrançois Tigeot enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
180519df918dSFrançois Tigeot
180619df918dSFrançois Tigeot if (cpu_transcoder != TRANSCODER_EDP)
180719df918dSFrançois Tigeot I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
180819df918dSFrançois Tigeot TRANS_CLK_SEL_PORT(port));
180919df918dSFrançois Tigeot }
181019df918dSFrançois Tigeot
intel_ddi_disable_pipe_clock(const struct intel_crtc_state * crtc_state)1811a85cb24fSFrançois Tigeot void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
181219df918dSFrançois Tigeot {
1813a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1814a85cb24fSFrançois Tigeot enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
181519df918dSFrançois Tigeot
181619df918dSFrançois Tigeot if (cpu_transcoder != TRANSCODER_EDP)
181719df918dSFrançois Tigeot I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
181819df918dSFrançois Tigeot TRANS_CLK_SEL_DISABLED);
181919df918dSFrançois Tigeot }
182019df918dSFrançois Tigeot
_skl_ddi_set_iboost(struct drm_i915_private * dev_priv,enum port port,uint8_t iboost)18218621f407SFrançois Tigeot static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
18228621f407SFrançois Tigeot enum port port, uint8_t iboost)
1823a05eeebfSFrançois Tigeot {
18248621f407SFrançois Tigeot u32 tmp;
18258621f407SFrançois Tigeot
18268621f407SFrançois Tigeot tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
18278621f407SFrançois Tigeot tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
18288621f407SFrançois Tigeot if (iboost)
18298621f407SFrançois Tigeot tmp |= iboost << BALANCE_LEG_SHIFT(port);
18308621f407SFrançois Tigeot else
18318621f407SFrançois Tigeot tmp |= BALANCE_LEG_DISABLE(port);
18328621f407SFrançois Tigeot I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
18338621f407SFrançois Tigeot }
18348621f407SFrançois Tigeot
skl_ddi_set_iboost(struct intel_encoder * encoder,int level,enum intel_output_type type)1835*3f2dd94aSFrançois Tigeot static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1836*3f2dd94aSFrançois Tigeot int level, enum intel_output_type type)
18378621f407SFrançois Tigeot {
18388621f407SFrançois Tigeot struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
18398621f407SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
18408621f407SFrançois Tigeot enum port port = intel_dig_port->port;
1841a05eeebfSFrançois Tigeot uint8_t iboost;
1842*3f2dd94aSFrançois Tigeot
1843*3f2dd94aSFrançois Tigeot if (type == INTEL_OUTPUT_HDMI)
1844*3f2dd94aSFrançois Tigeot iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1845*3f2dd94aSFrançois Tigeot else
1846*3f2dd94aSFrançois Tigeot iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1847*3f2dd94aSFrançois Tigeot
1848*3f2dd94aSFrançois Tigeot if (iboost == 0) {
1849*3f2dd94aSFrançois Tigeot const struct ddi_buf_trans *ddi_translations;
1850a05eeebfSFrançois Tigeot int n_entries;
1851a05eeebfSFrançois Tigeot
1852*3f2dd94aSFrançois Tigeot if (type == INTEL_OUTPUT_HDMI)
1853*3f2dd94aSFrançois Tigeot ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1854*3f2dd94aSFrançois Tigeot else if (type == INTEL_OUTPUT_EDP)
1855*3f2dd94aSFrançois Tigeot ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
18561e12ee3bSFrançois Tigeot else
1857*3f2dd94aSFrançois Tigeot ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1858c0e85e96SFrançois Tigeot
1859*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(!ddi_translations))
1860a05eeebfSFrançois Tigeot return;
1861*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(level >= n_entries))
1862*3f2dd94aSFrançois Tigeot level = n_entries - 1;
1863*3f2dd94aSFrançois Tigeot
1864*3f2dd94aSFrançois Tigeot iboost = ddi_translations[level].i_boost;
1865a05eeebfSFrançois Tigeot }
1866a05eeebfSFrançois Tigeot
1867a05eeebfSFrançois Tigeot /* Make sure that the requested I_boost is valid */
1868a05eeebfSFrançois Tigeot if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1869a05eeebfSFrançois Tigeot DRM_ERROR("Invalid I_boost value %u\n", iboost);
1870a05eeebfSFrançois Tigeot return;
1871a05eeebfSFrançois Tigeot }
1872a05eeebfSFrançois Tigeot
18738621f407SFrançois Tigeot _skl_ddi_set_iboost(dev_priv, port, iboost);
1874a05eeebfSFrançois Tigeot
18758621f407SFrançois Tigeot if (port == PORT_A && intel_dig_port->max_lanes == 4)
18768621f407SFrançois Tigeot _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1877a05eeebfSFrançois Tigeot }
1878a05eeebfSFrançois Tigeot
bxt_ddi_vswing_sequence(struct intel_encoder * encoder,int level,enum intel_output_type type)1879*3f2dd94aSFrançois Tigeot static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
1880*3f2dd94aSFrançois Tigeot int level, enum intel_output_type type)
188119c468b4SFrançois Tigeot {
1882*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
188319c468b4SFrançois Tigeot const struct bxt_ddi_buf_trans *ddi_translations;
1884*3f2dd94aSFrançois Tigeot enum port port = encoder->port;
1885*3f2dd94aSFrançois Tigeot int n_entries;
188619c468b4SFrançois Tigeot
1887*3f2dd94aSFrançois Tigeot if (type == INTEL_OUTPUT_HDMI)
1888*3f2dd94aSFrançois Tigeot ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
1889*3f2dd94aSFrançois Tigeot else if (type == INTEL_OUTPUT_EDP)
1890*3f2dd94aSFrançois Tigeot ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
1891*3f2dd94aSFrançois Tigeot else
1892*3f2dd94aSFrançois Tigeot ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
1893*3f2dd94aSFrançois Tigeot
1894*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(!ddi_translations))
189519c468b4SFrançois Tigeot return;
1896*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(level >= n_entries))
1897*3f2dd94aSFrançois Tigeot level = n_entries - 1;
189819c468b4SFrançois Tigeot
18994be47400SFrançois Tigeot bxt_ddi_phy_set_signal_level(dev_priv, port,
19004be47400SFrançois Tigeot ddi_translations[level].margin,
19014be47400SFrançois Tigeot ddi_translations[level].scale,
19024be47400SFrançois Tigeot ddi_translations[level].enable,
19034be47400SFrançois Tigeot ddi_translations[level].deemphasis);
190419c468b4SFrançois Tigeot }
190519c468b4SFrançois Tigeot
intel_ddi_dp_voltage_max(struct intel_encoder * encoder)1906a85cb24fSFrançois Tigeot u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
1907a05eeebfSFrançois Tigeot {
1908a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1909*3f2dd94aSFrançois Tigeot enum port port = encoder->port;
1910a85cb24fSFrançois Tigeot int n_entries;
1911a05eeebfSFrançois Tigeot
1912*3f2dd94aSFrançois Tigeot if (IS_CANNONLAKE(dev_priv)) {
1913a85cb24fSFrançois Tigeot if (encoder->type == INTEL_OUTPUT_EDP)
1914*3f2dd94aSFrançois Tigeot cnl_get_buf_trans_edp(dev_priv, &n_entries);
1915a85cb24fSFrançois Tigeot else
1916*3f2dd94aSFrançois Tigeot cnl_get_buf_trans_dp(dev_priv, &n_entries);
1917*3f2dd94aSFrançois Tigeot } else if (IS_GEN9_LP(dev_priv)) {
1918*3f2dd94aSFrançois Tigeot if (encoder->type == INTEL_OUTPUT_EDP)
1919*3f2dd94aSFrançois Tigeot bxt_get_buf_trans_edp(dev_priv, &n_entries);
1920*3f2dd94aSFrançois Tigeot else
1921*3f2dd94aSFrançois Tigeot bxt_get_buf_trans_dp(dev_priv, &n_entries);
1922*3f2dd94aSFrançois Tigeot } else {
1923*3f2dd94aSFrançois Tigeot if (encoder->type == INTEL_OUTPUT_EDP)
1924*3f2dd94aSFrançois Tigeot intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
1925*3f2dd94aSFrançois Tigeot else
1926*3f2dd94aSFrançois Tigeot intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
1927*3f2dd94aSFrançois Tigeot }
1928a05eeebfSFrançois Tigeot
1929a85cb24fSFrançois Tigeot if (WARN_ON(n_entries < 1))
1930a85cb24fSFrançois Tigeot n_entries = 1;
1931a85cb24fSFrançois Tigeot if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1932a85cb24fSFrançois Tigeot n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1933a05eeebfSFrançois Tigeot
1934a85cb24fSFrançois Tigeot return index_to_dp_signal_levels[n_entries - 1] &
1935a85cb24fSFrançois Tigeot DP_TRAIN_VOLTAGE_SWING_MASK;
1936a05eeebfSFrançois Tigeot }
1937a05eeebfSFrançois Tigeot
cnl_ddi_vswing_program(struct intel_encoder * encoder,int level,enum intel_output_type type)1938*3f2dd94aSFrançois Tigeot static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
1939*3f2dd94aSFrançois Tigeot int level, enum intel_output_type type)
1940*3f2dd94aSFrançois Tigeot {
1941*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1942*3f2dd94aSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
1943*3f2dd94aSFrançois Tigeot const struct cnl_ddi_buf_trans *ddi_translations;
1944*3f2dd94aSFrançois Tigeot int n_entries, ln;
1945*3f2dd94aSFrançois Tigeot u32 val;
1946*3f2dd94aSFrançois Tigeot
1947*3f2dd94aSFrançois Tigeot if (type == INTEL_OUTPUT_HDMI)
1948*3f2dd94aSFrançois Tigeot ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
1949*3f2dd94aSFrançois Tigeot else if (type == INTEL_OUTPUT_EDP)
1950*3f2dd94aSFrançois Tigeot ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
1951*3f2dd94aSFrançois Tigeot else
1952*3f2dd94aSFrançois Tigeot ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
1953*3f2dd94aSFrançois Tigeot
1954*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(!ddi_translations))
1955*3f2dd94aSFrançois Tigeot return;
1956*3f2dd94aSFrançois Tigeot if (WARN_ON_ONCE(level >= n_entries))
1957*3f2dd94aSFrançois Tigeot level = n_entries - 1;
1958*3f2dd94aSFrançois Tigeot
1959*3f2dd94aSFrançois Tigeot /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
1960*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1961*3f2dd94aSFrançois Tigeot val &= ~SCALING_MODE_SEL_MASK;
1962*3f2dd94aSFrançois Tigeot val |= SCALING_MODE_SEL(2);
1963*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1964*3f2dd94aSFrançois Tigeot
1965*3f2dd94aSFrançois Tigeot /* Program PORT_TX_DW2 */
1966*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1967*3f2dd94aSFrançois Tigeot val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1968*3f2dd94aSFrançois Tigeot RCOMP_SCALAR_MASK);
1969*3f2dd94aSFrançois Tigeot val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
1970*3f2dd94aSFrançois Tigeot val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
1971*3f2dd94aSFrançois Tigeot /* Rcomp scalar is fixed as 0x98 for every table entry */
1972*3f2dd94aSFrançois Tigeot val |= RCOMP_SCALAR(0x98);
1973*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
1974*3f2dd94aSFrançois Tigeot
1975*3f2dd94aSFrançois Tigeot /* Program PORT_TX_DW4 */
1976*3f2dd94aSFrançois Tigeot /* We cannot write to GRP. It would overrite individual loadgen */
1977*3f2dd94aSFrançois Tigeot for (ln = 0; ln < 4; ln++) {
1978*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1979*3f2dd94aSFrançois Tigeot val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1980*3f2dd94aSFrançois Tigeot CURSOR_COEFF_MASK);
1981*3f2dd94aSFrançois Tigeot val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
1982*3f2dd94aSFrançois Tigeot val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
1983*3f2dd94aSFrançois Tigeot val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
1984*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
1985*3f2dd94aSFrançois Tigeot }
1986*3f2dd94aSFrançois Tigeot
1987*3f2dd94aSFrançois Tigeot /* Program PORT_TX_DW5 */
1988*3f2dd94aSFrançois Tigeot /* All DW5 values are fixed for every table entry */
1989*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1990*3f2dd94aSFrançois Tigeot val &= ~RTERM_SELECT_MASK;
1991*3f2dd94aSFrançois Tigeot val |= RTERM_SELECT(6);
1992*3f2dd94aSFrançois Tigeot val |= TAP3_DISABLE;
1993*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
1994*3f2dd94aSFrançois Tigeot
1995*3f2dd94aSFrançois Tigeot /* Program PORT_TX_DW7 */
1996*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1997*3f2dd94aSFrançois Tigeot val &= ~N_SCALAR_MASK;
1998*3f2dd94aSFrançois Tigeot val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
1999*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2000*3f2dd94aSFrançois Tigeot }
2001*3f2dd94aSFrançois Tigeot
cnl_ddi_vswing_sequence(struct intel_encoder * encoder,int level,enum intel_output_type type)2002*3f2dd94aSFrançois Tigeot static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2003*3f2dd94aSFrançois Tigeot int level, enum intel_output_type type)
2004*3f2dd94aSFrançois Tigeot {
2005*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2006*3f2dd94aSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
2007*3f2dd94aSFrançois Tigeot int width, rate, ln;
2008*3f2dd94aSFrançois Tigeot u32 val;
2009*3f2dd94aSFrançois Tigeot
2010*3f2dd94aSFrançois Tigeot if (type == INTEL_OUTPUT_HDMI) {
2011*3f2dd94aSFrançois Tigeot width = 4;
2012*3f2dd94aSFrançois Tigeot rate = 0; /* Rate is always < than 6GHz for HDMI */
2013*3f2dd94aSFrançois Tigeot } else {
2014*3f2dd94aSFrançois Tigeot struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2015*3f2dd94aSFrançois Tigeot
2016*3f2dd94aSFrançois Tigeot width = intel_dp->lane_count;
2017*3f2dd94aSFrançois Tigeot rate = intel_dp->link_rate;
2018*3f2dd94aSFrançois Tigeot }
2019*3f2dd94aSFrançois Tigeot
2020*3f2dd94aSFrançois Tigeot /*
2021*3f2dd94aSFrançois Tigeot * 1. If port type is eDP or DP,
2022*3f2dd94aSFrançois Tigeot * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2023*3f2dd94aSFrançois Tigeot * else clear to 0b.
2024*3f2dd94aSFrançois Tigeot */
2025*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2026*3f2dd94aSFrançois Tigeot if (type != INTEL_OUTPUT_HDMI)
2027*3f2dd94aSFrançois Tigeot val |= COMMON_KEEPER_EN;
2028*3f2dd94aSFrançois Tigeot else
2029*3f2dd94aSFrançois Tigeot val &= ~COMMON_KEEPER_EN;
2030*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2031*3f2dd94aSFrançois Tigeot
2032*3f2dd94aSFrançois Tigeot /* 2. Program loadgen select */
2033*3f2dd94aSFrançois Tigeot /*
2034*3f2dd94aSFrançois Tigeot * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2035*3f2dd94aSFrançois Tigeot * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2036*3f2dd94aSFrançois Tigeot * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2037*3f2dd94aSFrançois Tigeot * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2038*3f2dd94aSFrançois Tigeot */
2039*3f2dd94aSFrançois Tigeot for (ln = 0; ln <= 3; ln++) {
2040*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2041*3f2dd94aSFrançois Tigeot val &= ~LOADGEN_SELECT;
2042*3f2dd94aSFrançois Tigeot
2043*3f2dd94aSFrançois Tigeot if ((rate <= 600000 && width == 4 && ln >= 1) ||
2044*3f2dd94aSFrançois Tigeot (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2045*3f2dd94aSFrançois Tigeot val |= LOADGEN_SELECT;
2046*3f2dd94aSFrançois Tigeot }
2047*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2048*3f2dd94aSFrançois Tigeot }
2049*3f2dd94aSFrançois Tigeot
2050*3f2dd94aSFrançois Tigeot /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2051*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_CL1CM_DW5);
2052*3f2dd94aSFrançois Tigeot val |= SUS_CLOCK_CONFIG;
2053*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2054*3f2dd94aSFrançois Tigeot
2055*3f2dd94aSFrançois Tigeot /* 4. Clear training enable to change swing values */
2056*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2057*3f2dd94aSFrançois Tigeot val &= ~TX_TRAINING_EN;
2058*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2059*3f2dd94aSFrançois Tigeot
2060*3f2dd94aSFrançois Tigeot /* 5. Program swing and de-emphasis */
2061*3f2dd94aSFrançois Tigeot cnl_ddi_vswing_program(encoder, level, type);
2062*3f2dd94aSFrançois Tigeot
2063*3f2dd94aSFrançois Tigeot /* 6. Set training enable to trigger update */
2064*3f2dd94aSFrançois Tigeot val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2065*3f2dd94aSFrançois Tigeot val |= TX_TRAINING_EN;
2066*3f2dd94aSFrançois Tigeot I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2067*3f2dd94aSFrançois Tigeot }
2068*3f2dd94aSFrançois Tigeot
translate_signal_level(int signal_levels)2069a85cb24fSFrançois Tigeot static uint32_t translate_signal_level(int signal_levels)
2070a85cb24fSFrançois Tigeot {
2071a85cb24fSFrançois Tigeot int i;
2072a85cb24fSFrançois Tigeot
2073a85cb24fSFrançois Tigeot for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2074a85cb24fSFrançois Tigeot if (index_to_dp_signal_levels[i] == signal_levels)
2075a85cb24fSFrançois Tigeot return i;
2076a85cb24fSFrançois Tigeot }
2077a85cb24fSFrançois Tigeot
2078a85cb24fSFrançois Tigeot WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2079a85cb24fSFrançois Tigeot signal_levels);
2080a85cb24fSFrançois Tigeot
2081a85cb24fSFrançois Tigeot return 0;
2082a05eeebfSFrançois Tigeot }
2083a05eeebfSFrançois Tigeot
intel_ddi_dp_level(struct intel_dp * intel_dp)2084*3f2dd94aSFrançois Tigeot static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2085*3f2dd94aSFrançois Tigeot {
2086*3f2dd94aSFrançois Tigeot uint8_t train_set = intel_dp->train_set[0];
2087*3f2dd94aSFrançois Tigeot int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2088*3f2dd94aSFrançois Tigeot DP_TRAIN_PRE_EMPHASIS_MASK);
2089*3f2dd94aSFrançois Tigeot
2090*3f2dd94aSFrançois Tigeot return translate_signal_level(signal_levels);
2091*3f2dd94aSFrançois Tigeot }
2092*3f2dd94aSFrançois Tigeot
bxt_signal_levels(struct intel_dp * intel_dp)2093*3f2dd94aSFrançois Tigeot u32 bxt_signal_levels(struct intel_dp *intel_dp)
2094*3f2dd94aSFrançois Tigeot {
2095*3f2dd94aSFrançois Tigeot struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2096*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2097*3f2dd94aSFrançois Tigeot struct intel_encoder *encoder = &dport->base;
2098*3f2dd94aSFrançois Tigeot int level = intel_ddi_dp_level(intel_dp);
2099*3f2dd94aSFrançois Tigeot
2100*3f2dd94aSFrançois Tigeot if (IS_CANNONLAKE(dev_priv))
2101*3f2dd94aSFrançois Tigeot cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2102*3f2dd94aSFrançois Tigeot else
2103*3f2dd94aSFrançois Tigeot bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2104*3f2dd94aSFrançois Tigeot
2105*3f2dd94aSFrançois Tigeot return 0;
2106*3f2dd94aSFrançois Tigeot }
2107*3f2dd94aSFrançois Tigeot
ddi_signal_levels(struct intel_dp * intel_dp)2108a05eeebfSFrançois Tigeot uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2109a05eeebfSFrançois Tigeot {
2110a05eeebfSFrançois Tigeot struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2111c0e85e96SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2112a05eeebfSFrançois Tigeot struct intel_encoder *encoder = &dport->base;
2113*3f2dd94aSFrançois Tigeot int level = intel_ddi_dp_level(intel_dp);
2114a05eeebfSFrançois Tigeot
2115a85cb24fSFrançois Tigeot if (IS_GEN9_BC(dev_priv))
2116*3f2dd94aSFrançois Tigeot skl_ddi_set_iboost(encoder, level, encoder->type);
2117a05eeebfSFrançois Tigeot
2118a05eeebfSFrançois Tigeot return DDI_BUF_TRANS_SELECT(level);
2119a05eeebfSFrançois Tigeot }
2120a05eeebfSFrançois Tigeot
intel_ddi_clk_select(struct intel_encoder * encoder,const struct intel_shared_dpll * pll)2121a85cb24fSFrançois Tigeot static void intel_ddi_clk_select(struct intel_encoder *encoder,
2122*3f2dd94aSFrançois Tigeot const struct intel_shared_dpll *pll)
2123aee94f86SFrançois Tigeot {
2124aee94f86SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2125aee94f86SFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
2126*3f2dd94aSFrançois Tigeot uint32_t val;
2127aee94f86SFrançois Tigeot
21281e12ee3bSFrançois Tigeot if (WARN_ON(!pll))
21291e12ee3bSFrançois Tigeot return;
21301e12ee3bSFrançois Tigeot
2131*3f2dd94aSFrançois Tigeot mutex_lock(&dev_priv->dpll_lock);
2132aee94f86SFrançois Tigeot
2133*3f2dd94aSFrançois Tigeot if (IS_CANNONLAKE(dev_priv)) {
2134*3f2dd94aSFrançois Tigeot /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2135*3f2dd94aSFrançois Tigeot val = I915_READ(DPCLKA_CFGCR0);
2136*3f2dd94aSFrançois Tigeot val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2137*3f2dd94aSFrançois Tigeot val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
2138*3f2dd94aSFrançois Tigeot I915_WRITE(DPCLKA_CFGCR0, val);
2139*3f2dd94aSFrançois Tigeot
2140*3f2dd94aSFrançois Tigeot /*
2141*3f2dd94aSFrançois Tigeot * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2142*3f2dd94aSFrançois Tigeot * This step and the step before must be done with separate
2143*3f2dd94aSFrançois Tigeot * register writes.
2144*3f2dd94aSFrançois Tigeot */
2145*3f2dd94aSFrançois Tigeot val = I915_READ(DPCLKA_CFGCR0);
2146*3f2dd94aSFrançois Tigeot val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2147*3f2dd94aSFrançois Tigeot I915_WRITE(DPCLKA_CFGCR0, val);
2148*3f2dd94aSFrançois Tigeot } else if (IS_GEN9_BC(dev_priv)) {
2149aee94f86SFrançois Tigeot /* DDI -> PLL mapping */
2150aee94f86SFrançois Tigeot val = I915_READ(DPLL_CTRL2);
2151aee94f86SFrançois Tigeot
2152aee94f86SFrançois Tigeot val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2153aee94f86SFrançois Tigeot DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
21541e12ee3bSFrançois Tigeot val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2155aee94f86SFrançois Tigeot DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2156aee94f86SFrançois Tigeot
2157aee94f86SFrançois Tigeot I915_WRITE(DPLL_CTRL2, val);
2158aee94f86SFrançois Tigeot
2159aee94f86SFrançois Tigeot } else if (INTEL_INFO(dev_priv)->gen < 9) {
21601e12ee3bSFrançois Tigeot I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2161aee94f86SFrançois Tigeot }
2162*3f2dd94aSFrançois Tigeot
2163*3f2dd94aSFrançois Tigeot mutex_unlock(&dev_priv->dpll_lock);
2164*3f2dd94aSFrançois Tigeot }
2165*3f2dd94aSFrançois Tigeot
intel_ddi_clk_disable(struct intel_encoder * encoder)2166*3f2dd94aSFrançois Tigeot static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2167*3f2dd94aSFrançois Tigeot {
2168*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2169*3f2dd94aSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
2170*3f2dd94aSFrançois Tigeot
2171*3f2dd94aSFrançois Tigeot if (IS_CANNONLAKE(dev_priv))
2172*3f2dd94aSFrançois Tigeot I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2173*3f2dd94aSFrançois Tigeot DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2174*3f2dd94aSFrançois Tigeot else if (IS_GEN9_BC(dev_priv))
2175*3f2dd94aSFrançois Tigeot I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2176*3f2dd94aSFrançois Tigeot DPLL_CTRL2_DDI_CLK_OFF(port));
2177*3f2dd94aSFrançois Tigeot else if (INTEL_GEN(dev_priv) < 9)
2178*3f2dd94aSFrançois Tigeot I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2179aee94f86SFrançois Tigeot }
2180aee94f86SFrançois Tigeot
intel_ddi_pre_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)21811e12ee3bSFrançois Tigeot static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
2182*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *crtc_state,
2183*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
218419df918dSFrançois Tigeot {
21851e12ee3bSFrançois Tigeot struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
21861e12ee3bSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
21871e12ee3bSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
2188a85cb24fSFrançois Tigeot struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2189*3f2dd94aSFrançois Tigeot bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2190*3f2dd94aSFrançois Tigeot int level = intel_ddi_dp_level(intel_dp);
2191a85cb24fSFrançois Tigeot
2192*3f2dd94aSFrançois Tigeot WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
2193c0e85e96SFrançois Tigeot
2194*3f2dd94aSFrançois Tigeot intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2195*3f2dd94aSFrançois Tigeot crtc_state->lane_count, is_mst);
2196*3f2dd94aSFrançois Tigeot
2197ba55f2f5SFrançois Tigeot intel_edp_panel_on(intel_dp);
2198ba55f2f5SFrançois Tigeot
2199*3f2dd94aSFrançois Tigeot intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2200a85cb24fSFrançois Tigeot
2201a85cb24fSFrançois Tigeot intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2202a85cb24fSFrançois Tigeot
2203*3f2dd94aSFrançois Tigeot if (IS_CANNONLAKE(dev_priv))
2204*3f2dd94aSFrançois Tigeot cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2205*3f2dd94aSFrançois Tigeot else if (IS_GEN9_LP(dev_priv))
2206*3f2dd94aSFrançois Tigeot bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2207*3f2dd94aSFrançois Tigeot else
22081e12ee3bSFrançois Tigeot intel_prepare_dp_ddi_buffers(encoder);
2209*3f2dd94aSFrançois Tigeot
22101e12ee3bSFrançois Tigeot intel_ddi_init_dp_buf_reg(encoder);
221119df918dSFrançois Tigeot intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
221219df918dSFrançois Tigeot intel_dp_start_link_train(intel_dp);
22131e12ee3bSFrançois Tigeot if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
22148e26cdf6SFrançois Tigeot intel_dp_stop_link_train(intel_dp);
22151e12ee3bSFrançois Tigeot }
22161e12ee3bSFrançois Tigeot
intel_ddi_pre_enable_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)22171e12ee3bSFrançois Tigeot static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
2218a85cb24fSFrançois Tigeot const struct intel_crtc_state *crtc_state,
2219*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
22201e12ee3bSFrançois Tigeot {
2221*3f2dd94aSFrançois Tigeot struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2222*3f2dd94aSFrançois Tigeot struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
22231e12ee3bSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22241e12ee3bSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
22258621f407SFrançois Tigeot int level = intel_ddi_hdmi_level(dev_priv, port);
2226a85cb24fSFrançois Tigeot struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
22278621f407SFrançois Tigeot
22281e12ee3bSFrançois Tigeot intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2229*3f2dd94aSFrançois Tigeot intel_ddi_clk_select(encoder, crtc_state->shared_dpll);
2230a85cb24fSFrançois Tigeot
2231a85cb24fSFrançois Tigeot intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2232a85cb24fSFrançois Tigeot
2233*3f2dd94aSFrançois Tigeot if (IS_CANNONLAKE(dev_priv))
2234*3f2dd94aSFrançois Tigeot cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2235a85cb24fSFrançois Tigeot else if (IS_GEN9_LP(dev_priv))
2236*3f2dd94aSFrançois Tigeot bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
2237*3f2dd94aSFrançois Tigeot else
2238*3f2dd94aSFrançois Tigeot intel_prepare_hdmi_ddi_buffers(encoder, level);
2239ba55f2f5SFrançois Tigeot
2240*3f2dd94aSFrançois Tigeot if (IS_GEN9_BC(dev_priv))
2241*3f2dd94aSFrançois Tigeot skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
2242*3f2dd94aSFrançois Tigeot
2243*3f2dd94aSFrançois Tigeot intel_dig_port->set_infoframes(&encoder->base,
2244*3f2dd94aSFrançois Tigeot crtc_state->has_infoframe,
2245a85cb24fSFrançois Tigeot crtc_state, conn_state);
22461e12ee3bSFrançois Tigeot }
22471e12ee3bSFrançois Tigeot
intel_ddi_pre_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2248a85cb24fSFrançois Tigeot static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2249*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *crtc_state,
2250*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
22511e12ee3bSFrançois Tigeot {
2252*3f2dd94aSFrançois Tigeot struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2253*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2254*3f2dd94aSFrançois Tigeot enum i915_pipe pipe = crtc->pipe;
22551e12ee3bSFrançois Tigeot
2256*3f2dd94aSFrançois Tigeot WARN_ON(crtc_state->has_pch_encoder);
2257*3f2dd94aSFrançois Tigeot
2258*3f2dd94aSFrançois Tigeot intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2259*3f2dd94aSFrançois Tigeot
2260*3f2dd94aSFrançois Tigeot if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2261*3f2dd94aSFrançois Tigeot intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
2262*3f2dd94aSFrançois Tigeot else
2263*3f2dd94aSFrançois Tigeot intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
226419df918dSFrançois Tigeot }
226519df918dSFrançois Tigeot
intel_disable_ddi_buf(struct intel_encoder * encoder)2266*3f2dd94aSFrançois Tigeot static void intel_disable_ddi_buf(struct intel_encoder *encoder)
226719df918dSFrançois Tigeot {
2268*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2269*3f2dd94aSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
227019df918dSFrançois Tigeot bool wait = false;
2271*3f2dd94aSFrançois Tigeot u32 val;
22721e12ee3bSFrançois Tigeot
227319df918dSFrançois Tigeot val = I915_READ(DDI_BUF_CTL(port));
227419df918dSFrançois Tigeot if (val & DDI_BUF_CTL_ENABLE) {
227519df918dSFrançois Tigeot val &= ~DDI_BUF_CTL_ENABLE;
227619df918dSFrançois Tigeot I915_WRITE(DDI_BUF_CTL(port), val);
227719df918dSFrançois Tigeot wait = true;
227819df918dSFrançois Tigeot }
227919df918dSFrançois Tigeot
228019df918dSFrançois Tigeot val = I915_READ(DP_TP_CTL(port));
228119df918dSFrançois Tigeot val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
228219df918dSFrançois Tigeot val |= DP_TP_CTL_LINK_TRAIN_PAT1;
228319df918dSFrançois Tigeot I915_WRITE(DP_TP_CTL(port), val);
228419df918dSFrançois Tigeot
228519df918dSFrançois Tigeot if (wait)
228619df918dSFrançois Tigeot intel_wait_ddi_buf_idle(dev_priv, port);
228719df918dSFrançois Tigeot }
228819df918dSFrançois Tigeot
intel_ddi_post_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2289*3f2dd94aSFrançois Tigeot static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
2290*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
2291*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
2292*3f2dd94aSFrançois Tigeot {
2293*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2294*3f2dd94aSFrançois Tigeot struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2295*3f2dd94aSFrançois Tigeot struct intel_dp *intel_dp = &dig_port->dp;
2296*3f2dd94aSFrançois Tigeot
2297*3f2dd94aSFrançois Tigeot /*
2298*3f2dd94aSFrançois Tigeot * Power down sink before disabling the port, otherwise we end
2299*3f2dd94aSFrançois Tigeot * up getting interrupts from the sink on detecting link loss.
2300*3f2dd94aSFrançois Tigeot */
2301*3f2dd94aSFrançois Tigeot intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2302*3f2dd94aSFrançois Tigeot
2303*3f2dd94aSFrançois Tigeot intel_disable_ddi_buf(encoder);
2304*3f2dd94aSFrançois Tigeot
2305*3f2dd94aSFrançois Tigeot intel_edp_panel_vdd_on(intel_dp);
2306*3f2dd94aSFrançois Tigeot intel_edp_panel_off(intel_dp);
2307*3f2dd94aSFrançois Tigeot
2308a85cb24fSFrançois Tigeot intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2309a85cb24fSFrançois Tigeot
2310*3f2dd94aSFrançois Tigeot intel_ddi_clk_disable(encoder);
2311*3f2dd94aSFrançois Tigeot }
23128621f407SFrançois Tigeot
intel_ddi_post_disable_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2313*3f2dd94aSFrançois Tigeot static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
2314*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
2315*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
2316*3f2dd94aSFrançois Tigeot {
2317*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2318*3f2dd94aSFrançois Tigeot struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2319*3f2dd94aSFrançois Tigeot struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2320*3f2dd94aSFrançois Tigeot
2321*3f2dd94aSFrançois Tigeot intel_disable_ddi_buf(encoder);
2322*3f2dd94aSFrançois Tigeot
2323*3f2dd94aSFrançois Tigeot dig_port->set_infoframes(&encoder->base, false,
2324*3f2dd94aSFrançois Tigeot old_crtc_state, old_conn_state);
2325*3f2dd94aSFrançois Tigeot
2326*3f2dd94aSFrançois Tigeot intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
2327*3f2dd94aSFrançois Tigeot
2328*3f2dd94aSFrançois Tigeot intel_ddi_clk_disable(encoder);
23298621f407SFrançois Tigeot
23308621f407SFrançois Tigeot intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
23318621f407SFrançois Tigeot }
2332*3f2dd94aSFrançois Tigeot
intel_ddi_post_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2333*3f2dd94aSFrançois Tigeot static void intel_ddi_post_disable(struct intel_encoder *encoder,
2334*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
2335*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
2336*3f2dd94aSFrançois Tigeot {
2337*3f2dd94aSFrançois Tigeot /*
2338*3f2dd94aSFrançois Tigeot * old_crtc_state and old_conn_state are NULL when called from
2339*3f2dd94aSFrançois Tigeot * DP_MST. The main connector associated with this port is never
2340*3f2dd94aSFrançois Tigeot * bound to a crtc for MST.
2341*3f2dd94aSFrançois Tigeot */
2342*3f2dd94aSFrançois Tigeot if (old_crtc_state &&
2343*3f2dd94aSFrançois Tigeot intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2344*3f2dd94aSFrançois Tigeot intel_ddi_post_disable_hdmi(encoder,
2345*3f2dd94aSFrançois Tigeot old_crtc_state, old_conn_state);
2346*3f2dd94aSFrançois Tigeot else
2347*3f2dd94aSFrançois Tigeot intel_ddi_post_disable_dp(encoder,
2348*3f2dd94aSFrançois Tigeot old_crtc_state, old_conn_state);
234919df918dSFrançois Tigeot }
235019df918dSFrançois Tigeot
intel_ddi_fdi_post_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2351a85cb24fSFrançois Tigeot void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2352*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
2353*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
23541e12ee3bSFrançois Tigeot {
2355a85cb24fSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
23561e12ee3bSFrançois Tigeot uint32_t val;
23571e12ee3bSFrançois Tigeot
23581e12ee3bSFrançois Tigeot /*
23591e12ee3bSFrançois Tigeot * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
23601e12ee3bSFrançois Tigeot * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
23611e12ee3bSFrançois Tigeot * step 13 is the correct place for it. Step 18 is where it was
23621e12ee3bSFrançois Tigeot * originally before the BUN.
23631e12ee3bSFrançois Tigeot */
23641e12ee3bSFrançois Tigeot val = I915_READ(FDI_RX_CTL(PIPE_A));
23651e12ee3bSFrançois Tigeot val &= ~FDI_RX_ENABLE;
23661e12ee3bSFrançois Tigeot I915_WRITE(FDI_RX_CTL(PIPE_A), val);
23671e12ee3bSFrançois Tigeot
2368*3f2dd94aSFrançois Tigeot intel_disable_ddi_buf(encoder);
2369*3f2dd94aSFrançois Tigeot intel_ddi_clk_disable(encoder);
23701e12ee3bSFrançois Tigeot
23711e12ee3bSFrançois Tigeot val = I915_READ(FDI_RX_MISC(PIPE_A));
23721e12ee3bSFrançois Tigeot val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
23731e12ee3bSFrançois Tigeot val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
23741e12ee3bSFrançois Tigeot I915_WRITE(FDI_RX_MISC(PIPE_A), val);
23751e12ee3bSFrançois Tigeot
23761e12ee3bSFrançois Tigeot val = I915_READ(FDI_RX_CTL(PIPE_A));
23771e12ee3bSFrançois Tigeot val &= ~FDI_PCDCLK;
23781e12ee3bSFrançois Tigeot I915_WRITE(FDI_RX_CTL(PIPE_A), val);
23791e12ee3bSFrançois Tigeot
23801e12ee3bSFrançois Tigeot val = I915_READ(FDI_RX_CTL(PIPE_A));
23811e12ee3bSFrançois Tigeot val &= ~FDI_RX_PLL_ENABLE;
23821e12ee3bSFrançois Tigeot I915_WRITE(FDI_RX_CTL(PIPE_A), val);
23831e12ee3bSFrançois Tigeot }
23841e12ee3bSFrançois Tigeot
intel_enable_ddi_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2385*3f2dd94aSFrançois Tigeot static void intel_enable_ddi_dp(struct intel_encoder *encoder,
2386*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *crtc_state,
2387*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
238819df918dSFrançois Tigeot {
2389*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2390*3f2dd94aSFrançois Tigeot struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2391*3f2dd94aSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
239219df918dSFrançois Tigeot
2393*3f2dd94aSFrançois Tigeot if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2394*3f2dd94aSFrançois Tigeot intel_dp_stop_link_train(intel_dp);
2395a85cb24fSFrançois Tigeot
2396*3f2dd94aSFrançois Tigeot intel_edp_backlight_on(crtc_state, conn_state);
2397*3f2dd94aSFrançois Tigeot intel_psr_enable(intel_dp, crtc_state);
2398*3f2dd94aSFrançois Tigeot intel_edp_drrs_enable(intel_dp, crtc_state);
2399*3f2dd94aSFrançois Tigeot
2400*3f2dd94aSFrançois Tigeot if (crtc_state->has_audio)
2401*3f2dd94aSFrançois Tigeot intel_audio_codec_enable(encoder, crtc_state, conn_state);
2402*3f2dd94aSFrançois Tigeot }
2403*3f2dd94aSFrançois Tigeot
intel_enable_ddi_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2404*3f2dd94aSFrançois Tigeot static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
2405*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *crtc_state,
2406*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
2407*3f2dd94aSFrançois Tigeot {
2408*3f2dd94aSFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2409*3f2dd94aSFrançois Tigeot struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2410*3f2dd94aSFrançois Tigeot enum port port = intel_ddi_get_encoder_port(encoder);
2411*3f2dd94aSFrançois Tigeot
2412*3f2dd94aSFrançois Tigeot intel_hdmi_handle_sink_scrambling(encoder,
2413a85cb24fSFrançois Tigeot conn_state->connector,
2414*3f2dd94aSFrançois Tigeot crtc_state->hdmi_high_tmds_clock_ratio,
2415*3f2dd94aSFrançois Tigeot crtc_state->hdmi_scrambling);
241619df918dSFrançois Tigeot
241719df918dSFrançois Tigeot /* In HDMI/DVI mode, the port width, and swing/emphasis values
241819df918dSFrançois Tigeot * are ignored so nothing special needs to be done besides
241919df918dSFrançois Tigeot * enabling the port.
242019df918dSFrançois Tigeot */
242119df918dSFrançois Tigeot I915_WRITE(DDI_BUF_CTL(port),
2422*3f2dd94aSFrançois Tigeot dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
242319df918dSFrançois Tigeot
2424*3f2dd94aSFrançois Tigeot if (crtc_state->has_audio)
2425*3f2dd94aSFrançois Tigeot intel_audio_codec_enable(encoder, crtc_state, conn_state);
242619df918dSFrançois Tigeot }
2427a2fdbec6SFrançois Tigeot
intel_enable_ddi(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2428*3f2dd94aSFrançois Tigeot static void intel_enable_ddi(struct intel_encoder *encoder,
2429*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *crtc_state,
2430*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
243119df918dSFrançois Tigeot {
2432*3f2dd94aSFrançois Tigeot if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2433*3f2dd94aSFrançois Tigeot intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
2434*3f2dd94aSFrançois Tigeot else
2435*3f2dd94aSFrançois Tigeot intel_enable_ddi_dp(encoder, crtc_state, conn_state);
2436*3f2dd94aSFrançois Tigeot }
2437*3f2dd94aSFrançois Tigeot
intel_disable_ddi_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2438*3f2dd94aSFrançois Tigeot static void intel_disable_ddi_dp(struct intel_encoder *encoder,
2439*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
2440*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
2441*3f2dd94aSFrançois Tigeot {
2442*3f2dd94aSFrançois Tigeot struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
244319df918dSFrançois Tigeot
2444a85cb24fSFrançois Tigeot if (old_crtc_state->has_audio)
2445*3f2dd94aSFrançois Tigeot intel_audio_codec_disable(encoder);
2446a85cb24fSFrançois Tigeot
2447*3f2dd94aSFrançois Tigeot intel_edp_drrs_disable(intel_dp, old_crtc_state);
2448*3f2dd94aSFrançois Tigeot intel_psr_disable(intel_dp, old_crtc_state);
2449*3f2dd94aSFrançois Tigeot intel_edp_backlight_off(old_conn_state);
2450*3f2dd94aSFrançois Tigeot }
2451*3f2dd94aSFrançois Tigeot
intel_disable_ddi_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2452*3f2dd94aSFrançois Tigeot static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
2453*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
2454*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
2455*3f2dd94aSFrançois Tigeot {
2456*3f2dd94aSFrançois Tigeot if (old_crtc_state->has_audio)
2457*3f2dd94aSFrançois Tigeot intel_audio_codec_disable(encoder);
2458*3f2dd94aSFrançois Tigeot
2459*3f2dd94aSFrançois Tigeot intel_hdmi_handle_sink_scrambling(encoder,
2460a85cb24fSFrançois Tigeot old_conn_state->connector,
2461a85cb24fSFrançois Tigeot false, false);
24625d0b1887SFrançois Tigeot }
24638e26cdf6SFrançois Tigeot
intel_disable_ddi(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)2464*3f2dd94aSFrançois Tigeot static void intel_disable_ddi(struct intel_encoder *encoder,
2465*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *old_crtc_state,
2466*3f2dd94aSFrançois Tigeot const struct drm_connector_state *old_conn_state)
2467*3f2dd94aSFrançois Tigeot {
2468*3f2dd94aSFrançois Tigeot if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2469*3f2dd94aSFrançois Tigeot intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
2470*3f2dd94aSFrançois Tigeot else
2471*3f2dd94aSFrançois Tigeot intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
247219df918dSFrançois Tigeot }
247319df918dSFrançois Tigeot
bxt_ddi_pre_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)24741e12ee3bSFrançois Tigeot static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
2475*3f2dd94aSFrançois Tigeot const struct intel_crtc_state *pipe_config,
2476*3f2dd94aSFrançois Tigeot const struct drm_connector_state *conn_state)
24771487f786SFrançois Tigeot {
2478a85cb24fSFrançois Tigeot uint8_t mask = pipe_config->lane_lat_optim_mask;
24791487f786SFrançois Tigeot
24804be47400SFrançois Tigeot bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
24812c9916cdSFrançois Tigeot }
248219df918dSFrançois Tigeot
intel_ddi_prepare_link_retrain(struct intel_dp * intel_dp)2483aee94f86SFrançois Tigeot void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
248419df918dSFrançois Tigeot {
2485aee94f86SFrançois Tigeot struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2486aee94f86SFrançois Tigeot struct drm_i915_private *dev_priv =
2487aee94f86SFrançois Tigeot to_i915(intel_dig_port->base.base.dev);
248819df918dSFrançois Tigeot enum port port = intel_dig_port->port;
248919df918dSFrançois Tigeot uint32_t val;
2490a2fdbec6SFrançois Tigeot bool wait = false;
249119df918dSFrançois Tigeot
249219df918dSFrançois Tigeot if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
249319df918dSFrançois Tigeot val = I915_READ(DDI_BUF_CTL(port));
249419df918dSFrançois Tigeot if (val & DDI_BUF_CTL_ENABLE) {
249519df918dSFrançois Tigeot val &= ~DDI_BUF_CTL_ENABLE;
249619df918dSFrançois Tigeot I915_WRITE(DDI_BUF_CTL(port), val);
249719df918dSFrançois Tigeot wait = true;
249819df918dSFrançois Tigeot }
249919df918dSFrançois Tigeot
250019df918dSFrançois Tigeot val = I915_READ(DP_TP_CTL(port));
250119df918dSFrançois Tigeot val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
250219df918dSFrançois Tigeot val |= DP_TP_CTL_LINK_TRAIN_PAT1;
250319df918dSFrançois Tigeot I915_WRITE(DP_TP_CTL(port), val);
250419df918dSFrançois Tigeot POSTING_READ(DP_TP_CTL(port));
250519df918dSFrançois Tigeot
250619df918dSFrançois Tigeot if (wait)
250719df918dSFrançois Tigeot intel_wait_ddi_buf_idle(dev_priv, port);
250819df918dSFrançois Tigeot }
250919df918dSFrançois Tigeot
25102c9916cdSFrançois Tigeot val = DP_TP_CTL_ENABLE |
251119df918dSFrançois Tigeot DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
251271f41f3eSFrançois Tigeot if (intel_dp->link_mst)
25132c9916cdSFrançois Tigeot val |= DP_TP_CTL_MODE_MST;
25142c9916cdSFrançois Tigeot else {
25152c9916cdSFrançois Tigeot val |= DP_TP_CTL_MODE_SST;
25169edbd4a0SFrançois Tigeot if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
251719df918dSFrançois Tigeot val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
25182c9916cdSFrançois Tigeot }
251919df918dSFrançois Tigeot I915_WRITE(DP_TP_CTL(port), val);
252019df918dSFrançois Tigeot POSTING_READ(DP_TP_CTL(port));
252119df918dSFrançois Tigeot
252219df918dSFrançois Tigeot intel_dp->DP |= DDI_BUF_CTL_ENABLE;
252319df918dSFrançois Tigeot I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
252419df918dSFrançois Tigeot POSTING_READ(DDI_BUF_CTL(port));
252519df918dSFrançois Tigeot
252619df918dSFrançois Tigeot udelay(600);
252719df918dSFrançois Tigeot }
252819df918dSFrançois Tigeot
intel_ddi_is_audio_enabled(struct drm_i915_private * dev_priv,struct intel_crtc * intel_crtc)2529a85cb24fSFrançois Tigeot bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
2530a85cb24fSFrançois Tigeot struct intel_crtc *intel_crtc)
2531a85cb24fSFrançois Tigeot {
2532a85cb24fSFrançois Tigeot u32 temp;
2533a85cb24fSFrançois Tigeot
2534a85cb24fSFrançois Tigeot if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2535a85cb24fSFrançois Tigeot temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2536a85cb24fSFrançois Tigeot if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2537a85cb24fSFrançois Tigeot return true;
2538a85cb24fSFrançois Tigeot }
2539a85cb24fSFrançois Tigeot return false;
2540a85cb24fSFrançois Tigeot }
2541a85cb24fSFrançois Tigeot
intel_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)25429edbd4a0SFrançois Tigeot void intel_ddi_get_config(struct intel_encoder *encoder,
25432c9916cdSFrançois Tigeot struct intel_crtc_state *pipe_config)
25445d0b1887SFrançois Tigeot {
2545303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
25465d0b1887SFrançois Tigeot struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
25472c9916cdSFrançois Tigeot enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2548*3f2dd94aSFrançois Tigeot struct intel_digital_port *intel_dig_port;
25495d0b1887SFrançois Tigeot u32 temp, flags = 0;
25505d0b1887SFrançois Tigeot
25518621f407SFrançois Tigeot /* XXX: DSI transcoder paranoia */
25528621f407SFrançois Tigeot if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
25538621f407SFrançois Tigeot return;
25548621f407SFrançois Tigeot
25555d0b1887SFrançois Tigeot temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
25565d0b1887SFrançois Tigeot if (temp & TRANS_DDI_PHSYNC)
25575d0b1887SFrançois Tigeot flags |= DRM_MODE_FLAG_PHSYNC;
25585d0b1887SFrançois Tigeot else
25595d0b1887SFrançois Tigeot flags |= DRM_MODE_FLAG_NHSYNC;
25605d0b1887SFrançois Tigeot if (temp & TRANS_DDI_PVSYNC)
25615d0b1887SFrançois Tigeot flags |= DRM_MODE_FLAG_PVSYNC;
25625d0b1887SFrançois Tigeot else
25635d0b1887SFrançois Tigeot flags |= DRM_MODE_FLAG_NVSYNC;
25645d0b1887SFrançois Tigeot
25652c9916cdSFrançois Tigeot pipe_config->base.adjusted_mode.flags |= flags;
25669edbd4a0SFrançois Tigeot
25679edbd4a0SFrançois Tigeot switch (temp & TRANS_DDI_BPC_MASK) {
25689edbd4a0SFrançois Tigeot case TRANS_DDI_BPC_6:
25699edbd4a0SFrançois Tigeot pipe_config->pipe_bpp = 18;
25709edbd4a0SFrançois Tigeot break;
25719edbd4a0SFrançois Tigeot case TRANS_DDI_BPC_8:
25729edbd4a0SFrançois Tigeot pipe_config->pipe_bpp = 24;
25739edbd4a0SFrançois Tigeot break;
25749edbd4a0SFrançois Tigeot case TRANS_DDI_BPC_10:
25759edbd4a0SFrançois Tigeot pipe_config->pipe_bpp = 30;
25769edbd4a0SFrançois Tigeot break;
25779edbd4a0SFrançois Tigeot case TRANS_DDI_BPC_12:
25789edbd4a0SFrançois Tigeot pipe_config->pipe_bpp = 36;
25799edbd4a0SFrançois Tigeot break;
25809edbd4a0SFrançois Tigeot default:
25819edbd4a0SFrançois Tigeot break;
25829edbd4a0SFrançois Tigeot }
25839edbd4a0SFrançois Tigeot
25849edbd4a0SFrançois Tigeot switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
25859edbd4a0SFrançois Tigeot case TRANS_DDI_MODE_SELECT_HDMI:
2586ba55f2f5SFrançois Tigeot pipe_config->has_hdmi_sink = true;
2587*3f2dd94aSFrançois Tigeot intel_dig_port = enc_to_dig_port(&encoder->base);
25882c9916cdSFrançois Tigeot
2589*3f2dd94aSFrançois Tigeot if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
25902c9916cdSFrançois Tigeot pipe_config->has_infoframe = true;
2591a85cb24fSFrançois Tigeot
2592a85cb24fSFrançois Tigeot if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
2593a85cb24fSFrançois Tigeot TRANS_DDI_HDMI_SCRAMBLING_MASK)
2594a85cb24fSFrançois Tigeot pipe_config->hdmi_scrambling = true;
2595a85cb24fSFrançois Tigeot if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
2596a85cb24fSFrançois Tigeot pipe_config->hdmi_high_tmds_clock_ratio = true;
25978621f407SFrançois Tigeot /* fall through */
25989edbd4a0SFrançois Tigeot case TRANS_DDI_MODE_SELECT_DVI:
25998621f407SFrançois Tigeot pipe_config->lane_count = 4;
26008621f407SFrançois Tigeot break;
26019edbd4a0SFrançois Tigeot case TRANS_DDI_MODE_SELECT_FDI:
26029edbd4a0SFrançois Tigeot break;
26039edbd4a0SFrançois Tigeot case TRANS_DDI_MODE_SELECT_DP_SST:
26049edbd4a0SFrançois Tigeot case TRANS_DDI_MODE_SELECT_DP_MST:
2605352ff8bdSFrançois Tigeot pipe_config->lane_count =
2606352ff8bdSFrançois Tigeot ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
26079edbd4a0SFrançois Tigeot intel_dp_get_m_n(intel_crtc, pipe_config);
26089edbd4a0SFrançois Tigeot break;
26099edbd4a0SFrançois Tigeot default:
26109edbd4a0SFrançois Tigeot break;
26119edbd4a0SFrançois Tigeot }
26129edbd4a0SFrançois Tigeot
2613a85cb24fSFrançois Tigeot pipe_config->has_audio =
2614a85cb24fSFrançois Tigeot intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2615ba55f2f5SFrançois Tigeot
26168621f407SFrançois Tigeot if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
26178621f407SFrançois Tigeot pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
26189edbd4a0SFrançois Tigeot /*
26199edbd4a0SFrançois Tigeot * This is a big fat ugly hack.
26209edbd4a0SFrançois Tigeot *
26219edbd4a0SFrançois Tigeot * Some machines in UEFI boot mode provide us a VBT that has 18
26229edbd4a0SFrançois Tigeot * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
26239edbd4a0SFrançois Tigeot * unknown we fail to light up. Yet the same BIOS boots up with
26249edbd4a0SFrançois Tigeot * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
26259edbd4a0SFrançois Tigeot * max, not what it tells us to use.
26269edbd4a0SFrançois Tigeot *
26279edbd4a0SFrançois Tigeot * Note: This will still be broken if the eDP panel is not lit
26289edbd4a0SFrançois Tigeot * up by the BIOS, and thus we can't get the mode at module
26299edbd4a0SFrançois Tigeot * load.
26309edbd4a0SFrançois Tigeot */
26319edbd4a0SFrançois Tigeot DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
26328621f407SFrançois Tigeot pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
26338621f407SFrançois Tigeot dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
26349edbd4a0SFrançois Tigeot }
2635ba55f2f5SFrançois Tigeot
26362c9916cdSFrançois Tigeot intel_ddi_clock_get(encoder, pipe_config);
26371487f786SFrançois Tigeot
2638a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv))
26391487f786SFrançois Tigeot pipe_config->lane_lat_optim_mask =
26401487f786SFrançois Tigeot bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
26415d0b1887SFrançois Tigeot }
26425d0b1887SFrançois Tigeot
intel_ddi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)26438e26cdf6SFrançois Tigeot static bool intel_ddi_compute_config(struct intel_encoder *encoder,
26441e12ee3bSFrançois Tigeot struct intel_crtc_state *pipe_config,
26451e12ee3bSFrançois Tigeot struct drm_connector_state *conn_state)
264619df918dSFrançois Tigeot {
2647303bf270SFrançois Tigeot struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
26488e26cdf6SFrançois Tigeot int type = encoder->type;
26495d0b1887SFrançois Tigeot int port = intel_ddi_get_encoder_port(encoder);
26501487f786SFrançois Tigeot int ret;
265119df918dSFrançois Tigeot
26528e26cdf6SFrançois Tigeot WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
265319df918dSFrançois Tigeot
26545d0b1887SFrançois Tigeot if (port == PORT_A)
26555d0b1887SFrançois Tigeot pipe_config->cpu_transcoder = TRANSCODER_EDP;
26565d0b1887SFrançois Tigeot
265719df918dSFrançois Tigeot if (type == INTEL_OUTPUT_HDMI)
26581e12ee3bSFrançois Tigeot ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
265919df918dSFrançois Tigeot else
26601e12ee3bSFrançois Tigeot ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
26611487f786SFrançois Tigeot
2662a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv) && ret)
26631487f786SFrançois Tigeot pipe_config->lane_lat_optim_mask =
26641487f786SFrançois Tigeot bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
26654be47400SFrançois Tigeot pipe_config->lane_count);
26661487f786SFrançois Tigeot
26671487f786SFrançois Tigeot return ret;
26681487f786SFrançois Tigeot
266919df918dSFrançois Tigeot }
267019df918dSFrançois Tigeot
267119df918dSFrançois Tigeot static const struct drm_encoder_funcs intel_ddi_funcs = {
2672c0e85e96SFrançois Tigeot .reset = intel_dp_encoder_reset,
2673c0e85e96SFrançois Tigeot .destroy = intel_dp_encoder_destroy,
267419df918dSFrançois Tigeot };
267519df918dSFrançois Tigeot
26769edbd4a0SFrançois Tigeot static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port * intel_dig_port)26779edbd4a0SFrançois Tigeot intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
26789edbd4a0SFrançois Tigeot {
26799edbd4a0SFrançois Tigeot struct intel_connector *connector;
26809edbd4a0SFrançois Tigeot enum port port = intel_dig_port->port;
26819edbd4a0SFrançois Tigeot
2682477eb7f9SFrançois Tigeot connector = intel_connector_alloc();
26839edbd4a0SFrançois Tigeot if (!connector)
26849edbd4a0SFrançois Tigeot return NULL;
26859edbd4a0SFrançois Tigeot
26869edbd4a0SFrançois Tigeot intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
26879edbd4a0SFrançois Tigeot if (!intel_dp_init_connector(intel_dig_port, connector)) {
26889edbd4a0SFrançois Tigeot kfree(connector);
26899edbd4a0SFrançois Tigeot return NULL;
26909edbd4a0SFrançois Tigeot }
26919edbd4a0SFrançois Tigeot
26929edbd4a0SFrançois Tigeot return connector;
26939edbd4a0SFrançois Tigeot }
26949edbd4a0SFrançois Tigeot
26959edbd4a0SFrançois Tigeot static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port * intel_dig_port)26969edbd4a0SFrançois Tigeot intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
26979edbd4a0SFrançois Tigeot {
26989edbd4a0SFrançois Tigeot struct intel_connector *connector;
26999edbd4a0SFrançois Tigeot enum port port = intel_dig_port->port;
27009edbd4a0SFrançois Tigeot
2701477eb7f9SFrançois Tigeot connector = intel_connector_alloc();
27029edbd4a0SFrançois Tigeot if (!connector)
27039edbd4a0SFrançois Tigeot return NULL;
27049edbd4a0SFrançois Tigeot
27059edbd4a0SFrançois Tigeot intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
27069edbd4a0SFrançois Tigeot intel_hdmi_init_connector(intel_dig_port, connector);
27079edbd4a0SFrançois Tigeot
27089edbd4a0SFrançois Tigeot return connector;
27099edbd4a0SFrançois Tigeot }
271019df918dSFrançois Tigeot
intel_ddi_init(struct drm_i915_private * dev_priv,enum port port)2711a85cb24fSFrançois Tigeot void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
27121e12ee3bSFrançois Tigeot {
271319df918dSFrançois Tigeot struct intel_digital_port *intel_dig_port;
271419df918dSFrançois Tigeot struct intel_encoder *intel_encoder;
271519df918dSFrançois Tigeot struct drm_encoder *encoder;
27161e12ee3bSFrançois Tigeot bool init_hdmi, init_dp, init_lspcon = false;
2717c0e85e96SFrançois Tigeot int max_lanes;
2718c0e85e96SFrançois Tigeot
2719c0e85e96SFrançois Tigeot if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2720c0e85e96SFrançois Tigeot switch (port) {
2721c0e85e96SFrançois Tigeot case PORT_A:
2722c0e85e96SFrançois Tigeot max_lanes = 4;
2723c0e85e96SFrançois Tigeot break;
2724c0e85e96SFrançois Tigeot case PORT_E:
2725c0e85e96SFrançois Tigeot max_lanes = 0;
2726c0e85e96SFrançois Tigeot break;
2727c0e85e96SFrançois Tigeot default:
2728c0e85e96SFrançois Tigeot max_lanes = 4;
2729c0e85e96SFrançois Tigeot break;
2730c0e85e96SFrançois Tigeot }
2731c0e85e96SFrançois Tigeot } else {
2732c0e85e96SFrançois Tigeot switch (port) {
2733c0e85e96SFrançois Tigeot case PORT_A:
2734c0e85e96SFrançois Tigeot max_lanes = 2;
2735c0e85e96SFrançois Tigeot break;
2736c0e85e96SFrançois Tigeot case PORT_E:
2737c0e85e96SFrançois Tigeot max_lanes = 2;
2738c0e85e96SFrançois Tigeot break;
2739c0e85e96SFrançois Tigeot default:
2740c0e85e96SFrançois Tigeot max_lanes = 4;
2741c0e85e96SFrançois Tigeot break;
2742c0e85e96SFrançois Tigeot }
2743c0e85e96SFrançois Tigeot }
274419df918dSFrançois Tigeot
27459edbd4a0SFrançois Tigeot init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
27469edbd4a0SFrançois Tigeot dev_priv->vbt.ddi_port_info[port].supports_hdmi);
27479edbd4a0SFrançois Tigeot init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
27481e12ee3bSFrançois Tigeot
27491e12ee3bSFrançois Tigeot if (intel_bios_is_lspcon_present(dev_priv, port)) {
27501e12ee3bSFrançois Tigeot /*
27511e12ee3bSFrançois Tigeot * Lspcon device needs to be driven with DP connector
27521e12ee3bSFrançois Tigeot * with special detection sequence. So make sure DP
27531e12ee3bSFrançois Tigeot * is initialized before lspcon.
27541e12ee3bSFrançois Tigeot */
27551e12ee3bSFrançois Tigeot init_dp = true;
27561e12ee3bSFrançois Tigeot init_lspcon = true;
27571e12ee3bSFrançois Tigeot init_hdmi = false;
27581e12ee3bSFrançois Tigeot DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
27591e12ee3bSFrançois Tigeot }
27601e12ee3bSFrançois Tigeot
27619edbd4a0SFrançois Tigeot if (!init_dp && !init_hdmi) {
2762a05eeebfSFrançois Tigeot DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
27639edbd4a0SFrançois Tigeot port_name(port));
2764a05eeebfSFrançois Tigeot return;
27659edbd4a0SFrançois Tigeot }
27669edbd4a0SFrançois Tigeot
27679edbd4a0SFrançois Tigeot intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
276819df918dSFrançois Tigeot if (!intel_dig_port)
276919df918dSFrançois Tigeot return;
277019df918dSFrançois Tigeot
277119df918dSFrançois Tigeot intel_encoder = &intel_dig_port->base;
277219df918dSFrançois Tigeot encoder = &intel_encoder->base;
277319df918dSFrançois Tigeot
2774a85cb24fSFrançois Tigeot drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
27751487f786SFrançois Tigeot DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
277619df918dSFrançois Tigeot
27778e26cdf6SFrançois Tigeot intel_encoder->compute_config = intel_ddi_compute_config;
277819df918dSFrançois Tigeot intel_encoder->enable = intel_enable_ddi;
2779a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv))
27801487f786SFrançois Tigeot intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
278119df918dSFrançois Tigeot intel_encoder->pre_enable = intel_ddi_pre_enable;
278219df918dSFrançois Tigeot intel_encoder->disable = intel_disable_ddi;
278319df918dSFrançois Tigeot intel_encoder->post_disable = intel_ddi_post_disable;
278419df918dSFrançois Tigeot intel_encoder->get_hw_state = intel_ddi_get_hw_state;
27855d0b1887SFrançois Tigeot intel_encoder->get_config = intel_ddi_get_config;
2786c0e85e96SFrançois Tigeot intel_encoder->suspend = intel_dp_encoder_suspend;
2787a85cb24fSFrançois Tigeot intel_encoder->get_power_domains = intel_ddi_get_power_domains;
278819df918dSFrançois Tigeot
278919df918dSFrançois Tigeot intel_dig_port->port = port;
27905d0b1887SFrançois Tigeot intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
27915d0b1887SFrançois Tigeot (DDI_BUF_PORT_REVERSAL |
27925d0b1887SFrançois Tigeot DDI_A_4_LANES);
279319df918dSFrançois Tigeot
2794a85cb24fSFrançois Tigeot switch (port) {
2795a85cb24fSFrançois Tigeot case PORT_A:
2796a85cb24fSFrançois Tigeot intel_dig_port->ddi_io_power_domain =
2797a85cb24fSFrançois Tigeot POWER_DOMAIN_PORT_DDI_A_IO;
2798a85cb24fSFrançois Tigeot break;
2799a85cb24fSFrançois Tigeot case PORT_B:
2800a85cb24fSFrançois Tigeot intel_dig_port->ddi_io_power_domain =
2801a85cb24fSFrançois Tigeot POWER_DOMAIN_PORT_DDI_B_IO;
2802a85cb24fSFrançois Tigeot break;
2803a85cb24fSFrançois Tigeot case PORT_C:
2804a85cb24fSFrançois Tigeot intel_dig_port->ddi_io_power_domain =
2805a85cb24fSFrançois Tigeot POWER_DOMAIN_PORT_DDI_C_IO;
2806a85cb24fSFrançois Tigeot break;
2807a85cb24fSFrançois Tigeot case PORT_D:
2808a85cb24fSFrançois Tigeot intel_dig_port->ddi_io_power_domain =
2809a85cb24fSFrançois Tigeot POWER_DOMAIN_PORT_DDI_D_IO;
2810a85cb24fSFrançois Tigeot break;
2811a85cb24fSFrançois Tigeot case PORT_E:
2812a85cb24fSFrançois Tigeot intel_dig_port->ddi_io_power_domain =
2813a85cb24fSFrançois Tigeot POWER_DOMAIN_PORT_DDI_E_IO;
2814a85cb24fSFrançois Tigeot break;
2815a85cb24fSFrançois Tigeot default:
2816a85cb24fSFrançois Tigeot MISSING_CASE(port);
2817a85cb24fSFrançois Tigeot }
2818a85cb24fSFrançois Tigeot
2819aee94f86SFrançois Tigeot /*
2820aee94f86SFrançois Tigeot * Bspec says that DDI_A_4_LANES is the only supported configuration
2821aee94f86SFrançois Tigeot * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2822aee94f86SFrançois Tigeot * wasn't lit up at boot. Force this bit on in our internal
2823aee94f86SFrançois Tigeot * configuration so that we use the proper lane count for our
2824aee94f86SFrançois Tigeot * calculations.
2825aee94f86SFrançois Tigeot */
2826a85cb24fSFrançois Tigeot if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2827aee94f86SFrançois Tigeot if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2828aee94f86SFrançois Tigeot DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2829aee94f86SFrançois Tigeot intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2830c0e85e96SFrançois Tigeot max_lanes = 4;
2831aee94f86SFrançois Tigeot }
2832aee94f86SFrançois Tigeot }
2833aee94f86SFrançois Tigeot
2834c0e85e96SFrançois Tigeot intel_dig_port->max_lanes = max_lanes;
2835c0e85e96SFrançois Tigeot
283619df918dSFrançois Tigeot intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2837a85cb24fSFrançois Tigeot intel_encoder->power_domain = intel_port_to_power_domain(port);
28381e12ee3bSFrançois Tigeot intel_encoder->port = port;
283919df918dSFrançois Tigeot intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2840ba55f2f5SFrançois Tigeot intel_encoder->cloneable = 0;
284119df918dSFrançois Tigeot
2842*3f2dd94aSFrançois Tigeot intel_infoframe_init(intel_dig_port);
2843*3f2dd94aSFrançois Tigeot
284424edb884SFrançois Tigeot if (init_dp) {
284524edb884SFrançois Tigeot if (!intel_ddi_init_dp_connector(intel_dig_port))
284624edb884SFrançois Tigeot goto err;
284724edb884SFrançois Tigeot
284824edb884SFrançois Tigeot intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2849a05eeebfSFrançois Tigeot dev_priv->hotplug.irq_port[port] = intel_dig_port;
285024edb884SFrançois Tigeot }
28519edbd4a0SFrançois Tigeot
28529edbd4a0SFrançois Tigeot /* In theory we don't need the encoder->type check, but leave it just in
28539edbd4a0SFrançois Tigeot * case we have some really bad VBTs... */
285424edb884SFrançois Tigeot if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
285524edb884SFrançois Tigeot if (!intel_ddi_init_hdmi_connector(intel_dig_port))
285624edb884SFrançois Tigeot goto err;
285724edb884SFrançois Tigeot }
28589edbd4a0SFrançois Tigeot
28591e12ee3bSFrançois Tigeot if (init_lspcon) {
28601e12ee3bSFrançois Tigeot if (lspcon_init(intel_dig_port))
28611e12ee3bSFrançois Tigeot /* TODO: handle hdmi info frame part */
28621e12ee3bSFrançois Tigeot DRM_DEBUG_KMS("LSPCON init success on port %c\n",
28631e12ee3bSFrançois Tigeot port_name(port));
28641e12ee3bSFrançois Tigeot else
28651e12ee3bSFrançois Tigeot /*
28661e12ee3bSFrançois Tigeot * LSPCON init faied, but DP init was success, so
28671e12ee3bSFrançois Tigeot * lets try to drive as DP++ port.
28681e12ee3bSFrançois Tigeot */
28691e12ee3bSFrançois Tigeot DRM_ERROR("LSPCON init failed on port %c\n",
28701e12ee3bSFrançois Tigeot port_name(port));
28711e12ee3bSFrançois Tigeot }
28721e12ee3bSFrançois Tigeot
287324edb884SFrançois Tigeot return;
287424edb884SFrançois Tigeot
287524edb884SFrançois Tigeot err:
28765d0b1887SFrançois Tigeot drm_encoder_cleanup(encoder);
28775d0b1887SFrançois Tigeot kfree(intel_dig_port);
28785d0b1887SFrançois Tigeot }
2879