1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 31 struct ddi_buf_trans { 32 u32 trans1; /* balance leg enable, de-emph level */ 33 u32 trans2; /* vref sel, vswing */ 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 35 }; 36 37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 38 * them for both DP and FDI transports, allowing those ports to 39 * automatically adapt to HDMI connections as well 40 */ 41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 42 { 0x00FFFFFF, 0x0006000E, 0x0 }, 43 { 0x00D75FFF, 0x0005000A, 0x0 }, 44 { 0x00C30FFF, 0x00040006, 0x0 }, 45 { 0x80AAAFFF, 0x000B0000, 0x0 }, 46 { 0x00FFFFFF, 0x0005000A, 0x0 }, 47 { 0x00D75FFF, 0x000C0004, 0x0 }, 48 { 0x80C30FFF, 0x000B0000, 0x0 }, 49 { 0x00FFFFFF, 0x00040006, 0x0 }, 50 { 0x80D75FFF, 0x000B0000, 0x0 }, 51 }; 52 53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 54 { 0x00FFFFFF, 0x0007000E, 0x0 }, 55 { 0x00D75FFF, 0x000F000A, 0x0 }, 56 { 0x00C30FFF, 0x00060006, 0x0 }, 57 { 0x00AAAFFF, 0x001E0000, 0x0 }, 58 { 0x00FFFFFF, 0x000F000A, 0x0 }, 59 { 0x00D75FFF, 0x00160004, 0x0 }, 60 { 0x00C30FFF, 0x001E0000, 0x0 }, 61 { 0x00FFFFFF, 0x00060006, 0x0 }, 62 { 0x00D75FFF, 0x001E0000, 0x0 }, 63 }; 64 65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 66 /* Idx NT mV d T mV d db */ 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 79 }; 80 81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 82 { 0x00FFFFFF, 0x00000012, 0x0 }, 83 { 0x00EBAFFF, 0x00020011, 0x0 }, 84 { 0x00C71FFF, 0x0006000F, 0x0 }, 85 { 0x00AAAFFF, 0x000E000A, 0x0 }, 86 { 0x00FFFFFF, 0x00020011, 0x0 }, 87 { 0x00DB6FFF, 0x0005000F, 0x0 }, 88 { 0x00BEEFFF, 0x000A000C, 0x0 }, 89 { 0x00FFFFFF, 0x0005000F, 0x0 }, 90 { 0x00DB6FFF, 0x000A000C, 0x0 }, 91 }; 92 93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 94 { 0x00FFFFFF, 0x0007000E, 0x0 }, 95 { 0x00D75FFF, 0x000E000A, 0x0 }, 96 { 0x00BEFFFF, 0x00140006, 0x0 }, 97 { 0x80B2CFFF, 0x001B0002, 0x0 }, 98 { 0x00FFFFFF, 0x000E000A, 0x0 }, 99 { 0x00DB6FFF, 0x00160005, 0x0 }, 100 { 0x80C71FFF, 0x001A0002, 0x0 }, 101 { 0x00F7DFFF, 0x00180004, 0x0 }, 102 { 0x80D75FFF, 0x001B0002, 0x0 }, 103 }; 104 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 106 { 0x00FFFFFF, 0x0001000E, 0x0 }, 107 { 0x00D75FFF, 0x0004000A, 0x0 }, 108 { 0x00C30FFF, 0x00070006, 0x0 }, 109 { 0x00AAAFFF, 0x000C0000, 0x0 }, 110 { 0x00FFFFFF, 0x0004000A, 0x0 }, 111 { 0x00D75FFF, 0x00090004, 0x0 }, 112 { 0x00C30FFF, 0x000C0000, 0x0 }, 113 { 0x00FFFFFF, 0x00070006, 0x0 }, 114 { 0x00D75FFF, 0x000C0000, 0x0 }, 115 }; 116 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 118 /* Idx NT mV d T mV df db */ 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 129 }; 130 131 /* Skylake H and S */ 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 133 { 0x00002016, 0x000000A0, 0x0 }, 134 { 0x00005012, 0x0000009B, 0x0 }, 135 { 0x00007011, 0x00000088, 0x0 }, 136 { 0x80009010, 0x000000C0, 0x1 }, 137 { 0x00002016, 0x0000009B, 0x0 }, 138 { 0x00005012, 0x00000088, 0x0 }, 139 { 0x80007011, 0x000000C0, 0x1 }, 140 { 0x00002016, 0x000000DF, 0x0 }, 141 { 0x80005012, 0x000000C0, 0x1 }, 142 }; 143 144 /* Skylake U */ 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 146 { 0x0000201B, 0x000000A2, 0x0 }, 147 { 0x00005012, 0x00000088, 0x0 }, 148 { 0x80007011, 0x000000CD, 0x1 }, 149 { 0x80009010, 0x000000C0, 0x1 }, 150 { 0x0000201B, 0x0000009D, 0x0 }, 151 { 0x80005012, 0x000000C0, 0x1 }, 152 { 0x80007011, 0x000000C0, 0x1 }, 153 { 0x00002016, 0x00000088, 0x0 }, 154 { 0x80005012, 0x000000C0, 0x1 }, 155 }; 156 157 /* Skylake Y */ 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 159 { 0x00000018, 0x000000A2, 0x0 }, 160 { 0x00005012, 0x00000088, 0x0 }, 161 { 0x80007011, 0x000000CD, 0x3 }, 162 { 0x80009010, 0x000000C0, 0x3 }, 163 { 0x00000018, 0x0000009D, 0x0 }, 164 { 0x80005012, 0x000000C0, 0x3 }, 165 { 0x80007011, 0x000000C0, 0x3 }, 166 { 0x00000018, 0x00000088, 0x0 }, 167 { 0x80005012, 0x000000C0, 0x3 }, 168 }; 169 170 /* 171 * Skylake H and S 172 * eDP 1.4 low vswing translation parameters 173 */ 174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 175 { 0x00000018, 0x000000A8, 0x0 }, 176 { 0x00004013, 0x000000A9, 0x0 }, 177 { 0x00007011, 0x000000A2, 0x0 }, 178 { 0x00009010, 0x0000009C, 0x0 }, 179 { 0x00000018, 0x000000A9, 0x0 }, 180 { 0x00006013, 0x000000A2, 0x0 }, 181 { 0x00007011, 0x000000A6, 0x0 }, 182 { 0x00000018, 0x000000AB, 0x0 }, 183 { 0x00007013, 0x0000009F, 0x0 }, 184 { 0x00000018, 0x000000DF, 0x0 }, 185 }; 186 187 /* 188 * Skylake U 189 * eDP 1.4 low vswing translation parameters 190 */ 191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 192 { 0x00000018, 0x000000A8, 0x0 }, 193 { 0x00004013, 0x000000A9, 0x0 }, 194 { 0x00007011, 0x000000A2, 0x0 }, 195 { 0x00009010, 0x0000009C, 0x0 }, 196 { 0x00000018, 0x000000A9, 0x0 }, 197 { 0x00006013, 0x000000A2, 0x0 }, 198 { 0x00007011, 0x000000A6, 0x0 }, 199 { 0x00002016, 0x000000AB, 0x0 }, 200 { 0x00005013, 0x0000009F, 0x0 }, 201 { 0x00000018, 0x000000DF, 0x0 }, 202 }; 203 204 /* 205 * Skylake Y 206 * eDP 1.4 low vswing translation parameters 207 */ 208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 209 { 0x00000018, 0x000000A8, 0x0 }, 210 { 0x00004013, 0x000000AB, 0x0 }, 211 { 0x00007011, 0x000000A4, 0x0 }, 212 { 0x00009010, 0x000000DF, 0x0 }, 213 { 0x00000018, 0x000000AA, 0x0 }, 214 { 0x00006013, 0x000000A4, 0x0 }, 215 { 0x00007011, 0x0000009D, 0x0 }, 216 { 0x00000018, 0x000000A0, 0x0 }, 217 { 0x00006012, 0x000000DF, 0x0 }, 218 { 0x00000018, 0x0000008A, 0x0 }, 219 }; 220 221 /* Skylake U, H and S */ 222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 223 { 0x00000018, 0x000000AC, 0x0 }, 224 { 0x00005012, 0x0000009D, 0x0 }, 225 { 0x00007011, 0x00000088, 0x0 }, 226 { 0x00000018, 0x000000A1, 0x0 }, 227 { 0x00000018, 0x00000098, 0x0 }, 228 { 0x00004013, 0x00000088, 0x0 }, 229 { 0x80006012, 0x000000CD, 0x1 }, 230 { 0x00000018, 0x000000DF, 0x0 }, 231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 232 { 0x80003015, 0x000000C0, 0x1 }, 233 { 0x80000018, 0x000000C0, 0x1 }, 234 }; 235 236 /* Skylake Y */ 237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 238 { 0x00000018, 0x000000A1, 0x0 }, 239 { 0x00005012, 0x000000DF, 0x0 }, 240 { 0x80007011, 0x000000CB, 0x3 }, 241 { 0x00000018, 0x000000A4, 0x0 }, 242 { 0x00000018, 0x0000009D, 0x0 }, 243 { 0x00004013, 0x00000080, 0x0 }, 244 { 0x80006013, 0x000000C0, 0x3 }, 245 { 0x00000018, 0x0000008A, 0x0 }, 246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 247 { 0x80003015, 0x000000C0, 0x3 }, 248 { 0x80000018, 0x000000C0, 0x3 }, 249 }; 250 251 struct bxt_ddi_buf_trans { 252 u32 margin; /* swing value */ 253 u32 scale; /* scale value */ 254 u32 enable; /* scale enable */ 255 u32 deemphasis; 256 bool default_index; /* true if the entry represents default value */ 257 }; 258 259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 260 /* Idx NT mV diff db */ 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ 262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ 264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ 268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 271 }; 272 273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 274 /* Idx NT mV diff db */ 275 { 26, 0, 0, 128, false }, /* 0: 200 0 */ 276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ 277 { 48, 0, 0, 96, false }, /* 2: 200 4 */ 278 { 54, 0, 0, 69, false }, /* 3: 200 6 */ 279 { 32, 0, 0, 128, false }, /* 4: 250 0 */ 280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ 281 { 54, 0, 0, 85, false }, /* 6: 250 4 */ 282 { 43, 0, 0, 128, false }, /* 7: 300 0 */ 283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ 284 { 48, 0, 0, 128, false }, /* 9: 300 0 */ 285 }; 286 287 /* BSpec has 2 recommended values - entries 0 and 8. 288 * Using the entry with higher vswing. 289 */ 290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 291 /* Idx NT mV diff db */ 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ 293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ 295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ 299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 302 }; 303 304 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, 305 u32 level, enum port port, int type); 306 307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, 308 struct intel_digital_port **dig_port, 309 enum port *port) 310 { 311 struct drm_encoder *encoder = &intel_encoder->base; 312 313 switch (intel_encoder->type) { 314 case INTEL_OUTPUT_DP_MST: 315 *dig_port = enc_to_mst(encoder)->primary; 316 *port = (*dig_port)->port; 317 break; 318 default: 319 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); 320 /* fallthrough and treat as unknown */ 321 case INTEL_OUTPUT_DISPLAYPORT: 322 case INTEL_OUTPUT_EDP: 323 case INTEL_OUTPUT_HDMI: 324 case INTEL_OUTPUT_UNKNOWN: 325 *dig_port = enc_to_dig_port(encoder); 326 *port = (*dig_port)->port; 327 break; 328 case INTEL_OUTPUT_ANALOG: 329 *dig_port = NULL; 330 *port = PORT_E; 331 break; 332 } 333 } 334 335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 336 { 337 struct intel_digital_port *dig_port; 338 enum port port; 339 340 ddi_get_encoder_port(intel_encoder, &dig_port, &port); 341 342 return port; 343 } 344 345 static const struct ddi_buf_trans * 346 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 347 { 348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 350 return skl_y_ddi_translations_dp; 351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { 352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 353 return skl_u_ddi_translations_dp; 354 } else { 355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 356 return skl_ddi_translations_dp; 357 } 358 } 359 360 static const struct ddi_buf_trans * 361 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 362 { 363 if (dev_priv->vbt.edp.low_vswing) { 364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 366 return skl_y_ddi_translations_edp; 367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { 368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 369 return skl_u_ddi_translations_edp; 370 } else { 371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 372 return skl_ddi_translations_edp; 373 } 374 } 375 376 return skl_get_buf_trans_dp(dev_priv, n_entries); 377 } 378 379 static const struct ddi_buf_trans * 380 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 381 { 382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 384 return skl_y_ddi_translations_hdmi; 385 } else { 386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 387 return skl_ddi_translations_hdmi; 388 } 389 } 390 391 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 392 { 393 int n_hdmi_entries; 394 int hdmi_level; 395 int hdmi_default_entry; 396 397 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 398 399 if (IS_BROXTON(dev_priv)) 400 return hdmi_level; 401 402 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 403 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 404 hdmi_default_entry = 8; 405 } else if (IS_BROADWELL(dev_priv)) { 406 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 407 hdmi_default_entry = 7; 408 } else if (IS_HASWELL(dev_priv)) { 409 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 410 hdmi_default_entry = 6; 411 } else { 412 WARN(1, "ddi translation table missing\n"); 413 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 414 hdmi_default_entry = 7; 415 } 416 417 /* Choose a good default if VBT is badly populated */ 418 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 419 hdmi_level >= n_hdmi_entries) 420 hdmi_level = hdmi_default_entry; 421 422 return hdmi_level; 423 } 424 425 /* 426 * Starting with Haswell, DDI port buffers must be programmed with correct 427 * values in advance. The buffer values are different for FDI and DP modes, 428 * but the HDMI/DVI fields are shared among those. So we program the DDI 429 * in either FDI or DP modes only, as HDMI connections will work with both 430 * of those 431 */ 432 void intel_prepare_ddi_buffer(struct intel_encoder *encoder) 433 { 434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 435 u32 iboost_bit = 0; 436 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, 437 size; 438 int hdmi_level; 439 enum port port; 440 const struct ddi_buf_trans *ddi_translations_fdi; 441 const struct ddi_buf_trans *ddi_translations_dp; 442 const struct ddi_buf_trans *ddi_translations_edp; 443 const struct ddi_buf_trans *ddi_translations_hdmi; 444 const struct ddi_buf_trans *ddi_translations; 445 446 port = intel_ddi_get_encoder_port(encoder); 447 hdmi_level = intel_ddi_hdmi_level(dev_priv, port); 448 449 if (IS_BROXTON(dev_priv)) { 450 if (encoder->type != INTEL_OUTPUT_HDMI) 451 return; 452 453 /* Vswing programming for HDMI */ 454 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port, 455 INTEL_OUTPUT_HDMI); 456 return; 457 } 458 459 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 460 ddi_translations_fdi = NULL; 461 ddi_translations_dp = 462 skl_get_buf_trans_dp(dev_priv, &n_dp_entries); 463 ddi_translations_edp = 464 skl_get_buf_trans_edp(dev_priv, &n_edp_entries); 465 ddi_translations_hdmi = 466 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 467 /* If we're boosting the current, set bit 31 of trans1 */ 468 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || 469 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 470 iboost_bit = 1<<31; 471 472 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && 473 port != PORT_A && port != PORT_E && 474 n_edp_entries > 9)) 475 n_edp_entries = 9; 476 } else if (IS_BROADWELL(dev_priv)) { 477 ddi_translations_fdi = bdw_ddi_translations_fdi; 478 ddi_translations_dp = bdw_ddi_translations_dp; 479 480 if (dev_priv->vbt.edp.low_vswing) { 481 ddi_translations_edp = bdw_ddi_translations_edp; 482 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 483 } else { 484 ddi_translations_edp = bdw_ddi_translations_dp; 485 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 486 } 487 488 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 489 490 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 491 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 492 } else if (IS_HASWELL(dev_priv)) { 493 ddi_translations_fdi = hsw_ddi_translations_fdi; 494 ddi_translations_dp = hsw_ddi_translations_dp; 495 ddi_translations_edp = hsw_ddi_translations_dp; 496 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 497 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 498 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 499 } else { 500 WARN(1, "ddi translation table missing\n"); 501 ddi_translations_edp = bdw_ddi_translations_dp; 502 ddi_translations_fdi = bdw_ddi_translations_fdi; 503 ddi_translations_dp = bdw_ddi_translations_dp; 504 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 505 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 506 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 507 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 508 } 509 510 switch (encoder->type) { 511 case INTEL_OUTPUT_EDP: 512 ddi_translations = ddi_translations_edp; 513 size = n_edp_entries; 514 break; 515 case INTEL_OUTPUT_DISPLAYPORT: 516 case INTEL_OUTPUT_HDMI: 517 ddi_translations = ddi_translations_dp; 518 size = n_dp_entries; 519 break; 520 case INTEL_OUTPUT_ANALOG: 521 ddi_translations = ddi_translations_fdi; 522 size = n_dp_entries; 523 break; 524 default: 525 BUG(); 526 } 527 528 for (i = 0; i < size; i++) { 529 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 530 ddi_translations[i].trans1 | iboost_bit); 531 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 532 ddi_translations[i].trans2); 533 } 534 535 if (encoder->type != INTEL_OUTPUT_HDMI) 536 return; 537 538 /* Entry 9 is for HDMI: */ 539 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 540 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); 541 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 542 ddi_translations_hdmi[hdmi_level].trans2); 543 } 544 545 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 546 enum port port) 547 { 548 i915_reg_t reg = DDI_BUF_CTL(port); 549 int i; 550 551 for (i = 0; i < 16; i++) { 552 udelay(1); 553 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 554 return; 555 } 556 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 557 } 558 559 /* Starting with Haswell, different DDI ports can work in FDI mode for 560 * connection to the PCH-located connectors. For this, it is necessary to train 561 * both the DDI port and PCH receiver for the desired DDI buffer settings. 562 * 563 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 564 * please note that when FDI mode is active on DDI E, it shares 2 lines with 565 * DDI A (which is used for eDP) 566 */ 567 568 void hsw_fdi_link_train(struct drm_crtc *crtc) 569 { 570 struct drm_device *dev = crtc->dev; 571 struct drm_i915_private *dev_priv = dev->dev_private; 572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 573 struct intel_encoder *encoder; 574 u32 temp, i, rx_ctl_val; 575 576 for_each_encoder_on_crtc(dev, crtc, encoder) { 577 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); 578 intel_prepare_ddi_buffer(encoder); 579 } 580 581 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 582 * mode set "sequence for CRT port" document: 583 * - TP1 to TP2 time with the default value 584 * - FDI delay to 90h 585 * 586 * WaFDIAutoLinkSetTimingOverrride:hsw 587 */ 588 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 589 FDI_RX_PWRDN_LANE0_VAL(2) | 590 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 591 592 /* Enable the PCH Receiver FDI PLL */ 593 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 594 FDI_RX_PLL_ENABLE | 595 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 596 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 597 POSTING_READ(FDI_RX_CTL(PIPE_A)); 598 udelay(220); 599 600 /* Switch from Rawclk to PCDclk */ 601 rx_ctl_val |= FDI_PCDCLK; 602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 603 604 /* Configure Port Clock Select */ 605 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 606 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 607 608 /* Start the training iterating through available voltages and emphasis, 609 * testing each value twice. */ 610 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 611 /* Configure DP_TP_CTL with auto-training */ 612 I915_WRITE(DP_TP_CTL(PORT_E), 613 DP_TP_CTL_FDI_AUTOTRAIN | 614 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 615 DP_TP_CTL_LINK_TRAIN_PAT1 | 616 DP_TP_CTL_ENABLE); 617 618 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 619 * DDI E does not support port reversal, the functionality is 620 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 621 * port reversal bit */ 622 I915_WRITE(DDI_BUF_CTL(PORT_E), 623 DDI_BUF_CTL_ENABLE | 624 ((intel_crtc->config->fdi_lanes - 1) << 1) | 625 DDI_BUF_TRANS_SELECT(i / 2)); 626 POSTING_READ(DDI_BUF_CTL(PORT_E)); 627 628 udelay(600); 629 630 /* Program PCH FDI Receiver TU */ 631 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 632 633 /* Enable PCH FDI Receiver with auto-training */ 634 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 635 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 636 POSTING_READ(FDI_RX_CTL(PIPE_A)); 637 638 /* Wait for FDI receiver lane calibration */ 639 udelay(30); 640 641 /* Unset FDI_RX_MISC pwrdn lanes */ 642 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 643 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 644 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 645 POSTING_READ(FDI_RX_MISC(PIPE_A)); 646 647 /* Wait for FDI auto training time */ 648 udelay(5); 649 650 temp = I915_READ(DP_TP_STATUS(PORT_E)); 651 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 652 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 653 break; 654 } 655 656 /* 657 * Leave things enabled even if we failed to train FDI. 658 * Results in less fireworks from the state checker. 659 */ 660 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 661 DRM_ERROR("FDI link training failed!\n"); 662 break; 663 } 664 665 rx_ctl_val &= ~FDI_RX_ENABLE; 666 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 667 POSTING_READ(FDI_RX_CTL(PIPE_A)); 668 669 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 670 temp &= ~DDI_BUF_CTL_ENABLE; 671 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 672 POSTING_READ(DDI_BUF_CTL(PORT_E)); 673 674 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 675 temp = I915_READ(DP_TP_CTL(PORT_E)); 676 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 677 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 678 I915_WRITE(DP_TP_CTL(PORT_E), temp); 679 POSTING_READ(DP_TP_CTL(PORT_E)); 680 681 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 682 683 /* Reset FDI_RX_MISC pwrdn lanes */ 684 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 685 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 686 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 687 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 688 POSTING_READ(FDI_RX_MISC(PIPE_A)); 689 } 690 691 /* Enable normal pixel sending for FDI */ 692 I915_WRITE(DP_TP_CTL(PORT_E), 693 DP_TP_CTL_FDI_AUTOTRAIN | 694 DP_TP_CTL_LINK_TRAIN_NORMAL | 695 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 696 DP_TP_CTL_ENABLE); 697 } 698 699 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 700 { 701 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 702 struct intel_digital_port *intel_dig_port = 703 enc_to_dig_port(&encoder->base); 704 705 intel_dp->DP = intel_dig_port->saved_port_bits | 706 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 707 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 708 } 709 710 static struct intel_encoder * 711 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 712 { 713 struct drm_device *dev = crtc->dev; 714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 715 struct intel_encoder *intel_encoder, *ret = NULL; 716 int num_encoders = 0; 717 718 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 719 ret = intel_encoder; 720 num_encoders++; 721 } 722 723 if (num_encoders != 1) 724 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 725 pipe_name(intel_crtc->pipe)); 726 727 BUG_ON(ret == NULL); 728 return ret; 729 } 730 731 struct intel_encoder * 732 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 733 { 734 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 735 struct intel_encoder *ret = NULL; 736 struct drm_atomic_state *state; 737 struct drm_connector *connector; 738 struct drm_connector_state *connector_state; 739 int num_encoders = 0; 740 int i; 741 742 state = crtc_state->base.state; 743 744 for_each_connector_in_state(state, connector, connector_state, i) { 745 if (connector_state->crtc != crtc_state->base.crtc) 746 continue; 747 748 ret = to_intel_encoder(connector_state->best_encoder); 749 num_encoders++; 750 } 751 752 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 753 pipe_name(crtc->pipe)); 754 755 BUG_ON(ret == NULL); 756 return ret; 757 } 758 759 #define LC_FREQ 2700 760 761 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 762 i915_reg_t reg) 763 { 764 int refclk = LC_FREQ; 765 int n, p, r; 766 u32 wrpll; 767 768 wrpll = I915_READ(reg); 769 switch (wrpll & WRPLL_PLL_REF_MASK) { 770 case WRPLL_PLL_SSC: 771 case WRPLL_PLL_NON_SSC: 772 /* 773 * We could calculate spread here, but our checking 774 * code only cares about 5% accuracy, and spread is a max of 775 * 0.5% downspread. 776 */ 777 refclk = 135; 778 break; 779 case WRPLL_PLL_LCPLL: 780 refclk = LC_FREQ; 781 break; 782 default: 783 WARN(1, "bad wrpll refclk\n"); 784 return 0; 785 } 786 787 r = wrpll & WRPLL_DIVIDER_REF_MASK; 788 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 789 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 790 791 /* Convert to KHz, p & r have a fixed point portion */ 792 return (refclk * n * 100) / (p * r); 793 } 794 795 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 796 uint32_t dpll) 797 { 798 i915_reg_t cfgcr1_reg, cfgcr2_reg; 799 uint32_t cfgcr1_val, cfgcr2_val; 800 uint32_t p0, p1, p2, dco_freq; 801 802 cfgcr1_reg = DPLL_CFGCR1(dpll); 803 cfgcr2_reg = DPLL_CFGCR2(dpll); 804 805 cfgcr1_val = I915_READ(cfgcr1_reg); 806 cfgcr2_val = I915_READ(cfgcr2_reg); 807 808 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 809 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 810 811 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 812 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 813 else 814 p1 = 1; 815 816 817 switch (p0) { 818 case DPLL_CFGCR2_PDIV_1: 819 p0 = 1; 820 break; 821 case DPLL_CFGCR2_PDIV_2: 822 p0 = 2; 823 break; 824 case DPLL_CFGCR2_PDIV_3: 825 p0 = 3; 826 break; 827 case DPLL_CFGCR2_PDIV_7: 828 p0 = 7; 829 break; 830 } 831 832 switch (p2) { 833 case DPLL_CFGCR2_KDIV_5: 834 p2 = 5; 835 break; 836 case DPLL_CFGCR2_KDIV_2: 837 p2 = 2; 838 break; 839 case DPLL_CFGCR2_KDIV_3: 840 p2 = 3; 841 break; 842 case DPLL_CFGCR2_KDIV_1: 843 p2 = 1; 844 break; 845 } 846 847 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 848 849 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 850 1000) / 0x8000; 851 852 return dco_freq / (p0 * p1 * p2 * 5); 853 } 854 855 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 856 { 857 int dotclock; 858 859 if (pipe_config->has_pch_encoder) 860 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 861 &pipe_config->fdi_m_n); 862 else if (pipe_config->has_dp_encoder) 863 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 864 &pipe_config->dp_m_n); 865 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 866 dotclock = pipe_config->port_clock * 2 / 3; 867 else 868 dotclock = pipe_config->port_clock; 869 870 if (pipe_config->pixel_multiplier) 871 dotclock /= pipe_config->pixel_multiplier; 872 873 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 874 } 875 876 static void skl_ddi_clock_get(struct intel_encoder *encoder, 877 struct intel_crtc_state *pipe_config) 878 { 879 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 880 int link_clock = 0; 881 uint32_t dpll_ctl1, dpll; 882 883 dpll = pipe_config->ddi_pll_sel; 884 885 dpll_ctl1 = I915_READ(DPLL_CTRL1); 886 887 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 888 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 889 } else { 890 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 891 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 892 893 switch (link_clock) { 894 case DPLL_CTRL1_LINK_RATE_810: 895 link_clock = 81000; 896 break; 897 case DPLL_CTRL1_LINK_RATE_1080: 898 link_clock = 108000; 899 break; 900 case DPLL_CTRL1_LINK_RATE_1350: 901 link_clock = 135000; 902 break; 903 case DPLL_CTRL1_LINK_RATE_1620: 904 link_clock = 162000; 905 break; 906 case DPLL_CTRL1_LINK_RATE_2160: 907 link_clock = 216000; 908 break; 909 case DPLL_CTRL1_LINK_RATE_2700: 910 link_clock = 270000; 911 break; 912 default: 913 WARN(1, "Unsupported link rate\n"); 914 break; 915 } 916 link_clock *= 2; 917 } 918 919 pipe_config->port_clock = link_clock; 920 921 ddi_dotclock_get(pipe_config); 922 } 923 924 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 925 struct intel_crtc_state *pipe_config) 926 { 927 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 928 int link_clock = 0; 929 u32 val, pll; 930 931 val = pipe_config->ddi_pll_sel; 932 switch (val & PORT_CLK_SEL_MASK) { 933 case PORT_CLK_SEL_LCPLL_810: 934 link_clock = 81000; 935 break; 936 case PORT_CLK_SEL_LCPLL_1350: 937 link_clock = 135000; 938 break; 939 case PORT_CLK_SEL_LCPLL_2700: 940 link_clock = 270000; 941 break; 942 case PORT_CLK_SEL_WRPLL1: 943 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 944 break; 945 case PORT_CLK_SEL_WRPLL2: 946 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 947 break; 948 case PORT_CLK_SEL_SPLL: 949 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 950 if (pll == SPLL_PLL_FREQ_810MHz) 951 link_clock = 81000; 952 else if (pll == SPLL_PLL_FREQ_1350MHz) 953 link_clock = 135000; 954 else if (pll == SPLL_PLL_FREQ_2700MHz) 955 link_clock = 270000; 956 else { 957 WARN(1, "bad spll freq\n"); 958 return; 959 } 960 break; 961 default: 962 WARN(1, "bad port clock sel\n"); 963 return; 964 } 965 966 pipe_config->port_clock = link_clock * 2; 967 968 ddi_dotclock_get(pipe_config); 969 } 970 971 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 972 enum intel_dpll_id dpll) 973 { 974 struct intel_shared_dpll *pll; 975 struct intel_dpll_hw_state *state; 976 intel_clock_t clock; 977 978 /* For DDI ports we always use a shared PLL. */ 979 if (WARN_ON(dpll == DPLL_ID_PRIVATE)) 980 return 0; 981 982 pll = &dev_priv->shared_dplls[dpll]; 983 state = &pll->config.hw_state; 984 985 clock.m1 = 2; 986 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; 987 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 988 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; 989 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 990 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 991 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 992 993 return chv_calc_dpll_params(100000, &clock); 994 } 995 996 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 997 struct intel_crtc_state *pipe_config) 998 { 999 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1000 enum port port = intel_ddi_get_encoder_port(encoder); 1001 uint32_t dpll = port; 1002 1003 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); 1004 1005 ddi_dotclock_get(pipe_config); 1006 } 1007 1008 void intel_ddi_clock_get(struct intel_encoder *encoder, 1009 struct intel_crtc_state *pipe_config) 1010 { 1011 struct drm_device *dev = encoder->base.dev; 1012 1013 if (INTEL_INFO(dev)->gen <= 8) 1014 hsw_ddi_clock_get(encoder, pipe_config); 1015 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1016 skl_ddi_clock_get(encoder, pipe_config); 1017 else if (IS_BROXTON(dev)) 1018 bxt_ddi_clock_get(encoder, pipe_config); 1019 } 1020 1021 static bool 1022 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 1023 struct intel_crtc_state *crtc_state, 1024 struct intel_encoder *intel_encoder) 1025 { 1026 struct intel_shared_dpll *pll; 1027 1028 pll = intel_get_shared_dpll(intel_crtc, crtc_state, 1029 intel_encoder); 1030 if (!pll) 1031 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1032 pipe_name(intel_crtc->pipe)); 1033 1034 return pll; 1035 } 1036 1037 static bool 1038 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1039 struct intel_crtc_state *crtc_state, 1040 struct intel_encoder *intel_encoder) 1041 { 1042 struct intel_shared_dpll *pll; 1043 1044 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); 1045 if (pll == NULL) { 1046 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1047 pipe_name(intel_crtc->pipe)); 1048 return false; 1049 } 1050 1051 return true; 1052 } 1053 1054 static bool 1055 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 1056 struct intel_crtc_state *crtc_state, 1057 struct intel_encoder *intel_encoder) 1058 { 1059 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); 1060 } 1061 1062 /* 1063 * Tries to find a *shared* PLL for the CRTC and store it in 1064 * intel_crtc->ddi_pll_sel. 1065 * 1066 * For private DPLLs, compute_config() should do the selection for us. This 1067 * function should be folded into compute_config() eventually. 1068 */ 1069 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1070 struct intel_crtc_state *crtc_state) 1071 { 1072 struct drm_device *dev = intel_crtc->base.dev; 1073 struct intel_encoder *intel_encoder = 1074 intel_ddi_get_crtc_new_encoder(crtc_state); 1075 1076 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1077 return skl_ddi_pll_select(intel_crtc, crtc_state, 1078 intel_encoder); 1079 else if (IS_BROXTON(dev)) 1080 return bxt_ddi_pll_select(intel_crtc, crtc_state, 1081 intel_encoder); 1082 else 1083 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1084 intel_encoder); 1085 } 1086 1087 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1088 { 1089 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1091 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1092 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1093 int type = intel_encoder->type; 1094 uint32_t temp; 1095 1096 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1097 WARN_ON(transcoder_is_dsi(cpu_transcoder)); 1098 1099 temp = TRANS_MSA_SYNC_CLK; 1100 switch (intel_crtc->config->pipe_bpp) { 1101 case 18: 1102 temp |= TRANS_MSA_6_BPC; 1103 break; 1104 case 24: 1105 temp |= TRANS_MSA_8_BPC; 1106 break; 1107 case 30: 1108 temp |= TRANS_MSA_10_BPC; 1109 break; 1110 case 36: 1111 temp |= TRANS_MSA_12_BPC; 1112 break; 1113 default: 1114 BUG(); 1115 } 1116 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1117 } 1118 } 1119 1120 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1121 { 1122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1123 struct drm_device *dev = crtc->dev; 1124 struct drm_i915_private *dev_priv = dev->dev_private; 1125 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1126 uint32_t temp; 1127 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1128 if (state == true) 1129 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1130 else 1131 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1132 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1133 } 1134 1135 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1136 { 1137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1138 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1139 struct drm_encoder *encoder = &intel_encoder->base; 1140 struct drm_device *dev = crtc->dev; 1141 struct drm_i915_private *dev_priv = dev->dev_private; 1142 enum i915_pipe pipe = intel_crtc->pipe; 1143 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1144 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1145 int type = intel_encoder->type; 1146 uint32_t temp; 1147 1148 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1149 temp = TRANS_DDI_FUNC_ENABLE; 1150 temp |= TRANS_DDI_SELECT_PORT(port); 1151 1152 switch (intel_crtc->config->pipe_bpp) { 1153 case 18: 1154 temp |= TRANS_DDI_BPC_6; 1155 break; 1156 case 24: 1157 temp |= TRANS_DDI_BPC_8; 1158 break; 1159 case 30: 1160 temp |= TRANS_DDI_BPC_10; 1161 break; 1162 case 36: 1163 temp |= TRANS_DDI_BPC_12; 1164 break; 1165 default: 1166 BUG(); 1167 } 1168 1169 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1170 temp |= TRANS_DDI_PVSYNC; 1171 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1172 temp |= TRANS_DDI_PHSYNC; 1173 1174 if (cpu_transcoder == TRANSCODER_EDP) { 1175 switch (pipe) { 1176 case PIPE_A: 1177 /* On Haswell, can only use the always-on power well for 1178 * eDP when not using the panel fitter, and when not 1179 * using motion blur mitigation (which we don't 1180 * support). */ 1181 if (IS_HASWELL(dev) && 1182 (intel_crtc->config->pch_pfit.enabled || 1183 intel_crtc->config->pch_pfit.force_thru)) 1184 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1185 else 1186 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1187 break; 1188 case PIPE_B: 1189 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1190 break; 1191 case PIPE_C: 1192 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1193 break; 1194 default: 1195 BUG(); 1196 break; 1197 } 1198 } 1199 1200 if (type == INTEL_OUTPUT_HDMI) { 1201 if (intel_crtc->config->has_hdmi_sink) 1202 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1203 else 1204 temp |= TRANS_DDI_MODE_SELECT_DVI; 1205 1206 } else if (type == INTEL_OUTPUT_ANALOG) { 1207 temp |= TRANS_DDI_MODE_SELECT_FDI; 1208 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1209 1210 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1211 type == INTEL_OUTPUT_EDP) { 1212 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1213 1214 if (intel_dp->is_mst) { 1215 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1216 } else 1217 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1218 1219 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1220 } else if (type == INTEL_OUTPUT_DP_MST) { 1221 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1222 1223 if (intel_dp->is_mst) { 1224 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1225 } else 1226 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1227 1228 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1229 } else { 1230 WARN(1, "Invalid encoder type %d for pipe %c\n", 1231 intel_encoder->type, pipe_name(pipe)); 1232 } 1233 1234 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1235 } 1236 1237 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1238 enum transcoder cpu_transcoder) 1239 { 1240 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1241 uint32_t val = I915_READ(reg); 1242 1243 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1244 val |= TRANS_DDI_PORT_NONE; 1245 I915_WRITE(reg, val); 1246 } 1247 1248 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1249 { 1250 struct drm_device *dev = intel_connector->base.dev; 1251 struct drm_i915_private *dev_priv = dev->dev_private; 1252 struct intel_encoder *intel_encoder = intel_connector->encoder; 1253 int type = intel_connector->base.connector_type; 1254 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1255 enum i915_pipe pipe = 0; 1256 enum transcoder cpu_transcoder; 1257 enum intel_display_power_domain power_domain; 1258 uint32_t tmp; 1259 bool ret; 1260 1261 power_domain = intel_display_port_power_domain(intel_encoder); 1262 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 1263 return false; 1264 1265 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { 1266 ret = false; 1267 goto out; 1268 } 1269 1270 if (port == PORT_A) 1271 cpu_transcoder = TRANSCODER_EDP; 1272 else 1273 cpu_transcoder = (enum transcoder) pipe; 1274 1275 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1276 1277 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1278 case TRANS_DDI_MODE_SELECT_HDMI: 1279 case TRANS_DDI_MODE_SELECT_DVI: 1280 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1281 break; 1282 1283 case TRANS_DDI_MODE_SELECT_DP_SST: 1284 ret = type == DRM_MODE_CONNECTOR_eDP || 1285 type == DRM_MODE_CONNECTOR_DisplayPort; 1286 break; 1287 1288 case TRANS_DDI_MODE_SELECT_DP_MST: 1289 /* if the transcoder is in MST state then 1290 * connector isn't connected */ 1291 ret = false; 1292 break; 1293 1294 case TRANS_DDI_MODE_SELECT_FDI: 1295 ret = type == DRM_MODE_CONNECTOR_VGA; 1296 break; 1297 1298 default: 1299 ret = false; 1300 break; 1301 } 1302 1303 out: 1304 intel_display_power_put(dev_priv, power_domain); 1305 1306 return ret; 1307 } 1308 1309 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1310 enum i915_pipe *pipe) 1311 { 1312 struct drm_device *dev = encoder->base.dev; 1313 struct drm_i915_private *dev_priv = dev->dev_private; 1314 enum port port = intel_ddi_get_encoder_port(encoder); 1315 enum intel_display_power_domain power_domain; 1316 u32 tmp; 1317 int i; 1318 bool ret; 1319 1320 power_domain = intel_display_port_power_domain(encoder); 1321 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 1322 return false; 1323 1324 ret = false; 1325 1326 tmp = I915_READ(DDI_BUF_CTL(port)); 1327 1328 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1329 goto out; 1330 1331 if (port == PORT_A) { 1332 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1333 1334 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1335 case TRANS_DDI_EDP_INPUT_A_ON: 1336 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1337 *pipe = PIPE_A; 1338 break; 1339 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1340 *pipe = PIPE_B; 1341 break; 1342 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1343 *pipe = PIPE_C; 1344 break; 1345 } 1346 1347 ret = true; 1348 1349 goto out; 1350 } 1351 1352 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 1353 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 1354 1355 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { 1356 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 1357 TRANS_DDI_MODE_SELECT_DP_MST) 1358 goto out; 1359 1360 *pipe = i; 1361 ret = true; 1362 1363 goto out; 1364 } 1365 } 1366 1367 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 1368 1369 out: 1370 intel_display_power_put(dev_priv, power_domain); 1371 1372 return ret; 1373 } 1374 1375 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 1376 { 1377 struct drm_crtc *crtc = &intel_crtc->base; 1378 struct drm_device *dev = crtc->dev; 1379 struct drm_i915_private *dev_priv = dev->dev_private; 1380 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1381 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1382 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1383 1384 if (cpu_transcoder != TRANSCODER_EDP) 1385 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1386 TRANS_CLK_SEL_PORT(port)); 1387 } 1388 1389 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 1390 { 1391 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1392 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1393 1394 if (cpu_transcoder != TRANSCODER_EDP) 1395 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1396 TRANS_CLK_SEL_DISABLED); 1397 } 1398 1399 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1400 enum port port, uint8_t iboost) 1401 { 1402 u32 tmp; 1403 1404 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); 1405 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1406 if (iboost) 1407 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1408 else 1409 tmp |= BALANCE_LEG_DISABLE(port); 1410 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); 1411 } 1412 1413 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level) 1414 { 1415 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 1416 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 1417 enum port port = intel_dig_port->port; 1418 int type = encoder->type; 1419 const struct ddi_buf_trans *ddi_translations; 1420 uint8_t iboost; 1421 uint8_t dp_iboost, hdmi_iboost; 1422 int n_entries; 1423 1424 /* VBT may override standard boost values */ 1425 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 1426 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 1427 1428 if (type == INTEL_OUTPUT_DISPLAYPORT) { 1429 if (dp_iboost) { 1430 iboost = dp_iboost; 1431 } else { 1432 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries); 1433 iboost = ddi_translations[level].i_boost; 1434 } 1435 } else if (type == INTEL_OUTPUT_EDP) { 1436 if (dp_iboost) { 1437 iboost = dp_iboost; 1438 } else { 1439 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); 1440 1441 if (WARN_ON(port != PORT_A && 1442 port != PORT_E && n_entries > 9)) 1443 n_entries = 9; 1444 1445 iboost = ddi_translations[level].i_boost; 1446 } 1447 } else if (type == INTEL_OUTPUT_HDMI) { 1448 if (hdmi_iboost) { 1449 iboost = hdmi_iboost; 1450 } else { 1451 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); 1452 iboost = ddi_translations[level].i_boost; 1453 } 1454 } else { 1455 return; 1456 } 1457 1458 /* Make sure that the requested I_boost is valid */ 1459 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1460 DRM_ERROR("Invalid I_boost value %u\n", iboost); 1461 return; 1462 } 1463 1464 _skl_ddi_set_iboost(dev_priv, port, iboost); 1465 1466 if (port == PORT_A && intel_dig_port->max_lanes == 4) 1467 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1468 } 1469 1470 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, 1471 u32 level, enum port port, int type) 1472 { 1473 const struct bxt_ddi_buf_trans *ddi_translations; 1474 u32 n_entries, i; 1475 uint32_t val; 1476 1477 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 1478 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 1479 ddi_translations = bxt_ddi_translations_edp; 1480 } else if (type == INTEL_OUTPUT_DISPLAYPORT 1481 || type == INTEL_OUTPUT_EDP) { 1482 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 1483 ddi_translations = bxt_ddi_translations_dp; 1484 } else if (type == INTEL_OUTPUT_HDMI) { 1485 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 1486 ddi_translations = bxt_ddi_translations_hdmi; 1487 } else { 1488 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 1489 type); 1490 return; 1491 } 1492 1493 /* Check if default value has to be used */ 1494 if (level >= n_entries || 1495 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 1496 for (i = 0; i < n_entries; i++) { 1497 if (ddi_translations[i].default_index) { 1498 level = i; 1499 break; 1500 } 1501 } 1502 } 1503 1504 /* 1505 * While we write to the group register to program all lanes at once we 1506 * can read only lane registers and we pick lanes 0/1 for that. 1507 */ 1508 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 1509 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 1510 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 1511 1512 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); 1513 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 1514 val |= ddi_translations[level].margin << MARGIN_000_SHIFT | 1515 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; 1516 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); 1517 1518 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); 1519 val &= ~SCALE_DCOMP_METHOD; 1520 if (ddi_translations[level].enable) 1521 val |= SCALE_DCOMP_METHOD; 1522 1523 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 1524 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); 1525 1526 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); 1527 1528 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); 1529 val &= ~DE_EMPHASIS; 1530 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; 1531 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); 1532 1533 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 1534 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 1535 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 1536 } 1537 1538 static uint32_t translate_signal_level(int signal_levels) 1539 { 1540 uint32_t level; 1541 1542 switch (signal_levels) { 1543 default: 1544 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1545 signal_levels); 1546 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1547 level = 0; 1548 break; 1549 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1550 level = 1; 1551 break; 1552 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1553 level = 2; 1554 break; 1555 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: 1556 level = 3; 1557 break; 1558 1559 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1560 level = 4; 1561 break; 1562 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1563 level = 5; 1564 break; 1565 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1566 level = 6; 1567 break; 1568 1569 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1570 level = 7; 1571 break; 1572 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1573 level = 8; 1574 break; 1575 1576 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1577 level = 9; 1578 break; 1579 } 1580 1581 return level; 1582 } 1583 1584 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 1585 { 1586 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1587 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 1588 struct intel_encoder *encoder = &dport->base; 1589 uint8_t train_set = intel_dp->train_set[0]; 1590 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1591 DP_TRAIN_PRE_EMPHASIS_MASK); 1592 enum port port = dport->port; 1593 uint32_t level; 1594 1595 level = translate_signal_level(signal_levels); 1596 1597 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 1598 skl_ddi_set_iboost(encoder, level); 1599 else if (IS_BROXTON(dev_priv)) 1600 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); 1601 1602 return DDI_BUF_TRANS_SELECT(level); 1603 } 1604 1605 void intel_ddi_clk_select(struct intel_encoder *encoder, 1606 const struct intel_crtc_state *pipe_config) 1607 { 1608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1609 enum port port = intel_ddi_get_encoder_port(encoder); 1610 1611 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 1612 uint32_t dpll = pipe_config->ddi_pll_sel; 1613 uint32_t val; 1614 1615 /* DDI -> PLL mapping */ 1616 val = I915_READ(DPLL_CTRL2); 1617 1618 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 1619 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 1620 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 1621 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1622 1623 I915_WRITE(DPLL_CTRL2, val); 1624 1625 } else if (INTEL_INFO(dev_priv)->gen < 9) { 1626 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); 1627 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); 1628 } 1629 } 1630 1631 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 1632 { 1633 struct drm_encoder *encoder = &intel_encoder->base; 1634 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 1635 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 1636 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1637 int type = intel_encoder->type; 1638 1639 if (type == INTEL_OUTPUT_HDMI) { 1640 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1641 1642 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1643 } 1644 1645 intel_prepare_ddi_buffer(intel_encoder); 1646 1647 if (type == INTEL_OUTPUT_EDP) { 1648 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1649 intel_edp_panel_on(intel_dp); 1650 } 1651 1652 intel_ddi_clk_select(intel_encoder, crtc->config); 1653 1654 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1655 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1656 1657 intel_dp_set_link_params(intel_dp, crtc->config); 1658 1659 intel_ddi_init_dp_buf_reg(intel_encoder); 1660 1661 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1662 intel_dp_start_link_train(intel_dp); 1663 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9) 1664 intel_dp_stop_link_train(intel_dp); 1665 } else if (type == INTEL_OUTPUT_HDMI) { 1666 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1667 int level = intel_ddi_hdmi_level(dev_priv, port); 1668 1669 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 1670 skl_ddi_set_iboost(intel_encoder, level); 1671 1672 intel_hdmi->set_infoframes(encoder, 1673 crtc->config->has_hdmi_sink, 1674 &crtc->config->base.adjusted_mode); 1675 } 1676 } 1677 1678 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 1679 { 1680 struct drm_encoder *encoder = &intel_encoder->base; 1681 struct drm_device *dev = encoder->dev; 1682 struct drm_i915_private *dev_priv = dev->dev_private; 1683 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1684 int type = intel_encoder->type; 1685 uint32_t val; 1686 bool wait = false; 1687 1688 val = I915_READ(DDI_BUF_CTL(port)); 1689 if (val & DDI_BUF_CTL_ENABLE) { 1690 val &= ~DDI_BUF_CTL_ENABLE; 1691 I915_WRITE(DDI_BUF_CTL(port), val); 1692 wait = true; 1693 } 1694 1695 val = I915_READ(DP_TP_CTL(port)); 1696 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1697 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1698 I915_WRITE(DP_TP_CTL(port), val); 1699 1700 if (wait) 1701 intel_wait_ddi_buf_idle(dev_priv, port); 1702 1703 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1704 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1705 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1706 intel_edp_panel_vdd_on(intel_dp); 1707 intel_edp_panel_off(intel_dp); 1708 } 1709 1710 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1711 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 1712 DPLL_CTRL2_DDI_CLK_OFF(port))); 1713 else if (INTEL_INFO(dev)->gen < 9) 1714 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1715 1716 if (type == INTEL_OUTPUT_HDMI) { 1717 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1718 1719 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1720 } 1721 } 1722 1723 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 1724 { 1725 struct drm_encoder *encoder = &intel_encoder->base; 1726 struct drm_crtc *crtc = encoder->crtc; 1727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1728 struct drm_device *dev = encoder->dev; 1729 struct drm_i915_private *dev_priv = dev->dev_private; 1730 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1731 int type = intel_encoder->type; 1732 1733 if (type == INTEL_OUTPUT_HDMI) { 1734 struct intel_digital_port *intel_dig_port = 1735 enc_to_dig_port(encoder); 1736 1737 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1738 * are ignored so nothing special needs to be done besides 1739 * enabling the port. 1740 */ 1741 I915_WRITE(DDI_BUF_CTL(port), 1742 intel_dig_port->saved_port_bits | 1743 DDI_BUF_CTL_ENABLE); 1744 } else if (type == INTEL_OUTPUT_EDP) { 1745 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1746 1747 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 1748 intel_dp_stop_link_train(intel_dp); 1749 1750 intel_edp_backlight_on(intel_dp); 1751 intel_psr_enable(intel_dp); 1752 intel_edp_drrs_enable(intel_dp); 1753 } 1754 1755 if (intel_crtc->config->has_audio) { 1756 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 1757 intel_audio_codec_enable(intel_encoder); 1758 } 1759 } 1760 1761 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 1762 { 1763 struct drm_encoder *encoder = &intel_encoder->base; 1764 struct drm_crtc *crtc = encoder->crtc; 1765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1766 int type = intel_encoder->type; 1767 struct drm_device *dev = encoder->dev; 1768 struct drm_i915_private *dev_priv = dev->dev_private; 1769 1770 if (intel_crtc->config->has_audio) { 1771 intel_audio_codec_disable(intel_encoder); 1772 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 1773 } 1774 1775 if (type == INTEL_OUTPUT_EDP) { 1776 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1777 1778 intel_edp_drrs_disable(intel_dp); 1779 intel_psr_disable(intel_dp); 1780 intel_edp_backlight_off(intel_dp); 1781 } 1782 } 1783 1784 static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv, 1785 enum dpio_phy phy) 1786 { 1787 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy))) 1788 return false; 1789 1790 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & 1791 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { 1792 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n", 1793 phy); 1794 1795 return false; 1796 } 1797 1798 if (phy == DPIO_PHY1 && 1799 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) { 1800 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n"); 1801 1802 return false; 1803 } 1804 1805 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 1806 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n", 1807 phy); 1808 1809 return false; 1810 } 1811 1812 return true; 1813 } 1814 1815 static u32 broxton_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) 1816 { 1817 u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); 1818 1819 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 1820 } 1821 1822 static void broxton_phy_wait_grc_done(struct drm_i915_private *dev_priv, 1823 enum dpio_phy phy) 1824 { 1825 if (wait_for(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE, 10)) 1826 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy); 1827 } 1828 1829 static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv, 1830 enum dpio_phy phy); 1831 1832 static void broxton_phy_init(struct drm_i915_private *dev_priv, 1833 enum dpio_phy phy) 1834 { 1835 enum port port; 1836 u32 ports, val; 1837 1838 if (broxton_phy_is_enabled(dev_priv, phy)) { 1839 /* Still read out the GRC value for state verification */ 1840 if (phy == DPIO_PHY0) 1841 dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, phy); 1842 1843 if (broxton_phy_verify_state(dev_priv, phy)) { 1844 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, " 1845 "won't reprogram it\n", phy); 1846 1847 return; 1848 } 1849 1850 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, " 1851 "force reprogramming it\n", phy); 1852 } else { 1853 DRM_DEBUG_DRIVER("DDI PHY %d not enabled, enabling it\n", phy); 1854 } 1855 1856 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 1857 val |= GT_DISPLAY_POWER_ON(phy); 1858 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 1859 1860 /* 1861 * The PHY registers start out inaccessible and respond to reads with 1862 * all 1s. Eventually they become accessible as they power up, then 1863 * the reserved bit will give the default 0. Poll on the reserved bit 1864 * becoming 0 to find when the PHY is accessible. 1865 * HW team confirmed that the time to reach phypowergood status is 1866 * anywhere between 50 us and 100us. 1867 */ 1868 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & 1869 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) { 1870 DRM_ERROR("timeout during PHY%d power on\n", phy); 1871 } 1872 1873 if (phy == DPIO_PHY0) 1874 ports = BIT(PORT_B) | BIT(PORT_C); 1875 else 1876 ports = BIT(PORT_A); 1877 1878 for_each_port_masked(port, ports) { 1879 int lane; 1880 1881 for (lane = 0; lane < 4; lane++) { 1882 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); 1883 /* 1884 * Note that on CHV this flag is called UPAR, but has 1885 * the same function. 1886 */ 1887 val &= ~LATENCY_OPTIM; 1888 if (lane != 1) 1889 val |= LATENCY_OPTIM; 1890 1891 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); 1892 } 1893 } 1894 1895 /* Program PLL Rcomp code offset */ 1896 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 1897 val &= ~IREF0RC_OFFSET_MASK; 1898 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 1899 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 1900 1901 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 1902 val &= ~IREF1RC_OFFSET_MASK; 1903 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 1904 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 1905 1906 /* Program power gating */ 1907 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 1908 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 1909 SUS_CLK_CONFIG; 1910 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 1911 1912 if (phy == DPIO_PHY0) { 1913 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); 1914 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 1915 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); 1916 } 1917 1918 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); 1919 val &= ~OCL2_LDOFUSE_PWR_DIS; 1920 /* 1921 * On PHY1 disable power on the second channel, since no port is 1922 * connected there. On PHY0 both channels have a port, so leave it 1923 * enabled. 1924 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should 1925 * power down the second channel on PHY0 as well. 1926 * 1927 * FIXME: Clarify programming of the following, the register is 1928 * read-only with bit 6 fixed at 0 at least in stepping A. 1929 */ 1930 if (phy == DPIO_PHY1) 1931 val |= OCL2_LDOFUSE_PWR_DIS; 1932 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); 1933 1934 if (phy == DPIO_PHY0) { 1935 uint32_t grc_code; 1936 /* 1937 * PHY0 isn't connected to an RCOMP resistor so copy over 1938 * the corresponding calibrated value from PHY1, and disable 1939 * the automatic calibration on PHY0. 1940 */ 1941 broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); 1942 1943 val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, 1944 DPIO_PHY1); 1945 grc_code = val << GRC_CODE_FAST_SHIFT | 1946 val << GRC_CODE_SLOW_SHIFT | 1947 val; 1948 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); 1949 1950 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); 1951 val |= GRC_DIS | GRC_RDY_OVRD; 1952 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); 1953 } 1954 /* 1955 * During PHY1 init delay waiting for GRC calibration to finish, since 1956 * it can happen in parallel with the subsequent PHY0 init. 1957 */ 1958 1959 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 1960 val |= COMMON_RESET_DIS; 1961 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 1962 } 1963 1964 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) 1965 { 1966 /* Enable PHY1 first since it provides Rcomp for PHY0 */ 1967 broxton_phy_init(dev_priv, DPIO_PHY1); 1968 broxton_phy_init(dev_priv, DPIO_PHY0); 1969 1970 /* 1971 * If BIOS enabled only PHY0 and not PHY1, we skipped waiting for the 1972 * PHY1 GRC calibration to finish, so wait for it here. 1973 */ 1974 broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); 1975 } 1976 1977 static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 1978 enum dpio_phy phy) 1979 { 1980 uint32_t val; 1981 1982 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 1983 val &= ~COMMON_RESET_DIS; 1984 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 1985 1986 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 1987 val &= ~GT_DISPLAY_POWER_ON(phy); 1988 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 1989 } 1990 1991 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv) 1992 { 1993 broxton_phy_uninit(dev_priv, DPIO_PHY1); 1994 broxton_phy_uninit(dev_priv, DPIO_PHY0); 1995 } 1996 1997 static bool __printf(6, 7) 1998 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1999 i915_reg_t reg, u32 mask, u32 expected, 2000 const char *reg_fmt, ...) 2001 { 2002 struct va_format vaf; 2003 __va_list args; 2004 u32 val; 2005 2006 val = I915_READ(reg); 2007 if ((val & mask) == expected) 2008 return true; 2009 2010 __va_start(args, reg_fmt); 2011 vaf.fmt = reg_fmt; 2012 vaf.va = &args; 2013 2014 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: " 2015 "current %08x, expected %08x (mask %08x)\n", 2016 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 2017 mask); 2018 2019 __va_end(args); 2020 2021 return false; 2022 } 2023 2024 static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv, 2025 enum dpio_phy phy) 2026 { 2027 enum port port; 2028 u32 ports; 2029 uint32_t mask; 2030 bool ok; 2031 2032 #define _CHK(reg, mask, exp, fmt, ...) \ 2033 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ 2034 ## __VA_ARGS__) 2035 2036 /* We expect the PHY to be always enabled */ 2037 if (!broxton_phy_is_enabled(dev_priv, phy)) 2038 return false; 2039 2040 ok = true; 2041 2042 if (phy == DPIO_PHY0) 2043 ports = BIT(PORT_B) | BIT(PORT_C); 2044 else 2045 ports = BIT(PORT_A); 2046 2047 for_each_port_masked(port, ports) { 2048 int lane; 2049 2050 for (lane = 0; lane < 4; lane++) 2051 ok &= _CHK(BXT_PORT_TX_DW14_LN(port, lane), 2052 LATENCY_OPTIM, 2053 lane != 1 ? LATENCY_OPTIM : 0, 2054 "BXT_PORT_TX_DW14_LN(%d, %d)", port, lane); 2055 } 2056 2057 /* PLL Rcomp code offset */ 2058 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), 2059 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, 2060 "BXT_PORT_CL1CM_DW9(%d)", phy); 2061 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), 2062 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, 2063 "BXT_PORT_CL1CM_DW10(%d)", phy); 2064 2065 /* Power gating */ 2066 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; 2067 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, 2068 "BXT_PORT_CL1CM_DW28(%d)", phy); 2069 2070 if (phy == DPIO_PHY0) 2071 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC, 2072 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, 2073 "BXT_PORT_CL2CM_DW6_BC"); 2074 2075 /* 2076 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS, 2077 * at least on stepping A this bit is read-only and fixed at 0. 2078 */ 2079 2080 if (phy == DPIO_PHY0) { 2081 u32 grc_code = dev_priv->bxt_phy_grc; 2082 2083 grc_code = grc_code << GRC_CODE_FAST_SHIFT | 2084 grc_code << GRC_CODE_SLOW_SHIFT | 2085 grc_code; 2086 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | 2087 GRC_CODE_NOM_MASK; 2088 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code, 2089 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0); 2090 2091 mask = GRC_DIS | GRC_RDY_OVRD; 2092 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask, 2093 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0); 2094 } 2095 2096 return ok; 2097 #undef _CHK 2098 } 2099 2100 void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv) 2101 { 2102 if (!broxton_phy_verify_state(dev_priv, DPIO_PHY0) || 2103 !broxton_phy_verify_state(dev_priv, DPIO_PHY1)) 2104 i915_report_error(dev_priv, "DDI PHY state mismatch\n"); 2105 } 2106 2107 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 2108 { 2109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2110 struct drm_i915_private *dev_priv = 2111 to_i915(intel_dig_port->base.base.dev); 2112 enum port port = intel_dig_port->port; 2113 uint32_t val; 2114 bool wait = false; 2115 2116 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 2117 val = I915_READ(DDI_BUF_CTL(port)); 2118 if (val & DDI_BUF_CTL_ENABLE) { 2119 val &= ~DDI_BUF_CTL_ENABLE; 2120 I915_WRITE(DDI_BUF_CTL(port), val); 2121 wait = true; 2122 } 2123 2124 val = I915_READ(DP_TP_CTL(port)); 2125 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2126 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2127 I915_WRITE(DP_TP_CTL(port), val); 2128 POSTING_READ(DP_TP_CTL(port)); 2129 2130 if (wait) 2131 intel_wait_ddi_buf_idle(dev_priv, port); 2132 } 2133 2134 val = DP_TP_CTL_ENABLE | 2135 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 2136 if (intel_dp->is_mst) 2137 val |= DP_TP_CTL_MODE_MST; 2138 else { 2139 val |= DP_TP_CTL_MODE_SST; 2140 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2141 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 2142 } 2143 I915_WRITE(DP_TP_CTL(port), val); 2144 POSTING_READ(DP_TP_CTL(port)); 2145 2146 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 2147 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 2148 POSTING_READ(DDI_BUF_CTL(port)); 2149 2150 udelay(600); 2151 } 2152 2153 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 2154 { 2155 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 2156 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2157 uint32_t val; 2158 2159 /* 2160 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 2161 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 2162 * step 13 is the correct place for it. Step 18 is where it was 2163 * originally before the BUN. 2164 */ 2165 val = I915_READ(FDI_RX_CTL(PIPE_A)); 2166 val &= ~FDI_RX_ENABLE; 2167 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 2168 2169 intel_ddi_post_disable(intel_encoder); 2170 2171 val = I915_READ(FDI_RX_MISC(PIPE_A)); 2172 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 2173 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 2174 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 2175 2176 val = I915_READ(FDI_RX_CTL(PIPE_A)); 2177 val &= ~FDI_PCDCLK; 2178 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 2179 2180 val = I915_READ(FDI_RX_CTL(PIPE_A)); 2181 val &= ~FDI_RX_PLL_ENABLE; 2182 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 2183 } 2184 2185 void intel_ddi_get_config(struct intel_encoder *encoder, 2186 struct intel_crtc_state *pipe_config) 2187 { 2188 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 2189 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2190 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2191 struct intel_hdmi *intel_hdmi; 2192 u32 temp, flags = 0; 2193 2194 /* XXX: DSI transcoder paranoia */ 2195 if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) 2196 return; 2197 2198 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2199 if (temp & TRANS_DDI_PHSYNC) 2200 flags |= DRM_MODE_FLAG_PHSYNC; 2201 else 2202 flags |= DRM_MODE_FLAG_NHSYNC; 2203 if (temp & TRANS_DDI_PVSYNC) 2204 flags |= DRM_MODE_FLAG_PVSYNC; 2205 else 2206 flags |= DRM_MODE_FLAG_NVSYNC; 2207 2208 pipe_config->base.adjusted_mode.flags |= flags; 2209 2210 switch (temp & TRANS_DDI_BPC_MASK) { 2211 case TRANS_DDI_BPC_6: 2212 pipe_config->pipe_bpp = 18; 2213 break; 2214 case TRANS_DDI_BPC_8: 2215 pipe_config->pipe_bpp = 24; 2216 break; 2217 case TRANS_DDI_BPC_10: 2218 pipe_config->pipe_bpp = 30; 2219 break; 2220 case TRANS_DDI_BPC_12: 2221 pipe_config->pipe_bpp = 36; 2222 break; 2223 default: 2224 break; 2225 } 2226 2227 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 2228 case TRANS_DDI_MODE_SELECT_HDMI: 2229 pipe_config->has_hdmi_sink = true; 2230 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 2231 2232 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 2233 pipe_config->has_infoframe = true; 2234 /* fall through */ 2235 case TRANS_DDI_MODE_SELECT_DVI: 2236 pipe_config->lane_count = 4; 2237 break; 2238 case TRANS_DDI_MODE_SELECT_FDI: 2239 break; 2240 case TRANS_DDI_MODE_SELECT_DP_SST: 2241 case TRANS_DDI_MODE_SELECT_DP_MST: 2242 pipe_config->has_dp_encoder = true; 2243 pipe_config->lane_count = 2244 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 2245 intel_dp_get_m_n(intel_crtc, pipe_config); 2246 break; 2247 default: 2248 break; 2249 } 2250 2251 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 2252 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 2253 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 2254 pipe_config->has_audio = true; 2255 } 2256 2257 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 2258 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 2259 /* 2260 * This is a big fat ugly hack. 2261 * 2262 * Some machines in UEFI boot mode provide us a VBT that has 18 2263 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2264 * unknown we fail to light up. Yet the same BIOS boots up with 2265 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2266 * max, not what it tells us to use. 2267 * 2268 * Note: This will still be broken if the eDP panel is not lit 2269 * up by the BIOS, and thus we can't get the mode at module 2270 * load. 2271 */ 2272 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2273 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 2274 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 2275 } 2276 2277 intel_ddi_clock_get(encoder, pipe_config); 2278 } 2279 2280 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 2281 struct intel_crtc_state *pipe_config) 2282 { 2283 int type = encoder->type; 2284 int port = intel_ddi_get_encoder_port(encoder); 2285 2286 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 2287 2288 if (port == PORT_A) 2289 pipe_config->cpu_transcoder = TRANSCODER_EDP; 2290 2291 if (type == INTEL_OUTPUT_HDMI) 2292 return intel_hdmi_compute_config(encoder, pipe_config); 2293 else 2294 return intel_dp_compute_config(encoder, pipe_config); 2295 } 2296 2297 static const struct drm_encoder_funcs intel_ddi_funcs = { 2298 .reset = intel_dp_encoder_reset, 2299 .destroy = intel_dp_encoder_destroy, 2300 }; 2301 2302 static struct intel_connector * 2303 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 2304 { 2305 struct intel_connector *connector; 2306 enum port port = intel_dig_port->port; 2307 2308 connector = intel_connector_alloc(); 2309 if (!connector) 2310 return NULL; 2311 2312 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 2313 if (!intel_dp_init_connector(intel_dig_port, connector)) { 2314 kfree(connector); 2315 return NULL; 2316 } 2317 2318 return connector; 2319 } 2320 2321 static struct intel_connector * 2322 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 2323 { 2324 struct intel_connector *connector; 2325 enum port port = intel_dig_port->port; 2326 2327 connector = intel_connector_alloc(); 2328 if (!connector) 2329 return NULL; 2330 2331 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 2332 intel_hdmi_init_connector(intel_dig_port, connector); 2333 2334 return connector; 2335 } 2336 2337 void intel_ddi_init(struct drm_device *dev, enum port port) 2338 { 2339 struct drm_i915_private *dev_priv = dev->dev_private; 2340 struct intel_digital_port *intel_dig_port; 2341 struct intel_encoder *intel_encoder; 2342 struct drm_encoder *encoder; 2343 bool init_hdmi, init_dp; 2344 int max_lanes; 2345 2346 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { 2347 switch (port) { 2348 case PORT_A: 2349 max_lanes = 4; 2350 break; 2351 case PORT_E: 2352 max_lanes = 0; 2353 break; 2354 default: 2355 max_lanes = 4; 2356 break; 2357 } 2358 } else { 2359 switch (port) { 2360 case PORT_A: 2361 max_lanes = 2; 2362 break; 2363 case PORT_E: 2364 max_lanes = 2; 2365 break; 2366 default: 2367 max_lanes = 4; 2368 break; 2369 } 2370 } 2371 2372 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 2373 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 2374 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 2375 if (!init_dp && !init_hdmi) { 2376 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 2377 port_name(port)); 2378 return; 2379 } 2380 2381 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2382 if (!intel_dig_port) 2383 return; 2384 2385 intel_encoder = &intel_dig_port->base; 2386 encoder = &intel_encoder->base; 2387 2388 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 2389 DRM_MODE_ENCODER_TMDS, NULL); 2390 2391 intel_encoder->compute_config = intel_ddi_compute_config; 2392 intel_encoder->enable = intel_enable_ddi; 2393 intel_encoder->pre_enable = intel_ddi_pre_enable; 2394 intel_encoder->disable = intel_disable_ddi; 2395 intel_encoder->post_disable = intel_ddi_post_disable; 2396 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 2397 intel_encoder->get_config = intel_ddi_get_config; 2398 intel_encoder->suspend = intel_dp_encoder_suspend; 2399 2400 intel_dig_port->port = port; 2401 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 2402 (DDI_BUF_PORT_REVERSAL | 2403 DDI_A_4_LANES); 2404 2405 /* 2406 * Bspec says that DDI_A_4_LANES is the only supported configuration 2407 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP 2408 * wasn't lit up at boot. Force this bit on in our internal 2409 * configuration so that we use the proper lane count for our 2410 * calculations. 2411 */ 2412 if (IS_BROXTON(dev) && port == PORT_A) { 2413 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { 2414 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); 2415 intel_dig_port->saved_port_bits |= DDI_A_4_LANES; 2416 max_lanes = 4; 2417 } 2418 } 2419 2420 intel_dig_port->max_lanes = max_lanes; 2421 2422 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 2423 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2424 intel_encoder->cloneable = 0; 2425 2426 if (init_dp) { 2427 if (!intel_ddi_init_dp_connector(intel_dig_port)) 2428 goto err; 2429 2430 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 2431 /* 2432 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 2433 * interrupts to check the external panel connection. 2434 */ 2435 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) 2436 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; 2437 else 2438 dev_priv->hotplug.irq_port[port] = intel_dig_port; 2439 } 2440 2441 /* In theory we don't need the encoder->type check, but leave it just in 2442 * case we have some really bad VBTs... */ 2443 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 2444 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 2445 goto err; 2446 } 2447 2448 return; 2449 2450 err: 2451 drm_encoder_cleanup(encoder); 2452 kfree(intel_dig_port); 2453 } 2454