1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 36 }; 37 38 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 39 * them for both DP and FDI transports, allowing those ports to 40 * automatically adapt to HDMI connections as well 41 */ 42 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 43 { 0x00FFFFFF, 0x0006000E, 0x0 }, 44 { 0x00D75FFF, 0x0005000A, 0x0 }, 45 { 0x00C30FFF, 0x00040006, 0x0 }, 46 { 0x80AAAFFF, 0x000B0000, 0x0 }, 47 { 0x00FFFFFF, 0x0005000A, 0x0 }, 48 { 0x00D75FFF, 0x000C0004, 0x0 }, 49 { 0x80C30FFF, 0x000B0000, 0x0 }, 50 { 0x00FFFFFF, 0x00040006, 0x0 }, 51 { 0x80D75FFF, 0x000B0000, 0x0 }, 52 }; 53 54 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 55 { 0x00FFFFFF, 0x0007000E, 0x0 }, 56 { 0x00D75FFF, 0x000F000A, 0x0 }, 57 { 0x00C30FFF, 0x00060006, 0x0 }, 58 { 0x00AAAFFF, 0x001E0000, 0x0 }, 59 { 0x00FFFFFF, 0x000F000A, 0x0 }, 60 { 0x00D75FFF, 0x00160004, 0x0 }, 61 { 0x00C30FFF, 0x001E0000, 0x0 }, 62 { 0x00FFFFFF, 0x00060006, 0x0 }, 63 { 0x00D75FFF, 0x001E0000, 0x0 }, 64 }; 65 66 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 67 /* Idx NT mV d T mV d db */ 68 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 69 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 70 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 71 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 72 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 73 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 74 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 75 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 76 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 77 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 78 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 79 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 80 }; 81 82 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 83 { 0x00FFFFFF, 0x00000012, 0x0 }, 84 { 0x00EBAFFF, 0x00020011, 0x0 }, 85 { 0x00C71FFF, 0x0006000F, 0x0 }, 86 { 0x00AAAFFF, 0x000E000A, 0x0 }, 87 { 0x00FFFFFF, 0x00020011, 0x0 }, 88 { 0x00DB6FFF, 0x0005000F, 0x0 }, 89 { 0x00BEEFFF, 0x000A000C, 0x0 }, 90 { 0x00FFFFFF, 0x0005000F, 0x0 }, 91 { 0x00DB6FFF, 0x000A000C, 0x0 }, 92 }; 93 94 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 95 { 0x00FFFFFF, 0x0007000E, 0x0 }, 96 { 0x00D75FFF, 0x000E000A, 0x0 }, 97 { 0x00BEFFFF, 0x00140006, 0x0 }, 98 { 0x80B2CFFF, 0x001B0002, 0x0 }, 99 { 0x00FFFFFF, 0x000E000A, 0x0 }, 100 { 0x00DB6FFF, 0x00160005, 0x0 }, 101 { 0x80C71FFF, 0x001A0002, 0x0 }, 102 { 0x00F7DFFF, 0x00180004, 0x0 }, 103 { 0x80D75FFF, 0x001B0002, 0x0 }, 104 }; 105 106 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 107 { 0x00FFFFFF, 0x0001000E, 0x0 }, 108 { 0x00D75FFF, 0x0004000A, 0x0 }, 109 { 0x00C30FFF, 0x00070006, 0x0 }, 110 { 0x00AAAFFF, 0x000C0000, 0x0 }, 111 { 0x00FFFFFF, 0x0004000A, 0x0 }, 112 { 0x00D75FFF, 0x00090004, 0x0 }, 113 { 0x00C30FFF, 0x000C0000, 0x0 }, 114 { 0x00FFFFFF, 0x00070006, 0x0 }, 115 { 0x00D75FFF, 0x000C0000, 0x0 }, 116 }; 117 118 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 119 /* Idx NT mV d T mV df db */ 120 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 121 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 122 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 123 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 124 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 125 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 126 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 127 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 128 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 129 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 130 }; 131 132 /* Skylake H and S */ 133 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 134 { 0x00002016, 0x000000A0, 0x0 }, 135 { 0x00005012, 0x0000009B, 0x0 }, 136 { 0x00007011, 0x00000088, 0x0 }, 137 { 0x00009010, 0x000000C7, 0x0 }, 138 { 0x00002016, 0x0000009B, 0x0 }, 139 { 0x00005012, 0x00000088, 0x0 }, 140 { 0x00007011, 0x000000C7, 0x0 }, 141 { 0x00002016, 0x000000DF, 0x0 }, 142 { 0x00005012, 0x000000C7, 0x0 }, 143 }; 144 145 /* Skylake U */ 146 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 147 { 0x0000201B, 0x000000A2, 0x0 }, 148 { 0x00005012, 0x00000088, 0x0 }, 149 { 0x00007011, 0x00000087, 0x0 }, 150 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */ 151 { 0x0000201B, 0x0000009D, 0x0 }, 152 { 0x00005012, 0x000000C7, 0x0 }, 153 { 0x00007011, 0x000000C7, 0x0 }, 154 { 0x00002016, 0x00000088, 0x0 }, 155 { 0x00005012, 0x000000C7, 0x0 }, 156 }; 157 158 /* Skylake Y */ 159 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 160 { 0x00000018, 0x000000A2, 0x0 }, 161 { 0x00005012, 0x00000088, 0x0 }, 162 { 0x00007011, 0x00000087, 0x0 }, 163 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */ 164 { 0x00000018, 0x0000009D, 0x0 }, 165 { 0x00005012, 0x000000C7, 0x0 }, 166 { 0x00007011, 0x000000C7, 0x0 }, 167 { 0x00000018, 0x00000088, 0x0 }, 168 { 0x00005012, 0x000000C7, 0x0 }, 169 }; 170 171 /* 172 * Skylake H and S 173 * eDP 1.4 low vswing translation parameters 174 */ 175 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 176 { 0x00000018, 0x000000A8, 0x0 }, 177 { 0x00004013, 0x000000A9, 0x0 }, 178 { 0x00007011, 0x000000A2, 0x0 }, 179 { 0x00009010, 0x0000009C, 0x0 }, 180 { 0x00000018, 0x000000A9, 0x0 }, 181 { 0x00006013, 0x000000A2, 0x0 }, 182 { 0x00007011, 0x000000A6, 0x0 }, 183 { 0x00000018, 0x000000AB, 0x0 }, 184 { 0x00007013, 0x0000009F, 0x0 }, 185 { 0x00000018, 0x000000DF, 0x0 }, 186 }; 187 188 /* 189 * Skylake U 190 * eDP 1.4 low vswing translation parameters 191 */ 192 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 193 { 0x00000018, 0x000000A8, 0x0 }, 194 { 0x00004013, 0x000000A9, 0x0 }, 195 { 0x00007011, 0x000000A2, 0x0 }, 196 { 0x00009010, 0x0000009C, 0x0 }, 197 { 0x00000018, 0x000000A9, 0x0 }, 198 { 0x00006013, 0x000000A2, 0x0 }, 199 { 0x00007011, 0x000000A6, 0x0 }, 200 { 0x00002016, 0x000000AB, 0x0 }, 201 { 0x00005013, 0x0000009F, 0x0 }, 202 { 0x00000018, 0x000000DF, 0x0 }, 203 }; 204 205 /* 206 * Skylake Y 207 * eDP 1.4 low vswing translation parameters 208 */ 209 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 210 { 0x00000018, 0x000000A8, 0x0 }, 211 { 0x00004013, 0x000000AB, 0x0 }, 212 { 0x00007011, 0x000000A4, 0x0 }, 213 { 0x00009010, 0x000000DF, 0x0 }, 214 { 0x00000018, 0x000000AA, 0x0 }, 215 { 0x00006013, 0x000000A4, 0x0 }, 216 { 0x00007011, 0x0000009D, 0x0 }, 217 { 0x00000018, 0x000000A0, 0x0 }, 218 { 0x00006012, 0x000000DF, 0x0 }, 219 { 0x00000018, 0x0000008A, 0x0 }, 220 }; 221 222 /* Skylake U, H and S */ 223 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 224 { 0x00000018, 0x000000AC, 0x0 }, 225 { 0x00005012, 0x0000009D, 0x0 }, 226 { 0x00007011, 0x00000088, 0x0 }, 227 { 0x00000018, 0x000000A1, 0x0 }, 228 { 0x00000018, 0x00000098, 0x0 }, 229 { 0x00004013, 0x00000088, 0x0 }, 230 { 0x00006012, 0x00000087, 0x0 }, 231 { 0x00000018, 0x000000DF, 0x0 }, 232 { 0x00003015, 0x00000087, 0x0 }, /* Default */ 233 { 0x00003015, 0x000000C7, 0x0 }, 234 { 0x00000018, 0x000000C7, 0x0 }, 235 }; 236 237 /* Skylake Y */ 238 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 239 { 0x00000018, 0x000000A1, 0x0 }, 240 { 0x00005012, 0x000000DF, 0x0 }, 241 { 0x00007011, 0x00000084, 0x0 }, 242 { 0x00000018, 0x000000A4, 0x0 }, 243 { 0x00000018, 0x0000009D, 0x0 }, 244 { 0x00004013, 0x00000080, 0x0 }, 245 { 0x00006013, 0x000000C7, 0x0 }, 246 { 0x00000018, 0x0000008A, 0x0 }, 247 { 0x00003015, 0x000000C7, 0x0 }, /* Default */ 248 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */ 249 { 0x00000018, 0x000000C7, 0x0 }, 250 }; 251 252 struct bxt_ddi_buf_trans { 253 u32 margin; /* swing value */ 254 u32 scale; /* scale value */ 255 u32 enable; /* scale enable */ 256 u32 deemphasis; 257 bool default_index; /* true if the entry represents default value */ 258 }; 259 260 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 261 /* Idx NT mV diff db */ 262 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ 263 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 264 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ 265 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 266 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 267 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 268 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ 269 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 270 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 271 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 272 }; 273 274 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 275 /* Idx NT mV diff db */ 276 { 26, 0, 0, 128, false }, /* 0: 200 0 */ 277 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ 278 { 48, 0, 0, 96, false }, /* 2: 200 4 */ 279 { 54, 0, 0, 69, false }, /* 3: 200 6 */ 280 { 32, 0, 0, 128, false }, /* 4: 250 0 */ 281 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ 282 { 54, 0, 0, 85, false }, /* 6: 250 4 */ 283 { 43, 0, 0, 128, false }, /* 7: 300 0 */ 284 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ 285 { 48, 0, 0, 128, false }, /* 9: 300 0 */ 286 }; 287 288 /* BSpec has 2 recommended values - entries 0 and 8. 289 * Using the entry with higher vswing. 290 */ 291 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 292 /* Idx NT mV diff db */ 293 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ 294 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 295 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ 296 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 297 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 298 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 299 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ 300 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 301 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 302 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 303 }; 304 305 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 306 enum port port, int type); 307 308 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, 309 struct intel_digital_port **dig_port, 310 enum port *port) 311 { 312 struct drm_encoder *encoder = &intel_encoder->base; 313 314 *dig_port = 0; /* silence gcc warnings */ 315 *port = 0; /* silence gcc warnings */ 316 317 switch (intel_encoder->type) { 318 case INTEL_OUTPUT_DP_MST: 319 *dig_port = enc_to_mst(encoder)->primary; 320 *port = (*dig_port)->port; 321 break; 322 case INTEL_OUTPUT_DISPLAYPORT: 323 case INTEL_OUTPUT_EDP: 324 case INTEL_OUTPUT_HDMI: 325 case INTEL_OUTPUT_UNKNOWN: 326 *dig_port = enc_to_dig_port(encoder); 327 *port = (*dig_port)->port; 328 break; 329 case INTEL_OUTPUT_ANALOG: 330 *dig_port = NULL; 331 *port = PORT_E; 332 break; 333 default: 334 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); 335 break; 336 } 337 } 338 339 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 340 { 341 struct intel_digital_port *dig_port; 342 enum port port; 343 344 ddi_get_encoder_port(intel_encoder, &dig_port, &port); 345 346 return port; 347 } 348 349 static bool 350 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) 351 { 352 return intel_dig_port->hdmi.hdmi_reg; 353 } 354 355 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, 356 int *n_entries) 357 { 358 const struct ddi_buf_trans *ddi_translations; 359 360 if (IS_SKL_ULX(dev)) { 361 ddi_translations = skl_y_ddi_translations_dp; 362 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 363 } else if (IS_SKL_ULT(dev)) { 364 ddi_translations = skl_u_ddi_translations_dp; 365 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 366 } else { 367 ddi_translations = skl_ddi_translations_dp; 368 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 369 } 370 371 return ddi_translations; 372 } 373 374 static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, 375 int *n_entries) 376 { 377 struct drm_i915_private *dev_priv = dev->dev_private; 378 const struct ddi_buf_trans *ddi_translations; 379 380 if (IS_SKL_ULX(dev)) { 381 if (dev_priv->edp_low_vswing) { 382 ddi_translations = skl_y_ddi_translations_edp; 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 384 } else { 385 ddi_translations = skl_y_ddi_translations_dp; 386 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 387 } 388 } else if (IS_SKL_ULT(dev)) { 389 if (dev_priv->edp_low_vswing) { 390 ddi_translations = skl_u_ddi_translations_edp; 391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 392 } else { 393 ddi_translations = skl_u_ddi_translations_dp; 394 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 395 } 396 } else { 397 if (dev_priv->edp_low_vswing) { 398 ddi_translations = skl_ddi_translations_edp; 399 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 400 } else { 401 ddi_translations = skl_ddi_translations_dp; 402 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 403 } 404 } 405 406 return ddi_translations; 407 } 408 409 static const struct ddi_buf_trans * 410 skl_get_buf_trans_hdmi(struct drm_device *dev, 411 int *n_entries) 412 { 413 const struct ddi_buf_trans *ddi_translations; 414 415 if (IS_SKL_ULX(dev)) { 416 ddi_translations = skl_y_ddi_translations_hdmi; 417 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 418 } else { 419 ddi_translations = skl_ddi_translations_hdmi; 420 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 421 } 422 423 return ddi_translations; 424 } 425 426 /* 427 * Starting with Haswell, DDI port buffers must be programmed with correct 428 * values in advance. The buffer values are different for FDI and DP modes, 429 * but the HDMI/DVI fields are shared among those. So we program the DDI 430 * in either FDI or DP modes only, as HDMI connections will work with both 431 * of those 432 */ 433 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, 434 bool supports_hdmi) 435 { 436 struct drm_i915_private *dev_priv = dev->dev_private; 437 u32 iboost_bit = 0; 438 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 439 size; 440 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 441 const struct ddi_buf_trans *ddi_translations_fdi; 442 const struct ddi_buf_trans *ddi_translations_dp; 443 const struct ddi_buf_trans *ddi_translations_edp; 444 const struct ddi_buf_trans *ddi_translations_hdmi; 445 const struct ddi_buf_trans *ddi_translations; 446 447 if (IS_BROXTON(dev)) { 448 if (!supports_hdmi) 449 return; 450 451 /* Vswing programming for HDMI */ 452 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 453 INTEL_OUTPUT_HDMI); 454 return; 455 } else if (IS_SKYLAKE(dev)) { 456 ddi_translations_fdi = NULL; 457 ddi_translations_dp = 458 skl_get_buf_trans_dp(dev, &n_dp_entries); 459 ddi_translations_edp = 460 skl_get_buf_trans_edp(dev, &n_edp_entries); 461 ddi_translations_hdmi = 462 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries); 463 hdmi_default_entry = 8; 464 /* If we're boosting the current, set bit 31 of trans1 */ 465 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || 466 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 467 iboost_bit = 1<<31; 468 } else if (IS_BROADWELL(dev)) { 469 ddi_translations_fdi = bdw_ddi_translations_fdi; 470 ddi_translations_dp = bdw_ddi_translations_dp; 471 ddi_translations_edp = bdw_ddi_translations_edp; 472 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 473 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 474 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 475 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 476 hdmi_default_entry = 7; 477 } else if (IS_HASWELL(dev)) { 478 ddi_translations_fdi = hsw_ddi_translations_fdi; 479 ddi_translations_dp = hsw_ddi_translations_dp; 480 ddi_translations_edp = hsw_ddi_translations_dp; 481 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 482 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 483 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 484 hdmi_default_entry = 6; 485 } else { 486 WARN(1, "ddi translation table missing\n"); 487 ddi_translations_edp = bdw_ddi_translations_dp; 488 ddi_translations_fdi = bdw_ddi_translations_fdi; 489 ddi_translations_dp = bdw_ddi_translations_dp; 490 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 491 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 492 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 493 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 494 hdmi_default_entry = 7; 495 } 496 497 switch (port) { 498 case PORT_A: 499 ddi_translations = ddi_translations_edp; 500 size = n_edp_entries; 501 break; 502 case PORT_B: 503 case PORT_C: 504 ddi_translations = ddi_translations_dp; 505 size = n_dp_entries; 506 break; 507 case PORT_D: 508 if (intel_dp_is_edp(dev, PORT_D)) { 509 ddi_translations = ddi_translations_edp; 510 size = n_edp_entries; 511 } else { 512 ddi_translations = ddi_translations_dp; 513 size = n_dp_entries; 514 } 515 break; 516 case PORT_E: 517 if (ddi_translations_fdi) 518 ddi_translations = ddi_translations_fdi; 519 else 520 ddi_translations = ddi_translations_dp; 521 size = n_dp_entries; 522 break; 523 default: 524 BUG(); 525 } 526 527 for (i = 0; i < size; i++) { 528 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 529 ddi_translations[i].trans1 | iboost_bit); 530 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 531 ddi_translations[i].trans2); 532 } 533 534 if (!supports_hdmi) 535 return; 536 537 /* Choose a good default if VBT is badly populated */ 538 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 539 hdmi_level >= n_hdmi_entries) 540 hdmi_level = hdmi_default_entry; 541 542 /* Entry 9 is for HDMI: */ 543 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 544 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); 545 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 546 ddi_translations_hdmi[hdmi_level].trans2); 547 } 548 549 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 550 * mode and port E for FDI. 551 */ 552 void intel_prepare_ddi(struct drm_device *dev) 553 { 554 struct intel_encoder *intel_encoder; 555 bool visited[I915_MAX_PORTS] = { 0, }; 556 557 if (!HAS_DDI(dev)) 558 return; 559 560 for_each_intel_encoder(dev, intel_encoder) { 561 struct intel_digital_port *intel_dig_port; 562 enum port port; 563 bool supports_hdmi; 564 565 if (intel_encoder->type == INTEL_OUTPUT_DSI) 566 continue; 567 568 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); 569 if (visited[port]) 570 continue; 571 572 supports_hdmi = intel_dig_port && 573 intel_dig_port_supports_hdmi(intel_dig_port); 574 575 intel_prepare_ddi_buffers(dev, port, supports_hdmi); 576 visited[port] = true; 577 } 578 } 579 580 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 581 enum port port) 582 { 583 uint32_t reg = DDI_BUF_CTL(port); 584 int i; 585 586 for (i = 0; i < 16; i++) { 587 udelay(1); 588 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 589 return; 590 } 591 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 592 } 593 594 /* Starting with Haswell, different DDI ports can work in FDI mode for 595 * connection to the PCH-located connectors. For this, it is necessary to train 596 * both the DDI port and PCH receiver for the desired DDI buffer settings. 597 * 598 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 599 * please note that when FDI mode is active on DDI E, it shares 2 lines with 600 * DDI A (which is used for eDP) 601 */ 602 603 void hsw_fdi_link_train(struct drm_crtc *crtc) 604 { 605 struct drm_device *dev = crtc->dev; 606 struct drm_i915_private *dev_priv = dev->dev_private; 607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 608 u32 temp, i, rx_ctl_val; 609 610 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 611 * mode set "sequence for CRT port" document: 612 * - TP1 to TP2 time with the default value 613 * - FDI delay to 90h 614 * 615 * WaFDIAutoLinkSetTimingOverrride:hsw 616 */ 617 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 618 FDI_RX_PWRDN_LANE0_VAL(2) | 619 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 620 621 /* Enable the PCH Receiver FDI PLL */ 622 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 623 FDI_RX_PLL_ENABLE | 624 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 625 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 626 POSTING_READ(FDI_RX_CTL(PIPE_A)); 627 udelay(220); 628 629 /* Switch from Rawclk to PCDclk */ 630 rx_ctl_val |= FDI_PCDCLK; 631 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 632 633 /* Configure Port Clock Select */ 634 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 635 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 636 637 /* Start the training iterating through available voltages and emphasis, 638 * testing each value twice. */ 639 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 640 /* Configure DP_TP_CTL with auto-training */ 641 I915_WRITE(DP_TP_CTL(PORT_E), 642 DP_TP_CTL_FDI_AUTOTRAIN | 643 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 644 DP_TP_CTL_LINK_TRAIN_PAT1 | 645 DP_TP_CTL_ENABLE); 646 647 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 648 * DDI E does not support port reversal, the functionality is 649 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 650 * port reversal bit */ 651 I915_WRITE(DDI_BUF_CTL(PORT_E), 652 DDI_BUF_CTL_ENABLE | 653 ((intel_crtc->config->fdi_lanes - 1) << 1) | 654 DDI_BUF_TRANS_SELECT(i / 2)); 655 POSTING_READ(DDI_BUF_CTL(PORT_E)); 656 657 udelay(600); 658 659 /* Program PCH FDI Receiver TU */ 660 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 661 662 /* Enable PCH FDI Receiver with auto-training */ 663 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 664 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 665 POSTING_READ(FDI_RX_CTL(PIPE_A)); 666 667 /* Wait for FDI receiver lane calibration */ 668 udelay(30); 669 670 /* Unset FDI_RX_MISC pwrdn lanes */ 671 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 672 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 673 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 674 POSTING_READ(FDI_RX_MISC(PIPE_A)); 675 676 /* Wait for FDI auto training time */ 677 udelay(5); 678 679 temp = I915_READ(DP_TP_STATUS(PORT_E)); 680 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 681 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 682 683 /* Enable normal pixel sending for FDI */ 684 I915_WRITE(DP_TP_CTL(PORT_E), 685 DP_TP_CTL_FDI_AUTOTRAIN | 686 DP_TP_CTL_LINK_TRAIN_NORMAL | 687 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 688 DP_TP_CTL_ENABLE); 689 690 return; 691 } 692 693 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 694 temp &= ~DDI_BUF_CTL_ENABLE; 695 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 696 POSTING_READ(DDI_BUF_CTL(PORT_E)); 697 698 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 699 temp = I915_READ(DP_TP_CTL(PORT_E)); 700 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 701 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 702 I915_WRITE(DP_TP_CTL(PORT_E), temp); 703 POSTING_READ(DP_TP_CTL(PORT_E)); 704 705 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 706 707 rx_ctl_val &= ~FDI_RX_ENABLE; 708 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 709 POSTING_READ(FDI_RX_CTL(PIPE_A)); 710 711 /* Reset FDI_RX_MISC pwrdn lanes */ 712 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 713 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 714 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 715 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 716 POSTING_READ(FDI_RX_MISC(PIPE_A)); 717 } 718 719 DRM_ERROR("FDI link training failed!\n"); 720 } 721 722 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 723 { 724 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 725 struct intel_digital_port *intel_dig_port = 726 enc_to_dig_port(&encoder->base); 727 728 intel_dp->DP = intel_dig_port->saved_port_bits | 729 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 730 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 731 } 732 733 static struct intel_encoder * 734 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 735 { 736 struct drm_device *dev = crtc->dev; 737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 738 struct intel_encoder *intel_encoder, *ret = NULL; 739 int num_encoders = 0; 740 741 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 742 ret = intel_encoder; 743 num_encoders++; 744 } 745 746 if (num_encoders != 1) 747 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 748 pipe_name(intel_crtc->pipe)); 749 750 BUG_ON(ret == NULL); 751 return ret; 752 } 753 754 struct intel_encoder * 755 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 756 { 757 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 758 struct intel_encoder *ret = NULL; 759 struct drm_atomic_state *state; 760 struct drm_connector *connector; 761 struct drm_connector_state *connector_state; 762 int num_encoders = 0; 763 int i; 764 765 state = crtc_state->base.state; 766 767 for_each_connector_in_state(state, connector, connector_state, i) { 768 if (connector_state->crtc != crtc_state->base.crtc) 769 continue; 770 771 ret = to_intel_encoder(connector_state->best_encoder); 772 num_encoders++; 773 } 774 775 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 776 pipe_name(crtc->pipe)); 777 778 BUG_ON(ret == NULL); 779 return ret; 780 } 781 782 #define LC_FREQ 2700 783 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 784 785 #define P_MIN 2 786 #define P_MAX 64 787 #define P_INC 2 788 789 /* Constraints for PLL good behavior */ 790 #define REF_MIN 48 791 #define REF_MAX 400 792 #define VCO_MIN 2400 793 #define VCO_MAX 4800 794 795 #define abs_diff(a, b) ({ \ 796 typeof(a) __a = (a); \ 797 typeof(b) __b = (b); \ 798 (void) (&__a == &__b); \ 799 __a > __b ? (__a - __b) : (__b - __a); }) 800 801 struct hsw_wrpll_rnp { 802 unsigned p, n2, r2; 803 }; 804 805 static unsigned hsw_wrpll_get_budget_for_freq(int clock) 806 { 807 unsigned budget; 808 809 switch (clock) { 810 case 25175000: 811 case 25200000: 812 case 27000000: 813 case 27027000: 814 case 37762500: 815 case 37800000: 816 case 40500000: 817 case 40541000: 818 case 54000000: 819 case 54054000: 820 case 59341000: 821 case 59400000: 822 case 72000000: 823 case 74176000: 824 case 74250000: 825 case 81000000: 826 case 81081000: 827 case 89012000: 828 case 89100000: 829 case 108000000: 830 case 108108000: 831 case 111264000: 832 case 111375000: 833 case 148352000: 834 case 148500000: 835 case 162000000: 836 case 162162000: 837 case 222525000: 838 case 222750000: 839 case 296703000: 840 case 297000000: 841 budget = 0; 842 break; 843 case 233500000: 844 case 245250000: 845 case 247750000: 846 case 253250000: 847 case 298000000: 848 budget = 1500; 849 break; 850 case 169128000: 851 case 169500000: 852 case 179500000: 853 case 202000000: 854 budget = 2000; 855 break; 856 case 256250000: 857 case 262500000: 858 case 270000000: 859 case 272500000: 860 case 273750000: 861 case 280750000: 862 case 281250000: 863 case 286000000: 864 case 291750000: 865 budget = 4000; 866 break; 867 case 267250000: 868 case 268500000: 869 budget = 5000; 870 break; 871 default: 872 budget = 1000; 873 break; 874 } 875 876 return budget; 877 } 878 879 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, 880 unsigned r2, unsigned n2, unsigned p, 881 struct hsw_wrpll_rnp *best) 882 { 883 uint64_t a, b, c, d, diff, diff_best; 884 885 /* No best (r,n,p) yet */ 886 if (best->p == 0) { 887 best->p = p; 888 best->n2 = n2; 889 best->r2 = r2; 890 return; 891 } 892 893 /* 894 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 895 * freq2k. 896 * 897 * delta = 1e6 * 898 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 899 * freq2k; 900 * 901 * and we would like delta <= budget. 902 * 903 * If the discrepancy is above the PPM-based budget, always prefer to 904 * improve upon the previous solution. However, if you're within the 905 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 906 */ 907 a = freq2k * budget * p * r2; 908 b = freq2k * budget * best->p * best->r2; 909 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); 910 diff_best = abs_diff(freq2k * best->p * best->r2, 911 LC_FREQ_2K * best->n2); 912 c = 1000000 * diff; 913 d = 1000000 * diff_best; 914 915 if (a < c && b < d) { 916 /* If both are above the budget, pick the closer */ 917 if (best->p * best->r2 * diff < p * r2 * diff_best) { 918 best->p = p; 919 best->n2 = n2; 920 best->r2 = r2; 921 } 922 } else if (a >= c && b < d) { 923 /* If A is below the threshold but B is above it? Update. */ 924 best->p = p; 925 best->n2 = n2; 926 best->r2 = r2; 927 } else if (a >= c && b >= d) { 928 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 929 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 930 best->p = p; 931 best->n2 = n2; 932 best->r2 = r2; 933 } 934 } 935 /* Otherwise a < c && b >= d, do nothing */ 936 } 937 938 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg) 939 { 940 int refclk = LC_FREQ; 941 int n, p, r; 942 u32 wrpll; 943 944 wrpll = I915_READ(reg); 945 switch (wrpll & WRPLL_PLL_REF_MASK) { 946 case WRPLL_PLL_SSC: 947 case WRPLL_PLL_NON_SSC: 948 /* 949 * We could calculate spread here, but our checking 950 * code only cares about 5% accuracy, and spread is a max of 951 * 0.5% downspread. 952 */ 953 refclk = 135; 954 break; 955 case WRPLL_PLL_LCPLL: 956 refclk = LC_FREQ; 957 break; 958 default: 959 WARN(1, "bad wrpll refclk\n"); 960 return 0; 961 } 962 963 r = wrpll & WRPLL_DIVIDER_REF_MASK; 964 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 965 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 966 967 /* Convert to KHz, p & r have a fixed point portion */ 968 return (refclk * n * 100) / (p * r); 969 } 970 971 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 972 uint32_t dpll) 973 { 974 uint32_t cfgcr1_reg, cfgcr2_reg; 975 uint32_t cfgcr1_val, cfgcr2_val; 976 uint32_t p0, p1, p2, dco_freq; 977 978 cfgcr1_reg = DPLL_CFGCR1(dpll); 979 cfgcr2_reg = DPLL_CFGCR2(dpll); 980 981 cfgcr1_val = I915_READ(cfgcr1_reg); 982 cfgcr2_val = I915_READ(cfgcr2_reg); 983 984 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 985 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 986 987 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 988 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 989 else 990 p1 = 1; 991 992 993 switch (p0) { 994 case DPLL_CFGCR2_PDIV_1: 995 p0 = 1; 996 break; 997 case DPLL_CFGCR2_PDIV_2: 998 p0 = 2; 999 break; 1000 case DPLL_CFGCR2_PDIV_3: 1001 p0 = 3; 1002 break; 1003 case DPLL_CFGCR2_PDIV_7: 1004 p0 = 7; 1005 break; 1006 } 1007 1008 switch (p2) { 1009 case DPLL_CFGCR2_KDIV_5: 1010 p2 = 5; 1011 break; 1012 case DPLL_CFGCR2_KDIV_2: 1013 p2 = 2; 1014 break; 1015 case DPLL_CFGCR2_KDIV_3: 1016 p2 = 3; 1017 break; 1018 case DPLL_CFGCR2_KDIV_1: 1019 p2 = 1; 1020 break; 1021 } 1022 1023 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 1024 1025 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 1026 1000) / 0x8000; 1027 1028 return dco_freq / (p0 * p1 * p2 * 5); 1029 } 1030 1031 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1032 { 1033 int dotclock; 1034 1035 if (pipe_config->has_pch_encoder) 1036 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1037 &pipe_config->fdi_m_n); 1038 else if (pipe_config->has_dp_encoder) 1039 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1040 &pipe_config->dp_m_n); 1041 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 1042 dotclock = pipe_config->port_clock * 2 / 3; 1043 else 1044 dotclock = pipe_config->port_clock; 1045 1046 if (pipe_config->pixel_multiplier) 1047 dotclock /= pipe_config->pixel_multiplier; 1048 1049 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1050 } 1051 1052 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1053 struct intel_crtc_state *pipe_config) 1054 { 1055 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1056 int link_clock = 0; 1057 uint32_t dpll_ctl1, dpll; 1058 1059 dpll = pipe_config->ddi_pll_sel; 1060 1061 dpll_ctl1 = I915_READ(DPLL_CTRL1); 1062 1063 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 1064 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 1065 } else { 1066 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 1067 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 1068 1069 switch (link_clock) { 1070 case DPLL_CTRL1_LINK_RATE_810: 1071 link_clock = 81000; 1072 break; 1073 case DPLL_CTRL1_LINK_RATE_1080: 1074 link_clock = 108000; 1075 break; 1076 case DPLL_CTRL1_LINK_RATE_1350: 1077 link_clock = 135000; 1078 break; 1079 case DPLL_CTRL1_LINK_RATE_1620: 1080 link_clock = 162000; 1081 break; 1082 case DPLL_CTRL1_LINK_RATE_2160: 1083 link_clock = 216000; 1084 break; 1085 case DPLL_CTRL1_LINK_RATE_2700: 1086 link_clock = 270000; 1087 break; 1088 default: 1089 WARN(1, "Unsupported link rate\n"); 1090 break; 1091 } 1092 link_clock *= 2; 1093 } 1094 1095 pipe_config->port_clock = link_clock; 1096 1097 ddi_dotclock_get(pipe_config); 1098 } 1099 1100 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1101 struct intel_crtc_state *pipe_config) 1102 { 1103 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1104 int link_clock = 0; 1105 u32 val, pll; 1106 1107 val = pipe_config->ddi_pll_sel; 1108 switch (val & PORT_CLK_SEL_MASK) { 1109 case PORT_CLK_SEL_LCPLL_810: 1110 link_clock = 81000; 1111 break; 1112 case PORT_CLK_SEL_LCPLL_1350: 1113 link_clock = 135000; 1114 break; 1115 case PORT_CLK_SEL_LCPLL_2700: 1116 link_clock = 270000; 1117 break; 1118 case PORT_CLK_SEL_WRPLL1: 1119 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); 1120 break; 1121 case PORT_CLK_SEL_WRPLL2: 1122 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); 1123 break; 1124 case PORT_CLK_SEL_SPLL: 1125 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 1126 if (pll == SPLL_PLL_FREQ_810MHz) 1127 link_clock = 81000; 1128 else if (pll == SPLL_PLL_FREQ_1350MHz) 1129 link_clock = 135000; 1130 else if (pll == SPLL_PLL_FREQ_2700MHz) 1131 link_clock = 270000; 1132 else { 1133 WARN(1, "bad spll freq\n"); 1134 return; 1135 } 1136 break; 1137 default: 1138 WARN(1, "bad port clock sel\n"); 1139 return; 1140 } 1141 1142 pipe_config->port_clock = link_clock * 2; 1143 1144 ddi_dotclock_get(pipe_config); 1145 } 1146 1147 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 1148 enum intel_dpll_id dpll) 1149 { 1150 struct intel_shared_dpll *pll; 1151 struct intel_dpll_hw_state *state; 1152 intel_clock_t clock; 1153 1154 /* For DDI ports we always use a shared PLL. */ 1155 if (WARN_ON(dpll == DPLL_ID_PRIVATE)) 1156 return 0; 1157 1158 pll = &dev_priv->shared_dplls[dpll]; 1159 state = &pll->config.hw_state; 1160 1161 clock.m1 = 2; 1162 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; 1163 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1164 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; 1165 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1166 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1167 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1168 1169 return chv_calc_dpll_params(100000, &clock); 1170 } 1171 1172 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1173 struct intel_crtc_state *pipe_config) 1174 { 1175 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1176 enum port port = intel_ddi_get_encoder_port(encoder); 1177 uint32_t dpll = port; 1178 1179 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); 1180 1181 ddi_dotclock_get(pipe_config); 1182 } 1183 1184 void intel_ddi_clock_get(struct intel_encoder *encoder, 1185 struct intel_crtc_state *pipe_config) 1186 { 1187 struct drm_device *dev = encoder->base.dev; 1188 1189 if (INTEL_INFO(dev)->gen <= 8) 1190 hsw_ddi_clock_get(encoder, pipe_config); 1191 else if (IS_SKYLAKE(dev)) 1192 skl_ddi_clock_get(encoder, pipe_config); 1193 else if (IS_BROXTON(dev)) 1194 bxt_ddi_clock_get(encoder, pipe_config); 1195 } 1196 1197 static void 1198 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 1199 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 1200 { 1201 uint64_t freq2k; 1202 unsigned p, n2, r2; 1203 struct hsw_wrpll_rnp best = { 0, 0, 0 }; 1204 unsigned budget; 1205 1206 freq2k = clock / 100; 1207 1208 budget = hsw_wrpll_get_budget_for_freq(clock); 1209 1210 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 1211 * and directly pass the LC PLL to it. */ 1212 if (freq2k == 5400000) { 1213 *n2_out = 2; 1214 *p_out = 1; 1215 *r2_out = 2; 1216 return; 1217 } 1218 1219 /* 1220 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 1221 * the WR PLL. 1222 * 1223 * We want R so that REF_MIN <= Ref <= REF_MAX. 1224 * Injecting R2 = 2 * R gives: 1225 * REF_MAX * r2 > LC_FREQ * 2 and 1226 * REF_MIN * r2 < LC_FREQ * 2 1227 * 1228 * Which means the desired boundaries for r2 are: 1229 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 1230 * 1231 */ 1232 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 1233 r2 <= LC_FREQ * 2 / REF_MIN; 1234 r2++) { 1235 1236 /* 1237 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 1238 * 1239 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 1240 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 1241 * VCO_MAX * r2 > n2 * LC_FREQ and 1242 * VCO_MIN * r2 < n2 * LC_FREQ) 1243 * 1244 * Which means the desired boundaries for n2 are: 1245 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 1246 */ 1247 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 1248 n2 <= VCO_MAX * r2 / LC_FREQ; 1249 n2++) { 1250 1251 for (p = P_MIN; p <= P_MAX; p += P_INC) 1252 hsw_wrpll_update_rnp(freq2k, budget, 1253 r2, n2, p, &best); 1254 } 1255 } 1256 1257 *n2_out = best.n2; 1258 *p_out = best.p; 1259 *r2_out = best.r2; 1260 } 1261 1262 static bool 1263 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 1264 struct intel_crtc_state *crtc_state, 1265 struct intel_encoder *intel_encoder) 1266 { 1267 int clock = crtc_state->port_clock; 1268 1269 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1270 struct intel_shared_dpll *pll; 1271 uint32_t val; 1272 unsigned p, n2, r2; 1273 1274 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 1275 1276 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 1277 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 1278 WRPLL_DIVIDER_POST(p); 1279 1280 memset(&crtc_state->dpll_hw_state, 0, 1281 sizeof(crtc_state->dpll_hw_state)); 1282 1283 crtc_state->dpll_hw_state.wrpll = val; 1284 1285 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1286 if (pll == NULL) { 1287 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1288 pipe_name(intel_crtc->pipe)); 1289 return false; 1290 } 1291 1292 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1293 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { 1294 struct drm_atomic_state *state = crtc_state->base.state; 1295 struct intel_shared_dpll_config *spll = 1296 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; 1297 1298 if (spll->crtc_mask && 1299 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) 1300 return false; 1301 1302 crtc_state->shared_dpll = DPLL_ID_SPLL; 1303 spll->hw_state.spll = crtc_state->dpll_hw_state.spll; 1304 spll->crtc_mask |= 1 << intel_crtc->pipe; 1305 } 1306 1307 return true; 1308 } 1309 1310 struct skl_wrpll_context { 1311 uint64_t min_deviation; /* current minimal deviation */ 1312 uint64_t central_freq; /* chosen central freq */ 1313 uint64_t dco_freq; /* chosen dco freq */ 1314 unsigned int p; /* chosen divider */ 1315 }; 1316 1317 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) 1318 { 1319 memset(ctx, 0, sizeof(*ctx)); 1320 1321 ctx->min_deviation = U64_MAX; 1322 } 1323 1324 /* DCO freq must be within +1%/-6% of the DCO central freq */ 1325 #define SKL_DCO_MAX_PDEVIATION 100 1326 #define SKL_DCO_MAX_NDEVIATION 600 1327 1328 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, 1329 uint64_t central_freq, 1330 uint64_t dco_freq, 1331 unsigned int divider) 1332 { 1333 uint64_t deviation; 1334 1335 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), 1336 central_freq); 1337 1338 /* positive deviation */ 1339 if (dco_freq >= central_freq) { 1340 if (deviation < SKL_DCO_MAX_PDEVIATION && 1341 deviation < ctx->min_deviation) { 1342 ctx->min_deviation = deviation; 1343 ctx->central_freq = central_freq; 1344 ctx->dco_freq = dco_freq; 1345 ctx->p = divider; 1346 } 1347 /* negative deviation */ 1348 } else if (deviation < SKL_DCO_MAX_NDEVIATION && 1349 deviation < ctx->min_deviation) { 1350 ctx->min_deviation = deviation; 1351 ctx->central_freq = central_freq; 1352 ctx->dco_freq = dco_freq; 1353 ctx->p = divider; 1354 } 1355 } 1356 1357 static void skl_wrpll_get_multipliers(unsigned int p, 1358 unsigned int *p0 /* out */, 1359 unsigned int *p1 /* out */, 1360 unsigned int *p2 /* out */) 1361 { 1362 /* even dividers */ 1363 if (p % 2 == 0) { 1364 unsigned int half = p / 2; 1365 1366 if (half == 1 || half == 2 || half == 3 || half == 5) { 1367 *p0 = 2; 1368 *p1 = 1; 1369 *p2 = half; 1370 } else if (half % 2 == 0) { 1371 *p0 = 2; 1372 *p1 = half / 2; 1373 *p2 = 2; 1374 } else if (half % 3 == 0) { 1375 *p0 = 3; 1376 *p1 = half / 3; 1377 *p2 = 2; 1378 } else if (half % 7 == 0) { 1379 *p0 = 7; 1380 *p1 = half / 7; 1381 *p2 = 2; 1382 } 1383 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ 1384 *p0 = 3; 1385 *p1 = 1; 1386 *p2 = p / 3; 1387 } else if (p == 5 || p == 7) { 1388 *p0 = p; 1389 *p1 = 1; 1390 *p2 = 1; 1391 } else if (p == 15) { 1392 *p0 = 3; 1393 *p1 = 1; 1394 *p2 = 5; 1395 } else if (p == 21) { 1396 *p0 = 7; 1397 *p1 = 1; 1398 *p2 = 3; 1399 } else if (p == 35) { 1400 *p0 = 7; 1401 *p1 = 1; 1402 *p2 = 5; 1403 } 1404 } 1405 1406 struct skl_wrpll_params { 1407 uint32_t dco_fraction; 1408 uint32_t dco_integer; 1409 uint32_t qdiv_ratio; 1410 uint32_t qdiv_mode; 1411 uint32_t kdiv; 1412 uint32_t pdiv; 1413 uint32_t central_freq; 1414 }; 1415 1416 static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 1417 uint64_t afe_clock, 1418 uint64_t central_freq, 1419 uint32_t p0, uint32_t p1, uint32_t p2) 1420 { 1421 uint64_t dco_freq; 1422 1423 switch (central_freq) { 1424 case 9600000000ULL: 1425 params->central_freq = 0; 1426 break; 1427 case 9000000000ULL: 1428 params->central_freq = 1; 1429 break; 1430 case 8400000000ULL: 1431 params->central_freq = 3; 1432 } 1433 1434 switch (p0) { 1435 case 1: 1436 params->pdiv = 0; 1437 break; 1438 case 2: 1439 params->pdiv = 1; 1440 break; 1441 case 3: 1442 params->pdiv = 2; 1443 break; 1444 case 7: 1445 params->pdiv = 4; 1446 break; 1447 default: 1448 WARN(1, "Incorrect PDiv\n"); 1449 } 1450 1451 switch (p2) { 1452 case 5: 1453 params->kdiv = 0; 1454 break; 1455 case 2: 1456 params->kdiv = 1; 1457 break; 1458 case 3: 1459 params->kdiv = 2; 1460 break; 1461 case 1: 1462 params->kdiv = 3; 1463 break; 1464 default: 1465 WARN(1, "Incorrect KDiv\n"); 1466 } 1467 1468 params->qdiv_ratio = p1; 1469 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; 1470 1471 dco_freq = p0 * p1 * p2 * afe_clock; 1472 1473 /* 1474 * Intermediate values are in Hz. 1475 * Divide by MHz to match bsepc 1476 */ 1477 params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); 1478 params->dco_fraction = 1479 div_u64((div_u64(dco_freq, 24) - 1480 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); 1481 } 1482 1483 static bool 1484 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1485 struct skl_wrpll_params *wrpll_params) 1486 { 1487 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1488 uint64_t dco_central_freq[3] = {8400000000ULL, 1489 9000000000ULL, 1490 9600000000ULL}; 1491 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 1492 24, 28, 30, 32, 36, 40, 42, 44, 1493 48, 52, 54, 56, 60, 64, 66, 68, 1494 70, 72, 76, 78, 80, 84, 88, 90, 1495 92, 96, 98 }; 1496 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; 1497 static const struct { 1498 const int *list; 1499 int n_dividers; 1500 } dividers[] = { 1501 { even_dividers, ARRAY_SIZE(even_dividers) }, 1502 { odd_dividers, ARRAY_SIZE(odd_dividers) }, 1503 }; 1504 struct skl_wrpll_context ctx; 1505 unsigned int dco, d, i; 1506 unsigned int p0, p1, p2; 1507 1508 skl_wrpll_context_init(&ctx); 1509 1510 for (d = 0; d < ARRAY_SIZE(dividers); d++) { 1511 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { 1512 for (i = 0; i < dividers[d].n_dividers; i++) { 1513 unsigned int p = dividers[d].list[i]; 1514 uint64_t dco_freq = p * afe_clock; 1515 1516 skl_wrpll_try_divider(&ctx, 1517 dco_central_freq[dco], 1518 dco_freq, 1519 p); 1520 /* 1521 * Skip the remaining dividers if we're sure to 1522 * have found the definitive divider, we can't 1523 * improve a 0 deviation. 1524 */ 1525 if (ctx.min_deviation == 0) 1526 goto skip_remaining_dividers; 1527 } 1528 } 1529 1530 skip_remaining_dividers: 1531 /* 1532 * If a solution is found with an even divider, prefer 1533 * this one. 1534 */ 1535 if (d == 0 && ctx.p) 1536 break; 1537 } 1538 1539 if (!ctx.p) { 1540 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); 1541 return false; 1542 } 1543 1544 /* 1545 * gcc incorrectly analyses that these can be used without being 1546 * initialized. To be fair, it's hard to guess. 1547 */ 1548 p0 = p1 = p2 = 0; 1549 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); 1550 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, 1551 p0, p1, p2); 1552 1553 return true; 1554 } 1555 1556 static bool 1557 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1558 struct intel_crtc_state *crtc_state, 1559 struct intel_encoder *intel_encoder) 1560 { 1561 struct intel_shared_dpll *pll; 1562 uint32_t ctrl1, cfgcr1, cfgcr2; 1563 int clock = crtc_state->port_clock; 1564 1565 /* 1566 * See comment in intel_dpll_hw_state to understand why we always use 0 1567 * as the DPLL id in this function. 1568 */ 1569 1570 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1571 1572 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1573 struct skl_wrpll_params wrpll_params = { 0, }; 1574 1575 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1576 1577 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) 1578 return false; 1579 1580 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1581 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1582 wrpll_params.dco_integer; 1583 1584 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1585 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1586 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1587 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1588 wrpll_params.central_freq; 1589 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1590 switch (crtc_state->port_clock / 2) { 1591 case 81000: 1592 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1593 break; 1594 case 135000: 1595 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1596 break; 1597 case 270000: 1598 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1599 break; 1600 } 1601 1602 cfgcr1 = cfgcr2 = 0; 1603 } else /* eDP */ 1604 return true; 1605 1606 memset(&crtc_state->dpll_hw_state, 0, 1607 sizeof(crtc_state->dpll_hw_state)); 1608 1609 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1610 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1611 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1612 1613 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1614 if (pll == NULL) { 1615 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1616 pipe_name(intel_crtc->pipe)); 1617 return false; 1618 } 1619 1620 /* shared DPLL id 0 is DPLL 1 */ 1621 crtc_state->ddi_pll_sel = pll->id + 1; 1622 1623 return true; 1624 } 1625 1626 /* bxt clock parameters */ 1627 struct bxt_clk_div { 1628 int clock; 1629 uint32_t p1; 1630 uint32_t p2; 1631 uint32_t m2_int; 1632 uint32_t m2_frac; 1633 bool m2_frac_en; 1634 uint32_t n; 1635 }; 1636 1637 /* pre-calculated values for DP linkrates */ 1638 static const struct bxt_clk_div bxt_dp_clk_val[] = { 1639 {162000, 4, 2, 32, 1677722, 1, 1}, 1640 {270000, 4, 1, 27, 0, 0, 1}, 1641 {540000, 2, 1, 27, 0, 0, 1}, 1642 {216000, 3, 2, 32, 1677722, 1, 1}, 1643 {243000, 4, 1, 24, 1258291, 1, 1}, 1644 {324000, 4, 1, 32, 1677722, 1, 1}, 1645 {432000, 3, 1, 32, 1677722, 1, 1} 1646 }; 1647 1648 static bool 1649 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 1650 struct intel_crtc_state *crtc_state, 1651 struct intel_encoder *intel_encoder) 1652 { 1653 struct intel_shared_dpll *pll; 1654 struct bxt_clk_div clk_div = {0}; 1655 int vco = 0; 1656 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1657 uint32_t lanestagger; 1658 int clock = crtc_state->port_clock; 1659 1660 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1661 intel_clock_t best_clock; 1662 1663 /* Calculate HDMI div */ 1664 /* 1665 * FIXME: tie the following calculation into 1666 * i9xx_crtc_compute_clock 1667 */ 1668 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1669 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1670 clock, pipe_name(intel_crtc->pipe)); 1671 return false; 1672 } 1673 1674 clk_div.p1 = best_clock.p1; 1675 clk_div.p2 = best_clock.p2; 1676 WARN_ON(best_clock.m1 != 2); 1677 clk_div.n = best_clock.n; 1678 clk_div.m2_int = best_clock.m2 >> 22; 1679 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1680 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1681 1682 vco = best_clock.vco; 1683 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1684 intel_encoder->type == INTEL_OUTPUT_EDP) { 1685 int i; 1686 1687 clk_div = bxt_dp_clk_val[0]; 1688 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { 1689 if (bxt_dp_clk_val[i].clock == clock) { 1690 clk_div = bxt_dp_clk_val[i]; 1691 break; 1692 } 1693 } 1694 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1695 } 1696 1697 if (vco >= 6200000 && vco <= 6700000) { 1698 prop_coef = 4; 1699 int_coef = 9; 1700 gain_ctl = 3; 1701 targ_cnt = 8; 1702 } else if ((vco > 5400000 && vco < 6200000) || 1703 (vco >= 4800000 && vco < 5400000)) { 1704 prop_coef = 5; 1705 int_coef = 11; 1706 gain_ctl = 3; 1707 targ_cnt = 9; 1708 } else if (vco == 5400000) { 1709 prop_coef = 3; 1710 int_coef = 8; 1711 gain_ctl = 1; 1712 targ_cnt = 9; 1713 } else { 1714 DRM_ERROR("Invalid VCO\n"); 1715 return false; 1716 } 1717 1718 memset(&crtc_state->dpll_hw_state, 0, 1719 sizeof(crtc_state->dpll_hw_state)); 1720 1721 if (clock > 270000) 1722 lanestagger = 0x18; 1723 else if (clock > 135000) 1724 lanestagger = 0x0d; 1725 else if (clock > 67000) 1726 lanestagger = 0x07; 1727 else if (clock > 33000) 1728 lanestagger = 0x04; 1729 else 1730 lanestagger = 0x02; 1731 1732 crtc_state->dpll_hw_state.ebb0 = 1733 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1734 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1735 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1736 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1737 1738 if (clk_div.m2_frac_en) 1739 crtc_state->dpll_hw_state.pll3 = 1740 PORT_PLL_M2_FRAC_ENABLE; 1741 1742 crtc_state->dpll_hw_state.pll6 = 1743 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1744 crtc_state->dpll_hw_state.pll6 |= 1745 PORT_PLL_GAIN_CTL(gain_ctl); 1746 1747 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1748 1749 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; 1750 1751 crtc_state->dpll_hw_state.pll10 = 1752 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) 1753 | PORT_PLL_DCO_AMP_OVR_EN_H; 1754 1755 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; 1756 1757 crtc_state->dpll_hw_state.pcsdw12 = 1758 LANESTAGGER_STRAP_OVRD | lanestagger; 1759 1760 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1761 if (pll == NULL) { 1762 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1763 pipe_name(intel_crtc->pipe)); 1764 return false; 1765 } 1766 1767 /* shared DPLL id 0 is DPLL A */ 1768 crtc_state->ddi_pll_sel = pll->id; 1769 1770 return true; 1771 } 1772 1773 /* 1774 * Tries to find a *shared* PLL for the CRTC and store it in 1775 * intel_crtc->ddi_pll_sel. 1776 * 1777 * For private DPLLs, compute_config() should do the selection for us. This 1778 * function should be folded into compute_config() eventually. 1779 */ 1780 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1781 struct intel_crtc_state *crtc_state) 1782 { 1783 struct drm_device *dev = intel_crtc->base.dev; 1784 struct intel_encoder *intel_encoder = 1785 intel_ddi_get_crtc_new_encoder(crtc_state); 1786 1787 if (IS_SKYLAKE(dev)) 1788 return skl_ddi_pll_select(intel_crtc, crtc_state, 1789 intel_encoder); 1790 else if (IS_BROXTON(dev)) 1791 return bxt_ddi_pll_select(intel_crtc, crtc_state, 1792 intel_encoder); 1793 else 1794 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1795 intel_encoder); 1796 } 1797 1798 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1799 { 1800 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1802 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1803 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1804 int type = intel_encoder->type; 1805 uint32_t temp; 1806 1807 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1808 temp = TRANS_MSA_SYNC_CLK; 1809 switch (intel_crtc->config->pipe_bpp) { 1810 case 18: 1811 temp |= TRANS_MSA_6_BPC; 1812 break; 1813 case 24: 1814 temp |= TRANS_MSA_8_BPC; 1815 break; 1816 case 30: 1817 temp |= TRANS_MSA_10_BPC; 1818 break; 1819 case 36: 1820 temp |= TRANS_MSA_12_BPC; 1821 break; 1822 default: 1823 BUG(); 1824 } 1825 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1826 } 1827 } 1828 1829 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1830 { 1831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1832 struct drm_device *dev = crtc->dev; 1833 struct drm_i915_private *dev_priv = dev->dev_private; 1834 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1835 uint32_t temp; 1836 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1837 if (state == true) 1838 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1839 else 1840 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1841 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1842 } 1843 1844 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1845 { 1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1847 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1848 struct drm_encoder *encoder = &intel_encoder->base; 1849 struct drm_device *dev = crtc->dev; 1850 struct drm_i915_private *dev_priv = dev->dev_private; 1851 enum i915_pipe pipe = intel_crtc->pipe; 1852 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1853 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1854 int type = intel_encoder->type; 1855 uint32_t temp; 1856 1857 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1858 temp = TRANS_DDI_FUNC_ENABLE; 1859 temp |= TRANS_DDI_SELECT_PORT(port); 1860 1861 switch (intel_crtc->config->pipe_bpp) { 1862 case 18: 1863 temp |= TRANS_DDI_BPC_6; 1864 break; 1865 case 24: 1866 temp |= TRANS_DDI_BPC_8; 1867 break; 1868 case 30: 1869 temp |= TRANS_DDI_BPC_10; 1870 break; 1871 case 36: 1872 temp |= TRANS_DDI_BPC_12; 1873 break; 1874 default: 1875 BUG(); 1876 } 1877 1878 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1879 temp |= TRANS_DDI_PVSYNC; 1880 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1881 temp |= TRANS_DDI_PHSYNC; 1882 1883 if (cpu_transcoder == TRANSCODER_EDP) { 1884 switch (pipe) { 1885 case PIPE_A: 1886 /* On Haswell, can only use the always-on power well for 1887 * eDP when not using the panel fitter, and when not 1888 * using motion blur mitigation (which we don't 1889 * support). */ 1890 if (IS_HASWELL(dev) && 1891 (intel_crtc->config->pch_pfit.enabled || 1892 intel_crtc->config->pch_pfit.force_thru)) 1893 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1894 else 1895 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1896 break; 1897 case PIPE_B: 1898 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1899 break; 1900 case PIPE_C: 1901 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1902 break; 1903 default: 1904 BUG(); 1905 break; 1906 } 1907 } 1908 1909 if (type == INTEL_OUTPUT_HDMI) { 1910 if (intel_crtc->config->has_hdmi_sink) 1911 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1912 else 1913 temp |= TRANS_DDI_MODE_SELECT_DVI; 1914 1915 } else if (type == INTEL_OUTPUT_ANALOG) { 1916 temp |= TRANS_DDI_MODE_SELECT_FDI; 1917 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1918 1919 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1920 type == INTEL_OUTPUT_EDP) { 1921 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1922 1923 if (intel_dp->is_mst) { 1924 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1925 } else 1926 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1927 1928 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1929 } else if (type == INTEL_OUTPUT_DP_MST) { 1930 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1931 1932 if (intel_dp->is_mst) { 1933 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1934 } else 1935 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1936 1937 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1938 } else { 1939 WARN(1, "Invalid encoder type %d for pipe %c\n", 1940 intel_encoder->type, pipe_name(pipe)); 1941 } 1942 1943 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1944 } 1945 1946 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1947 enum transcoder cpu_transcoder) 1948 { 1949 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1950 uint32_t val = I915_READ(reg); 1951 1952 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1953 val |= TRANS_DDI_PORT_NONE; 1954 I915_WRITE(reg, val); 1955 } 1956 1957 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1958 { 1959 struct drm_device *dev = intel_connector->base.dev; 1960 struct drm_i915_private *dev_priv = dev->dev_private; 1961 struct intel_encoder *intel_encoder = intel_connector->encoder; 1962 int type = intel_connector->base.connector_type; 1963 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1964 enum i915_pipe pipe = 0; 1965 enum transcoder cpu_transcoder; 1966 enum intel_display_power_domain power_domain; 1967 uint32_t tmp; 1968 1969 power_domain = intel_display_port_power_domain(intel_encoder); 1970 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1971 return false; 1972 1973 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1974 return false; 1975 1976 if (port == PORT_A) 1977 cpu_transcoder = TRANSCODER_EDP; 1978 else 1979 cpu_transcoder = (enum transcoder) pipe; 1980 1981 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1982 1983 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1984 case TRANS_DDI_MODE_SELECT_HDMI: 1985 case TRANS_DDI_MODE_SELECT_DVI: 1986 return (type == DRM_MODE_CONNECTOR_HDMIA); 1987 1988 case TRANS_DDI_MODE_SELECT_DP_SST: 1989 if (type == DRM_MODE_CONNECTOR_eDP) 1990 return true; 1991 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1992 case TRANS_DDI_MODE_SELECT_DP_MST: 1993 /* if the transcoder is in MST state then 1994 * connector isn't connected */ 1995 return false; 1996 1997 case TRANS_DDI_MODE_SELECT_FDI: 1998 return (type == DRM_MODE_CONNECTOR_VGA); 1999 2000 default: 2001 return false; 2002 } 2003 } 2004 2005 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2006 enum i915_pipe *pipe) 2007 { 2008 struct drm_device *dev = encoder->base.dev; 2009 struct drm_i915_private *dev_priv = dev->dev_private; 2010 enum port port = intel_ddi_get_encoder_port(encoder); 2011 enum intel_display_power_domain power_domain; 2012 u32 tmp; 2013 int i; 2014 2015 power_domain = intel_display_port_power_domain(encoder); 2016 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 2017 return false; 2018 2019 tmp = I915_READ(DDI_BUF_CTL(port)); 2020 2021 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2022 return false; 2023 2024 if (port == PORT_A) { 2025 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2026 2027 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2028 case TRANS_DDI_EDP_INPUT_A_ON: 2029 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2030 *pipe = PIPE_A; 2031 break; 2032 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2033 *pipe = PIPE_B; 2034 break; 2035 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2036 *pipe = PIPE_C; 2037 break; 2038 } 2039 2040 return true; 2041 } else { 2042 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 2043 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 2044 2045 if ((tmp & TRANS_DDI_PORT_MASK) 2046 == TRANS_DDI_SELECT_PORT(port)) { 2047 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) 2048 return false; 2049 2050 *pipe = i; 2051 return true; 2052 } 2053 } 2054 } 2055 2056 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 2057 2058 return false; 2059 } 2060 2061 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 2062 { 2063 struct drm_crtc *crtc = &intel_crtc->base; 2064 struct drm_device *dev = crtc->dev; 2065 struct drm_i915_private *dev_priv = dev->dev_private; 2066 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2067 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2068 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2069 2070 if (cpu_transcoder != TRANSCODER_EDP) 2071 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2072 TRANS_CLK_SEL_PORT(port)); 2073 } 2074 2075 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 2076 { 2077 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 2078 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2079 2080 if (cpu_transcoder != TRANSCODER_EDP) 2081 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2082 TRANS_CLK_SEL_DISABLED); 2083 } 2084 2085 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level, 2086 enum port port, int type) 2087 { 2088 struct drm_i915_private *dev_priv = dev->dev_private; 2089 const struct ddi_buf_trans *ddi_translations; 2090 uint8_t iboost; 2091 uint8_t dp_iboost, hdmi_iboost; 2092 int n_entries; 2093 u32 reg; 2094 2095 /* VBT may override standard boost values */ 2096 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2097 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2098 2099 if (type == INTEL_OUTPUT_DISPLAYPORT) { 2100 if (dp_iboost) { 2101 iboost = dp_iboost; 2102 } else { 2103 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries); 2104 iboost = ddi_translations[port].i_boost; 2105 } 2106 } else if (type == INTEL_OUTPUT_EDP) { 2107 if (dp_iboost) { 2108 iboost = dp_iboost; 2109 } else { 2110 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries); 2111 iboost = ddi_translations[port].i_boost; 2112 } 2113 } else if (type == INTEL_OUTPUT_HDMI) { 2114 if (hdmi_iboost) { 2115 iboost = hdmi_iboost; 2116 } else { 2117 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries); 2118 iboost = ddi_translations[port].i_boost; 2119 } 2120 } else { 2121 return; 2122 } 2123 2124 /* Make sure that the requested I_boost is valid */ 2125 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2126 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2127 return; 2128 } 2129 2130 reg = I915_READ(DISPIO_CR_TX_BMU_CR0); 2131 reg &= ~BALANCE_LEG_MASK(port); 2132 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); 2133 2134 if (iboost) 2135 reg |= iboost << BALANCE_LEG_SHIFT(port); 2136 else 2137 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); 2138 2139 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); 2140 } 2141 2142 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 2143 enum port port, int type) 2144 { 2145 struct drm_i915_private *dev_priv = dev->dev_private; 2146 const struct bxt_ddi_buf_trans *ddi_translations; 2147 u32 n_entries, i; 2148 uint32_t val; 2149 2150 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) { 2151 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 2152 ddi_translations = bxt_ddi_translations_edp; 2153 } else if (type == INTEL_OUTPUT_DISPLAYPORT 2154 || type == INTEL_OUTPUT_EDP) { 2155 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 2156 ddi_translations = bxt_ddi_translations_dp; 2157 } else if (type == INTEL_OUTPUT_HDMI) { 2158 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 2159 ddi_translations = bxt_ddi_translations_hdmi; 2160 } else { 2161 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 2162 type); 2163 return; 2164 } 2165 2166 /* Check if default value has to be used */ 2167 if (level >= n_entries || 2168 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 2169 for (i = 0; i < n_entries; i++) { 2170 if (ddi_translations[i].default_index) { 2171 level = i; 2172 break; 2173 } 2174 } 2175 } 2176 2177 /* 2178 * While we write to the group register to program all lanes at once we 2179 * can read only lane registers and we pick lanes 0/1 for that. 2180 */ 2181 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2182 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 2183 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2184 2185 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); 2186 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 2187 val |= ddi_translations[level].margin << MARGIN_000_SHIFT | 2188 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; 2189 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); 2190 2191 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); 2192 val &= ~SCALE_DCOMP_METHOD; 2193 if (ddi_translations[level].enable) 2194 val |= SCALE_DCOMP_METHOD; 2195 2196 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 2197 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); 2198 2199 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); 2200 2201 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); 2202 val &= ~DE_EMPHASIS; 2203 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; 2204 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); 2205 2206 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2207 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 2208 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2209 } 2210 2211 static uint32_t translate_signal_level(int signal_levels) 2212 { 2213 uint32_t level; 2214 2215 switch (signal_levels) { 2216 default: 2217 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2218 signal_levels); 2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2220 level = 0; 2221 break; 2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2223 level = 1; 2224 break; 2225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2226 level = 2; 2227 break; 2228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: 2229 level = 3; 2230 break; 2231 2232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2233 level = 4; 2234 break; 2235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2236 level = 5; 2237 break; 2238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2239 level = 6; 2240 break; 2241 2242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2243 level = 7; 2244 break; 2245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2246 level = 8; 2247 break; 2248 2249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2250 level = 9; 2251 break; 2252 } 2253 2254 return level; 2255 } 2256 2257 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 2258 { 2259 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2260 struct drm_device *dev = dport->base.base.dev; 2261 struct intel_encoder *encoder = &dport->base; 2262 uint8_t train_set = intel_dp->train_set[0]; 2263 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2264 DP_TRAIN_PRE_EMPHASIS_MASK); 2265 enum port port = dport->port; 2266 uint32_t level; 2267 2268 level = translate_signal_level(signal_levels); 2269 2270 if (IS_SKYLAKE(dev)) 2271 skl_ddi_set_iboost(dev, level, port, encoder->type); 2272 else if (IS_BROXTON(dev)) 2273 bxt_ddi_vswing_sequence(dev, level, port, encoder->type); 2274 2275 return DDI_BUF_TRANS_SELECT(level); 2276 } 2277 2278 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 2279 { 2280 struct drm_encoder *encoder = &intel_encoder->base; 2281 struct drm_device *dev = encoder->dev; 2282 struct drm_i915_private *dev_priv = dev->dev_private; 2283 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 2284 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2285 int type = intel_encoder->type; 2286 int hdmi_level; 2287 2288 if (type == INTEL_OUTPUT_EDP) { 2289 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2290 intel_edp_panel_on(intel_dp); 2291 } 2292 2293 if (IS_SKYLAKE(dev)) { 2294 uint32_t dpll = crtc->config->ddi_pll_sel; 2295 uint32_t val; 2296 2297 /* 2298 * DPLL0 is used for eDP and is the only "private" DPLL (as 2299 * opposed to shared) on SKL 2300 */ 2301 if (type == INTEL_OUTPUT_EDP) { 2302 WARN_ON(dpll != SKL_DPLL0); 2303 2304 val = I915_READ(DPLL_CTRL1); 2305 2306 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 2307 DPLL_CTRL1_SSC(dpll) | 2308 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2309 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); 2310 2311 I915_WRITE(DPLL_CTRL1, val); 2312 POSTING_READ(DPLL_CTRL1); 2313 } 2314 2315 /* DDI -> PLL mapping */ 2316 val = I915_READ(DPLL_CTRL2); 2317 2318 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2319 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2320 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 2321 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2322 2323 I915_WRITE(DPLL_CTRL2, val); 2324 2325 } else if (INTEL_INFO(dev)->gen < 9) { 2326 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); 2327 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); 2328 } 2329 2330 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2331 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2332 2333 intel_dp_set_link_params(intel_dp, crtc->config); 2334 2335 intel_ddi_init_dp_buf_reg(intel_encoder); 2336 2337 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2338 intel_dp_start_link_train(intel_dp); 2339 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) 2340 intel_dp_stop_link_train(intel_dp); 2341 } else if (type == INTEL_OUTPUT_HDMI) { 2342 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2343 2344 if (IS_BROXTON(dev)) { 2345 hdmi_level = dev_priv->vbt. 2346 ddi_port_info[port].hdmi_level_shift; 2347 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 2348 INTEL_OUTPUT_HDMI); 2349 } 2350 intel_hdmi->set_infoframes(encoder, 2351 crtc->config->has_hdmi_sink, 2352 &crtc->config->base.adjusted_mode); 2353 } 2354 } 2355 2356 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 2357 { 2358 struct drm_encoder *encoder = &intel_encoder->base; 2359 struct drm_device *dev = encoder->dev; 2360 struct drm_i915_private *dev_priv = dev->dev_private; 2361 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2362 int type = intel_encoder->type; 2363 uint32_t val; 2364 bool wait = false; 2365 2366 val = I915_READ(DDI_BUF_CTL(port)); 2367 if (val & DDI_BUF_CTL_ENABLE) { 2368 val &= ~DDI_BUF_CTL_ENABLE; 2369 I915_WRITE(DDI_BUF_CTL(port), val); 2370 wait = true; 2371 } 2372 2373 val = I915_READ(DP_TP_CTL(port)); 2374 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2375 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2376 I915_WRITE(DP_TP_CTL(port), val); 2377 2378 if (wait) 2379 intel_wait_ddi_buf_idle(dev_priv, port); 2380 2381 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2382 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2383 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2384 intel_edp_panel_vdd_on(intel_dp); 2385 intel_edp_panel_off(intel_dp); 2386 } 2387 2388 if (IS_SKYLAKE(dev)) 2389 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 2390 DPLL_CTRL2_DDI_CLK_OFF(port))); 2391 else if (INTEL_INFO(dev)->gen < 9) 2392 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2393 } 2394 2395 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 2396 { 2397 struct drm_encoder *encoder = &intel_encoder->base; 2398 struct drm_crtc *crtc = encoder->crtc; 2399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2400 struct drm_device *dev = encoder->dev; 2401 struct drm_i915_private *dev_priv = dev->dev_private; 2402 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2403 int type = intel_encoder->type; 2404 2405 if (type == INTEL_OUTPUT_HDMI) { 2406 struct intel_digital_port *intel_dig_port = 2407 enc_to_dig_port(encoder); 2408 2409 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2410 * are ignored so nothing special needs to be done besides 2411 * enabling the port. 2412 */ 2413 I915_WRITE(DDI_BUF_CTL(port), 2414 intel_dig_port->saved_port_bits | 2415 DDI_BUF_CTL_ENABLE); 2416 } else if (type == INTEL_OUTPUT_EDP) { 2417 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2418 2419 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 2420 intel_dp_stop_link_train(intel_dp); 2421 2422 intel_edp_backlight_on(intel_dp); 2423 intel_psr_enable(intel_dp); 2424 intel_edp_drrs_enable(intel_dp); 2425 } 2426 2427 if (intel_crtc->config->has_audio) { 2428 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 2429 intel_audio_codec_enable(intel_encoder); 2430 } 2431 } 2432 2433 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 2434 { 2435 struct drm_encoder *encoder = &intel_encoder->base; 2436 struct drm_crtc *crtc = encoder->crtc; 2437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2438 int type = intel_encoder->type; 2439 struct drm_device *dev = encoder->dev; 2440 struct drm_i915_private *dev_priv = dev->dev_private; 2441 2442 if (intel_crtc->config->has_audio) { 2443 intel_audio_codec_disable(intel_encoder); 2444 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 2445 } 2446 2447 if (type == INTEL_OUTPUT_EDP) { 2448 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2449 2450 intel_edp_drrs_disable(intel_dp); 2451 intel_psr_disable(intel_dp); 2452 intel_edp_backlight_off(intel_dp); 2453 } 2454 } 2455 2456 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, 2457 struct intel_shared_dpll *pll) 2458 { 2459 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 2460 POSTING_READ(WRPLL_CTL(pll->id)); 2461 udelay(20); 2462 } 2463 2464 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, 2465 struct intel_shared_dpll *pll) 2466 { 2467 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); 2468 POSTING_READ(SPLL_CTL); 2469 udelay(20); 2470 } 2471 2472 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 2473 struct intel_shared_dpll *pll) 2474 { 2475 uint32_t val; 2476 2477 val = I915_READ(WRPLL_CTL(pll->id)); 2478 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 2479 POSTING_READ(WRPLL_CTL(pll->id)); 2480 } 2481 2482 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 2483 struct intel_shared_dpll *pll) 2484 { 2485 uint32_t val; 2486 2487 val = I915_READ(SPLL_CTL); 2488 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 2489 POSTING_READ(SPLL_CTL); 2490 } 2491 2492 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, 2493 struct intel_shared_dpll *pll, 2494 struct intel_dpll_hw_state *hw_state) 2495 { 2496 uint32_t val; 2497 2498 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2499 return false; 2500 2501 val = I915_READ(WRPLL_CTL(pll->id)); 2502 hw_state->wrpll = val; 2503 2504 return val & WRPLL_PLL_ENABLE; 2505 } 2506 2507 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 2508 struct intel_shared_dpll *pll, 2509 struct intel_dpll_hw_state *hw_state) 2510 { 2511 uint32_t val; 2512 2513 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2514 return false; 2515 2516 val = I915_READ(SPLL_CTL); 2517 hw_state->spll = val; 2518 2519 return val & SPLL_PLL_ENABLE; 2520 } 2521 2522 2523 static const char * const hsw_ddi_pll_names[] = { 2524 "WRPLL 1", 2525 "WRPLL 2", 2526 "SPLL" 2527 }; 2528 2529 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 2530 { 2531 int i; 2532 2533 dev_priv->num_shared_dpll = 3; 2534 2535 for (i = 0; i < 2; i++) { 2536 dev_priv->shared_dplls[i].id = i; 2537 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2538 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; 2539 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; 2540 dev_priv->shared_dplls[i].get_hw_state = 2541 hsw_ddi_wrpll_get_hw_state; 2542 } 2543 2544 /* SPLL is special, but needs to be initialized anyway.. */ 2545 dev_priv->shared_dplls[i].id = i; 2546 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2547 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; 2548 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; 2549 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; 2550 2551 } 2552 2553 static const char * const skl_ddi_pll_names[] = { 2554 "DPLL 1", 2555 "DPLL 2", 2556 "DPLL 3", 2557 }; 2558 2559 struct skl_dpll_regs { 2560 u32 ctl, cfgcr1, cfgcr2; 2561 }; 2562 2563 /* this array is indexed by the *shared* pll id */ 2564 static const struct skl_dpll_regs skl_dpll_regs[3] = { 2565 { 2566 /* DPLL 1 */ 2567 .ctl = LCPLL2_CTL, 2568 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), 2569 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), 2570 }, 2571 { 2572 /* DPLL 2 */ 2573 .ctl = WRPLL_CTL1, 2574 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), 2575 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), 2576 }, 2577 { 2578 /* DPLL 3 */ 2579 .ctl = WRPLL_CTL2, 2580 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), 2581 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), 2582 }, 2583 }; 2584 2585 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 2586 struct intel_shared_dpll *pll) 2587 { 2588 uint32_t val; 2589 unsigned int dpll; 2590 const struct skl_dpll_regs *regs = skl_dpll_regs; 2591 2592 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2593 dpll = pll->id + 1; 2594 2595 val = I915_READ(DPLL_CTRL1); 2596 2597 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 2598 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2599 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 2600 2601 I915_WRITE(DPLL_CTRL1, val); 2602 POSTING_READ(DPLL_CTRL1); 2603 2604 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 2605 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 2606 POSTING_READ(regs[pll->id].cfgcr1); 2607 POSTING_READ(regs[pll->id].cfgcr2); 2608 2609 /* the enable bit is always bit 31 */ 2610 I915_WRITE(regs[pll->id].ctl, 2611 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 2612 2613 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 2614 DRM_ERROR("DPLL %d not locked\n", dpll); 2615 } 2616 2617 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 2618 struct intel_shared_dpll *pll) 2619 { 2620 const struct skl_dpll_regs *regs = skl_dpll_regs; 2621 2622 /* the enable bit is always bit 31 */ 2623 I915_WRITE(regs[pll->id].ctl, 2624 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 2625 POSTING_READ(regs[pll->id].ctl); 2626 } 2627 2628 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2629 struct intel_shared_dpll *pll, 2630 struct intel_dpll_hw_state *hw_state) 2631 { 2632 uint32_t val; 2633 unsigned int dpll; 2634 const struct skl_dpll_regs *regs = skl_dpll_regs; 2635 2636 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2637 return false; 2638 2639 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2640 dpll = pll->id + 1; 2641 2642 val = I915_READ(regs[pll->id].ctl); 2643 if (!(val & LCPLL_PLL_ENABLE)) 2644 return false; 2645 2646 val = I915_READ(DPLL_CTRL1); 2647 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 2648 2649 /* avoid reading back stale values if HDMI mode is not enabled */ 2650 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 2651 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 2652 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 2653 } 2654 2655 return true; 2656 } 2657 2658 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 2659 { 2660 int i; 2661 2662 dev_priv->num_shared_dpll = 3; 2663 2664 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2665 dev_priv->shared_dplls[i].id = i; 2666 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 2667 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 2668 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 2669 dev_priv->shared_dplls[i].get_hw_state = 2670 skl_ddi_pll_get_hw_state; 2671 } 2672 } 2673 2674 static void broxton_phy_init(struct drm_i915_private *dev_priv, 2675 enum dpio_phy phy) 2676 { 2677 enum port port; 2678 uint32_t val; 2679 2680 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 2681 val |= GT_DISPLAY_POWER_ON(phy); 2682 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 2683 2684 /* Considering 10ms timeout until BSpec is updated */ 2685 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) 2686 DRM_ERROR("timeout during PHY%d power on\n", phy); 2687 2688 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); 2689 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { 2690 int lane; 2691 2692 for (lane = 0; lane < 4; lane++) { 2693 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); 2694 /* 2695 * Note that on CHV this flag is called UPAR, but has 2696 * the same function. 2697 */ 2698 val &= ~LATENCY_OPTIM; 2699 if (lane != 1) 2700 val |= LATENCY_OPTIM; 2701 2702 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); 2703 } 2704 } 2705 2706 /* Program PLL Rcomp code offset */ 2707 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 2708 val &= ~IREF0RC_OFFSET_MASK; 2709 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 2710 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 2711 2712 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 2713 val &= ~IREF1RC_OFFSET_MASK; 2714 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 2715 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 2716 2717 /* Program power gating */ 2718 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 2719 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 2720 SUS_CLK_CONFIG; 2721 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 2722 2723 if (phy == DPIO_PHY0) { 2724 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); 2725 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 2726 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); 2727 } 2728 2729 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); 2730 val &= ~OCL2_LDOFUSE_PWR_DIS; 2731 /* 2732 * On PHY1 disable power on the second channel, since no port is 2733 * connected there. On PHY0 both channels have a port, so leave it 2734 * enabled. 2735 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should 2736 * power down the second channel on PHY0 as well. 2737 */ 2738 if (phy == DPIO_PHY1) 2739 val |= OCL2_LDOFUSE_PWR_DIS; 2740 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); 2741 2742 if (phy == DPIO_PHY0) { 2743 uint32_t grc_code; 2744 /* 2745 * PHY0 isn't connected to an RCOMP resistor so copy over 2746 * the corresponding calibrated value from PHY1, and disable 2747 * the automatic calibration on PHY0. 2748 */ 2749 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, 2750 10)) 2751 DRM_ERROR("timeout waiting for PHY1 GRC\n"); 2752 2753 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); 2754 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 2755 grc_code = val << GRC_CODE_FAST_SHIFT | 2756 val << GRC_CODE_SLOW_SHIFT | 2757 val; 2758 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); 2759 2760 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); 2761 val |= GRC_DIS | GRC_RDY_OVRD; 2762 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); 2763 } 2764 2765 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2766 val |= COMMON_RESET_DIS; 2767 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2768 } 2769 2770 void broxton_ddi_phy_init(struct drm_device *dev) 2771 { 2772 /* Enable PHY1 first since it provides Rcomp for PHY0 */ 2773 broxton_phy_init(dev->dev_private, DPIO_PHY1); 2774 broxton_phy_init(dev->dev_private, DPIO_PHY0); 2775 } 2776 2777 static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 2778 enum dpio_phy phy) 2779 { 2780 uint32_t val; 2781 2782 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2783 val &= ~COMMON_RESET_DIS; 2784 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2785 } 2786 2787 void broxton_ddi_phy_uninit(struct drm_device *dev) 2788 { 2789 struct drm_i915_private *dev_priv = dev->dev_private; 2790 2791 broxton_phy_uninit(dev_priv, DPIO_PHY1); 2792 broxton_phy_uninit(dev_priv, DPIO_PHY0); 2793 2794 /* FIXME: do this in broxton_phy_uninit per phy */ 2795 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); 2796 } 2797 2798 static const char * const bxt_ddi_pll_names[] = { 2799 "PORT PLL A", 2800 "PORT PLL B", 2801 "PORT PLL C", 2802 }; 2803 2804 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 2805 struct intel_shared_dpll *pll) 2806 { 2807 uint32_t temp; 2808 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2809 2810 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2811 temp &= ~PORT_PLL_REF_SEL; 2812 /* Non-SSC reference */ 2813 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2814 2815 /* Disable 10 bit clock */ 2816 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2817 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2818 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2819 2820 /* Write P1 & P2 */ 2821 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2822 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 2823 temp |= pll->config.hw_state.ebb0; 2824 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 2825 2826 /* Write M2 integer */ 2827 temp = I915_READ(BXT_PORT_PLL(port, 0)); 2828 temp &= ~PORT_PLL_M2_MASK; 2829 temp |= pll->config.hw_state.pll0; 2830 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 2831 2832 /* Write N */ 2833 temp = I915_READ(BXT_PORT_PLL(port, 1)); 2834 temp &= ~PORT_PLL_N_MASK; 2835 temp |= pll->config.hw_state.pll1; 2836 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 2837 2838 /* Write M2 fraction */ 2839 temp = I915_READ(BXT_PORT_PLL(port, 2)); 2840 temp &= ~PORT_PLL_M2_FRAC_MASK; 2841 temp |= pll->config.hw_state.pll2; 2842 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 2843 2844 /* Write M2 fraction enable */ 2845 temp = I915_READ(BXT_PORT_PLL(port, 3)); 2846 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 2847 temp |= pll->config.hw_state.pll3; 2848 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 2849 2850 /* Write coeff */ 2851 temp = I915_READ(BXT_PORT_PLL(port, 6)); 2852 temp &= ~PORT_PLL_PROP_COEFF_MASK; 2853 temp &= ~PORT_PLL_INT_COEFF_MASK; 2854 temp &= ~PORT_PLL_GAIN_CTL_MASK; 2855 temp |= pll->config.hw_state.pll6; 2856 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 2857 2858 /* Write calibration val */ 2859 temp = I915_READ(BXT_PORT_PLL(port, 8)); 2860 temp &= ~PORT_PLL_TARGET_CNT_MASK; 2861 temp |= pll->config.hw_state.pll8; 2862 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 2863 2864 temp = I915_READ(BXT_PORT_PLL(port, 9)); 2865 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 2866 temp |= pll->config.hw_state.pll9; 2867 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 2868 2869 temp = I915_READ(BXT_PORT_PLL(port, 10)); 2870 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 2871 temp &= ~PORT_PLL_DCO_AMP_MASK; 2872 temp |= pll->config.hw_state.pll10; 2873 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 2874 2875 /* Recalibrate with new settings */ 2876 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2877 temp |= PORT_PLL_RECALIBRATE; 2878 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2879 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2880 temp |= pll->config.hw_state.ebb4; 2881 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2882 2883 /* Enable PLL */ 2884 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2885 temp |= PORT_PLL_ENABLE; 2886 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2887 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2888 2889 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & 2890 PORT_PLL_LOCK), 200)) 2891 DRM_ERROR("PLL %d not locked\n", port); 2892 2893 /* 2894 * While we write to the group register to program all lanes at once we 2895 * can read only lane registers and we pick lanes 0/1 for that. 2896 */ 2897 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2898 temp &= ~LANE_STAGGER_MASK; 2899 temp &= ~LANESTAGGER_STRAP_OVRD; 2900 temp |= pll->config.hw_state.pcsdw12; 2901 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 2902 } 2903 2904 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 2905 struct intel_shared_dpll *pll) 2906 { 2907 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2908 uint32_t temp; 2909 2910 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2911 temp &= ~PORT_PLL_ENABLE; 2912 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2913 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2914 } 2915 2916 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2917 struct intel_shared_dpll *pll, 2918 struct intel_dpll_hw_state *hw_state) 2919 { 2920 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2921 uint32_t val; 2922 2923 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2924 return false; 2925 2926 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2927 if (!(val & PORT_PLL_ENABLE)) 2928 return false; 2929 2930 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2931 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; 2932 2933 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2934 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; 2935 2936 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 2937 hw_state->pll0 &= PORT_PLL_M2_MASK; 2938 2939 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 2940 hw_state->pll1 &= PORT_PLL_N_MASK; 2941 2942 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 2943 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; 2944 2945 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 2946 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; 2947 2948 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 2949 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | 2950 PORT_PLL_INT_COEFF_MASK | 2951 PORT_PLL_GAIN_CTL_MASK; 2952 2953 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 2954 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; 2955 2956 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); 2957 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; 2958 2959 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 2960 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | 2961 PORT_PLL_DCO_AMP_MASK; 2962 2963 /* 2964 * While we write to the group register to program all lanes at once we 2965 * can read only lane registers. We configure all lanes the same way, so 2966 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 2967 */ 2968 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2969 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) 2970 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 2971 hw_state->pcsdw12, 2972 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 2973 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; 2974 2975 return true; 2976 } 2977 2978 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) 2979 { 2980 int i; 2981 2982 dev_priv->num_shared_dpll = 3; 2983 2984 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2985 dev_priv->shared_dplls[i].id = i; 2986 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; 2987 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; 2988 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; 2989 dev_priv->shared_dplls[i].get_hw_state = 2990 bxt_ddi_pll_get_hw_state; 2991 } 2992 } 2993 2994 void intel_ddi_pll_init(struct drm_device *dev) 2995 { 2996 struct drm_i915_private *dev_priv = dev->dev_private; 2997 uint32_t val = I915_READ(LCPLL_CTL); 2998 2999 if (IS_SKYLAKE(dev)) 3000 skl_shared_dplls_init(dev_priv); 3001 else if (IS_BROXTON(dev)) 3002 bxt_shared_dplls_init(dev_priv); 3003 else 3004 hsw_shared_dplls_init(dev_priv); 3005 3006 if (IS_SKYLAKE(dev)) { 3007 int cdclk_freq; 3008 3009 cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 3010 dev_priv->skl_boot_cdclk = cdclk_freq; 3011 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 3012 DRM_ERROR("LCPLL1 is disabled\n"); 3013 else 3014 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 3015 } else if (IS_BROXTON(dev)) { 3016 broxton_init_cdclk(dev); 3017 broxton_ddi_phy_init(dev); 3018 } else { 3019 /* 3020 * The LCPLL register should be turned on by the BIOS. For now 3021 * let's just check its state and print errors in case 3022 * something is wrong. Don't even try to turn it on. 3023 */ 3024 3025 if (val & LCPLL_CD_SOURCE_FCLK) 3026 DRM_ERROR("CDCLK source is not LCPLL\n"); 3027 3028 if (val & LCPLL_PLL_DISABLE) 3029 DRM_ERROR("LCPLL is disabled\n"); 3030 } 3031 } 3032 3033 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 3034 { 3035 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3036 struct intel_dp *intel_dp = &intel_dig_port->dp; 3037 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 3038 enum port port = intel_dig_port->port; 3039 uint32_t val; 3040 bool wait = false; 3041 3042 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 3043 val = I915_READ(DDI_BUF_CTL(port)); 3044 if (val & DDI_BUF_CTL_ENABLE) { 3045 val &= ~DDI_BUF_CTL_ENABLE; 3046 I915_WRITE(DDI_BUF_CTL(port), val); 3047 wait = true; 3048 } 3049 3050 val = I915_READ(DP_TP_CTL(port)); 3051 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3052 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3053 I915_WRITE(DP_TP_CTL(port), val); 3054 POSTING_READ(DP_TP_CTL(port)); 3055 3056 if (wait) 3057 intel_wait_ddi_buf_idle(dev_priv, port); 3058 } 3059 3060 val = DP_TP_CTL_ENABLE | 3061 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 3062 if (intel_dp->is_mst) 3063 val |= DP_TP_CTL_MODE_MST; 3064 else { 3065 val |= DP_TP_CTL_MODE_SST; 3066 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3067 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3068 } 3069 I915_WRITE(DP_TP_CTL(port), val); 3070 POSTING_READ(DP_TP_CTL(port)); 3071 3072 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3073 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 3074 POSTING_READ(DDI_BUF_CTL(port)); 3075 3076 udelay(600); 3077 } 3078 3079 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 3080 { 3081 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 3082 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 3083 uint32_t val; 3084 3085 intel_ddi_post_disable(intel_encoder); 3086 3087 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3088 val &= ~FDI_RX_ENABLE; 3089 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3090 3091 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3092 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3093 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3094 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3095 3096 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3097 val &= ~FDI_PCDCLK; 3098 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3099 3100 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3101 val &= ~FDI_RX_PLL_ENABLE; 3102 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3103 } 3104 3105 void intel_ddi_get_config(struct intel_encoder *encoder, 3106 struct intel_crtc_state *pipe_config) 3107 { 3108 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 3109 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 3110 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3111 struct intel_hdmi *intel_hdmi; 3112 u32 temp, flags = 0; 3113 3114 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3115 if (temp & TRANS_DDI_PHSYNC) 3116 flags |= DRM_MODE_FLAG_PHSYNC; 3117 else 3118 flags |= DRM_MODE_FLAG_NHSYNC; 3119 if (temp & TRANS_DDI_PVSYNC) 3120 flags |= DRM_MODE_FLAG_PVSYNC; 3121 else 3122 flags |= DRM_MODE_FLAG_NVSYNC; 3123 3124 pipe_config->base.adjusted_mode.flags |= flags; 3125 3126 switch (temp & TRANS_DDI_BPC_MASK) { 3127 case TRANS_DDI_BPC_6: 3128 pipe_config->pipe_bpp = 18; 3129 break; 3130 case TRANS_DDI_BPC_8: 3131 pipe_config->pipe_bpp = 24; 3132 break; 3133 case TRANS_DDI_BPC_10: 3134 pipe_config->pipe_bpp = 30; 3135 break; 3136 case TRANS_DDI_BPC_12: 3137 pipe_config->pipe_bpp = 36; 3138 break; 3139 default: 3140 break; 3141 } 3142 3143 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3144 case TRANS_DDI_MODE_SELECT_HDMI: 3145 pipe_config->has_hdmi_sink = true; 3146 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 3147 3148 if (intel_hdmi->infoframe_enabled(&encoder->base)) 3149 pipe_config->has_infoframe = true; 3150 break; 3151 case TRANS_DDI_MODE_SELECT_DVI: 3152 case TRANS_DDI_MODE_SELECT_FDI: 3153 break; 3154 case TRANS_DDI_MODE_SELECT_DP_SST: 3155 case TRANS_DDI_MODE_SELECT_DP_MST: 3156 pipe_config->has_dp_encoder = true; 3157 pipe_config->lane_count = 3158 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3159 intel_dp_get_m_n(intel_crtc, pipe_config); 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 3166 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 3167 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 3168 pipe_config->has_audio = true; 3169 } 3170 3171 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 3172 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 3173 /* 3174 * This is a big fat ugly hack. 3175 * 3176 * Some machines in UEFI boot mode provide us a VBT that has 18 3177 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3178 * unknown we fail to light up. Yet the same BIOS boots up with 3179 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3180 * max, not what it tells us to use. 3181 * 3182 * Note: This will still be broken if the eDP panel is not lit 3183 * up by the BIOS, and thus we can't get the mode at module 3184 * load. 3185 */ 3186 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3187 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 3188 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 3189 } 3190 3191 intel_ddi_clock_get(encoder, pipe_config); 3192 } 3193 3194 static void intel_ddi_destroy(struct drm_encoder *encoder) 3195 { 3196 /* HDMI has nothing special to destroy, so we can go with this. */ 3197 intel_dp_encoder_destroy(encoder); 3198 } 3199 3200 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 3201 struct intel_crtc_state *pipe_config) 3202 { 3203 int type = encoder->type; 3204 int port = intel_ddi_get_encoder_port(encoder); 3205 3206 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 3207 3208 if (port == PORT_A) 3209 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3210 3211 if (type == INTEL_OUTPUT_HDMI) 3212 return intel_hdmi_compute_config(encoder, pipe_config); 3213 else 3214 return intel_dp_compute_config(encoder, pipe_config); 3215 } 3216 3217 static const struct drm_encoder_funcs intel_ddi_funcs = { 3218 .destroy = intel_ddi_destroy, 3219 }; 3220 3221 static struct intel_connector * 3222 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 3223 { 3224 struct intel_connector *connector; 3225 enum port port = intel_dig_port->port; 3226 3227 connector = intel_connector_alloc(); 3228 if (!connector) 3229 return NULL; 3230 3231 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 3232 if (!intel_dp_init_connector(intel_dig_port, connector)) { 3233 kfree(connector); 3234 return NULL; 3235 } 3236 3237 return connector; 3238 } 3239 3240 static struct intel_connector * 3241 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 3242 { 3243 struct intel_connector *connector; 3244 enum port port = intel_dig_port->port; 3245 3246 connector = intel_connector_alloc(); 3247 if (!connector) 3248 return NULL; 3249 3250 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 3251 intel_hdmi_init_connector(intel_dig_port, connector); 3252 3253 return connector; 3254 } 3255 3256 void intel_ddi_init(struct drm_device *dev, enum port port) 3257 { 3258 struct drm_i915_private *dev_priv = dev->dev_private; 3259 struct intel_digital_port *intel_dig_port; 3260 struct intel_encoder *intel_encoder; 3261 struct drm_encoder *encoder; 3262 bool init_hdmi, init_dp; 3263 3264 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 3265 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 3266 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 3267 if (!init_dp && !init_hdmi) { 3268 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 3269 port_name(port)); 3270 return; 3271 } 3272 3273 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3274 if (!intel_dig_port) 3275 return; 3276 3277 intel_encoder = &intel_dig_port->base; 3278 encoder = &intel_encoder->base; 3279 3280 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 3281 DRM_MODE_ENCODER_TMDS); 3282 3283 intel_encoder->compute_config = intel_ddi_compute_config; 3284 intel_encoder->enable = intel_enable_ddi; 3285 intel_encoder->pre_enable = intel_ddi_pre_enable; 3286 intel_encoder->disable = intel_disable_ddi; 3287 intel_encoder->post_disable = intel_ddi_post_disable; 3288 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 3289 intel_encoder->get_config = intel_ddi_get_config; 3290 3291 intel_dig_port->port = port; 3292 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 3293 (DDI_BUF_PORT_REVERSAL | 3294 DDI_A_4_LANES); 3295 3296 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 3297 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3298 intel_encoder->cloneable = 0; 3299 3300 if (init_dp) { 3301 if (!intel_ddi_init_dp_connector(intel_dig_port)) 3302 goto err; 3303 3304 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 3305 /* 3306 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 3307 * interrupts to check the external panel connection. 3308 */ 3309 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) 3310 && port == PORT_B) 3311 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; 3312 else 3313 dev_priv->hotplug.irq_port[port] = intel_dig_port; 3314 } 3315 3316 /* In theory we don't need the encoder->type check, but leave it just in 3317 * case we have some really bad VBTs... */ 3318 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 3319 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 3320 goto err; 3321 } 3322 3323 return; 3324 3325 err: 3326 drm_encoder_cleanup(encoder); 3327 kfree(intel_dig_port); 3328 } 3329