1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 36 }; 37 38 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 39 * them for both DP and FDI transports, allowing those ports to 40 * automatically adapt to HDMI connections as well 41 */ 42 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 43 { 0x00FFFFFF, 0x0006000E, 0x0 }, 44 { 0x00D75FFF, 0x0005000A, 0x0 }, 45 { 0x00C30FFF, 0x00040006, 0x0 }, 46 { 0x80AAAFFF, 0x000B0000, 0x0 }, 47 { 0x00FFFFFF, 0x0005000A, 0x0 }, 48 { 0x00D75FFF, 0x000C0004, 0x0 }, 49 { 0x80C30FFF, 0x000B0000, 0x0 }, 50 { 0x00FFFFFF, 0x00040006, 0x0 }, 51 { 0x80D75FFF, 0x000B0000, 0x0 }, 52 }; 53 54 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 55 { 0x00FFFFFF, 0x0007000E, 0x0 }, 56 { 0x00D75FFF, 0x000F000A, 0x0 }, 57 { 0x00C30FFF, 0x00060006, 0x0 }, 58 { 0x00AAAFFF, 0x001E0000, 0x0 }, 59 { 0x00FFFFFF, 0x000F000A, 0x0 }, 60 { 0x00D75FFF, 0x00160004, 0x0 }, 61 { 0x00C30FFF, 0x001E0000, 0x0 }, 62 { 0x00FFFFFF, 0x00060006, 0x0 }, 63 { 0x00D75FFF, 0x001E0000, 0x0 }, 64 }; 65 66 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 67 /* Idx NT mV d T mV d db */ 68 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 69 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 70 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 71 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 72 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 73 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 74 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 75 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 76 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 77 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 78 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 79 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 80 }; 81 82 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 83 { 0x00FFFFFF, 0x00000012, 0x0 }, 84 { 0x00EBAFFF, 0x00020011, 0x0 }, 85 { 0x00C71FFF, 0x0006000F, 0x0 }, 86 { 0x00AAAFFF, 0x000E000A, 0x0 }, 87 { 0x00FFFFFF, 0x00020011, 0x0 }, 88 { 0x00DB6FFF, 0x0005000F, 0x0 }, 89 { 0x00BEEFFF, 0x000A000C, 0x0 }, 90 { 0x00FFFFFF, 0x0005000F, 0x0 }, 91 { 0x00DB6FFF, 0x000A000C, 0x0 }, 92 }; 93 94 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 95 { 0x00FFFFFF, 0x0007000E, 0x0 }, 96 { 0x00D75FFF, 0x000E000A, 0x0 }, 97 { 0x00BEFFFF, 0x00140006, 0x0 }, 98 { 0x80B2CFFF, 0x001B0002, 0x0 }, 99 { 0x00FFFFFF, 0x000E000A, 0x0 }, 100 { 0x00DB6FFF, 0x00160005, 0x0 }, 101 { 0x80C71FFF, 0x001A0002, 0x0 }, 102 { 0x00F7DFFF, 0x00180004, 0x0 }, 103 { 0x80D75FFF, 0x001B0002, 0x0 }, 104 }; 105 106 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 107 { 0x00FFFFFF, 0x0001000E, 0x0 }, 108 { 0x00D75FFF, 0x0004000A, 0x0 }, 109 { 0x00C30FFF, 0x00070006, 0x0 }, 110 { 0x00AAAFFF, 0x000C0000, 0x0 }, 111 { 0x00FFFFFF, 0x0004000A, 0x0 }, 112 { 0x00D75FFF, 0x00090004, 0x0 }, 113 { 0x00C30FFF, 0x000C0000, 0x0 }, 114 { 0x00FFFFFF, 0x00070006, 0x0 }, 115 { 0x00D75FFF, 0x000C0000, 0x0 }, 116 }; 117 118 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 119 /* Idx NT mV d T mV df db */ 120 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 121 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 122 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 123 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 124 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 125 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 126 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 127 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 128 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 129 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 130 }; 131 132 /* Skylake H and S */ 133 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 134 { 0x00002016, 0x000000A0, 0x0 }, 135 { 0x00005012, 0x0000009B, 0x0 }, 136 { 0x00007011, 0x00000088, 0x0 }, 137 { 0x00009010, 0x000000C7, 0x0 }, 138 { 0x00002016, 0x0000009B, 0x0 }, 139 { 0x00005012, 0x00000088, 0x0 }, 140 { 0x00007011, 0x000000C7, 0x0 }, 141 { 0x00002016, 0x000000DF, 0x0 }, 142 { 0x00005012, 0x000000C7, 0x0 }, 143 }; 144 145 /* Skylake U */ 146 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 147 { 0x0000201B, 0x000000A2, 0x0 }, 148 { 0x00005012, 0x00000088, 0x0 }, 149 { 0x00007011, 0x00000087, 0x0 }, 150 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */ 151 { 0x0000201B, 0x0000009D, 0x0 }, 152 { 0x00005012, 0x000000C7, 0x0 }, 153 { 0x00007011, 0x000000C7, 0x0 }, 154 { 0x00002016, 0x00000088, 0x0 }, 155 { 0x00005012, 0x000000C7, 0x0 }, 156 }; 157 158 /* Skylake Y */ 159 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 160 { 0x00000018, 0x000000A2, 0x0 }, 161 { 0x00005012, 0x00000088, 0x0 }, 162 { 0x00007011, 0x00000087, 0x0 }, 163 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */ 164 { 0x00000018, 0x0000009D, 0x0 }, 165 { 0x00005012, 0x000000C7, 0x0 }, 166 { 0x00007011, 0x000000C7, 0x0 }, 167 { 0x00000018, 0x00000088, 0x0 }, 168 { 0x00005012, 0x000000C7, 0x0 }, 169 }; 170 171 /* 172 * Skylake H and S 173 * eDP 1.4 low vswing translation parameters 174 */ 175 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 176 { 0x00000018, 0x000000A8, 0x0 }, 177 { 0x00004013, 0x000000A9, 0x0 }, 178 { 0x00007011, 0x000000A2, 0x0 }, 179 { 0x00009010, 0x0000009C, 0x0 }, 180 { 0x00000018, 0x000000A9, 0x0 }, 181 { 0x00006013, 0x000000A2, 0x0 }, 182 { 0x00007011, 0x000000A6, 0x0 }, 183 { 0x00000018, 0x000000AB, 0x0 }, 184 { 0x00007013, 0x0000009F, 0x0 }, 185 { 0x00000018, 0x000000DF, 0x0 }, 186 }; 187 188 /* 189 * Skylake U 190 * eDP 1.4 low vswing translation parameters 191 */ 192 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 193 { 0x00000018, 0x000000A8, 0x0 }, 194 { 0x00004013, 0x000000A9, 0x0 }, 195 { 0x00007011, 0x000000A2, 0x0 }, 196 { 0x00009010, 0x0000009C, 0x0 }, 197 { 0x00000018, 0x000000A9, 0x0 }, 198 { 0x00006013, 0x000000A2, 0x0 }, 199 { 0x00007011, 0x000000A6, 0x0 }, 200 { 0x00002016, 0x000000AB, 0x0 }, 201 { 0x00005013, 0x0000009F, 0x0 }, 202 { 0x00000018, 0x000000DF, 0x0 }, 203 }; 204 205 /* 206 * Skylake Y 207 * eDP 1.4 low vswing translation parameters 208 */ 209 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 210 { 0x00000018, 0x000000A8, 0x0 }, 211 { 0x00004013, 0x000000AB, 0x0 }, 212 { 0x00007011, 0x000000A4, 0x0 }, 213 { 0x00009010, 0x000000DF, 0x0 }, 214 { 0x00000018, 0x000000AA, 0x0 }, 215 { 0x00006013, 0x000000A4, 0x0 }, 216 { 0x00007011, 0x0000009D, 0x0 }, 217 { 0x00000018, 0x000000A0, 0x0 }, 218 { 0x00006012, 0x000000DF, 0x0 }, 219 { 0x00000018, 0x0000008A, 0x0 }, 220 }; 221 222 /* Skylake U, H and S */ 223 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 224 { 0x00000018, 0x000000AC, 0x0 }, 225 { 0x00005012, 0x0000009D, 0x0 }, 226 { 0x00007011, 0x00000088, 0x0 }, 227 { 0x00000018, 0x000000A1, 0x0 }, 228 { 0x00000018, 0x00000098, 0x0 }, 229 { 0x00004013, 0x00000088, 0x0 }, 230 { 0x00006012, 0x00000087, 0x0 }, 231 { 0x00000018, 0x000000DF, 0x0 }, 232 { 0x00003015, 0x00000087, 0x0 }, /* Default */ 233 { 0x00003015, 0x000000C7, 0x0 }, 234 { 0x00000018, 0x000000C7, 0x0 }, 235 }; 236 237 /* Skylake Y */ 238 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 239 { 0x00000018, 0x000000A1, 0x0 }, 240 { 0x00005012, 0x000000DF, 0x0 }, 241 { 0x00007011, 0x00000084, 0x0 }, 242 { 0x00000018, 0x000000A4, 0x0 }, 243 { 0x00000018, 0x0000009D, 0x0 }, 244 { 0x00004013, 0x00000080, 0x0 }, 245 { 0x00006013, 0x000000C7, 0x0 }, 246 { 0x00000018, 0x0000008A, 0x0 }, 247 { 0x00003015, 0x000000C7, 0x0 }, /* Default */ 248 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */ 249 { 0x00000018, 0x000000C7, 0x0 }, 250 }; 251 252 struct bxt_ddi_buf_trans { 253 u32 margin; /* swing value */ 254 u32 scale; /* scale value */ 255 u32 enable; /* scale enable */ 256 u32 deemphasis; 257 bool default_index; /* true if the entry represents default value */ 258 }; 259 260 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 261 /* Idx NT mV diff db */ 262 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ 263 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 264 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ 265 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 266 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 267 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 268 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ 269 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 270 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 271 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 272 }; 273 274 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 275 /* Idx NT mV diff db */ 276 { 26, 0, 0, 128, false }, /* 0: 200 0 */ 277 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ 278 { 48, 0, 0, 96, false }, /* 2: 200 4 */ 279 { 54, 0, 0, 69, false }, /* 3: 200 6 */ 280 { 32, 0, 0, 128, false }, /* 4: 250 0 */ 281 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ 282 { 54, 0, 0, 85, false }, /* 6: 250 4 */ 283 { 43, 0, 0, 128, false }, /* 7: 300 0 */ 284 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ 285 { 48, 0, 0, 128, false }, /* 9: 300 0 */ 286 }; 287 288 /* BSpec has 2 recommended values - entries 0 and 8. 289 * Using the entry with higher vswing. 290 */ 291 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 292 /* Idx NT mV diff db */ 293 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ 294 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 295 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ 296 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 297 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 298 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 299 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ 300 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 301 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 302 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 303 }; 304 305 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 306 enum port port, int type); 307 308 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, 309 struct intel_digital_port **dig_port, 310 enum port *port) 311 { 312 struct drm_encoder *encoder = &intel_encoder->base; 313 314 switch (intel_encoder->type) { 315 case INTEL_OUTPUT_DP_MST: 316 *dig_port = enc_to_mst(encoder)->primary; 317 *port = (*dig_port)->port; 318 break; 319 case INTEL_OUTPUT_DISPLAYPORT: 320 case INTEL_OUTPUT_EDP: 321 case INTEL_OUTPUT_HDMI: 322 case INTEL_OUTPUT_UNKNOWN: 323 *dig_port = enc_to_dig_port(encoder); 324 *port = (*dig_port)->port; 325 break; 326 case INTEL_OUTPUT_ANALOG: 327 *dig_port = NULL; 328 *port = PORT_E; 329 break; 330 default: 331 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); 332 break; 333 } 334 } 335 336 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 337 { 338 struct intel_digital_port *dig_port; 339 enum port port; 340 341 ddi_get_encoder_port(intel_encoder, &dig_port, &port); 342 343 return port; 344 } 345 346 static bool 347 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) 348 { 349 return intel_dig_port->hdmi.hdmi_reg; 350 } 351 352 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, 353 int *n_entries) 354 { 355 const struct ddi_buf_trans *ddi_translations; 356 357 if (IS_SKL_ULX(dev)) { 358 ddi_translations = skl_y_ddi_translations_dp; 359 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 360 } else if (IS_SKL_ULT(dev)) { 361 ddi_translations = skl_u_ddi_translations_dp; 362 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 363 } else { 364 ddi_translations = skl_ddi_translations_dp; 365 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 366 } 367 368 return ddi_translations; 369 } 370 371 static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, 372 int *n_entries) 373 { 374 struct drm_i915_private *dev_priv = dev->dev_private; 375 const struct ddi_buf_trans *ddi_translations; 376 377 if (IS_SKL_ULX(dev)) { 378 if (dev_priv->edp_low_vswing) { 379 ddi_translations = skl_y_ddi_translations_edp; 380 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 381 } else { 382 ddi_translations = skl_y_ddi_translations_dp; 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 384 } 385 } else if (IS_SKL_ULT(dev)) { 386 if (dev_priv->edp_low_vswing) { 387 ddi_translations = skl_u_ddi_translations_edp; 388 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 389 } else { 390 ddi_translations = skl_u_ddi_translations_dp; 391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 392 } 393 } else { 394 if (dev_priv->edp_low_vswing) { 395 ddi_translations = skl_ddi_translations_edp; 396 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 397 } else { 398 ddi_translations = skl_ddi_translations_dp; 399 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 400 } 401 } 402 403 return ddi_translations; 404 } 405 406 static const struct ddi_buf_trans * 407 skl_get_buf_trans_hdmi(struct drm_device *dev, 408 int *n_entries) 409 { 410 const struct ddi_buf_trans *ddi_translations; 411 412 if (IS_SKL_ULX(dev)) { 413 ddi_translations = skl_y_ddi_translations_hdmi; 414 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 415 } else { 416 ddi_translations = skl_ddi_translations_hdmi; 417 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 418 } 419 420 return ddi_translations; 421 } 422 423 /* 424 * Starting with Haswell, DDI port buffers must be programmed with correct 425 * values in advance. The buffer values are different for FDI and DP modes, 426 * but the HDMI/DVI fields are shared among those. So we program the DDI 427 * in either FDI or DP modes only, as HDMI connections will work with both 428 * of those 429 */ 430 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, 431 bool supports_hdmi) 432 { 433 struct drm_i915_private *dev_priv = dev->dev_private; 434 u32 iboost_bit = 0; 435 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 436 size; 437 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 438 const struct ddi_buf_trans *ddi_translations_fdi; 439 const struct ddi_buf_trans *ddi_translations_dp; 440 const struct ddi_buf_trans *ddi_translations_edp; 441 const struct ddi_buf_trans *ddi_translations_hdmi; 442 const struct ddi_buf_trans *ddi_translations; 443 444 if (IS_BROXTON(dev)) { 445 if (!supports_hdmi) 446 return; 447 448 /* Vswing programming for HDMI */ 449 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 450 INTEL_OUTPUT_HDMI); 451 return; 452 } else if (IS_SKYLAKE(dev)) { 453 ddi_translations_fdi = NULL; 454 ddi_translations_dp = 455 skl_get_buf_trans_dp(dev, &n_dp_entries); 456 ddi_translations_edp = 457 skl_get_buf_trans_edp(dev, &n_edp_entries); 458 ddi_translations_hdmi = 459 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries); 460 hdmi_default_entry = 8; 461 /* If we're boosting the current, set bit 31 of trans1 */ 462 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || 463 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 464 iboost_bit = 1<<31; 465 } else if (IS_BROADWELL(dev)) { 466 ddi_translations_fdi = bdw_ddi_translations_fdi; 467 ddi_translations_dp = bdw_ddi_translations_dp; 468 ddi_translations_edp = bdw_ddi_translations_edp; 469 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 470 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 471 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 472 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 473 hdmi_default_entry = 7; 474 } else if (IS_HASWELL(dev)) { 475 ddi_translations_fdi = hsw_ddi_translations_fdi; 476 ddi_translations_dp = hsw_ddi_translations_dp; 477 ddi_translations_edp = hsw_ddi_translations_dp; 478 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 479 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 480 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 481 hdmi_default_entry = 6; 482 } else { 483 WARN(1, "ddi translation table missing\n"); 484 ddi_translations_edp = bdw_ddi_translations_dp; 485 ddi_translations_fdi = bdw_ddi_translations_fdi; 486 ddi_translations_dp = bdw_ddi_translations_dp; 487 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 488 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 489 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 490 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 491 hdmi_default_entry = 7; 492 } 493 494 switch (port) { 495 case PORT_A: 496 ddi_translations = ddi_translations_edp; 497 size = n_edp_entries; 498 break; 499 case PORT_B: 500 case PORT_C: 501 ddi_translations = ddi_translations_dp; 502 size = n_dp_entries; 503 break; 504 case PORT_D: 505 if (intel_dp_is_edp(dev, PORT_D)) { 506 ddi_translations = ddi_translations_edp; 507 size = n_edp_entries; 508 } else { 509 ddi_translations = ddi_translations_dp; 510 size = n_dp_entries; 511 } 512 break; 513 case PORT_E: 514 if (ddi_translations_fdi) 515 ddi_translations = ddi_translations_fdi; 516 else 517 ddi_translations = ddi_translations_dp; 518 size = n_dp_entries; 519 break; 520 default: 521 BUG(); 522 } 523 524 for (i = 0; i < size; i++) { 525 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 526 ddi_translations[i].trans1 | iboost_bit); 527 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 528 ddi_translations[i].trans2); 529 } 530 531 if (!supports_hdmi) 532 return; 533 534 /* Choose a good default if VBT is badly populated */ 535 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 536 hdmi_level >= n_hdmi_entries) 537 hdmi_level = hdmi_default_entry; 538 539 /* Entry 9 is for HDMI: */ 540 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 541 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); 542 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 543 ddi_translations_hdmi[hdmi_level].trans2); 544 } 545 546 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 547 * mode and port E for FDI. 548 */ 549 void intel_prepare_ddi(struct drm_device *dev) 550 { 551 struct intel_encoder *intel_encoder; 552 bool visited[I915_MAX_PORTS] = { 0, }; 553 554 if (!HAS_DDI(dev)) 555 return; 556 557 for_each_intel_encoder(dev, intel_encoder) { 558 struct intel_digital_port *intel_dig_port; 559 enum port port; 560 bool supports_hdmi; 561 562 if (intel_encoder->type == INTEL_OUTPUT_DSI) 563 continue; 564 565 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); 566 if (visited[port]) 567 continue; 568 569 supports_hdmi = intel_dig_port && 570 intel_dig_port_supports_hdmi(intel_dig_port); 571 572 intel_prepare_ddi_buffers(dev, port, supports_hdmi); 573 visited[port] = true; 574 } 575 } 576 577 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 578 enum port port) 579 { 580 uint32_t reg = DDI_BUF_CTL(port); 581 int i; 582 583 for (i = 0; i < 16; i++) { 584 udelay(1); 585 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 586 return; 587 } 588 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 589 } 590 591 /* Starting with Haswell, different DDI ports can work in FDI mode for 592 * connection to the PCH-located connectors. For this, it is necessary to train 593 * both the DDI port and PCH receiver for the desired DDI buffer settings. 594 * 595 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 596 * please note that when FDI mode is active on DDI E, it shares 2 lines with 597 * DDI A (which is used for eDP) 598 */ 599 600 void hsw_fdi_link_train(struct drm_crtc *crtc) 601 { 602 struct drm_device *dev = crtc->dev; 603 struct drm_i915_private *dev_priv = dev->dev_private; 604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 605 u32 temp, i, rx_ctl_val; 606 607 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 608 * mode set "sequence for CRT port" document: 609 * - TP1 to TP2 time with the default value 610 * - FDI delay to 90h 611 * 612 * WaFDIAutoLinkSetTimingOverrride:hsw 613 */ 614 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 615 FDI_RX_PWRDN_LANE0_VAL(2) | 616 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 617 618 /* Enable the PCH Receiver FDI PLL */ 619 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 620 FDI_RX_PLL_ENABLE | 621 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 622 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 623 POSTING_READ(FDI_RX_CTL(PIPE_A)); 624 udelay(220); 625 626 /* Switch from Rawclk to PCDclk */ 627 rx_ctl_val |= FDI_PCDCLK; 628 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 629 630 /* Configure Port Clock Select */ 631 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 632 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 633 634 /* Start the training iterating through available voltages and emphasis, 635 * testing each value twice. */ 636 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 637 /* Configure DP_TP_CTL with auto-training */ 638 I915_WRITE(DP_TP_CTL(PORT_E), 639 DP_TP_CTL_FDI_AUTOTRAIN | 640 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 641 DP_TP_CTL_LINK_TRAIN_PAT1 | 642 DP_TP_CTL_ENABLE); 643 644 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 645 * DDI E does not support port reversal, the functionality is 646 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 647 * port reversal bit */ 648 I915_WRITE(DDI_BUF_CTL(PORT_E), 649 DDI_BUF_CTL_ENABLE | 650 ((intel_crtc->config->fdi_lanes - 1) << 1) | 651 DDI_BUF_TRANS_SELECT(i / 2)); 652 POSTING_READ(DDI_BUF_CTL(PORT_E)); 653 654 udelay(600); 655 656 /* Program PCH FDI Receiver TU */ 657 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 658 659 /* Enable PCH FDI Receiver with auto-training */ 660 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 661 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 662 POSTING_READ(FDI_RX_CTL(PIPE_A)); 663 664 /* Wait for FDI receiver lane calibration */ 665 udelay(30); 666 667 /* Unset FDI_RX_MISC pwrdn lanes */ 668 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 669 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 670 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 671 POSTING_READ(FDI_RX_MISC(PIPE_A)); 672 673 /* Wait for FDI auto training time */ 674 udelay(5); 675 676 temp = I915_READ(DP_TP_STATUS(PORT_E)); 677 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 678 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 679 680 /* Enable normal pixel sending for FDI */ 681 I915_WRITE(DP_TP_CTL(PORT_E), 682 DP_TP_CTL_FDI_AUTOTRAIN | 683 DP_TP_CTL_LINK_TRAIN_NORMAL | 684 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 685 DP_TP_CTL_ENABLE); 686 687 return; 688 } 689 690 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 691 temp &= ~DDI_BUF_CTL_ENABLE; 692 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 693 POSTING_READ(DDI_BUF_CTL(PORT_E)); 694 695 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 696 temp = I915_READ(DP_TP_CTL(PORT_E)); 697 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 698 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 699 I915_WRITE(DP_TP_CTL(PORT_E), temp); 700 POSTING_READ(DP_TP_CTL(PORT_E)); 701 702 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 703 704 rx_ctl_val &= ~FDI_RX_ENABLE; 705 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 706 POSTING_READ(FDI_RX_CTL(PIPE_A)); 707 708 /* Reset FDI_RX_MISC pwrdn lanes */ 709 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 710 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 711 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 712 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 713 POSTING_READ(FDI_RX_MISC(PIPE_A)); 714 } 715 716 DRM_ERROR("FDI link training failed!\n"); 717 } 718 719 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 720 { 721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 722 struct intel_digital_port *intel_dig_port = 723 enc_to_dig_port(&encoder->base); 724 725 intel_dp->DP = intel_dig_port->saved_port_bits | 726 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 727 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 728 } 729 730 static struct intel_encoder * 731 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 732 { 733 struct drm_device *dev = crtc->dev; 734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 735 struct intel_encoder *intel_encoder, *ret = NULL; 736 int num_encoders = 0; 737 738 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 739 ret = intel_encoder; 740 num_encoders++; 741 } 742 743 if (num_encoders != 1) 744 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 745 pipe_name(intel_crtc->pipe)); 746 747 BUG_ON(ret == NULL); 748 return ret; 749 } 750 751 struct intel_encoder * 752 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 753 { 754 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 755 struct intel_encoder *ret = NULL; 756 struct drm_atomic_state *state; 757 struct drm_connector *connector; 758 struct drm_connector_state *connector_state; 759 int num_encoders = 0; 760 int i; 761 762 state = crtc_state->base.state; 763 764 for_each_connector_in_state(state, connector, connector_state, i) { 765 if (connector_state->crtc != crtc_state->base.crtc) 766 continue; 767 768 ret = to_intel_encoder(connector_state->best_encoder); 769 num_encoders++; 770 } 771 772 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 773 pipe_name(crtc->pipe)); 774 775 BUG_ON(ret == NULL); 776 return ret; 777 } 778 779 #define LC_FREQ 2700 780 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 781 782 #define P_MIN 2 783 #define P_MAX 64 784 #define P_INC 2 785 786 /* Constraints for PLL good behavior */ 787 #define REF_MIN 48 788 #define REF_MAX 400 789 #define VCO_MIN 2400 790 #define VCO_MAX 4800 791 792 #define abs_diff(a, b) ({ \ 793 typeof(a) __a = (a); \ 794 typeof(b) __b = (b); \ 795 (void) (&__a == &__b); \ 796 __a > __b ? (__a - __b) : (__b - __a); }) 797 798 struct hsw_wrpll_rnp { 799 unsigned p, n2, r2; 800 }; 801 802 static unsigned hsw_wrpll_get_budget_for_freq(int clock) 803 { 804 unsigned budget; 805 806 switch (clock) { 807 case 25175000: 808 case 25200000: 809 case 27000000: 810 case 27027000: 811 case 37762500: 812 case 37800000: 813 case 40500000: 814 case 40541000: 815 case 54000000: 816 case 54054000: 817 case 59341000: 818 case 59400000: 819 case 72000000: 820 case 74176000: 821 case 74250000: 822 case 81000000: 823 case 81081000: 824 case 89012000: 825 case 89100000: 826 case 108000000: 827 case 108108000: 828 case 111264000: 829 case 111375000: 830 case 148352000: 831 case 148500000: 832 case 162000000: 833 case 162162000: 834 case 222525000: 835 case 222750000: 836 case 296703000: 837 case 297000000: 838 budget = 0; 839 break; 840 case 233500000: 841 case 245250000: 842 case 247750000: 843 case 253250000: 844 case 298000000: 845 budget = 1500; 846 break; 847 case 169128000: 848 case 169500000: 849 case 179500000: 850 case 202000000: 851 budget = 2000; 852 break; 853 case 256250000: 854 case 262500000: 855 case 270000000: 856 case 272500000: 857 case 273750000: 858 case 280750000: 859 case 281250000: 860 case 286000000: 861 case 291750000: 862 budget = 4000; 863 break; 864 case 267250000: 865 case 268500000: 866 budget = 5000; 867 break; 868 default: 869 budget = 1000; 870 break; 871 } 872 873 return budget; 874 } 875 876 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, 877 unsigned r2, unsigned n2, unsigned p, 878 struct hsw_wrpll_rnp *best) 879 { 880 uint64_t a, b, c, d, diff, diff_best; 881 882 /* No best (r,n,p) yet */ 883 if (best->p == 0) { 884 best->p = p; 885 best->n2 = n2; 886 best->r2 = r2; 887 return; 888 } 889 890 /* 891 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 892 * freq2k. 893 * 894 * delta = 1e6 * 895 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 896 * freq2k; 897 * 898 * and we would like delta <= budget. 899 * 900 * If the discrepancy is above the PPM-based budget, always prefer to 901 * improve upon the previous solution. However, if you're within the 902 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 903 */ 904 a = freq2k * budget * p * r2; 905 b = freq2k * budget * best->p * best->r2; 906 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); 907 diff_best = abs_diff(freq2k * best->p * best->r2, 908 LC_FREQ_2K * best->n2); 909 c = 1000000 * diff; 910 d = 1000000 * diff_best; 911 912 if (a < c && b < d) { 913 /* If both are above the budget, pick the closer */ 914 if (best->p * best->r2 * diff < p * r2 * diff_best) { 915 best->p = p; 916 best->n2 = n2; 917 best->r2 = r2; 918 } 919 } else if (a >= c && b < d) { 920 /* If A is below the threshold but B is above it? Update. */ 921 best->p = p; 922 best->n2 = n2; 923 best->r2 = r2; 924 } else if (a >= c && b >= d) { 925 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 926 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 927 best->p = p; 928 best->n2 = n2; 929 best->r2 = r2; 930 } 931 } 932 /* Otherwise a < c && b >= d, do nothing */ 933 } 934 935 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg) 936 { 937 int refclk = LC_FREQ; 938 int n, p, r; 939 u32 wrpll; 940 941 wrpll = I915_READ(reg); 942 switch (wrpll & WRPLL_PLL_REF_MASK) { 943 case WRPLL_PLL_SSC: 944 case WRPLL_PLL_NON_SSC: 945 /* 946 * We could calculate spread here, but our checking 947 * code only cares about 5% accuracy, and spread is a max of 948 * 0.5% downspread. 949 */ 950 refclk = 135; 951 break; 952 case WRPLL_PLL_LCPLL: 953 refclk = LC_FREQ; 954 break; 955 default: 956 WARN(1, "bad wrpll refclk\n"); 957 return 0; 958 } 959 960 r = wrpll & WRPLL_DIVIDER_REF_MASK; 961 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 962 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 963 964 /* Convert to KHz, p & r have a fixed point portion */ 965 return (refclk * n * 100) / (p * r); 966 } 967 968 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 969 uint32_t dpll) 970 { 971 uint32_t cfgcr1_reg, cfgcr2_reg; 972 uint32_t cfgcr1_val, cfgcr2_val; 973 uint32_t p0, p1, p2, dco_freq; 974 975 cfgcr1_reg = DPLL_CFGCR1(dpll); 976 cfgcr2_reg = DPLL_CFGCR2(dpll); 977 978 cfgcr1_val = I915_READ(cfgcr1_reg); 979 cfgcr2_val = I915_READ(cfgcr2_reg); 980 981 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 982 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 983 984 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 985 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 986 else 987 p1 = 1; 988 989 990 switch (p0) { 991 case DPLL_CFGCR2_PDIV_1: 992 p0 = 1; 993 break; 994 case DPLL_CFGCR2_PDIV_2: 995 p0 = 2; 996 break; 997 case DPLL_CFGCR2_PDIV_3: 998 p0 = 3; 999 break; 1000 case DPLL_CFGCR2_PDIV_7: 1001 p0 = 7; 1002 break; 1003 } 1004 1005 switch (p2) { 1006 case DPLL_CFGCR2_KDIV_5: 1007 p2 = 5; 1008 break; 1009 case DPLL_CFGCR2_KDIV_2: 1010 p2 = 2; 1011 break; 1012 case DPLL_CFGCR2_KDIV_3: 1013 p2 = 3; 1014 break; 1015 case DPLL_CFGCR2_KDIV_1: 1016 p2 = 1; 1017 break; 1018 } 1019 1020 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 1021 1022 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 1023 1000) / 0x8000; 1024 1025 return dco_freq / (p0 * p1 * p2 * 5); 1026 } 1027 1028 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1029 { 1030 int dotclock; 1031 1032 if (pipe_config->has_pch_encoder) 1033 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1034 &pipe_config->fdi_m_n); 1035 else if (pipe_config->has_dp_encoder) 1036 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1037 &pipe_config->dp_m_n); 1038 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 1039 dotclock = pipe_config->port_clock * 2 / 3; 1040 else 1041 dotclock = pipe_config->port_clock; 1042 1043 if (pipe_config->pixel_multiplier) 1044 dotclock /= pipe_config->pixel_multiplier; 1045 1046 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1047 } 1048 1049 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1050 struct intel_crtc_state *pipe_config) 1051 { 1052 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1053 int link_clock = 0; 1054 uint32_t dpll_ctl1, dpll; 1055 1056 dpll = pipe_config->ddi_pll_sel; 1057 1058 dpll_ctl1 = I915_READ(DPLL_CTRL1); 1059 1060 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 1061 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 1062 } else { 1063 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 1064 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 1065 1066 switch (link_clock) { 1067 case DPLL_CTRL1_LINK_RATE_810: 1068 link_clock = 81000; 1069 break; 1070 case DPLL_CTRL1_LINK_RATE_1080: 1071 link_clock = 108000; 1072 break; 1073 case DPLL_CTRL1_LINK_RATE_1350: 1074 link_clock = 135000; 1075 break; 1076 case DPLL_CTRL1_LINK_RATE_1620: 1077 link_clock = 162000; 1078 break; 1079 case DPLL_CTRL1_LINK_RATE_2160: 1080 link_clock = 216000; 1081 break; 1082 case DPLL_CTRL1_LINK_RATE_2700: 1083 link_clock = 270000; 1084 break; 1085 default: 1086 WARN(1, "Unsupported link rate\n"); 1087 break; 1088 } 1089 link_clock *= 2; 1090 } 1091 1092 pipe_config->port_clock = link_clock; 1093 1094 ddi_dotclock_get(pipe_config); 1095 } 1096 1097 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1098 struct intel_crtc_state *pipe_config) 1099 { 1100 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1101 int link_clock = 0; 1102 u32 val, pll; 1103 1104 val = pipe_config->ddi_pll_sel; 1105 switch (val & PORT_CLK_SEL_MASK) { 1106 case PORT_CLK_SEL_LCPLL_810: 1107 link_clock = 81000; 1108 break; 1109 case PORT_CLK_SEL_LCPLL_1350: 1110 link_clock = 135000; 1111 break; 1112 case PORT_CLK_SEL_LCPLL_2700: 1113 link_clock = 270000; 1114 break; 1115 case PORT_CLK_SEL_WRPLL1: 1116 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); 1117 break; 1118 case PORT_CLK_SEL_WRPLL2: 1119 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); 1120 break; 1121 case PORT_CLK_SEL_SPLL: 1122 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 1123 if (pll == SPLL_PLL_FREQ_810MHz) 1124 link_clock = 81000; 1125 else if (pll == SPLL_PLL_FREQ_1350MHz) 1126 link_clock = 135000; 1127 else if (pll == SPLL_PLL_FREQ_2700MHz) 1128 link_clock = 270000; 1129 else { 1130 WARN(1, "bad spll freq\n"); 1131 return; 1132 } 1133 break; 1134 default: 1135 WARN(1, "bad port clock sel\n"); 1136 return; 1137 } 1138 1139 pipe_config->port_clock = link_clock * 2; 1140 1141 ddi_dotclock_get(pipe_config); 1142 } 1143 1144 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 1145 enum intel_dpll_id dpll) 1146 { 1147 struct intel_shared_dpll *pll; 1148 struct intel_dpll_hw_state *state; 1149 intel_clock_t clock; 1150 1151 /* For DDI ports we always use a shared PLL. */ 1152 if (WARN_ON(dpll == DPLL_ID_PRIVATE)) 1153 return 0; 1154 1155 pll = &dev_priv->shared_dplls[dpll]; 1156 state = &pll->config.hw_state; 1157 1158 clock.m1 = 2; 1159 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; 1160 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1161 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; 1162 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1163 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1164 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1165 1166 return chv_calc_dpll_params(100000, &clock); 1167 } 1168 1169 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1170 struct intel_crtc_state *pipe_config) 1171 { 1172 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1173 enum port port = intel_ddi_get_encoder_port(encoder); 1174 uint32_t dpll = port; 1175 1176 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); 1177 1178 ddi_dotclock_get(pipe_config); 1179 } 1180 1181 void intel_ddi_clock_get(struct intel_encoder *encoder, 1182 struct intel_crtc_state *pipe_config) 1183 { 1184 struct drm_device *dev = encoder->base.dev; 1185 1186 if (INTEL_INFO(dev)->gen <= 8) 1187 hsw_ddi_clock_get(encoder, pipe_config); 1188 else if (IS_SKYLAKE(dev)) 1189 skl_ddi_clock_get(encoder, pipe_config); 1190 else if (IS_BROXTON(dev)) 1191 bxt_ddi_clock_get(encoder, pipe_config); 1192 } 1193 1194 static void 1195 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 1196 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 1197 { 1198 uint64_t freq2k; 1199 unsigned p, n2, r2; 1200 struct hsw_wrpll_rnp best = { 0, 0, 0 }; 1201 unsigned budget; 1202 1203 freq2k = clock / 100; 1204 1205 budget = hsw_wrpll_get_budget_for_freq(clock); 1206 1207 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 1208 * and directly pass the LC PLL to it. */ 1209 if (freq2k == 5400000) { 1210 *n2_out = 2; 1211 *p_out = 1; 1212 *r2_out = 2; 1213 return; 1214 } 1215 1216 /* 1217 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 1218 * the WR PLL. 1219 * 1220 * We want R so that REF_MIN <= Ref <= REF_MAX. 1221 * Injecting R2 = 2 * R gives: 1222 * REF_MAX * r2 > LC_FREQ * 2 and 1223 * REF_MIN * r2 < LC_FREQ * 2 1224 * 1225 * Which means the desired boundaries for r2 are: 1226 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 1227 * 1228 */ 1229 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 1230 r2 <= LC_FREQ * 2 / REF_MIN; 1231 r2++) { 1232 1233 /* 1234 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 1235 * 1236 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 1237 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 1238 * VCO_MAX * r2 > n2 * LC_FREQ and 1239 * VCO_MIN * r2 < n2 * LC_FREQ) 1240 * 1241 * Which means the desired boundaries for n2 are: 1242 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 1243 */ 1244 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 1245 n2 <= VCO_MAX * r2 / LC_FREQ; 1246 n2++) { 1247 1248 for (p = P_MIN; p <= P_MAX; p += P_INC) 1249 hsw_wrpll_update_rnp(freq2k, budget, 1250 r2, n2, p, &best); 1251 } 1252 } 1253 1254 *n2_out = best.n2; 1255 *p_out = best.p; 1256 *r2_out = best.r2; 1257 } 1258 1259 static bool 1260 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 1261 struct intel_crtc_state *crtc_state, 1262 struct intel_encoder *intel_encoder) 1263 { 1264 int clock = crtc_state->port_clock; 1265 1266 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1267 struct intel_shared_dpll *pll; 1268 uint32_t val; 1269 unsigned p, n2, r2; 1270 1271 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 1272 1273 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 1274 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 1275 WRPLL_DIVIDER_POST(p); 1276 1277 memset(&crtc_state->dpll_hw_state, 0, 1278 sizeof(crtc_state->dpll_hw_state)); 1279 1280 crtc_state->dpll_hw_state.wrpll = val; 1281 1282 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1283 if (pll == NULL) { 1284 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1285 pipe_name(intel_crtc->pipe)); 1286 return false; 1287 } 1288 1289 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1290 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { 1291 struct drm_atomic_state *state = crtc_state->base.state; 1292 struct intel_shared_dpll_config *spll = 1293 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; 1294 1295 if (spll->crtc_mask && 1296 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) 1297 return false; 1298 1299 crtc_state->shared_dpll = DPLL_ID_SPLL; 1300 spll->hw_state.spll = crtc_state->dpll_hw_state.spll; 1301 spll->crtc_mask |= 1 << intel_crtc->pipe; 1302 } 1303 1304 return true; 1305 } 1306 1307 struct skl_wrpll_context { 1308 uint64_t min_deviation; /* current minimal deviation */ 1309 uint64_t central_freq; /* chosen central freq */ 1310 uint64_t dco_freq; /* chosen dco freq */ 1311 unsigned int p; /* chosen divider */ 1312 }; 1313 1314 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) 1315 { 1316 memset(ctx, 0, sizeof(*ctx)); 1317 1318 ctx->min_deviation = U64_MAX; 1319 } 1320 1321 /* DCO freq must be within +1%/-6% of the DCO central freq */ 1322 #define SKL_DCO_MAX_PDEVIATION 100 1323 #define SKL_DCO_MAX_NDEVIATION 600 1324 1325 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, 1326 uint64_t central_freq, 1327 uint64_t dco_freq, 1328 unsigned int divider) 1329 { 1330 uint64_t deviation; 1331 1332 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), 1333 central_freq); 1334 1335 /* positive deviation */ 1336 if (dco_freq >= central_freq) { 1337 if (deviation < SKL_DCO_MAX_PDEVIATION && 1338 deviation < ctx->min_deviation) { 1339 ctx->min_deviation = deviation; 1340 ctx->central_freq = central_freq; 1341 ctx->dco_freq = dco_freq; 1342 ctx->p = divider; 1343 } 1344 /* negative deviation */ 1345 } else if (deviation < SKL_DCO_MAX_NDEVIATION && 1346 deviation < ctx->min_deviation) { 1347 ctx->min_deviation = deviation; 1348 ctx->central_freq = central_freq; 1349 ctx->dco_freq = dco_freq; 1350 ctx->p = divider; 1351 } 1352 } 1353 1354 static void skl_wrpll_get_multipliers(unsigned int p, 1355 unsigned int *p0 /* out */, 1356 unsigned int *p1 /* out */, 1357 unsigned int *p2 /* out */) 1358 { 1359 /* even dividers */ 1360 if (p % 2 == 0) { 1361 unsigned int half = p / 2; 1362 1363 if (half == 1 || half == 2 || half == 3 || half == 5) { 1364 *p0 = 2; 1365 *p1 = 1; 1366 *p2 = half; 1367 } else if (half % 2 == 0) { 1368 *p0 = 2; 1369 *p1 = half / 2; 1370 *p2 = 2; 1371 } else if (half % 3 == 0) { 1372 *p0 = 3; 1373 *p1 = half / 3; 1374 *p2 = 2; 1375 } else if (half % 7 == 0) { 1376 *p0 = 7; 1377 *p1 = half / 7; 1378 *p2 = 2; 1379 } 1380 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ 1381 *p0 = 3; 1382 *p1 = 1; 1383 *p2 = p / 3; 1384 } else if (p == 5 || p == 7) { 1385 *p0 = p; 1386 *p1 = 1; 1387 *p2 = 1; 1388 } else if (p == 15) { 1389 *p0 = 3; 1390 *p1 = 1; 1391 *p2 = 5; 1392 } else if (p == 21) { 1393 *p0 = 7; 1394 *p1 = 1; 1395 *p2 = 3; 1396 } else if (p == 35) { 1397 *p0 = 7; 1398 *p1 = 1; 1399 *p2 = 5; 1400 } 1401 } 1402 1403 struct skl_wrpll_params { 1404 uint32_t dco_fraction; 1405 uint32_t dco_integer; 1406 uint32_t qdiv_ratio; 1407 uint32_t qdiv_mode; 1408 uint32_t kdiv; 1409 uint32_t pdiv; 1410 uint32_t central_freq; 1411 }; 1412 1413 static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 1414 uint64_t afe_clock, 1415 uint64_t central_freq, 1416 uint32_t p0, uint32_t p1, uint32_t p2) 1417 { 1418 uint64_t dco_freq; 1419 1420 switch (central_freq) { 1421 case 9600000000ULL: 1422 params->central_freq = 0; 1423 break; 1424 case 9000000000ULL: 1425 params->central_freq = 1; 1426 break; 1427 case 8400000000ULL: 1428 params->central_freq = 3; 1429 } 1430 1431 switch (p0) { 1432 case 1: 1433 params->pdiv = 0; 1434 break; 1435 case 2: 1436 params->pdiv = 1; 1437 break; 1438 case 3: 1439 params->pdiv = 2; 1440 break; 1441 case 7: 1442 params->pdiv = 4; 1443 break; 1444 default: 1445 WARN(1, "Incorrect PDiv\n"); 1446 } 1447 1448 switch (p2) { 1449 case 5: 1450 params->kdiv = 0; 1451 break; 1452 case 2: 1453 params->kdiv = 1; 1454 break; 1455 case 3: 1456 params->kdiv = 2; 1457 break; 1458 case 1: 1459 params->kdiv = 3; 1460 break; 1461 default: 1462 WARN(1, "Incorrect KDiv\n"); 1463 } 1464 1465 params->qdiv_ratio = p1; 1466 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; 1467 1468 dco_freq = p0 * p1 * p2 * afe_clock; 1469 1470 /* 1471 * Intermediate values are in Hz. 1472 * Divide by MHz to match bsepc 1473 */ 1474 params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); 1475 params->dco_fraction = 1476 div_u64((div_u64(dco_freq, 24) - 1477 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); 1478 } 1479 1480 static bool 1481 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1482 struct skl_wrpll_params *wrpll_params) 1483 { 1484 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1485 uint64_t dco_central_freq[3] = {8400000000ULL, 1486 9000000000ULL, 1487 9600000000ULL}; 1488 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 1489 24, 28, 30, 32, 36, 40, 42, 44, 1490 48, 52, 54, 56, 60, 64, 66, 68, 1491 70, 72, 76, 78, 80, 84, 88, 90, 1492 92, 96, 98 }; 1493 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; 1494 static const struct { 1495 const int *list; 1496 int n_dividers; 1497 } dividers[] = { 1498 { even_dividers, ARRAY_SIZE(even_dividers) }, 1499 { odd_dividers, ARRAY_SIZE(odd_dividers) }, 1500 }; 1501 struct skl_wrpll_context ctx; 1502 unsigned int dco, d, i; 1503 unsigned int p0, p1, p2; 1504 1505 skl_wrpll_context_init(&ctx); 1506 1507 for (d = 0; d < ARRAY_SIZE(dividers); d++) { 1508 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { 1509 for (i = 0; i < dividers[d].n_dividers; i++) { 1510 unsigned int p = dividers[d].list[i]; 1511 uint64_t dco_freq = p * afe_clock; 1512 1513 skl_wrpll_try_divider(&ctx, 1514 dco_central_freq[dco], 1515 dco_freq, 1516 p); 1517 /* 1518 * Skip the remaining dividers if we're sure to 1519 * have found the definitive divider, we can't 1520 * improve a 0 deviation. 1521 */ 1522 if (ctx.min_deviation == 0) 1523 goto skip_remaining_dividers; 1524 } 1525 } 1526 1527 skip_remaining_dividers: 1528 /* 1529 * If a solution is found with an even divider, prefer 1530 * this one. 1531 */ 1532 if (d == 0 && ctx.p) 1533 break; 1534 } 1535 1536 if (!ctx.p) { 1537 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); 1538 return false; 1539 } 1540 1541 /* 1542 * gcc incorrectly analyses that these can be used without being 1543 * initialized. To be fair, it's hard to guess. 1544 */ 1545 p0 = p1 = p2 = 0; 1546 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); 1547 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, 1548 p0, p1, p2); 1549 1550 return true; 1551 } 1552 1553 static bool 1554 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1555 struct intel_crtc_state *crtc_state, 1556 struct intel_encoder *intel_encoder) 1557 { 1558 struct intel_shared_dpll *pll; 1559 uint32_t ctrl1, cfgcr1, cfgcr2; 1560 int clock = crtc_state->port_clock; 1561 1562 /* 1563 * See comment in intel_dpll_hw_state to understand why we always use 0 1564 * as the DPLL id in this function. 1565 */ 1566 1567 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1568 1569 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1570 struct skl_wrpll_params wrpll_params = { 0, }; 1571 1572 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1573 1574 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) 1575 return false; 1576 1577 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1578 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1579 wrpll_params.dco_integer; 1580 1581 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1582 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1583 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1584 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1585 wrpll_params.central_freq; 1586 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1587 switch (crtc_state->port_clock / 2) { 1588 case 81000: 1589 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1590 break; 1591 case 135000: 1592 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1593 break; 1594 case 270000: 1595 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1596 break; 1597 } 1598 1599 cfgcr1 = cfgcr2 = 0; 1600 } else /* eDP */ 1601 return true; 1602 1603 memset(&crtc_state->dpll_hw_state, 0, 1604 sizeof(crtc_state->dpll_hw_state)); 1605 1606 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1607 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1608 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1609 1610 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1611 if (pll == NULL) { 1612 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1613 pipe_name(intel_crtc->pipe)); 1614 return false; 1615 } 1616 1617 /* shared DPLL id 0 is DPLL 1 */ 1618 crtc_state->ddi_pll_sel = pll->id + 1; 1619 1620 return true; 1621 } 1622 1623 /* bxt clock parameters */ 1624 struct bxt_clk_div { 1625 int clock; 1626 uint32_t p1; 1627 uint32_t p2; 1628 uint32_t m2_int; 1629 uint32_t m2_frac; 1630 bool m2_frac_en; 1631 uint32_t n; 1632 }; 1633 1634 /* pre-calculated values for DP linkrates */ 1635 static const struct bxt_clk_div bxt_dp_clk_val[] = { 1636 {162000, 4, 2, 32, 1677722, 1, 1}, 1637 {270000, 4, 1, 27, 0, 0, 1}, 1638 {540000, 2, 1, 27, 0, 0, 1}, 1639 {216000, 3, 2, 32, 1677722, 1, 1}, 1640 {243000, 4, 1, 24, 1258291, 1, 1}, 1641 {324000, 4, 1, 32, 1677722, 1, 1}, 1642 {432000, 3, 1, 32, 1677722, 1, 1} 1643 }; 1644 1645 static bool 1646 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 1647 struct intel_crtc_state *crtc_state, 1648 struct intel_encoder *intel_encoder) 1649 { 1650 struct intel_shared_dpll *pll; 1651 struct bxt_clk_div clk_div = {0}; 1652 int vco = 0; 1653 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1654 uint32_t lanestagger; 1655 int clock = crtc_state->port_clock; 1656 1657 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1658 intel_clock_t best_clock; 1659 1660 /* Calculate HDMI div */ 1661 /* 1662 * FIXME: tie the following calculation into 1663 * i9xx_crtc_compute_clock 1664 */ 1665 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1666 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1667 clock, pipe_name(intel_crtc->pipe)); 1668 return false; 1669 } 1670 1671 clk_div.p1 = best_clock.p1; 1672 clk_div.p2 = best_clock.p2; 1673 WARN_ON(best_clock.m1 != 2); 1674 clk_div.n = best_clock.n; 1675 clk_div.m2_int = best_clock.m2 >> 22; 1676 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1677 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1678 1679 vco = best_clock.vco; 1680 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1681 intel_encoder->type == INTEL_OUTPUT_EDP) { 1682 int i; 1683 1684 clk_div = bxt_dp_clk_val[0]; 1685 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { 1686 if (bxt_dp_clk_val[i].clock == clock) { 1687 clk_div = bxt_dp_clk_val[i]; 1688 break; 1689 } 1690 } 1691 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1692 } 1693 1694 if (vco >= 6200000 && vco <= 6700000) { 1695 prop_coef = 4; 1696 int_coef = 9; 1697 gain_ctl = 3; 1698 targ_cnt = 8; 1699 } else if ((vco > 5400000 && vco < 6200000) || 1700 (vco >= 4800000 && vco < 5400000)) { 1701 prop_coef = 5; 1702 int_coef = 11; 1703 gain_ctl = 3; 1704 targ_cnt = 9; 1705 } else if (vco == 5400000) { 1706 prop_coef = 3; 1707 int_coef = 8; 1708 gain_ctl = 1; 1709 targ_cnt = 9; 1710 } else { 1711 DRM_ERROR("Invalid VCO\n"); 1712 return false; 1713 } 1714 1715 memset(&crtc_state->dpll_hw_state, 0, 1716 sizeof(crtc_state->dpll_hw_state)); 1717 1718 if (clock > 270000) 1719 lanestagger = 0x18; 1720 else if (clock > 135000) 1721 lanestagger = 0x0d; 1722 else if (clock > 67000) 1723 lanestagger = 0x07; 1724 else if (clock > 33000) 1725 lanestagger = 0x04; 1726 else 1727 lanestagger = 0x02; 1728 1729 crtc_state->dpll_hw_state.ebb0 = 1730 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1731 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1732 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1733 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1734 1735 if (clk_div.m2_frac_en) 1736 crtc_state->dpll_hw_state.pll3 = 1737 PORT_PLL_M2_FRAC_ENABLE; 1738 1739 crtc_state->dpll_hw_state.pll6 = 1740 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1741 crtc_state->dpll_hw_state.pll6 |= 1742 PORT_PLL_GAIN_CTL(gain_ctl); 1743 1744 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1745 1746 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; 1747 1748 crtc_state->dpll_hw_state.pll10 = 1749 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) 1750 | PORT_PLL_DCO_AMP_OVR_EN_H; 1751 1752 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; 1753 1754 crtc_state->dpll_hw_state.pcsdw12 = 1755 LANESTAGGER_STRAP_OVRD | lanestagger; 1756 1757 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1758 if (pll == NULL) { 1759 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1760 pipe_name(intel_crtc->pipe)); 1761 return false; 1762 } 1763 1764 /* shared DPLL id 0 is DPLL A */ 1765 crtc_state->ddi_pll_sel = pll->id; 1766 1767 return true; 1768 } 1769 1770 /* 1771 * Tries to find a *shared* PLL for the CRTC and store it in 1772 * intel_crtc->ddi_pll_sel. 1773 * 1774 * For private DPLLs, compute_config() should do the selection for us. This 1775 * function should be folded into compute_config() eventually. 1776 */ 1777 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1778 struct intel_crtc_state *crtc_state) 1779 { 1780 struct drm_device *dev = intel_crtc->base.dev; 1781 struct intel_encoder *intel_encoder = 1782 intel_ddi_get_crtc_new_encoder(crtc_state); 1783 1784 if (IS_SKYLAKE(dev)) 1785 return skl_ddi_pll_select(intel_crtc, crtc_state, 1786 intel_encoder); 1787 else if (IS_BROXTON(dev)) 1788 return bxt_ddi_pll_select(intel_crtc, crtc_state, 1789 intel_encoder); 1790 else 1791 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1792 intel_encoder); 1793 } 1794 1795 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1796 { 1797 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1799 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1800 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1801 int type = intel_encoder->type; 1802 uint32_t temp; 1803 1804 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1805 temp = TRANS_MSA_SYNC_CLK; 1806 switch (intel_crtc->config->pipe_bpp) { 1807 case 18: 1808 temp |= TRANS_MSA_6_BPC; 1809 break; 1810 case 24: 1811 temp |= TRANS_MSA_8_BPC; 1812 break; 1813 case 30: 1814 temp |= TRANS_MSA_10_BPC; 1815 break; 1816 case 36: 1817 temp |= TRANS_MSA_12_BPC; 1818 break; 1819 default: 1820 BUG(); 1821 } 1822 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1823 } 1824 } 1825 1826 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1827 { 1828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1829 struct drm_device *dev = crtc->dev; 1830 struct drm_i915_private *dev_priv = dev->dev_private; 1831 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1832 uint32_t temp; 1833 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1834 if (state == true) 1835 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1836 else 1837 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1838 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1839 } 1840 1841 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1842 { 1843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1844 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1845 struct drm_encoder *encoder = &intel_encoder->base; 1846 struct drm_device *dev = crtc->dev; 1847 struct drm_i915_private *dev_priv = dev->dev_private; 1848 enum i915_pipe pipe = intel_crtc->pipe; 1849 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1850 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1851 int type = intel_encoder->type; 1852 uint32_t temp; 1853 1854 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1855 temp = TRANS_DDI_FUNC_ENABLE; 1856 temp |= TRANS_DDI_SELECT_PORT(port); 1857 1858 switch (intel_crtc->config->pipe_bpp) { 1859 case 18: 1860 temp |= TRANS_DDI_BPC_6; 1861 break; 1862 case 24: 1863 temp |= TRANS_DDI_BPC_8; 1864 break; 1865 case 30: 1866 temp |= TRANS_DDI_BPC_10; 1867 break; 1868 case 36: 1869 temp |= TRANS_DDI_BPC_12; 1870 break; 1871 default: 1872 BUG(); 1873 } 1874 1875 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1876 temp |= TRANS_DDI_PVSYNC; 1877 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1878 temp |= TRANS_DDI_PHSYNC; 1879 1880 if (cpu_transcoder == TRANSCODER_EDP) { 1881 switch (pipe) { 1882 case PIPE_A: 1883 /* On Haswell, can only use the always-on power well for 1884 * eDP when not using the panel fitter, and when not 1885 * using motion blur mitigation (which we don't 1886 * support). */ 1887 if (IS_HASWELL(dev) && 1888 (intel_crtc->config->pch_pfit.enabled || 1889 intel_crtc->config->pch_pfit.force_thru)) 1890 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1891 else 1892 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1893 break; 1894 case PIPE_B: 1895 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1896 break; 1897 case PIPE_C: 1898 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1899 break; 1900 default: 1901 BUG(); 1902 break; 1903 } 1904 } 1905 1906 if (type == INTEL_OUTPUT_HDMI) { 1907 if (intel_crtc->config->has_hdmi_sink) 1908 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1909 else 1910 temp |= TRANS_DDI_MODE_SELECT_DVI; 1911 1912 } else if (type == INTEL_OUTPUT_ANALOG) { 1913 temp |= TRANS_DDI_MODE_SELECT_FDI; 1914 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1915 1916 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1917 type == INTEL_OUTPUT_EDP) { 1918 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1919 1920 if (intel_dp->is_mst) { 1921 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1922 } else 1923 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1924 1925 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1926 } else if (type == INTEL_OUTPUT_DP_MST) { 1927 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1928 1929 if (intel_dp->is_mst) { 1930 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1931 } else 1932 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1933 1934 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1935 } else { 1936 WARN(1, "Invalid encoder type %d for pipe %c\n", 1937 intel_encoder->type, pipe_name(pipe)); 1938 } 1939 1940 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1941 } 1942 1943 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1944 enum transcoder cpu_transcoder) 1945 { 1946 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1947 uint32_t val = I915_READ(reg); 1948 1949 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1950 val |= TRANS_DDI_PORT_NONE; 1951 I915_WRITE(reg, val); 1952 } 1953 1954 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1955 { 1956 struct drm_device *dev = intel_connector->base.dev; 1957 struct drm_i915_private *dev_priv = dev->dev_private; 1958 struct intel_encoder *intel_encoder = intel_connector->encoder; 1959 int type = intel_connector->base.connector_type; 1960 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1961 enum i915_pipe pipe = 0; 1962 enum transcoder cpu_transcoder; 1963 enum intel_display_power_domain power_domain; 1964 uint32_t tmp; 1965 1966 power_domain = intel_display_port_power_domain(intel_encoder); 1967 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1968 return false; 1969 1970 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1971 return false; 1972 1973 if (port == PORT_A) 1974 cpu_transcoder = TRANSCODER_EDP; 1975 else 1976 cpu_transcoder = (enum transcoder) pipe; 1977 1978 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1979 1980 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1981 case TRANS_DDI_MODE_SELECT_HDMI: 1982 case TRANS_DDI_MODE_SELECT_DVI: 1983 return (type == DRM_MODE_CONNECTOR_HDMIA); 1984 1985 case TRANS_DDI_MODE_SELECT_DP_SST: 1986 if (type == DRM_MODE_CONNECTOR_eDP) 1987 return true; 1988 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1989 case TRANS_DDI_MODE_SELECT_DP_MST: 1990 /* if the transcoder is in MST state then 1991 * connector isn't connected */ 1992 return false; 1993 1994 case TRANS_DDI_MODE_SELECT_FDI: 1995 return (type == DRM_MODE_CONNECTOR_VGA); 1996 1997 default: 1998 return false; 1999 } 2000 } 2001 2002 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2003 enum i915_pipe *pipe) 2004 { 2005 struct drm_device *dev = encoder->base.dev; 2006 struct drm_i915_private *dev_priv = dev->dev_private; 2007 enum port port = intel_ddi_get_encoder_port(encoder); 2008 enum intel_display_power_domain power_domain; 2009 u32 tmp; 2010 int i; 2011 2012 power_domain = intel_display_port_power_domain(encoder); 2013 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 2014 return false; 2015 2016 tmp = I915_READ(DDI_BUF_CTL(port)); 2017 2018 if (!(tmp & DDI_BUF_CTL_ENABLE)) 2019 return false; 2020 2021 if (port == PORT_A) { 2022 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2023 2024 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2025 case TRANS_DDI_EDP_INPUT_A_ON: 2026 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2027 *pipe = PIPE_A; 2028 break; 2029 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2030 *pipe = PIPE_B; 2031 break; 2032 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2033 *pipe = PIPE_C; 2034 break; 2035 } 2036 2037 return true; 2038 } else { 2039 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 2040 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 2041 2042 if ((tmp & TRANS_DDI_PORT_MASK) 2043 == TRANS_DDI_SELECT_PORT(port)) { 2044 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) 2045 return false; 2046 2047 *pipe = i; 2048 return true; 2049 } 2050 } 2051 } 2052 2053 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 2054 2055 return false; 2056 } 2057 2058 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 2059 { 2060 struct drm_crtc *crtc = &intel_crtc->base; 2061 struct drm_device *dev = crtc->dev; 2062 struct drm_i915_private *dev_priv = dev->dev_private; 2063 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2064 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2065 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2066 2067 if (cpu_transcoder != TRANSCODER_EDP) 2068 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2069 TRANS_CLK_SEL_PORT(port)); 2070 } 2071 2072 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 2073 { 2074 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 2075 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2076 2077 if (cpu_transcoder != TRANSCODER_EDP) 2078 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2079 TRANS_CLK_SEL_DISABLED); 2080 } 2081 2082 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level, 2083 enum port port, int type) 2084 { 2085 struct drm_i915_private *dev_priv = dev->dev_private; 2086 const struct ddi_buf_trans *ddi_translations; 2087 uint8_t iboost; 2088 uint8_t dp_iboost, hdmi_iboost; 2089 int n_entries; 2090 u32 reg; 2091 2092 /* VBT may override standard boost values */ 2093 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2094 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2095 2096 if (type == INTEL_OUTPUT_DISPLAYPORT) { 2097 if (dp_iboost) { 2098 iboost = dp_iboost; 2099 } else { 2100 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries); 2101 iboost = ddi_translations[port].i_boost; 2102 } 2103 } else if (type == INTEL_OUTPUT_EDP) { 2104 if (dp_iboost) { 2105 iboost = dp_iboost; 2106 } else { 2107 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries); 2108 iboost = ddi_translations[port].i_boost; 2109 } 2110 } else if (type == INTEL_OUTPUT_HDMI) { 2111 if (hdmi_iboost) { 2112 iboost = hdmi_iboost; 2113 } else { 2114 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries); 2115 iboost = ddi_translations[port].i_boost; 2116 } 2117 } else { 2118 return; 2119 } 2120 2121 /* Make sure that the requested I_boost is valid */ 2122 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2123 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2124 return; 2125 } 2126 2127 reg = I915_READ(DISPIO_CR_TX_BMU_CR0); 2128 reg &= ~BALANCE_LEG_MASK(port); 2129 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); 2130 2131 if (iboost) 2132 reg |= iboost << BALANCE_LEG_SHIFT(port); 2133 else 2134 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); 2135 2136 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); 2137 } 2138 2139 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 2140 enum port port, int type) 2141 { 2142 struct drm_i915_private *dev_priv = dev->dev_private; 2143 const struct bxt_ddi_buf_trans *ddi_translations; 2144 u32 n_entries, i; 2145 uint32_t val; 2146 2147 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) { 2148 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 2149 ddi_translations = bxt_ddi_translations_edp; 2150 } else if (type == INTEL_OUTPUT_DISPLAYPORT 2151 || type == INTEL_OUTPUT_EDP) { 2152 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 2153 ddi_translations = bxt_ddi_translations_dp; 2154 } else if (type == INTEL_OUTPUT_HDMI) { 2155 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 2156 ddi_translations = bxt_ddi_translations_hdmi; 2157 } else { 2158 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 2159 type); 2160 return; 2161 } 2162 2163 /* Check if default value has to be used */ 2164 if (level >= n_entries || 2165 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 2166 for (i = 0; i < n_entries; i++) { 2167 if (ddi_translations[i].default_index) { 2168 level = i; 2169 break; 2170 } 2171 } 2172 } 2173 2174 /* 2175 * While we write to the group register to program all lanes at once we 2176 * can read only lane registers and we pick lanes 0/1 for that. 2177 */ 2178 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2179 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 2180 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2181 2182 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); 2183 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 2184 val |= ddi_translations[level].margin << MARGIN_000_SHIFT | 2185 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; 2186 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); 2187 2188 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); 2189 val &= ~SCALE_DCOMP_METHOD; 2190 if (ddi_translations[level].enable) 2191 val |= SCALE_DCOMP_METHOD; 2192 2193 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 2194 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); 2195 2196 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); 2197 2198 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); 2199 val &= ~DE_EMPHASIS; 2200 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; 2201 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); 2202 2203 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2204 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 2205 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2206 } 2207 2208 static uint32_t translate_signal_level(int signal_levels) 2209 { 2210 uint32_t level; 2211 2212 switch (signal_levels) { 2213 default: 2214 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2215 signal_levels); 2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2217 level = 0; 2218 break; 2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2220 level = 1; 2221 break; 2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2223 level = 2; 2224 break; 2225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: 2226 level = 3; 2227 break; 2228 2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2230 level = 4; 2231 break; 2232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2233 level = 5; 2234 break; 2235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2236 level = 6; 2237 break; 2238 2239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2240 level = 7; 2241 break; 2242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2243 level = 8; 2244 break; 2245 2246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2247 level = 9; 2248 break; 2249 } 2250 2251 return level; 2252 } 2253 2254 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 2255 { 2256 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2257 struct drm_device *dev = dport->base.base.dev; 2258 struct intel_encoder *encoder = &dport->base; 2259 uint8_t train_set = intel_dp->train_set[0]; 2260 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2261 DP_TRAIN_PRE_EMPHASIS_MASK); 2262 enum port port = dport->port; 2263 uint32_t level; 2264 2265 level = translate_signal_level(signal_levels); 2266 2267 if (IS_SKYLAKE(dev)) 2268 skl_ddi_set_iboost(dev, level, port, encoder->type); 2269 else if (IS_BROXTON(dev)) 2270 bxt_ddi_vswing_sequence(dev, level, port, encoder->type); 2271 2272 return DDI_BUF_TRANS_SELECT(level); 2273 } 2274 2275 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 2276 { 2277 struct drm_encoder *encoder = &intel_encoder->base; 2278 struct drm_device *dev = encoder->dev; 2279 struct drm_i915_private *dev_priv = dev->dev_private; 2280 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 2281 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2282 int type = intel_encoder->type; 2283 int hdmi_level; 2284 2285 if (type == INTEL_OUTPUT_EDP) { 2286 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2287 intel_edp_panel_on(intel_dp); 2288 } 2289 2290 if (IS_SKYLAKE(dev)) { 2291 uint32_t dpll = crtc->config->ddi_pll_sel; 2292 uint32_t val; 2293 2294 /* 2295 * DPLL0 is used for eDP and is the only "private" DPLL (as 2296 * opposed to shared) on SKL 2297 */ 2298 if (type == INTEL_OUTPUT_EDP) { 2299 WARN_ON(dpll != SKL_DPLL0); 2300 2301 val = I915_READ(DPLL_CTRL1); 2302 2303 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 2304 DPLL_CTRL1_SSC(dpll) | 2305 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2306 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); 2307 2308 I915_WRITE(DPLL_CTRL1, val); 2309 POSTING_READ(DPLL_CTRL1); 2310 } 2311 2312 /* DDI -> PLL mapping */ 2313 val = I915_READ(DPLL_CTRL2); 2314 2315 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2316 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2317 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 2318 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2319 2320 I915_WRITE(DPLL_CTRL2, val); 2321 2322 } else if (INTEL_INFO(dev)->gen < 9) { 2323 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); 2324 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); 2325 } 2326 2327 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2328 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2329 2330 intel_dp_set_link_params(intel_dp, crtc->config); 2331 2332 intel_ddi_init_dp_buf_reg(intel_encoder); 2333 2334 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2335 intel_dp_start_link_train(intel_dp); 2336 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) 2337 intel_dp_stop_link_train(intel_dp); 2338 } else if (type == INTEL_OUTPUT_HDMI) { 2339 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2340 2341 if (IS_BROXTON(dev)) { 2342 hdmi_level = dev_priv->vbt. 2343 ddi_port_info[port].hdmi_level_shift; 2344 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 2345 INTEL_OUTPUT_HDMI); 2346 } 2347 intel_hdmi->set_infoframes(encoder, 2348 crtc->config->has_hdmi_sink, 2349 &crtc->config->base.adjusted_mode); 2350 } 2351 } 2352 2353 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 2354 { 2355 struct drm_encoder *encoder = &intel_encoder->base; 2356 struct drm_device *dev = encoder->dev; 2357 struct drm_i915_private *dev_priv = dev->dev_private; 2358 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2359 int type = intel_encoder->type; 2360 uint32_t val; 2361 bool wait = false; 2362 2363 val = I915_READ(DDI_BUF_CTL(port)); 2364 if (val & DDI_BUF_CTL_ENABLE) { 2365 val &= ~DDI_BUF_CTL_ENABLE; 2366 I915_WRITE(DDI_BUF_CTL(port), val); 2367 wait = true; 2368 } 2369 2370 val = I915_READ(DP_TP_CTL(port)); 2371 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2372 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2373 I915_WRITE(DP_TP_CTL(port), val); 2374 2375 if (wait) 2376 intel_wait_ddi_buf_idle(dev_priv, port); 2377 2378 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2379 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2380 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2381 intel_edp_panel_vdd_on(intel_dp); 2382 intel_edp_panel_off(intel_dp); 2383 } 2384 2385 if (IS_SKYLAKE(dev)) 2386 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 2387 DPLL_CTRL2_DDI_CLK_OFF(port))); 2388 else if (INTEL_INFO(dev)->gen < 9) 2389 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2390 } 2391 2392 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 2393 { 2394 struct drm_encoder *encoder = &intel_encoder->base; 2395 struct drm_crtc *crtc = encoder->crtc; 2396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2397 struct drm_device *dev = encoder->dev; 2398 struct drm_i915_private *dev_priv = dev->dev_private; 2399 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2400 int type = intel_encoder->type; 2401 2402 if (type == INTEL_OUTPUT_HDMI) { 2403 struct intel_digital_port *intel_dig_port = 2404 enc_to_dig_port(encoder); 2405 2406 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2407 * are ignored so nothing special needs to be done besides 2408 * enabling the port. 2409 */ 2410 I915_WRITE(DDI_BUF_CTL(port), 2411 intel_dig_port->saved_port_bits | 2412 DDI_BUF_CTL_ENABLE); 2413 } else if (type == INTEL_OUTPUT_EDP) { 2414 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2415 2416 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 2417 intel_dp_stop_link_train(intel_dp); 2418 2419 intel_edp_backlight_on(intel_dp); 2420 intel_psr_enable(intel_dp); 2421 intel_edp_drrs_enable(intel_dp); 2422 } 2423 2424 if (intel_crtc->config->has_audio) { 2425 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 2426 intel_audio_codec_enable(intel_encoder); 2427 } 2428 } 2429 2430 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 2431 { 2432 struct drm_encoder *encoder = &intel_encoder->base; 2433 struct drm_crtc *crtc = encoder->crtc; 2434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2435 int type = intel_encoder->type; 2436 struct drm_device *dev = encoder->dev; 2437 struct drm_i915_private *dev_priv = dev->dev_private; 2438 2439 if (intel_crtc->config->has_audio) { 2440 intel_audio_codec_disable(intel_encoder); 2441 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 2442 } 2443 2444 if (type == INTEL_OUTPUT_EDP) { 2445 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2446 2447 intel_edp_drrs_disable(intel_dp); 2448 intel_psr_disable(intel_dp); 2449 intel_edp_backlight_off(intel_dp); 2450 } 2451 } 2452 2453 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, 2454 struct intel_shared_dpll *pll) 2455 { 2456 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 2457 POSTING_READ(WRPLL_CTL(pll->id)); 2458 udelay(20); 2459 } 2460 2461 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, 2462 struct intel_shared_dpll *pll) 2463 { 2464 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); 2465 POSTING_READ(SPLL_CTL); 2466 udelay(20); 2467 } 2468 2469 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 2470 struct intel_shared_dpll *pll) 2471 { 2472 uint32_t val; 2473 2474 val = I915_READ(WRPLL_CTL(pll->id)); 2475 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 2476 POSTING_READ(WRPLL_CTL(pll->id)); 2477 } 2478 2479 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 2480 struct intel_shared_dpll *pll) 2481 { 2482 uint32_t val; 2483 2484 val = I915_READ(SPLL_CTL); 2485 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 2486 POSTING_READ(SPLL_CTL); 2487 } 2488 2489 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, 2490 struct intel_shared_dpll *pll, 2491 struct intel_dpll_hw_state *hw_state) 2492 { 2493 uint32_t val; 2494 2495 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2496 return false; 2497 2498 val = I915_READ(WRPLL_CTL(pll->id)); 2499 hw_state->wrpll = val; 2500 2501 return val & WRPLL_PLL_ENABLE; 2502 } 2503 2504 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 2505 struct intel_shared_dpll *pll, 2506 struct intel_dpll_hw_state *hw_state) 2507 { 2508 uint32_t val; 2509 2510 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2511 return false; 2512 2513 val = I915_READ(SPLL_CTL); 2514 hw_state->spll = val; 2515 2516 return val & SPLL_PLL_ENABLE; 2517 } 2518 2519 2520 static const char * const hsw_ddi_pll_names[] = { 2521 "WRPLL 1", 2522 "WRPLL 2", 2523 "SPLL" 2524 }; 2525 2526 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 2527 { 2528 int i; 2529 2530 dev_priv->num_shared_dpll = 3; 2531 2532 for (i = 0; i < 2; i++) { 2533 dev_priv->shared_dplls[i].id = i; 2534 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2535 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; 2536 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; 2537 dev_priv->shared_dplls[i].get_hw_state = 2538 hsw_ddi_wrpll_get_hw_state; 2539 } 2540 2541 /* SPLL is special, but needs to be initialized anyway.. */ 2542 dev_priv->shared_dplls[i].id = i; 2543 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2544 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; 2545 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; 2546 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; 2547 2548 } 2549 2550 static const char * const skl_ddi_pll_names[] = { 2551 "DPLL 1", 2552 "DPLL 2", 2553 "DPLL 3", 2554 }; 2555 2556 struct skl_dpll_regs { 2557 u32 ctl, cfgcr1, cfgcr2; 2558 }; 2559 2560 /* this array is indexed by the *shared* pll id */ 2561 static const struct skl_dpll_regs skl_dpll_regs[3] = { 2562 { 2563 /* DPLL 1 */ 2564 .ctl = LCPLL2_CTL, 2565 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), 2566 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), 2567 }, 2568 { 2569 /* DPLL 2 */ 2570 .ctl = WRPLL_CTL1, 2571 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), 2572 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), 2573 }, 2574 { 2575 /* DPLL 3 */ 2576 .ctl = WRPLL_CTL2, 2577 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), 2578 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), 2579 }, 2580 }; 2581 2582 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 2583 struct intel_shared_dpll *pll) 2584 { 2585 uint32_t val; 2586 unsigned int dpll; 2587 const struct skl_dpll_regs *regs = skl_dpll_regs; 2588 2589 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2590 dpll = pll->id + 1; 2591 2592 val = I915_READ(DPLL_CTRL1); 2593 2594 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 2595 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2596 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 2597 2598 I915_WRITE(DPLL_CTRL1, val); 2599 POSTING_READ(DPLL_CTRL1); 2600 2601 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 2602 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 2603 POSTING_READ(regs[pll->id].cfgcr1); 2604 POSTING_READ(regs[pll->id].cfgcr2); 2605 2606 /* the enable bit is always bit 31 */ 2607 I915_WRITE(regs[pll->id].ctl, 2608 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 2609 2610 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 2611 DRM_ERROR("DPLL %d not locked\n", dpll); 2612 } 2613 2614 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 2615 struct intel_shared_dpll *pll) 2616 { 2617 const struct skl_dpll_regs *regs = skl_dpll_regs; 2618 2619 /* the enable bit is always bit 31 */ 2620 I915_WRITE(regs[pll->id].ctl, 2621 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 2622 POSTING_READ(regs[pll->id].ctl); 2623 } 2624 2625 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2626 struct intel_shared_dpll *pll, 2627 struct intel_dpll_hw_state *hw_state) 2628 { 2629 uint32_t val; 2630 unsigned int dpll; 2631 const struct skl_dpll_regs *regs = skl_dpll_regs; 2632 2633 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2634 return false; 2635 2636 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2637 dpll = pll->id + 1; 2638 2639 val = I915_READ(regs[pll->id].ctl); 2640 if (!(val & LCPLL_PLL_ENABLE)) 2641 return false; 2642 2643 val = I915_READ(DPLL_CTRL1); 2644 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 2645 2646 /* avoid reading back stale values if HDMI mode is not enabled */ 2647 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 2648 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 2649 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 2650 } 2651 2652 return true; 2653 } 2654 2655 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 2656 { 2657 int i; 2658 2659 dev_priv->num_shared_dpll = 3; 2660 2661 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2662 dev_priv->shared_dplls[i].id = i; 2663 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 2664 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 2665 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 2666 dev_priv->shared_dplls[i].get_hw_state = 2667 skl_ddi_pll_get_hw_state; 2668 } 2669 } 2670 2671 static void broxton_phy_init(struct drm_i915_private *dev_priv, 2672 enum dpio_phy phy) 2673 { 2674 enum port port; 2675 uint32_t val; 2676 2677 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 2678 val |= GT_DISPLAY_POWER_ON(phy); 2679 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 2680 2681 /* Considering 10ms timeout until BSpec is updated */ 2682 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) 2683 DRM_ERROR("timeout during PHY%d power on\n", phy); 2684 2685 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); 2686 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { 2687 int lane; 2688 2689 for (lane = 0; lane < 4; lane++) { 2690 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); 2691 /* 2692 * Note that on CHV this flag is called UPAR, but has 2693 * the same function. 2694 */ 2695 val &= ~LATENCY_OPTIM; 2696 if (lane != 1) 2697 val |= LATENCY_OPTIM; 2698 2699 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); 2700 } 2701 } 2702 2703 /* Program PLL Rcomp code offset */ 2704 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 2705 val &= ~IREF0RC_OFFSET_MASK; 2706 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 2707 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 2708 2709 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 2710 val &= ~IREF1RC_OFFSET_MASK; 2711 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 2712 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 2713 2714 /* Program power gating */ 2715 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 2716 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 2717 SUS_CLK_CONFIG; 2718 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 2719 2720 if (phy == DPIO_PHY0) { 2721 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); 2722 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 2723 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); 2724 } 2725 2726 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); 2727 val &= ~OCL2_LDOFUSE_PWR_DIS; 2728 /* 2729 * On PHY1 disable power on the second channel, since no port is 2730 * connected there. On PHY0 both channels have a port, so leave it 2731 * enabled. 2732 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should 2733 * power down the second channel on PHY0 as well. 2734 */ 2735 if (phy == DPIO_PHY1) 2736 val |= OCL2_LDOFUSE_PWR_DIS; 2737 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); 2738 2739 if (phy == DPIO_PHY0) { 2740 uint32_t grc_code; 2741 /* 2742 * PHY0 isn't connected to an RCOMP resistor so copy over 2743 * the corresponding calibrated value from PHY1, and disable 2744 * the automatic calibration on PHY0. 2745 */ 2746 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, 2747 10)) 2748 DRM_ERROR("timeout waiting for PHY1 GRC\n"); 2749 2750 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); 2751 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 2752 grc_code = val << GRC_CODE_FAST_SHIFT | 2753 val << GRC_CODE_SLOW_SHIFT | 2754 val; 2755 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); 2756 2757 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); 2758 val |= GRC_DIS | GRC_RDY_OVRD; 2759 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); 2760 } 2761 2762 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2763 val |= COMMON_RESET_DIS; 2764 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2765 } 2766 2767 void broxton_ddi_phy_init(struct drm_device *dev) 2768 { 2769 /* Enable PHY1 first since it provides Rcomp for PHY0 */ 2770 broxton_phy_init(dev->dev_private, DPIO_PHY1); 2771 broxton_phy_init(dev->dev_private, DPIO_PHY0); 2772 } 2773 2774 static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 2775 enum dpio_phy phy) 2776 { 2777 uint32_t val; 2778 2779 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2780 val &= ~COMMON_RESET_DIS; 2781 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2782 } 2783 2784 void broxton_ddi_phy_uninit(struct drm_device *dev) 2785 { 2786 struct drm_i915_private *dev_priv = dev->dev_private; 2787 2788 broxton_phy_uninit(dev_priv, DPIO_PHY1); 2789 broxton_phy_uninit(dev_priv, DPIO_PHY0); 2790 2791 /* FIXME: do this in broxton_phy_uninit per phy */ 2792 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); 2793 } 2794 2795 static const char * const bxt_ddi_pll_names[] = { 2796 "PORT PLL A", 2797 "PORT PLL B", 2798 "PORT PLL C", 2799 }; 2800 2801 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 2802 struct intel_shared_dpll *pll) 2803 { 2804 uint32_t temp; 2805 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2806 2807 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2808 temp &= ~PORT_PLL_REF_SEL; 2809 /* Non-SSC reference */ 2810 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2811 2812 /* Disable 10 bit clock */ 2813 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2814 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2815 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2816 2817 /* Write P1 & P2 */ 2818 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2819 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 2820 temp |= pll->config.hw_state.ebb0; 2821 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 2822 2823 /* Write M2 integer */ 2824 temp = I915_READ(BXT_PORT_PLL(port, 0)); 2825 temp &= ~PORT_PLL_M2_MASK; 2826 temp |= pll->config.hw_state.pll0; 2827 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 2828 2829 /* Write N */ 2830 temp = I915_READ(BXT_PORT_PLL(port, 1)); 2831 temp &= ~PORT_PLL_N_MASK; 2832 temp |= pll->config.hw_state.pll1; 2833 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 2834 2835 /* Write M2 fraction */ 2836 temp = I915_READ(BXT_PORT_PLL(port, 2)); 2837 temp &= ~PORT_PLL_M2_FRAC_MASK; 2838 temp |= pll->config.hw_state.pll2; 2839 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 2840 2841 /* Write M2 fraction enable */ 2842 temp = I915_READ(BXT_PORT_PLL(port, 3)); 2843 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 2844 temp |= pll->config.hw_state.pll3; 2845 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 2846 2847 /* Write coeff */ 2848 temp = I915_READ(BXT_PORT_PLL(port, 6)); 2849 temp &= ~PORT_PLL_PROP_COEFF_MASK; 2850 temp &= ~PORT_PLL_INT_COEFF_MASK; 2851 temp &= ~PORT_PLL_GAIN_CTL_MASK; 2852 temp |= pll->config.hw_state.pll6; 2853 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 2854 2855 /* Write calibration val */ 2856 temp = I915_READ(BXT_PORT_PLL(port, 8)); 2857 temp &= ~PORT_PLL_TARGET_CNT_MASK; 2858 temp |= pll->config.hw_state.pll8; 2859 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 2860 2861 temp = I915_READ(BXT_PORT_PLL(port, 9)); 2862 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 2863 temp |= pll->config.hw_state.pll9; 2864 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 2865 2866 temp = I915_READ(BXT_PORT_PLL(port, 10)); 2867 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 2868 temp &= ~PORT_PLL_DCO_AMP_MASK; 2869 temp |= pll->config.hw_state.pll10; 2870 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 2871 2872 /* Recalibrate with new settings */ 2873 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2874 temp |= PORT_PLL_RECALIBRATE; 2875 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2876 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2877 temp |= pll->config.hw_state.ebb4; 2878 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2879 2880 /* Enable PLL */ 2881 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2882 temp |= PORT_PLL_ENABLE; 2883 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2884 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2885 2886 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & 2887 PORT_PLL_LOCK), 200)) 2888 DRM_ERROR("PLL %d not locked\n", port); 2889 2890 /* 2891 * While we write to the group register to program all lanes at once we 2892 * can read only lane registers and we pick lanes 0/1 for that. 2893 */ 2894 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2895 temp &= ~LANE_STAGGER_MASK; 2896 temp &= ~LANESTAGGER_STRAP_OVRD; 2897 temp |= pll->config.hw_state.pcsdw12; 2898 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 2899 } 2900 2901 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 2902 struct intel_shared_dpll *pll) 2903 { 2904 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2905 uint32_t temp; 2906 2907 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2908 temp &= ~PORT_PLL_ENABLE; 2909 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2910 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2911 } 2912 2913 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2914 struct intel_shared_dpll *pll, 2915 struct intel_dpll_hw_state *hw_state) 2916 { 2917 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2918 uint32_t val; 2919 2920 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2921 return false; 2922 2923 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2924 if (!(val & PORT_PLL_ENABLE)) 2925 return false; 2926 2927 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2928 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; 2929 2930 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2931 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; 2932 2933 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 2934 hw_state->pll0 &= PORT_PLL_M2_MASK; 2935 2936 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 2937 hw_state->pll1 &= PORT_PLL_N_MASK; 2938 2939 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 2940 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; 2941 2942 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 2943 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; 2944 2945 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 2946 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | 2947 PORT_PLL_INT_COEFF_MASK | 2948 PORT_PLL_GAIN_CTL_MASK; 2949 2950 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 2951 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; 2952 2953 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); 2954 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; 2955 2956 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 2957 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | 2958 PORT_PLL_DCO_AMP_MASK; 2959 2960 /* 2961 * While we write to the group register to program all lanes at once we 2962 * can read only lane registers. We configure all lanes the same way, so 2963 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 2964 */ 2965 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2966 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) 2967 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 2968 hw_state->pcsdw12, 2969 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 2970 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; 2971 2972 return true; 2973 } 2974 2975 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) 2976 { 2977 int i; 2978 2979 dev_priv->num_shared_dpll = 3; 2980 2981 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2982 dev_priv->shared_dplls[i].id = i; 2983 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; 2984 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; 2985 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; 2986 dev_priv->shared_dplls[i].get_hw_state = 2987 bxt_ddi_pll_get_hw_state; 2988 } 2989 } 2990 2991 void intel_ddi_pll_init(struct drm_device *dev) 2992 { 2993 struct drm_i915_private *dev_priv = dev->dev_private; 2994 uint32_t val = I915_READ(LCPLL_CTL); 2995 2996 if (IS_SKYLAKE(dev)) 2997 skl_shared_dplls_init(dev_priv); 2998 else if (IS_BROXTON(dev)) 2999 bxt_shared_dplls_init(dev_priv); 3000 else 3001 hsw_shared_dplls_init(dev_priv); 3002 3003 if (IS_SKYLAKE(dev)) { 3004 int cdclk_freq; 3005 3006 cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 3007 dev_priv->skl_boot_cdclk = cdclk_freq; 3008 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 3009 DRM_ERROR("LCPLL1 is disabled\n"); 3010 else 3011 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 3012 } else if (IS_BROXTON(dev)) { 3013 broxton_init_cdclk(dev); 3014 broxton_ddi_phy_init(dev); 3015 } else { 3016 /* 3017 * The LCPLL register should be turned on by the BIOS. For now 3018 * let's just check its state and print errors in case 3019 * something is wrong. Don't even try to turn it on. 3020 */ 3021 3022 if (val & LCPLL_CD_SOURCE_FCLK) 3023 DRM_ERROR("CDCLK source is not LCPLL\n"); 3024 3025 if (val & LCPLL_PLL_DISABLE) 3026 DRM_ERROR("LCPLL is disabled\n"); 3027 } 3028 } 3029 3030 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 3031 { 3032 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3033 struct intel_dp *intel_dp = &intel_dig_port->dp; 3034 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 3035 enum port port = intel_dig_port->port; 3036 uint32_t val; 3037 bool wait = false; 3038 3039 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 3040 val = I915_READ(DDI_BUF_CTL(port)); 3041 if (val & DDI_BUF_CTL_ENABLE) { 3042 val &= ~DDI_BUF_CTL_ENABLE; 3043 I915_WRITE(DDI_BUF_CTL(port), val); 3044 wait = true; 3045 } 3046 3047 val = I915_READ(DP_TP_CTL(port)); 3048 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3049 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3050 I915_WRITE(DP_TP_CTL(port), val); 3051 POSTING_READ(DP_TP_CTL(port)); 3052 3053 if (wait) 3054 intel_wait_ddi_buf_idle(dev_priv, port); 3055 } 3056 3057 val = DP_TP_CTL_ENABLE | 3058 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 3059 if (intel_dp->is_mst) 3060 val |= DP_TP_CTL_MODE_MST; 3061 else { 3062 val |= DP_TP_CTL_MODE_SST; 3063 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3064 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3065 } 3066 I915_WRITE(DP_TP_CTL(port), val); 3067 POSTING_READ(DP_TP_CTL(port)); 3068 3069 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3070 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 3071 POSTING_READ(DDI_BUF_CTL(port)); 3072 3073 udelay(600); 3074 } 3075 3076 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 3077 { 3078 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 3079 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 3080 uint32_t val; 3081 3082 intel_ddi_post_disable(intel_encoder); 3083 3084 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3085 val &= ~FDI_RX_ENABLE; 3086 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3087 3088 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3089 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3090 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3091 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3092 3093 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3094 val &= ~FDI_PCDCLK; 3095 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3096 3097 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3098 val &= ~FDI_RX_PLL_ENABLE; 3099 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3100 } 3101 3102 void intel_ddi_get_config(struct intel_encoder *encoder, 3103 struct intel_crtc_state *pipe_config) 3104 { 3105 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 3106 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 3107 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3108 struct intel_hdmi *intel_hdmi; 3109 u32 temp, flags = 0; 3110 3111 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3112 if (temp & TRANS_DDI_PHSYNC) 3113 flags |= DRM_MODE_FLAG_PHSYNC; 3114 else 3115 flags |= DRM_MODE_FLAG_NHSYNC; 3116 if (temp & TRANS_DDI_PVSYNC) 3117 flags |= DRM_MODE_FLAG_PVSYNC; 3118 else 3119 flags |= DRM_MODE_FLAG_NVSYNC; 3120 3121 pipe_config->base.adjusted_mode.flags |= flags; 3122 3123 switch (temp & TRANS_DDI_BPC_MASK) { 3124 case TRANS_DDI_BPC_6: 3125 pipe_config->pipe_bpp = 18; 3126 break; 3127 case TRANS_DDI_BPC_8: 3128 pipe_config->pipe_bpp = 24; 3129 break; 3130 case TRANS_DDI_BPC_10: 3131 pipe_config->pipe_bpp = 30; 3132 break; 3133 case TRANS_DDI_BPC_12: 3134 pipe_config->pipe_bpp = 36; 3135 break; 3136 default: 3137 break; 3138 } 3139 3140 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3141 case TRANS_DDI_MODE_SELECT_HDMI: 3142 pipe_config->has_hdmi_sink = true; 3143 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 3144 3145 if (intel_hdmi->infoframe_enabled(&encoder->base)) 3146 pipe_config->has_infoframe = true; 3147 break; 3148 case TRANS_DDI_MODE_SELECT_DVI: 3149 case TRANS_DDI_MODE_SELECT_FDI: 3150 break; 3151 case TRANS_DDI_MODE_SELECT_DP_SST: 3152 case TRANS_DDI_MODE_SELECT_DP_MST: 3153 pipe_config->has_dp_encoder = true; 3154 pipe_config->lane_count = 3155 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3156 intel_dp_get_m_n(intel_crtc, pipe_config); 3157 break; 3158 default: 3159 break; 3160 } 3161 3162 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 3163 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 3164 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 3165 pipe_config->has_audio = true; 3166 } 3167 3168 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 3169 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 3170 /* 3171 * This is a big fat ugly hack. 3172 * 3173 * Some machines in UEFI boot mode provide us a VBT that has 18 3174 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3175 * unknown we fail to light up. Yet the same BIOS boots up with 3176 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3177 * max, not what it tells us to use. 3178 * 3179 * Note: This will still be broken if the eDP panel is not lit 3180 * up by the BIOS, and thus we can't get the mode at module 3181 * load. 3182 */ 3183 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3184 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 3185 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 3186 } 3187 3188 intel_ddi_clock_get(encoder, pipe_config); 3189 } 3190 3191 static void intel_ddi_destroy(struct drm_encoder *encoder) 3192 { 3193 /* HDMI has nothing special to destroy, so we can go with this. */ 3194 intel_dp_encoder_destroy(encoder); 3195 } 3196 3197 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 3198 struct intel_crtc_state *pipe_config) 3199 { 3200 int type = encoder->type; 3201 int port = intel_ddi_get_encoder_port(encoder); 3202 3203 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 3204 3205 if (port == PORT_A) 3206 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3207 3208 if (type == INTEL_OUTPUT_HDMI) 3209 return intel_hdmi_compute_config(encoder, pipe_config); 3210 else 3211 return intel_dp_compute_config(encoder, pipe_config); 3212 } 3213 3214 static const struct drm_encoder_funcs intel_ddi_funcs = { 3215 .destroy = intel_ddi_destroy, 3216 }; 3217 3218 static struct intel_connector * 3219 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 3220 { 3221 struct intel_connector *connector; 3222 enum port port = intel_dig_port->port; 3223 3224 connector = intel_connector_alloc(); 3225 if (!connector) 3226 return NULL; 3227 3228 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 3229 if (!intel_dp_init_connector(intel_dig_port, connector)) { 3230 kfree(connector); 3231 return NULL; 3232 } 3233 3234 return connector; 3235 } 3236 3237 static struct intel_connector * 3238 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 3239 { 3240 struct intel_connector *connector; 3241 enum port port = intel_dig_port->port; 3242 3243 connector = intel_connector_alloc(); 3244 if (!connector) 3245 return NULL; 3246 3247 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 3248 intel_hdmi_init_connector(intel_dig_port, connector); 3249 3250 return connector; 3251 } 3252 3253 void intel_ddi_init(struct drm_device *dev, enum port port) 3254 { 3255 struct drm_i915_private *dev_priv = dev->dev_private; 3256 struct intel_digital_port *intel_dig_port; 3257 struct intel_encoder *intel_encoder; 3258 struct drm_encoder *encoder; 3259 bool init_hdmi, init_dp; 3260 3261 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 3262 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 3263 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 3264 if (!init_dp && !init_hdmi) { 3265 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 3266 port_name(port)); 3267 return; 3268 } 3269 3270 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3271 if (!intel_dig_port) 3272 return; 3273 3274 intel_encoder = &intel_dig_port->base; 3275 encoder = &intel_encoder->base; 3276 3277 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 3278 DRM_MODE_ENCODER_TMDS); 3279 3280 intel_encoder->compute_config = intel_ddi_compute_config; 3281 intel_encoder->enable = intel_enable_ddi; 3282 intel_encoder->pre_enable = intel_ddi_pre_enable; 3283 intel_encoder->disable = intel_disable_ddi; 3284 intel_encoder->post_disable = intel_ddi_post_disable; 3285 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 3286 intel_encoder->get_config = intel_ddi_get_config; 3287 3288 intel_dig_port->port = port; 3289 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 3290 (DDI_BUF_PORT_REVERSAL | 3291 DDI_A_4_LANES); 3292 3293 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 3294 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3295 intel_encoder->cloneable = 0; 3296 3297 if (init_dp) { 3298 if (!intel_ddi_init_dp_connector(intel_dig_port)) 3299 goto err; 3300 3301 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 3302 /* 3303 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 3304 * interrupts to check the external panel connection. 3305 */ 3306 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) 3307 && port == PORT_B) 3308 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; 3309 else 3310 dev_priv->hotplug.irq_port[port] = intel_dig_port; 3311 } 3312 3313 /* In theory we don't need the encoder->type check, but leave it just in 3314 * case we have some really bad VBTs... */ 3315 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 3316 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 3317 goto err; 3318 } 3319 3320 return; 3321 3322 err: 3323 drm_encoder_cleanup(encoder); 3324 kfree(intel_dig_port); 3325 } 3326