1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 32 * them for both DP and FDI transports, allowing those ports to 33 * automatically adapt to HDMI connections as well 34 */ 35 static const u32 hsw_ddi_translations_dp[] = { 36 0x00FFFFFF, 0x0006000E, /* DP parameters */ 37 0x00D75FFF, 0x0005000A, 38 0x00C30FFF, 0x00040006, 39 0x80AAAFFF, 0x000B0000, 40 0x00FFFFFF, 0x0005000A, 41 0x00D75FFF, 0x000C0004, 42 0x80C30FFF, 0x000B0000, 43 0x00FFFFFF, 0x00040006, 44 0x80D75FFF, 0x000B0000, 45 }; 46 47 static const u32 hsw_ddi_translations_fdi[] = { 48 0x00FFFFFF, 0x0007000E, /* FDI parameters */ 49 0x00D75FFF, 0x000F000A, 50 0x00C30FFF, 0x00060006, 51 0x00AAAFFF, 0x001E0000, 52 0x00FFFFFF, 0x000F000A, 53 0x00D75FFF, 0x00160004, 54 0x00C30FFF, 0x001E0000, 55 0x00FFFFFF, 0x00060006, 56 0x00D75FFF, 0x001E0000, 57 }; 58 59 static const u32 hsw_ddi_translations_hdmi[] = { 60 /* Idx NT mV diff T mV diff db */ 61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ 62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ 63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ 64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ 65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ 66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ 67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ 68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ 69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ 70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ 71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ 72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ 73 }; 74 75 static const u32 bdw_ddi_translations_edp[] = { 76 0x00FFFFFF, 0x00000012, /* eDP parameters */ 77 0x00EBAFFF, 0x00020011, 78 0x00C71FFF, 0x0006000F, 79 0x00AAAFFF, 0x000E000A, 80 0x00FFFFFF, 0x00020011, 81 0x00DB6FFF, 0x0005000F, 82 0x00BEEFFF, 0x000A000C, 83 0x00FFFFFF, 0x0005000F, 84 0x00DB6FFF, 0x000A000C, 85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ 86 }; 87 88 static const u32 bdw_ddi_translations_dp[] = { 89 0x00FFFFFF, 0x0007000E, /* DP parameters */ 90 0x00D75FFF, 0x000E000A, 91 0x00BEFFFF, 0x00140006, 92 0x80B2CFFF, 0x001B0002, 93 0x00FFFFFF, 0x000E000A, 94 0x00D75FFF, 0x00180004, 95 0x80CB2FFF, 0x001B0002, 96 0x00F7DFFF, 0x00180004, 97 0x80D75FFF, 0x001B0002, 98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ 99 }; 100 101 static const u32 bdw_ddi_translations_fdi[] = { 102 0x00FFFFFF, 0x0001000E, /* FDI parameters */ 103 0x00D75FFF, 0x0004000A, 104 0x00C30FFF, 0x00070006, 105 0x00AAAFFF, 0x000C0000, 106 0x00FFFFFF, 0x0004000A, 107 0x00D75FFF, 0x00090004, 108 0x00C30FFF, 0x000C0000, 109 0x00FFFFFF, 0x00070006, 110 0x00D75FFF, 0x000C0000, 111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ 112 }; 113 114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 115 { 116 struct drm_encoder *encoder = &intel_encoder->base; 117 int type = intel_encoder->type; 118 119 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || 120 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { 121 struct intel_digital_port *intel_dig_port = 122 enc_to_dig_port(encoder); 123 return intel_dig_port->port; 124 125 } else if (type == INTEL_OUTPUT_ANALOG) { 126 return PORT_E; 127 128 } else { 129 DRM_ERROR("Invalid DDI encoder type %d\n", type); 130 BUG(); 131 } 132 } 133 134 /* 135 * Starting with Haswell, DDI port buffers must be programmed with correct 136 * values in advance. The buffer values are different for FDI and DP modes, 137 * but the HDMI/DVI fields are shared among those. So we program the DDI 138 * in either FDI or DP modes only, as HDMI connections will work with both 139 * of those 140 */ 141 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) 142 { 143 struct drm_i915_private *dev_priv = dev->dev_private; 144 u32 reg; 145 int i; 146 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 147 const u32 *ddi_translations_fdi; 148 const u32 *ddi_translations_dp; 149 const u32 *ddi_translations_edp; 150 const u32 *ddi_translations; 151 152 if (IS_BROADWELL(dev)) { 153 ddi_translations_fdi = bdw_ddi_translations_fdi; 154 ddi_translations_dp = bdw_ddi_translations_dp; 155 ddi_translations_edp = bdw_ddi_translations_edp; 156 } else if (IS_HASWELL(dev)) { 157 ddi_translations_fdi = hsw_ddi_translations_fdi; 158 ddi_translations_dp = hsw_ddi_translations_dp; 159 ddi_translations_edp = hsw_ddi_translations_dp; 160 } else { 161 WARN(1, "ddi translation table missing\n"); 162 ddi_translations_edp = bdw_ddi_translations_dp; 163 ddi_translations_fdi = bdw_ddi_translations_fdi; 164 ddi_translations_dp = bdw_ddi_translations_dp; 165 } 166 167 switch (port) { 168 case PORT_A: 169 ddi_translations = ddi_translations_edp; 170 break; 171 case PORT_B: 172 case PORT_C: 173 ddi_translations = ddi_translations_dp; 174 break; 175 case PORT_D: 176 if (intel_dp_is_edp(dev, PORT_D)) 177 ddi_translations = ddi_translations_edp; 178 else 179 ddi_translations = ddi_translations_dp; 180 break; 181 case PORT_E: 182 ddi_translations = ddi_translations_fdi; 183 break; 184 default: 185 BUG(); 186 } 187 188 for (i = 0, reg = DDI_BUF_TRANS(port); 189 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { 190 I915_WRITE(reg, ddi_translations[i]); 191 reg += 4; 192 } 193 /* Entry 9 is for HDMI: */ 194 for (i = 0; i < 2; i++) { 195 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); 196 reg += 4; 197 } 198 } 199 200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 201 * mode and port E for FDI. 202 */ 203 void intel_prepare_ddi(struct drm_device *dev) 204 { 205 int port; 206 207 if (!HAS_DDI(dev)) 208 return; 209 210 for (port = PORT_A; port <= PORT_E; port++) 211 intel_prepare_ddi_buffers(dev, port); 212 } 213 214 static const long hsw_ddi_buf_ctl_values[] = { 215 DDI_BUF_EMP_400MV_0DB_HSW, 216 DDI_BUF_EMP_400MV_3_5DB_HSW, 217 DDI_BUF_EMP_400MV_6DB_HSW, 218 DDI_BUF_EMP_400MV_9_5DB_HSW, 219 DDI_BUF_EMP_600MV_0DB_HSW, 220 DDI_BUF_EMP_600MV_3_5DB_HSW, 221 DDI_BUF_EMP_600MV_6DB_HSW, 222 DDI_BUF_EMP_800MV_0DB_HSW, 223 DDI_BUF_EMP_800MV_3_5DB_HSW 224 }; 225 226 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 227 enum port port) 228 { 229 uint32_t reg = DDI_BUF_CTL(port); 230 int i; 231 232 for (i = 0; i < 8; i++) { 233 udelay(1); 234 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 235 return; 236 } 237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 238 } 239 240 /* Starting with Haswell, different DDI ports can work in FDI mode for 241 * connection to the PCH-located connectors. For this, it is necessary to train 242 * both the DDI port and PCH receiver for the desired DDI buffer settings. 243 * 244 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 245 * please note that when FDI mode is active on DDI E, it shares 2 lines with 246 * DDI A (which is used for eDP) 247 */ 248 249 void hsw_fdi_link_train(struct drm_crtc *crtc) 250 { 251 struct drm_device *dev = crtc->dev; 252 struct drm_i915_private *dev_priv = dev->dev_private; 253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 254 u32 temp, i, rx_ctl_val; 255 256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 257 * mode set "sequence for CRT port" document: 258 * - TP1 to TP2 time with the default value 259 * - FDI delay to 90h 260 * 261 * WaFDIAutoLinkSetTimingOverrride:hsw 262 */ 263 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | 264 FDI_RX_PWRDN_LANE0_VAL(2) | 265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 266 267 /* Enable the PCH Receiver FDI PLL */ 268 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 269 FDI_RX_PLL_ENABLE | 270 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); 271 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 272 POSTING_READ(_FDI_RXA_CTL); 273 udelay(220); 274 275 /* Switch from Rawclk to PCDclk */ 276 rx_ctl_val |= FDI_PCDCLK; 277 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 278 279 /* Configure Port Clock Select */ 280 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); 281 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); 282 283 /* Start the training iterating through available voltages and emphasis, 284 * testing each value twice. */ 285 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { 286 /* Configure DP_TP_CTL with auto-training */ 287 I915_WRITE(DP_TP_CTL(PORT_E), 288 DP_TP_CTL_FDI_AUTOTRAIN | 289 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 290 DP_TP_CTL_LINK_TRAIN_PAT1 | 291 DP_TP_CTL_ENABLE); 292 293 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 294 * DDI E does not support port reversal, the functionality is 295 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 296 * port reversal bit */ 297 I915_WRITE(DDI_BUF_CTL(PORT_E), 298 DDI_BUF_CTL_ENABLE | 299 ((intel_crtc->config.fdi_lanes - 1) << 1) | 300 hsw_ddi_buf_ctl_values[i / 2]); 301 POSTING_READ(DDI_BUF_CTL(PORT_E)); 302 303 udelay(600); 304 305 /* Program PCH FDI Receiver TU */ 306 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); 307 308 /* Enable PCH FDI Receiver with auto-training */ 309 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 310 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 311 POSTING_READ(_FDI_RXA_CTL); 312 313 /* Wait for FDI receiver lane calibration */ 314 udelay(30); 315 316 /* Unset FDI_RX_MISC pwrdn lanes */ 317 temp = I915_READ(_FDI_RXA_MISC); 318 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 319 I915_WRITE(_FDI_RXA_MISC, temp); 320 POSTING_READ(_FDI_RXA_MISC); 321 322 /* Wait for FDI auto training time */ 323 udelay(5); 324 325 temp = I915_READ(DP_TP_STATUS(PORT_E)); 326 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 327 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 328 329 /* Enable normal pixel sending for FDI */ 330 I915_WRITE(DP_TP_CTL(PORT_E), 331 DP_TP_CTL_FDI_AUTOTRAIN | 332 DP_TP_CTL_LINK_TRAIN_NORMAL | 333 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 334 DP_TP_CTL_ENABLE); 335 336 return; 337 } 338 339 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 340 temp &= ~DDI_BUF_CTL_ENABLE; 341 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 342 POSTING_READ(DDI_BUF_CTL(PORT_E)); 343 344 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 345 temp = I915_READ(DP_TP_CTL(PORT_E)); 346 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 347 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 348 I915_WRITE(DP_TP_CTL(PORT_E), temp); 349 POSTING_READ(DP_TP_CTL(PORT_E)); 350 351 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 352 353 rx_ctl_val &= ~FDI_RX_ENABLE; 354 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 355 POSTING_READ(_FDI_RXA_CTL); 356 357 /* Reset FDI_RX_MISC pwrdn lanes */ 358 temp = I915_READ(_FDI_RXA_MISC); 359 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 360 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 361 I915_WRITE(_FDI_RXA_MISC, temp); 362 POSTING_READ(_FDI_RXA_MISC); 363 } 364 365 DRM_ERROR("FDI link training failed!\n"); 366 } 367 368 static struct intel_encoder * 369 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 370 { 371 struct drm_device *dev = crtc->dev; 372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 373 struct intel_encoder *intel_encoder, *ret = NULL; 374 int num_encoders = 0; 375 376 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 377 ret = intel_encoder; 378 num_encoders++; 379 } 380 381 if (num_encoders != 1) 382 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 383 pipe_name(intel_crtc->pipe)); 384 385 BUG_ON(ret == NULL); 386 return ret; 387 } 388 389 #define LC_FREQ 2700 390 #define LC_FREQ_2K (LC_FREQ * 2000) 391 392 #define P_MIN 2 393 #define P_MAX 64 394 #define P_INC 2 395 396 /* Constraints for PLL good behavior */ 397 #define REF_MIN 48 398 #define REF_MAX 400 399 #define VCO_MIN 2400 400 #define VCO_MAX 4800 401 402 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) 403 404 struct wrpll_rnp { 405 unsigned p, n2, r2; 406 }; 407 408 static unsigned wrpll_get_budget_for_freq(int clock) 409 { 410 unsigned budget; 411 412 switch (clock) { 413 case 25175000: 414 case 25200000: 415 case 27000000: 416 case 27027000: 417 case 37762500: 418 case 37800000: 419 case 40500000: 420 case 40541000: 421 case 54000000: 422 case 54054000: 423 case 59341000: 424 case 59400000: 425 case 72000000: 426 case 74176000: 427 case 74250000: 428 case 81000000: 429 case 81081000: 430 case 89012000: 431 case 89100000: 432 case 108000000: 433 case 108108000: 434 case 111264000: 435 case 111375000: 436 case 148352000: 437 case 148500000: 438 case 162000000: 439 case 162162000: 440 case 222525000: 441 case 222750000: 442 case 296703000: 443 case 297000000: 444 budget = 0; 445 break; 446 case 233500000: 447 case 245250000: 448 case 247750000: 449 case 253250000: 450 case 298000000: 451 budget = 1500; 452 break; 453 case 169128000: 454 case 169500000: 455 case 179500000: 456 case 202000000: 457 budget = 2000; 458 break; 459 case 256250000: 460 case 262500000: 461 case 270000000: 462 case 272500000: 463 case 273750000: 464 case 280750000: 465 case 281250000: 466 case 286000000: 467 case 291750000: 468 budget = 4000; 469 break; 470 case 267250000: 471 case 268500000: 472 budget = 5000; 473 break; 474 default: 475 budget = 1000; 476 break; 477 } 478 479 return budget; 480 } 481 482 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, 483 unsigned r2, unsigned n2, unsigned p, 484 struct wrpll_rnp *best) 485 { 486 uint64_t a, b, c, d, diff, diff_best; 487 488 /* No best (r,n,p) yet */ 489 if (best->p == 0) { 490 best->p = p; 491 best->n2 = n2; 492 best->r2 = r2; 493 return; 494 } 495 496 /* 497 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 498 * freq2k. 499 * 500 * delta = 1e6 * 501 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 502 * freq2k; 503 * 504 * and we would like delta <= budget. 505 * 506 * If the discrepancy is above the PPM-based budget, always prefer to 507 * improve upon the previous solution. However, if you're within the 508 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 509 */ 510 a = freq2k * budget * p * r2; 511 b = freq2k * budget * best->p * best->r2; 512 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); 513 diff_best = ABS_DIFF((freq2k * best->p * best->r2), 514 (LC_FREQ_2K * best->n2)); 515 c = 1000000 * diff; 516 d = 1000000 * diff_best; 517 518 if (a < c && b < d) { 519 /* If both are above the budget, pick the closer */ 520 if (best->p * best->r2 * diff < p * r2 * diff_best) { 521 best->p = p; 522 best->n2 = n2; 523 best->r2 = r2; 524 } 525 } else if (a >= c && b < d) { 526 /* If A is below the threshold but B is above it? Update. */ 527 best->p = p; 528 best->n2 = n2; 529 best->r2 = r2; 530 } else if (a >= c && b >= d) { 531 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 532 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 533 best->p = p; 534 best->n2 = n2; 535 best->r2 = r2; 536 } 537 } 538 /* Otherwise a < c && b >= d, do nothing */ 539 } 540 541 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 542 int reg) 543 { 544 int refclk = LC_FREQ; 545 int n, p, r; 546 u32 wrpll; 547 548 wrpll = I915_READ(reg); 549 switch (wrpll & WRPLL_PLL_REF_MASK) { 550 case WRPLL_PLL_SSC: 551 case WRPLL_PLL_NON_SSC: 552 /* 553 * We could calculate spread here, but our checking 554 * code only cares about 5% accuracy, and spread is a max of 555 * 0.5% downspread. 556 */ 557 refclk = 135; 558 break; 559 case WRPLL_PLL_LCPLL: 560 refclk = LC_FREQ; 561 break; 562 default: 563 WARN(1, "bad wrpll refclk\n"); 564 return 0; 565 } 566 567 r = wrpll & WRPLL_DIVIDER_REF_MASK; 568 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 569 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 570 571 /* Convert to KHz, p & r have a fixed point portion */ 572 return (refclk * n * 100) / (p * r); 573 } 574 575 void intel_ddi_clock_get(struct intel_encoder *encoder, 576 struct intel_crtc_config *pipe_config) 577 { 578 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 579 int link_clock = 0; 580 u32 val, pll; 581 582 val = pipe_config->ddi_pll_sel; 583 switch (val & PORT_CLK_SEL_MASK) { 584 case PORT_CLK_SEL_LCPLL_810: 585 link_clock = 81000; 586 break; 587 case PORT_CLK_SEL_LCPLL_1350: 588 link_clock = 135000; 589 break; 590 case PORT_CLK_SEL_LCPLL_2700: 591 link_clock = 270000; 592 break; 593 case PORT_CLK_SEL_WRPLL1: 594 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); 595 break; 596 case PORT_CLK_SEL_WRPLL2: 597 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); 598 break; 599 case PORT_CLK_SEL_SPLL: 600 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 601 if (pll == SPLL_PLL_FREQ_810MHz) 602 link_clock = 81000; 603 else if (pll == SPLL_PLL_FREQ_1350MHz) 604 link_clock = 135000; 605 else if (pll == SPLL_PLL_FREQ_2700MHz) 606 link_clock = 270000; 607 else { 608 WARN(1, "bad spll freq\n"); 609 return; 610 } 611 break; 612 default: 613 WARN(1, "bad port clock sel\n"); 614 return; 615 } 616 617 pipe_config->port_clock = link_clock * 2; 618 619 if (pipe_config->has_pch_encoder) 620 pipe_config->adjusted_mode.crtc_clock = 621 intel_dotclock_calculate(pipe_config->port_clock, 622 &pipe_config->fdi_m_n); 623 else if (pipe_config->has_dp_encoder) 624 pipe_config->adjusted_mode.crtc_clock = 625 intel_dotclock_calculate(pipe_config->port_clock, 626 &pipe_config->dp_m_n); 627 else 628 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; 629 } 630 631 static void 632 intel_ddi_calculate_wrpll(int clock /* in Hz */, 633 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 634 { 635 uint64_t freq2k; 636 unsigned p, n2, r2; 637 struct wrpll_rnp best = { 0, 0, 0 }; 638 unsigned budget; 639 640 freq2k = clock / 100; 641 642 budget = wrpll_get_budget_for_freq(clock); 643 644 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 645 * and directly pass the LC PLL to it. */ 646 if (freq2k == 5400000) { 647 *n2_out = 2; 648 *p_out = 1; 649 *r2_out = 2; 650 return; 651 } 652 653 /* 654 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 655 * the WR PLL. 656 * 657 * We want R so that REF_MIN <= Ref <= REF_MAX. 658 * Injecting R2 = 2 * R gives: 659 * REF_MAX * r2 > LC_FREQ * 2 and 660 * REF_MIN * r2 < LC_FREQ * 2 661 * 662 * Which means the desired boundaries for r2 are: 663 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 664 * 665 */ 666 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 667 r2 <= LC_FREQ * 2 / REF_MIN; 668 r2++) { 669 670 /* 671 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 672 * 673 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 674 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 675 * VCO_MAX * r2 > n2 * LC_FREQ and 676 * VCO_MIN * r2 < n2 * LC_FREQ) 677 * 678 * Which means the desired boundaries for n2 are: 679 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 680 */ 681 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 682 n2 <= VCO_MAX * r2 / LC_FREQ; 683 n2++) { 684 685 for (p = P_MIN; p <= P_MAX; p += P_INC) 686 wrpll_update_rnp(freq2k, budget, 687 r2, n2, p, &best); 688 } 689 } 690 691 *n2_out = best.n2; 692 *p_out = best.p; 693 *r2_out = best.r2; 694 } 695 696 /* 697 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and 698 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to 699 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually 700 * enable the PLL. 701 */ 702 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) 703 { 704 struct drm_crtc *crtc = &intel_crtc->base; 705 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 706 int type = intel_encoder->type; 707 int clock = intel_crtc->config.port_clock; 708 709 intel_put_shared_dpll(intel_crtc); 710 711 if (type == INTEL_OUTPUT_HDMI) { 712 struct intel_shared_dpll *pll; 713 uint32_t val; 714 unsigned p, n2, r2; 715 716 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 717 718 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 719 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 720 WRPLL_DIVIDER_POST(p); 721 722 intel_crtc->config.dpll_hw_state.wrpll = val; 723 724 pll = intel_get_shared_dpll(intel_crtc); 725 if (pll == NULL) { 726 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 727 pipe_name(intel_crtc->pipe)); 728 return false; 729 } 730 731 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 732 } 733 734 return true; 735 } 736 737 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 738 { 739 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 741 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 742 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 743 int type = intel_encoder->type; 744 uint32_t temp; 745 746 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 747 748 temp = TRANS_MSA_SYNC_CLK; 749 switch (intel_crtc->config.pipe_bpp) { 750 case 18: 751 temp |= TRANS_MSA_6_BPC; 752 break; 753 case 24: 754 temp |= TRANS_MSA_8_BPC; 755 break; 756 case 30: 757 temp |= TRANS_MSA_10_BPC; 758 break; 759 case 36: 760 temp |= TRANS_MSA_12_BPC; 761 break; 762 default: 763 BUG(); 764 } 765 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 766 } 767 } 768 769 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 770 { 771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 772 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 773 struct drm_encoder *encoder = &intel_encoder->base; 774 struct drm_device *dev = crtc->dev; 775 struct drm_i915_private *dev_priv = dev->dev_private; 776 enum i915_pipe pipe = intel_crtc->pipe; 777 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 778 enum port port = intel_ddi_get_encoder_port(intel_encoder); 779 int type = intel_encoder->type; 780 uint32_t temp; 781 782 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 783 temp = TRANS_DDI_FUNC_ENABLE; 784 temp |= TRANS_DDI_SELECT_PORT(port); 785 786 switch (intel_crtc->config.pipe_bpp) { 787 case 18: 788 temp |= TRANS_DDI_BPC_6; 789 break; 790 case 24: 791 temp |= TRANS_DDI_BPC_8; 792 break; 793 case 30: 794 temp |= TRANS_DDI_BPC_10; 795 break; 796 case 36: 797 temp |= TRANS_DDI_BPC_12; 798 break; 799 default: 800 BUG(); 801 } 802 803 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 804 temp |= TRANS_DDI_PVSYNC; 805 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 806 temp |= TRANS_DDI_PHSYNC; 807 808 if (cpu_transcoder == TRANSCODER_EDP) { 809 switch (pipe) { 810 case PIPE_A: 811 /* On Haswell, can only use the always-on power well for 812 * eDP when not using the panel fitter, and when not 813 * using motion blur mitigation (which we don't 814 * support). */ 815 if (IS_HASWELL(dev) && 816 (intel_crtc->config.pch_pfit.enabled || 817 intel_crtc->config.pch_pfit.force_thru)) 818 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 819 else 820 temp |= TRANS_DDI_EDP_INPUT_A_ON; 821 break; 822 case PIPE_B: 823 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 824 break; 825 case PIPE_C: 826 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 827 break; 828 default: 829 BUG(); 830 break; 831 } 832 } 833 834 if (type == INTEL_OUTPUT_HDMI) { 835 if (intel_crtc->config.has_hdmi_sink) 836 temp |= TRANS_DDI_MODE_SELECT_HDMI; 837 else 838 temp |= TRANS_DDI_MODE_SELECT_DVI; 839 840 } else if (type == INTEL_OUTPUT_ANALOG) { 841 temp |= TRANS_DDI_MODE_SELECT_FDI; 842 temp |= (intel_crtc->config.fdi_lanes - 1) << 1; 843 844 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 845 type == INTEL_OUTPUT_EDP) { 846 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 847 848 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 849 850 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 851 } else { 852 WARN(1, "Invalid encoder type %d for pipe %c\n", 853 intel_encoder->type, pipe_name(pipe)); 854 } 855 856 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 857 } 858 859 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 860 enum transcoder cpu_transcoder) 861 { 862 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 863 uint32_t val = I915_READ(reg); 864 865 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); 866 val |= TRANS_DDI_PORT_NONE; 867 I915_WRITE(reg, val); 868 } 869 870 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 871 { 872 struct drm_device *dev = intel_connector->base.dev; 873 struct drm_i915_private *dev_priv = dev->dev_private; 874 struct intel_encoder *intel_encoder = intel_connector->encoder; 875 int type = intel_connector->base.connector_type; 876 enum port port = intel_ddi_get_encoder_port(intel_encoder); 877 enum i915_pipe pipe = 0; 878 enum transcoder cpu_transcoder; 879 enum intel_display_power_domain power_domain; 880 uint32_t tmp; 881 882 power_domain = intel_display_port_power_domain(intel_encoder); 883 if (!intel_display_power_enabled(dev_priv, power_domain)) 884 return false; 885 886 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 887 return false; 888 889 if (port == PORT_A) 890 cpu_transcoder = TRANSCODER_EDP; 891 else 892 cpu_transcoder = (enum transcoder) pipe; 893 894 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 895 896 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 897 case TRANS_DDI_MODE_SELECT_HDMI: 898 case TRANS_DDI_MODE_SELECT_DVI: 899 return (type == DRM_MODE_CONNECTOR_HDMIA); 900 901 case TRANS_DDI_MODE_SELECT_DP_SST: 902 if (type == DRM_MODE_CONNECTOR_eDP) 903 return true; 904 case TRANS_DDI_MODE_SELECT_DP_MST: 905 return (type == DRM_MODE_CONNECTOR_DisplayPort); 906 907 case TRANS_DDI_MODE_SELECT_FDI: 908 return (type == DRM_MODE_CONNECTOR_VGA); 909 910 default: 911 return false; 912 } 913 } 914 915 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 916 enum i915_pipe *pipe) 917 { 918 struct drm_device *dev = encoder->base.dev; 919 struct drm_i915_private *dev_priv = dev->dev_private; 920 enum port port = intel_ddi_get_encoder_port(encoder); 921 enum intel_display_power_domain power_domain; 922 u32 tmp; 923 int i; 924 925 power_domain = intel_display_port_power_domain(encoder); 926 if (!intel_display_power_enabled(dev_priv, power_domain)) 927 return false; 928 929 tmp = I915_READ(DDI_BUF_CTL(port)); 930 931 if (!(tmp & DDI_BUF_CTL_ENABLE)) 932 return false; 933 934 if (port == PORT_A) { 935 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 936 937 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 938 case TRANS_DDI_EDP_INPUT_A_ON: 939 case TRANS_DDI_EDP_INPUT_A_ONOFF: 940 *pipe = PIPE_A; 941 break; 942 case TRANS_DDI_EDP_INPUT_B_ONOFF: 943 *pipe = PIPE_B; 944 break; 945 case TRANS_DDI_EDP_INPUT_C_ONOFF: 946 *pipe = PIPE_C; 947 break; 948 } 949 950 return true; 951 } else { 952 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 953 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 954 955 if ((tmp & TRANS_DDI_PORT_MASK) 956 == TRANS_DDI_SELECT_PORT(port)) { 957 *pipe = i; 958 return true; 959 } 960 } 961 } 962 963 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 964 965 return false; 966 } 967 968 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 969 { 970 struct drm_crtc *crtc = &intel_crtc->base; 971 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 972 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 973 enum port port = intel_ddi_get_encoder_port(intel_encoder); 974 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 975 976 if (cpu_transcoder != TRANSCODER_EDP) 977 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 978 TRANS_CLK_SEL_PORT(port)); 979 } 980 981 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 982 { 983 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 984 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 985 986 if (cpu_transcoder != TRANSCODER_EDP) 987 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 988 TRANS_CLK_SEL_DISABLED); 989 } 990 991 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 992 { 993 struct drm_encoder *encoder = &intel_encoder->base; 994 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 995 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 996 enum port port = intel_ddi_get_encoder_port(intel_encoder); 997 int type = intel_encoder->type; 998 999 if (crtc->config.has_audio) { 1000 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n", 1001 pipe_name(crtc->pipe)); 1002 1003 /* write eld */ 1004 DRM_DEBUG_DRIVER("DDI audio: write eld information\n"); 1005 intel_write_eld(encoder, &crtc->config.adjusted_mode); 1006 } 1007 1008 if (type == INTEL_OUTPUT_EDP) { 1009 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1010 intel_edp_panel_on(intel_dp); 1011 } 1012 1013 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); 1014 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); 1015 1016 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1017 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1018 struct intel_digital_port *intel_dig_port = 1019 enc_to_dig_port(encoder); 1020 1021 intel_dp->DP = intel_dig_port->saved_port_bits | 1022 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; 1023 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1024 1025 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1026 intel_dp_start_link_train(intel_dp); 1027 intel_dp_complete_link_train(intel_dp); 1028 if (port != PORT_A) 1029 intel_dp_stop_link_train(intel_dp); 1030 } else if (type == INTEL_OUTPUT_HDMI) { 1031 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1032 1033 intel_hdmi->set_infoframes(encoder, 1034 crtc->config.has_hdmi_sink, 1035 &crtc->config.adjusted_mode); 1036 } 1037 } 1038 1039 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 1040 { 1041 struct drm_encoder *encoder = &intel_encoder->base; 1042 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1043 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1044 int type = intel_encoder->type; 1045 uint32_t val; 1046 bool wait = false; 1047 1048 val = I915_READ(DDI_BUF_CTL(port)); 1049 if (val & DDI_BUF_CTL_ENABLE) { 1050 val &= ~DDI_BUF_CTL_ENABLE; 1051 I915_WRITE(DDI_BUF_CTL(port), val); 1052 wait = true; 1053 } 1054 1055 val = I915_READ(DP_TP_CTL(port)); 1056 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1057 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1058 I915_WRITE(DP_TP_CTL(port), val); 1059 1060 if (wait) 1061 intel_wait_ddi_buf_idle(dev_priv, port); 1062 1063 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1064 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1065 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1066 intel_edp_panel_vdd_on(intel_dp); 1067 intel_edp_panel_off(intel_dp); 1068 } 1069 1070 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1071 } 1072 1073 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 1074 { 1075 struct drm_encoder *encoder = &intel_encoder->base; 1076 struct drm_crtc *crtc = encoder->crtc; 1077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1078 int pipe = intel_crtc->pipe; 1079 struct drm_device *dev = encoder->dev; 1080 struct drm_i915_private *dev_priv = dev->dev_private; 1081 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1082 int type = intel_encoder->type; 1083 uint32_t tmp; 1084 1085 if (type == INTEL_OUTPUT_HDMI) { 1086 struct intel_digital_port *intel_dig_port = 1087 enc_to_dig_port(encoder); 1088 1089 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1090 * are ignored so nothing special needs to be done besides 1091 * enabling the port. 1092 */ 1093 I915_WRITE(DDI_BUF_CTL(port), 1094 intel_dig_port->saved_port_bits | 1095 DDI_BUF_CTL_ENABLE); 1096 } else if (type == INTEL_OUTPUT_EDP) { 1097 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1098 1099 if (port == PORT_A) 1100 intel_dp_stop_link_train(intel_dp); 1101 1102 intel_edp_backlight_on(intel_dp); 1103 intel_edp_psr_enable(intel_dp); 1104 } 1105 1106 if (intel_crtc->config.has_audio) { 1107 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 1108 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 1109 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); 1110 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 1111 } 1112 } 1113 1114 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 1115 { 1116 struct drm_encoder *encoder = &intel_encoder->base; 1117 struct drm_crtc *crtc = encoder->crtc; 1118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1119 int pipe = intel_crtc->pipe; 1120 int type = intel_encoder->type; 1121 struct drm_device *dev = encoder->dev; 1122 struct drm_i915_private *dev_priv = dev->dev_private; 1123 uint32_t tmp; 1124 1125 /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this 1126 * register is part of the power well on Haswell. */ 1127 if (intel_crtc->config.has_audio) { 1128 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 1129 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << 1130 (pipe * 4)); 1131 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 1132 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 1133 } 1134 1135 if (type == INTEL_OUTPUT_EDP) { 1136 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1137 1138 intel_edp_psr_disable(intel_dp); 1139 intel_edp_backlight_off(intel_dp); 1140 } 1141 } 1142 1143 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) 1144 { 1145 struct drm_device *dev = dev_priv->dev; 1146 uint32_t lcpll = I915_READ(LCPLL_CTL); 1147 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; 1148 1149 if (lcpll & LCPLL_CD_SOURCE_FCLK) { 1150 return 800000; 1151 } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) { 1152 return 450000; 1153 } else if (freq == LCPLL_CLK_FREQ_450) { 1154 return 450000; 1155 } else if (IS_HASWELL(dev)) { 1156 if (IS_ULT(dev)) 1157 return 337500; 1158 else 1159 return 540000; 1160 } else { 1161 if (freq == LCPLL_CLK_FREQ_54O_BDW) 1162 return 540000; 1163 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 1164 return 337500; 1165 else 1166 return 675000; 1167 } 1168 } 1169 1170 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 1171 struct intel_shared_dpll *pll) 1172 { 1173 I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll); 1174 POSTING_READ(WRPLL_CTL(pll->id)); 1175 udelay(20); 1176 } 1177 1178 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, 1179 struct intel_shared_dpll *pll) 1180 { 1181 uint32_t val; 1182 1183 val = I915_READ(WRPLL_CTL(pll->id)); 1184 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 1185 POSTING_READ(WRPLL_CTL(pll->id)); 1186 } 1187 1188 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 1189 struct intel_shared_dpll *pll, 1190 struct intel_dpll_hw_state *hw_state) 1191 { 1192 uint32_t val; 1193 1194 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) 1195 return false; 1196 1197 val = I915_READ(WRPLL_CTL(pll->id)); 1198 hw_state->wrpll = val; 1199 1200 return val & WRPLL_PLL_ENABLE; 1201 } 1202 1203 static const char * const hsw_ddi_pll_names[] = { 1204 "WRPLL 1", 1205 "WRPLL 2", 1206 }; 1207 1208 void intel_ddi_pll_init(struct drm_device *dev) 1209 { 1210 struct drm_i915_private *dev_priv = dev->dev_private; 1211 uint32_t val = I915_READ(LCPLL_CTL); 1212 int i; 1213 1214 dev_priv->num_shared_dpll = 2; 1215 1216 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 1217 dev_priv->shared_dplls[i].id = i; 1218 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 1219 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; 1220 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; 1221 dev_priv->shared_dplls[i].get_hw_state = 1222 hsw_ddi_pll_get_hw_state; 1223 } 1224 1225 /* The LCPLL register should be turned on by the BIOS. For now let's 1226 * just check its state and print errors in case something is wrong. 1227 * Don't even try to turn it on. 1228 */ 1229 1230 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", 1231 intel_ddi_get_cdclk_freq(dev_priv)); 1232 1233 if (val & LCPLL_CD_SOURCE_FCLK) 1234 DRM_ERROR("CDCLK source is not LCPLL\n"); 1235 1236 if (val & LCPLL_PLL_DISABLE) 1237 DRM_ERROR("LCPLL is disabled\n"); 1238 } 1239 1240 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 1241 { 1242 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1243 struct intel_dp *intel_dp = &intel_dig_port->dp; 1244 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1245 enum port port = intel_dig_port->port; 1246 uint32_t val; 1247 bool wait = false; 1248 1249 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 1250 val = I915_READ(DDI_BUF_CTL(port)); 1251 if (val & DDI_BUF_CTL_ENABLE) { 1252 val &= ~DDI_BUF_CTL_ENABLE; 1253 I915_WRITE(DDI_BUF_CTL(port), val); 1254 wait = true; 1255 } 1256 1257 val = I915_READ(DP_TP_CTL(port)); 1258 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1259 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1260 I915_WRITE(DP_TP_CTL(port), val); 1261 POSTING_READ(DP_TP_CTL(port)); 1262 1263 if (wait) 1264 intel_wait_ddi_buf_idle(dev_priv, port); 1265 } 1266 1267 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | 1268 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 1269 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1270 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 1271 I915_WRITE(DP_TP_CTL(port), val); 1272 POSTING_READ(DP_TP_CTL(port)); 1273 1274 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 1275 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 1276 POSTING_READ(DDI_BUF_CTL(port)); 1277 1278 udelay(600); 1279 } 1280 1281 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 1282 { 1283 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1284 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1285 uint32_t val; 1286 1287 intel_ddi_post_disable(intel_encoder); 1288 1289 val = I915_READ(_FDI_RXA_CTL); 1290 val &= ~FDI_RX_ENABLE; 1291 I915_WRITE(_FDI_RXA_CTL, val); 1292 1293 val = I915_READ(_FDI_RXA_MISC); 1294 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1295 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1296 I915_WRITE(_FDI_RXA_MISC, val); 1297 1298 val = I915_READ(_FDI_RXA_CTL); 1299 val &= ~FDI_PCDCLK; 1300 I915_WRITE(_FDI_RXA_CTL, val); 1301 1302 val = I915_READ(_FDI_RXA_CTL); 1303 val &= ~FDI_RX_PLL_ENABLE; 1304 I915_WRITE(_FDI_RXA_CTL, val); 1305 } 1306 1307 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) 1308 { 1309 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 1310 int type = intel_encoder->type; 1311 1312 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) 1313 intel_dp_check_link_status(intel_dp); 1314 } 1315 1316 void intel_ddi_get_config(struct intel_encoder *encoder, 1317 struct intel_crtc_config *pipe_config) 1318 { 1319 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1320 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1321 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 1322 u32 temp, flags = 0; 1323 1324 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1325 if (temp & TRANS_DDI_PHSYNC) 1326 flags |= DRM_MODE_FLAG_PHSYNC; 1327 else 1328 flags |= DRM_MODE_FLAG_NHSYNC; 1329 if (temp & TRANS_DDI_PVSYNC) 1330 flags |= DRM_MODE_FLAG_PVSYNC; 1331 else 1332 flags |= DRM_MODE_FLAG_NVSYNC; 1333 1334 pipe_config->adjusted_mode.flags |= flags; 1335 1336 switch (temp & TRANS_DDI_BPC_MASK) { 1337 case TRANS_DDI_BPC_6: 1338 pipe_config->pipe_bpp = 18; 1339 break; 1340 case TRANS_DDI_BPC_8: 1341 pipe_config->pipe_bpp = 24; 1342 break; 1343 case TRANS_DDI_BPC_10: 1344 pipe_config->pipe_bpp = 30; 1345 break; 1346 case TRANS_DDI_BPC_12: 1347 pipe_config->pipe_bpp = 36; 1348 break; 1349 default: 1350 break; 1351 } 1352 1353 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 1354 case TRANS_DDI_MODE_SELECT_HDMI: 1355 pipe_config->has_hdmi_sink = true; 1356 case TRANS_DDI_MODE_SELECT_DVI: 1357 case TRANS_DDI_MODE_SELECT_FDI: 1358 break; 1359 case TRANS_DDI_MODE_SELECT_DP_SST: 1360 case TRANS_DDI_MODE_SELECT_DP_MST: 1361 pipe_config->has_dp_encoder = true; 1362 intel_dp_get_m_n(intel_crtc, pipe_config); 1363 break; 1364 default: 1365 break; 1366 } 1367 1368 if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 1369 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 1370 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) 1371 pipe_config->has_audio = true; 1372 } 1373 1374 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 1375 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1376 /* 1377 * This is a big fat ugly hack. 1378 * 1379 * Some machines in UEFI boot mode provide us a VBT that has 18 1380 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1381 * unknown we fail to light up. Yet the same BIOS boots up with 1382 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1383 * max, not what it tells us to use. 1384 * 1385 * Note: This will still be broken if the eDP panel is not lit 1386 * up by the BIOS, and thus we can't get the mode at module 1387 * load. 1388 */ 1389 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1390 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1391 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1392 } 1393 1394 intel_ddi_clock_get(encoder, pipe_config); 1395 } 1396 1397 static void intel_ddi_destroy(struct drm_encoder *encoder) 1398 { 1399 /* HDMI has nothing special to destroy, so we can go with this. */ 1400 intel_dp_encoder_destroy(encoder); 1401 } 1402 1403 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 1404 struct intel_crtc_config *pipe_config) 1405 { 1406 int type = encoder->type; 1407 int port = intel_ddi_get_encoder_port(encoder); 1408 1409 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 1410 1411 if (port == PORT_A) 1412 pipe_config->cpu_transcoder = TRANSCODER_EDP; 1413 1414 if (type == INTEL_OUTPUT_HDMI) 1415 return intel_hdmi_compute_config(encoder, pipe_config); 1416 else 1417 return intel_dp_compute_config(encoder, pipe_config); 1418 } 1419 1420 static const struct drm_encoder_funcs intel_ddi_funcs = { 1421 .destroy = intel_ddi_destroy, 1422 }; 1423 1424 static struct intel_connector * 1425 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 1426 { 1427 struct intel_connector *connector; 1428 enum port port = intel_dig_port->port; 1429 1430 connector = kzalloc(sizeof(*connector), GFP_KERNEL); 1431 if (!connector) 1432 return NULL; 1433 1434 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 1435 if (!intel_dp_init_connector(intel_dig_port, connector)) { 1436 kfree(connector); 1437 return NULL; 1438 } 1439 1440 return connector; 1441 } 1442 1443 static struct intel_connector * 1444 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 1445 { 1446 struct intel_connector *connector; 1447 enum port port = intel_dig_port->port; 1448 1449 connector = kzalloc(sizeof(*connector), GFP_KERNEL); 1450 if (!connector) 1451 return NULL; 1452 1453 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 1454 intel_hdmi_init_connector(intel_dig_port, connector); 1455 1456 return connector; 1457 } 1458 1459 void intel_ddi_init(struct drm_device *dev, enum port port) 1460 { 1461 struct drm_i915_private *dev_priv = dev->dev_private; 1462 struct intel_digital_port *intel_dig_port; 1463 struct intel_encoder *intel_encoder; 1464 struct drm_encoder *encoder; 1465 bool init_hdmi, init_dp; 1466 1467 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 1468 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 1469 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 1470 if (!init_dp && !init_hdmi) { 1471 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", 1472 port_name(port)); 1473 init_hdmi = true; 1474 init_dp = true; 1475 } 1476 1477 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 1478 if (!intel_dig_port) 1479 return; 1480 1481 intel_encoder = &intel_dig_port->base; 1482 encoder = &intel_encoder->base; 1483 1484 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 1485 DRM_MODE_ENCODER_TMDS); 1486 1487 intel_encoder->compute_config = intel_ddi_compute_config; 1488 intel_encoder->enable = intel_enable_ddi; 1489 intel_encoder->pre_enable = intel_ddi_pre_enable; 1490 intel_encoder->disable = intel_disable_ddi; 1491 intel_encoder->post_disable = intel_ddi_post_disable; 1492 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 1493 intel_encoder->get_config = intel_ddi_get_config; 1494 1495 intel_dig_port->port = port; 1496 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 1497 (DDI_BUF_PORT_REVERSAL | 1498 DDI_A_4_LANES); 1499 1500 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 1501 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1502 intel_encoder->cloneable = 0; 1503 intel_encoder->hot_plug = intel_ddi_hot_plug; 1504 1505 if (init_dp) { 1506 if (!intel_ddi_init_dp_connector(intel_dig_port)) 1507 goto err; 1508 1509 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 1510 dev_priv->hpd_irq_port[port] = intel_dig_port; 1511 } 1512 1513 /* In theory we don't need the encoder->type check, but leave it just in 1514 * case we have some really bad VBTs... */ 1515 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 1516 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 1517 goto err; 1518 } 1519 1520 return; 1521 1522 err: 1523 drm_encoder_cleanup(encoder); 1524 kfree(intel_dig_port); 1525 } 1526