1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 31 struct ddi_buf_trans { 32 u32 trans1; /* balance leg enable, de-emph level */ 33 u32 trans2; /* vref sel, vswing */ 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 35 }; 36 37 static const u8 index_to_dp_signal_levels[] = { 38 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 39 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 40 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 41 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 42 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 43 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 44 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 45 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 46 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 47 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 48 }; 49 50 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 51 * them for both DP and FDI transports, allowing those ports to 52 * automatically adapt to HDMI connections as well 53 */ 54 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 55 { 0x00FFFFFF, 0x0006000E, 0x0 }, 56 { 0x00D75FFF, 0x0005000A, 0x0 }, 57 { 0x00C30FFF, 0x00040006, 0x0 }, 58 { 0x80AAAFFF, 0x000B0000, 0x0 }, 59 { 0x00FFFFFF, 0x0005000A, 0x0 }, 60 { 0x00D75FFF, 0x000C0004, 0x0 }, 61 { 0x80C30FFF, 0x000B0000, 0x0 }, 62 { 0x00FFFFFF, 0x00040006, 0x0 }, 63 { 0x80D75FFF, 0x000B0000, 0x0 }, 64 }; 65 66 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 67 { 0x00FFFFFF, 0x0007000E, 0x0 }, 68 { 0x00D75FFF, 0x000F000A, 0x0 }, 69 { 0x00C30FFF, 0x00060006, 0x0 }, 70 { 0x00AAAFFF, 0x001E0000, 0x0 }, 71 { 0x00FFFFFF, 0x000F000A, 0x0 }, 72 { 0x00D75FFF, 0x00160004, 0x0 }, 73 { 0x00C30FFF, 0x001E0000, 0x0 }, 74 { 0x00FFFFFF, 0x00060006, 0x0 }, 75 { 0x00D75FFF, 0x001E0000, 0x0 }, 76 }; 77 78 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 79 /* Idx NT mV d T mV d db */ 80 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 81 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 82 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 83 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 84 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 85 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 86 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 87 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 88 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 89 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 90 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 91 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 92 }; 93 94 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 95 { 0x00FFFFFF, 0x00000012, 0x0 }, 96 { 0x00EBAFFF, 0x00020011, 0x0 }, 97 { 0x00C71FFF, 0x0006000F, 0x0 }, 98 { 0x00AAAFFF, 0x000E000A, 0x0 }, 99 { 0x00FFFFFF, 0x00020011, 0x0 }, 100 { 0x00DB6FFF, 0x0005000F, 0x0 }, 101 { 0x00BEEFFF, 0x000A000C, 0x0 }, 102 { 0x00FFFFFF, 0x0005000F, 0x0 }, 103 { 0x00DB6FFF, 0x000A000C, 0x0 }, 104 }; 105 106 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 107 { 0x00FFFFFF, 0x0007000E, 0x0 }, 108 { 0x00D75FFF, 0x000E000A, 0x0 }, 109 { 0x00BEFFFF, 0x00140006, 0x0 }, 110 { 0x80B2CFFF, 0x001B0002, 0x0 }, 111 { 0x00FFFFFF, 0x000E000A, 0x0 }, 112 { 0x00DB6FFF, 0x00160005, 0x0 }, 113 { 0x80C71FFF, 0x001A0002, 0x0 }, 114 { 0x00F7DFFF, 0x00180004, 0x0 }, 115 { 0x80D75FFF, 0x001B0002, 0x0 }, 116 }; 117 118 #if 0 119 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 120 { 0x00FFFFFF, 0x0001000E, 0x0 }, 121 { 0x00D75FFF, 0x0004000A, 0x0 }, 122 { 0x00C30FFF, 0x00070006, 0x0 }, 123 { 0x00AAAFFF, 0x000C0000, 0x0 }, 124 { 0x00FFFFFF, 0x0004000A, 0x0 }, 125 { 0x00D75FFF, 0x00090004, 0x0 }, 126 { 0x00C30FFF, 0x000C0000, 0x0 }, 127 { 0x00FFFFFF, 0x00070006, 0x0 }, 128 { 0x00D75FFF, 0x000C0000, 0x0 }, 129 }; 130 #endif 131 132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 133 /* Idx NT mV d T mV df db */ 134 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 135 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 136 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 137 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 138 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 139 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 140 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 141 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 142 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 143 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 144 }; 145 146 /* Skylake H and S */ 147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 148 { 0x00002016, 0x000000A0, 0x0 }, 149 { 0x00005012, 0x0000009B, 0x0 }, 150 { 0x00007011, 0x00000088, 0x0 }, 151 { 0x80009010, 0x000000C0, 0x1 }, 152 { 0x00002016, 0x0000009B, 0x0 }, 153 { 0x00005012, 0x00000088, 0x0 }, 154 { 0x80007011, 0x000000C0, 0x1 }, 155 { 0x00002016, 0x000000DF, 0x0 }, 156 { 0x80005012, 0x000000C0, 0x1 }, 157 }; 158 159 /* Skylake U */ 160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 161 { 0x0000201B, 0x000000A2, 0x0 }, 162 { 0x00005012, 0x00000088, 0x0 }, 163 { 0x80007011, 0x000000CD, 0x1 }, 164 { 0x80009010, 0x000000C0, 0x1 }, 165 { 0x0000201B, 0x0000009D, 0x0 }, 166 { 0x80005012, 0x000000C0, 0x1 }, 167 { 0x80007011, 0x000000C0, 0x1 }, 168 { 0x00002016, 0x00000088, 0x0 }, 169 { 0x80005012, 0x000000C0, 0x1 }, 170 }; 171 172 /* Skylake Y */ 173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 174 { 0x00000018, 0x000000A2, 0x0 }, 175 { 0x00005012, 0x00000088, 0x0 }, 176 { 0x80007011, 0x000000CD, 0x3 }, 177 { 0x80009010, 0x000000C0, 0x3 }, 178 { 0x00000018, 0x0000009D, 0x0 }, 179 { 0x80005012, 0x000000C0, 0x3 }, 180 { 0x80007011, 0x000000C0, 0x3 }, 181 { 0x00000018, 0x00000088, 0x0 }, 182 { 0x80005012, 0x000000C0, 0x3 }, 183 }; 184 185 /* Kabylake H and S */ 186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 187 { 0x00002016, 0x000000A0, 0x0 }, 188 { 0x00005012, 0x0000009B, 0x0 }, 189 { 0x00007011, 0x00000088, 0x0 }, 190 { 0x80009010, 0x000000C0, 0x1 }, 191 { 0x00002016, 0x0000009B, 0x0 }, 192 { 0x00005012, 0x00000088, 0x0 }, 193 { 0x80007011, 0x000000C0, 0x1 }, 194 { 0x00002016, 0x00000097, 0x0 }, 195 { 0x80005012, 0x000000C0, 0x1 }, 196 }; 197 198 /* Kabylake U */ 199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 200 { 0x0000201B, 0x000000A1, 0x0 }, 201 { 0x00005012, 0x00000088, 0x0 }, 202 { 0x80007011, 0x000000CD, 0x3 }, 203 { 0x80009010, 0x000000C0, 0x3 }, 204 { 0x0000201B, 0x0000009D, 0x0 }, 205 { 0x80005012, 0x000000C0, 0x3 }, 206 { 0x80007011, 0x000000C0, 0x3 }, 207 { 0x00002016, 0x0000004F, 0x0 }, 208 { 0x80005012, 0x000000C0, 0x3 }, 209 }; 210 211 /* Kabylake Y */ 212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 213 { 0x00001017, 0x000000A1, 0x0 }, 214 { 0x00005012, 0x00000088, 0x0 }, 215 { 0x80007011, 0x000000CD, 0x3 }, 216 { 0x8000800F, 0x000000C0, 0x3 }, 217 { 0x00001017, 0x0000009D, 0x0 }, 218 { 0x80005012, 0x000000C0, 0x3 }, 219 { 0x80007011, 0x000000C0, 0x3 }, 220 { 0x00001017, 0x0000004C, 0x0 }, 221 { 0x80005012, 0x000000C0, 0x3 }, 222 }; 223 224 /* 225 * Skylake/Kabylake H and S 226 * eDP 1.4 low vswing translation parameters 227 */ 228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 229 { 0x00000018, 0x000000A8, 0x0 }, 230 { 0x00004013, 0x000000A9, 0x0 }, 231 { 0x00007011, 0x000000A2, 0x0 }, 232 { 0x00009010, 0x0000009C, 0x0 }, 233 { 0x00000018, 0x000000A9, 0x0 }, 234 { 0x00006013, 0x000000A2, 0x0 }, 235 { 0x00007011, 0x000000A6, 0x0 }, 236 { 0x00000018, 0x000000AB, 0x0 }, 237 { 0x00007013, 0x0000009F, 0x0 }, 238 { 0x00000018, 0x000000DF, 0x0 }, 239 }; 240 241 /* 242 * Skylake/Kabylake U 243 * eDP 1.4 low vswing translation parameters 244 */ 245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 246 { 0x00000018, 0x000000A8, 0x0 }, 247 { 0x00004013, 0x000000A9, 0x0 }, 248 { 0x00007011, 0x000000A2, 0x0 }, 249 { 0x00009010, 0x0000009C, 0x0 }, 250 { 0x00000018, 0x000000A9, 0x0 }, 251 { 0x00006013, 0x000000A2, 0x0 }, 252 { 0x00007011, 0x000000A6, 0x0 }, 253 { 0x00002016, 0x000000AB, 0x0 }, 254 { 0x00005013, 0x0000009F, 0x0 }, 255 { 0x00000018, 0x000000DF, 0x0 }, 256 }; 257 258 /* 259 * Skylake/Kabylake Y 260 * eDP 1.4 low vswing translation parameters 261 */ 262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 263 { 0x00000018, 0x000000A8, 0x0 }, 264 { 0x00004013, 0x000000AB, 0x0 }, 265 { 0x00007011, 0x000000A4, 0x0 }, 266 { 0x00009010, 0x000000DF, 0x0 }, 267 { 0x00000018, 0x000000AA, 0x0 }, 268 { 0x00006013, 0x000000A4, 0x0 }, 269 { 0x00007011, 0x0000009D, 0x0 }, 270 { 0x00000018, 0x000000A0, 0x0 }, 271 { 0x00006012, 0x000000DF, 0x0 }, 272 { 0x00000018, 0x0000008A, 0x0 }, 273 }; 274 275 /* Skylake/Kabylake U, H and S */ 276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 277 { 0x00000018, 0x000000AC, 0x0 }, 278 { 0x00005012, 0x0000009D, 0x0 }, 279 { 0x00007011, 0x00000088, 0x0 }, 280 { 0x00000018, 0x000000A1, 0x0 }, 281 { 0x00000018, 0x00000098, 0x0 }, 282 { 0x00004013, 0x00000088, 0x0 }, 283 { 0x80006012, 0x000000CD, 0x1 }, 284 { 0x00000018, 0x000000DF, 0x0 }, 285 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 286 { 0x80003015, 0x000000C0, 0x1 }, 287 { 0x80000018, 0x000000C0, 0x1 }, 288 }; 289 290 /* Skylake/Kabylake Y */ 291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 292 { 0x00000018, 0x000000A1, 0x0 }, 293 { 0x00005012, 0x000000DF, 0x0 }, 294 { 0x80007011, 0x000000CB, 0x3 }, 295 { 0x00000018, 0x000000A4, 0x0 }, 296 { 0x00000018, 0x0000009D, 0x0 }, 297 { 0x00004013, 0x00000080, 0x0 }, 298 { 0x80006013, 0x000000C0, 0x3 }, 299 { 0x00000018, 0x0000008A, 0x0 }, 300 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 301 { 0x80003015, 0x000000C0, 0x3 }, 302 { 0x80000018, 0x000000C0, 0x3 }, 303 }; 304 305 struct bxt_ddi_buf_trans { 306 u32 margin; /* swing value */ 307 u32 scale; /* scale value */ 308 u32 enable; /* scale enable */ 309 u32 deemphasis; 310 bool default_index; /* true if the entry represents default value */ 311 }; 312 313 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 314 /* Idx NT mV diff db */ 315 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ 316 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 317 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ 318 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 319 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 320 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 321 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ 322 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 323 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 324 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 325 }; 326 327 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 328 /* Idx NT mV diff db */ 329 { 26, 0, 0, 128, false }, /* 0: 200 0 */ 330 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ 331 { 48, 0, 0, 96, false }, /* 2: 200 4 */ 332 { 54, 0, 0, 69, false }, /* 3: 200 6 */ 333 { 32, 0, 0, 128, false }, /* 4: 250 0 */ 334 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ 335 { 54, 0, 0, 85, false }, /* 6: 250 4 */ 336 { 43, 0, 0, 128, false }, /* 7: 300 0 */ 337 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ 338 { 48, 0, 0, 128, false }, /* 9: 300 0 */ 339 }; 340 341 /* BSpec has 2 recommended values - entries 0 and 8. 342 * Using the entry with higher vswing. 343 */ 344 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 345 /* Idx NT mV diff db */ 346 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ 347 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 348 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ 349 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 350 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 351 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 352 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ 353 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 354 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 355 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 356 }; 357 358 enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder) 359 { 360 switch (encoder->type) { 361 case INTEL_OUTPUT_DP_MST: 362 return enc_to_mst(&encoder->base)->primary->port; 363 case INTEL_OUTPUT_DP: 364 case INTEL_OUTPUT_EDP: 365 case INTEL_OUTPUT_HDMI: 366 case INTEL_OUTPUT_UNKNOWN: 367 return enc_to_dig_port(&encoder->base)->port; 368 case INTEL_OUTPUT_ANALOG: 369 return PORT_E; 370 default: 371 MISSING_CASE(encoder->type); 372 return PORT_A; 373 } 374 } 375 376 static const struct ddi_buf_trans * 377 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 378 { 379 if (dev_priv->vbt.edp.low_vswing) { 380 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 381 return bdw_ddi_translations_edp; 382 } else { 383 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 384 return bdw_ddi_translations_dp; 385 } 386 } 387 388 static const struct ddi_buf_trans * 389 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 390 { 391 if (IS_SKL_ULX(dev_priv)) { 392 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 393 return skl_y_ddi_translations_dp; 394 } else if (IS_SKL_ULT(dev_priv)) { 395 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 396 return skl_u_ddi_translations_dp; 397 } else { 398 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 399 return skl_ddi_translations_dp; 400 } 401 } 402 403 static const struct ddi_buf_trans * 404 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 405 { 406 if (IS_KBL_ULX(dev_priv)) { 407 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 408 return kbl_y_ddi_translations_dp; 409 } else if (IS_KBL_ULT(dev_priv)) { 410 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 411 return kbl_u_ddi_translations_dp; 412 } else { 413 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 414 return kbl_ddi_translations_dp; 415 } 416 } 417 418 static const struct ddi_buf_trans * 419 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 420 { 421 if (dev_priv->vbt.edp.low_vswing) { 422 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 423 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 424 return skl_y_ddi_translations_edp; 425 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { 426 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 427 return skl_u_ddi_translations_edp; 428 } else { 429 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 430 return skl_ddi_translations_edp; 431 } 432 } 433 434 if (IS_KABYLAKE(dev_priv)) 435 return kbl_get_buf_trans_dp(dev_priv, n_entries); 436 else 437 return skl_get_buf_trans_dp(dev_priv, n_entries); 438 } 439 440 static const struct ddi_buf_trans * 441 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 442 { 443 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 444 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 445 return skl_y_ddi_translations_hdmi; 446 } else { 447 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 448 return skl_ddi_translations_hdmi; 449 } 450 } 451 452 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 453 { 454 int n_hdmi_entries; 455 int hdmi_level; 456 int hdmi_default_entry; 457 458 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 459 460 if (IS_GEN9_LP(dev_priv)) 461 return hdmi_level; 462 463 if (IS_GEN9_BC(dev_priv)) { 464 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 465 hdmi_default_entry = 8; 466 } else if (IS_BROADWELL(dev_priv)) { 467 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 468 hdmi_default_entry = 7; 469 } else if (IS_HASWELL(dev_priv)) { 470 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 471 hdmi_default_entry = 6; 472 } else { 473 WARN(1, "ddi translation table missing\n"); 474 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 475 hdmi_default_entry = 7; 476 } 477 478 /* Choose a good default if VBT is badly populated */ 479 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 480 hdmi_level >= n_hdmi_entries) 481 hdmi_level = hdmi_default_entry; 482 483 return hdmi_level; 484 } 485 486 static const struct ddi_buf_trans * 487 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, 488 int *n_entries) 489 { 490 if (IS_KABYLAKE(dev_priv)) { 491 return kbl_get_buf_trans_dp(dev_priv, n_entries); 492 } else if (IS_SKYLAKE(dev_priv)) { 493 return skl_get_buf_trans_dp(dev_priv, n_entries); 494 } else if (IS_BROADWELL(dev_priv)) { 495 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 496 return bdw_ddi_translations_dp; 497 } else if (IS_HASWELL(dev_priv)) { 498 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 499 return hsw_ddi_translations_dp; 500 } 501 502 *n_entries = 0; 503 return NULL; 504 } 505 506 static const struct ddi_buf_trans * 507 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, 508 int *n_entries) 509 { 510 if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) { 511 return skl_get_buf_trans_edp(dev_priv, n_entries); 512 } else if (IS_BROADWELL(dev_priv)) { 513 return bdw_get_buf_trans_edp(dev_priv, n_entries); 514 } else if (IS_HASWELL(dev_priv)) { 515 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 516 return hsw_ddi_translations_dp; 517 } 518 519 *n_entries = 0; 520 return NULL; 521 } 522 523 static const struct ddi_buf_trans * 524 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 525 int *n_entries) 526 { 527 if (IS_BROADWELL(dev_priv)) { 528 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 529 return hsw_ddi_translations_fdi; 530 } else if (IS_HASWELL(dev_priv)) { 531 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 532 return hsw_ddi_translations_fdi; 533 } 534 535 *n_entries = 0; 536 return NULL; 537 } 538 539 /* 540 * Starting with Haswell, DDI port buffers must be programmed with correct 541 * values in advance. This function programs the correct values for 542 * DP/eDP/FDI use cases. 543 */ 544 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) 545 { 546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 547 u32 iboost_bit = 0; 548 int i, n_entries; 549 enum port port = intel_ddi_get_encoder_port(encoder); 550 const struct ddi_buf_trans *ddi_translations; 551 552 if (IS_GEN9_LP(dev_priv)) 553 return; 554 555 switch (encoder->type) { 556 case INTEL_OUTPUT_EDP: 557 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, 558 &n_entries); 559 break; 560 case INTEL_OUTPUT_DP: 561 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, 562 &n_entries); 563 break; 564 case INTEL_OUTPUT_ANALOG: 565 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 566 &n_entries); 567 break; 568 default: 569 MISSING_CASE(encoder->type); 570 return; 571 } 572 573 if (IS_GEN9_BC(dev_priv)) { 574 /* If we're boosting the current, set bit 31 of trans1 */ 575 if (dev_priv->vbt.ddi_port_info[port].dp_boost_level) 576 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 577 578 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && 579 port != PORT_A && port != PORT_E && 580 n_entries > 9)) 581 n_entries = 9; 582 } 583 584 for (i = 0; i < n_entries; i++) { 585 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 586 ddi_translations[i].trans1 | iboost_bit); 587 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 588 ddi_translations[i].trans2); 589 } 590 } 591 592 /* 593 * Starting with Haswell, DDI port buffers must be programmed with correct 594 * values in advance. This function programs the correct values for 595 * HDMI/DVI use cases. 596 */ 597 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder) 598 { 599 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 600 u32 iboost_bit = 0; 601 int n_hdmi_entries, hdmi_level; 602 enum port port = intel_ddi_get_encoder_port(encoder); 603 const struct ddi_buf_trans *ddi_translations_hdmi; 604 605 if (IS_GEN9_LP(dev_priv)) 606 return; 607 608 hdmi_level = intel_ddi_hdmi_level(dev_priv, port); 609 610 if (IS_GEN9_BC(dev_priv)) { 611 ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 612 613 /* If we're boosting the current, set bit 31 of trans1 */ 614 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) 615 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 616 } else if (IS_BROADWELL(dev_priv)) { 617 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 618 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 619 } else if (IS_HASWELL(dev_priv)) { 620 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 621 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 622 } else { 623 WARN(1, "ddi translation table missing\n"); 624 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 625 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 626 } 627 628 /* Entry 9 is for HDMI: */ 629 I915_WRITE(DDI_BUF_TRANS_LO(port, 9), 630 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); 631 I915_WRITE(DDI_BUF_TRANS_HI(port, 9), 632 ddi_translations_hdmi[hdmi_level].trans2); 633 } 634 635 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 636 enum port port) 637 { 638 i915_reg_t reg = DDI_BUF_CTL(port); 639 int i; 640 641 for (i = 0; i < 16; i++) { 642 udelay(1); 643 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 644 return; 645 } 646 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 647 } 648 649 static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) 650 { 651 switch (pll->id) { 652 case DPLL_ID_WRPLL1: 653 return PORT_CLK_SEL_WRPLL1; 654 case DPLL_ID_WRPLL2: 655 return PORT_CLK_SEL_WRPLL2; 656 case DPLL_ID_SPLL: 657 return PORT_CLK_SEL_SPLL; 658 case DPLL_ID_LCPLL_810: 659 return PORT_CLK_SEL_LCPLL_810; 660 case DPLL_ID_LCPLL_1350: 661 return PORT_CLK_SEL_LCPLL_1350; 662 case DPLL_ID_LCPLL_2700: 663 return PORT_CLK_SEL_LCPLL_2700; 664 default: 665 MISSING_CASE(pll->id); 666 return PORT_CLK_SEL_NONE; 667 } 668 } 669 670 /* Starting with Haswell, different DDI ports can work in FDI mode for 671 * connection to the PCH-located connectors. For this, it is necessary to train 672 * both the DDI port and PCH receiver for the desired DDI buffer settings. 673 * 674 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 675 * please note that when FDI mode is active on DDI E, it shares 2 lines with 676 * DDI A (which is used for eDP) 677 */ 678 679 void hsw_fdi_link_train(struct intel_crtc *crtc, 680 const struct intel_crtc_state *crtc_state) 681 { 682 struct drm_device *dev = crtc->base.dev; 683 struct drm_i915_private *dev_priv = to_i915(dev); 684 struct intel_encoder *encoder; 685 u32 temp, i, rx_ctl_val, ddi_pll_sel; 686 687 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 688 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); 689 intel_prepare_dp_ddi_buffers(encoder); 690 } 691 692 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 693 * mode set "sequence for CRT port" document: 694 * - TP1 to TP2 time with the default value 695 * - FDI delay to 90h 696 * 697 * WaFDIAutoLinkSetTimingOverrride:hsw 698 */ 699 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 700 FDI_RX_PWRDN_LANE0_VAL(2) | 701 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 702 703 /* Enable the PCH Receiver FDI PLL */ 704 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 705 FDI_RX_PLL_ENABLE | 706 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 707 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 708 POSTING_READ(FDI_RX_CTL(PIPE_A)); 709 udelay(220); 710 711 /* Switch from Rawclk to PCDclk */ 712 rx_ctl_val |= FDI_PCDCLK; 713 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 714 715 /* Configure Port Clock Select */ 716 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 717 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); 718 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); 719 720 /* Start the training iterating through available voltages and emphasis, 721 * testing each value twice. */ 722 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 723 /* Configure DP_TP_CTL with auto-training */ 724 I915_WRITE(DP_TP_CTL(PORT_E), 725 DP_TP_CTL_FDI_AUTOTRAIN | 726 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 727 DP_TP_CTL_LINK_TRAIN_PAT1 | 728 DP_TP_CTL_ENABLE); 729 730 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 731 * DDI E does not support port reversal, the functionality is 732 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 733 * port reversal bit */ 734 I915_WRITE(DDI_BUF_CTL(PORT_E), 735 DDI_BUF_CTL_ENABLE | 736 ((crtc_state->fdi_lanes - 1) << 1) | 737 DDI_BUF_TRANS_SELECT(i / 2)); 738 POSTING_READ(DDI_BUF_CTL(PORT_E)); 739 740 udelay(600); 741 742 /* Program PCH FDI Receiver TU */ 743 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 744 745 /* Enable PCH FDI Receiver with auto-training */ 746 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 747 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 748 POSTING_READ(FDI_RX_CTL(PIPE_A)); 749 750 /* Wait for FDI receiver lane calibration */ 751 udelay(30); 752 753 /* Unset FDI_RX_MISC pwrdn lanes */ 754 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 755 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 756 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 757 POSTING_READ(FDI_RX_MISC(PIPE_A)); 758 759 /* Wait for FDI auto training time */ 760 udelay(5); 761 762 temp = I915_READ(DP_TP_STATUS(PORT_E)); 763 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 764 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 765 break; 766 } 767 768 /* 769 * Leave things enabled even if we failed to train FDI. 770 * Results in less fireworks from the state checker. 771 */ 772 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 773 DRM_ERROR("FDI link training failed!\n"); 774 break; 775 } 776 777 rx_ctl_val &= ~FDI_RX_ENABLE; 778 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 779 POSTING_READ(FDI_RX_CTL(PIPE_A)); 780 781 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 782 temp &= ~DDI_BUF_CTL_ENABLE; 783 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 784 POSTING_READ(DDI_BUF_CTL(PORT_E)); 785 786 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 787 temp = I915_READ(DP_TP_CTL(PORT_E)); 788 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 789 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 790 I915_WRITE(DP_TP_CTL(PORT_E), temp); 791 POSTING_READ(DP_TP_CTL(PORT_E)); 792 793 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 794 795 /* Reset FDI_RX_MISC pwrdn lanes */ 796 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 797 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 798 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 799 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 800 POSTING_READ(FDI_RX_MISC(PIPE_A)); 801 } 802 803 /* Enable normal pixel sending for FDI */ 804 I915_WRITE(DP_TP_CTL(PORT_E), 805 DP_TP_CTL_FDI_AUTOTRAIN | 806 DP_TP_CTL_LINK_TRAIN_NORMAL | 807 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 808 DP_TP_CTL_ENABLE); 809 } 810 811 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 812 { 813 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 814 struct intel_digital_port *intel_dig_port = 815 enc_to_dig_port(&encoder->base); 816 817 intel_dp->DP = intel_dig_port->saved_port_bits | 818 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 819 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 820 } 821 822 static struct intel_encoder * 823 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) 824 { 825 struct drm_device *dev = crtc->base.dev; 826 struct intel_encoder *encoder, *ret = NULL; 827 int num_encoders = 0; 828 829 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 830 ret = encoder; 831 num_encoders++; 832 } 833 834 if (num_encoders != 1) 835 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 836 pipe_name(crtc->pipe)); 837 838 BUG_ON(ret == NULL); 839 return ret; 840 } 841 842 /* Finds the only possible encoder associated with the given CRTC. */ 843 struct intel_encoder * 844 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 845 { 846 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 847 struct intel_encoder *ret = NULL; 848 struct drm_atomic_state *state; 849 struct drm_connector *connector; 850 struct drm_connector_state *connector_state; 851 int num_encoders = 0; 852 int i; 853 854 state = crtc_state->base.state; 855 856 for_each_new_connector_in_state(state, connector, connector_state, i) { 857 if (connector_state->crtc != crtc_state->base.crtc) 858 continue; 859 860 ret = to_intel_encoder(connector_state->best_encoder); 861 num_encoders++; 862 } 863 864 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 865 pipe_name(crtc->pipe)); 866 867 BUG_ON(ret == NULL); 868 return ret; 869 } 870 871 #define LC_FREQ 2700 872 873 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 874 i915_reg_t reg) 875 { 876 int refclk = LC_FREQ; 877 int n, p, r; 878 u32 wrpll; 879 880 wrpll = I915_READ(reg); 881 switch (wrpll & WRPLL_PLL_REF_MASK) { 882 case WRPLL_PLL_SSC: 883 case WRPLL_PLL_NON_SSC: 884 /* 885 * We could calculate spread here, but our checking 886 * code only cares about 5% accuracy, and spread is a max of 887 * 0.5% downspread. 888 */ 889 refclk = 135; 890 break; 891 case WRPLL_PLL_LCPLL: 892 refclk = LC_FREQ; 893 break; 894 default: 895 WARN(1, "bad wrpll refclk\n"); 896 return 0; 897 } 898 899 r = wrpll & WRPLL_DIVIDER_REF_MASK; 900 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 901 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 902 903 /* Convert to KHz, p & r have a fixed point portion */ 904 return (refclk * n * 100) / (p * r); 905 } 906 907 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 908 uint32_t dpll) 909 { 910 i915_reg_t cfgcr1_reg, cfgcr2_reg; 911 uint32_t cfgcr1_val, cfgcr2_val; 912 uint32_t p0, p1, p2, dco_freq; 913 914 cfgcr1_reg = DPLL_CFGCR1(dpll); 915 cfgcr2_reg = DPLL_CFGCR2(dpll); 916 917 cfgcr1_val = I915_READ(cfgcr1_reg); 918 cfgcr2_val = I915_READ(cfgcr2_reg); 919 920 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 921 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 922 923 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 924 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 925 else 926 p1 = 1; 927 928 929 switch (p0) { 930 case DPLL_CFGCR2_PDIV_1: 931 p0 = 1; 932 break; 933 case DPLL_CFGCR2_PDIV_2: 934 p0 = 2; 935 break; 936 case DPLL_CFGCR2_PDIV_3: 937 p0 = 3; 938 break; 939 case DPLL_CFGCR2_PDIV_7: 940 p0 = 7; 941 break; 942 } 943 944 switch (p2) { 945 case DPLL_CFGCR2_KDIV_5: 946 p2 = 5; 947 break; 948 case DPLL_CFGCR2_KDIV_2: 949 p2 = 2; 950 break; 951 case DPLL_CFGCR2_KDIV_3: 952 p2 = 3; 953 break; 954 case DPLL_CFGCR2_KDIV_1: 955 p2 = 1; 956 break; 957 } 958 959 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 960 961 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 962 1000) / 0x8000; 963 964 return dco_freq / (p0 * p1 * p2 * 5); 965 } 966 967 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 968 { 969 int dotclock; 970 971 if (pipe_config->has_pch_encoder) 972 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 973 &pipe_config->fdi_m_n); 974 else if (intel_crtc_has_dp_encoder(pipe_config)) 975 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 976 &pipe_config->dp_m_n); 977 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 978 dotclock = pipe_config->port_clock * 2 / 3; 979 else 980 dotclock = pipe_config->port_clock; 981 982 if (pipe_config->pixel_multiplier) 983 dotclock /= pipe_config->pixel_multiplier; 984 985 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 986 } 987 988 static void skl_ddi_clock_get(struct intel_encoder *encoder, 989 struct intel_crtc_state *pipe_config) 990 { 991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 992 int link_clock = 0; 993 uint32_t dpll_ctl1, dpll; 994 995 dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); 996 997 dpll_ctl1 = I915_READ(DPLL_CTRL1); 998 999 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 1000 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 1001 } else { 1002 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 1003 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 1004 1005 switch (link_clock) { 1006 case DPLL_CTRL1_LINK_RATE_810: 1007 link_clock = 81000; 1008 break; 1009 case DPLL_CTRL1_LINK_RATE_1080: 1010 link_clock = 108000; 1011 break; 1012 case DPLL_CTRL1_LINK_RATE_1350: 1013 link_clock = 135000; 1014 break; 1015 case DPLL_CTRL1_LINK_RATE_1620: 1016 link_clock = 162000; 1017 break; 1018 case DPLL_CTRL1_LINK_RATE_2160: 1019 link_clock = 216000; 1020 break; 1021 case DPLL_CTRL1_LINK_RATE_2700: 1022 link_clock = 270000; 1023 break; 1024 default: 1025 WARN(1, "Unsupported link rate\n"); 1026 break; 1027 } 1028 link_clock *= 2; 1029 } 1030 1031 pipe_config->port_clock = link_clock; 1032 1033 ddi_dotclock_get(pipe_config); 1034 } 1035 1036 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1037 struct intel_crtc_state *pipe_config) 1038 { 1039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1040 int link_clock = 0; 1041 u32 val, pll; 1042 1043 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); 1044 switch (val & PORT_CLK_SEL_MASK) { 1045 case PORT_CLK_SEL_LCPLL_810: 1046 link_clock = 81000; 1047 break; 1048 case PORT_CLK_SEL_LCPLL_1350: 1049 link_clock = 135000; 1050 break; 1051 case PORT_CLK_SEL_LCPLL_2700: 1052 link_clock = 270000; 1053 break; 1054 case PORT_CLK_SEL_WRPLL1: 1055 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1056 break; 1057 case PORT_CLK_SEL_WRPLL2: 1058 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1059 break; 1060 case PORT_CLK_SEL_SPLL: 1061 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 1062 if (pll == SPLL_PLL_FREQ_810MHz) 1063 link_clock = 81000; 1064 else if (pll == SPLL_PLL_FREQ_1350MHz) 1065 link_clock = 135000; 1066 else if (pll == SPLL_PLL_FREQ_2700MHz) 1067 link_clock = 270000; 1068 else { 1069 WARN(1, "bad spll freq\n"); 1070 return; 1071 } 1072 break; 1073 default: 1074 WARN(1, "bad port clock sel\n"); 1075 return; 1076 } 1077 1078 pipe_config->port_clock = link_clock * 2; 1079 1080 ddi_dotclock_get(pipe_config); 1081 } 1082 1083 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 1084 enum intel_dpll_id dpll) 1085 { 1086 struct intel_shared_dpll *pll; 1087 struct intel_dpll_hw_state *state; 1088 struct dpll clock; 1089 1090 /* For DDI ports we always use a shared PLL. */ 1091 if (WARN_ON(dpll == DPLL_ID_PRIVATE)) 1092 return 0; 1093 1094 pll = &dev_priv->shared_dplls[dpll]; 1095 state = &pll->state.hw_state; 1096 1097 clock.m1 = 2; 1098 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; 1099 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1100 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; 1101 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1102 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1103 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1104 1105 return chv_calc_dpll_params(100000, &clock); 1106 } 1107 1108 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1109 struct intel_crtc_state *pipe_config) 1110 { 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 enum port port = intel_ddi_get_encoder_port(encoder); 1113 uint32_t dpll = port; 1114 1115 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); 1116 1117 ddi_dotclock_get(pipe_config); 1118 } 1119 1120 void intel_ddi_clock_get(struct intel_encoder *encoder, 1121 struct intel_crtc_state *pipe_config) 1122 { 1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1124 1125 if (INTEL_GEN(dev_priv) <= 8) 1126 hsw_ddi_clock_get(encoder, pipe_config); 1127 else if (IS_GEN9_BC(dev_priv)) 1128 skl_ddi_clock_get(encoder, pipe_config); 1129 else if (IS_GEN9_LP(dev_priv)) 1130 bxt_ddi_clock_get(encoder, pipe_config); 1131 } 1132 1133 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state) 1134 { 1135 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1136 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1137 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1138 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1139 int type = encoder->type; 1140 uint32_t temp; 1141 1142 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1143 WARN_ON(transcoder_is_dsi(cpu_transcoder)); 1144 1145 temp = TRANS_MSA_SYNC_CLK; 1146 switch (crtc_state->pipe_bpp) { 1147 case 18: 1148 temp |= TRANS_MSA_6_BPC; 1149 break; 1150 case 24: 1151 temp |= TRANS_MSA_8_BPC; 1152 break; 1153 case 30: 1154 temp |= TRANS_MSA_10_BPC; 1155 break; 1156 case 36: 1157 temp |= TRANS_MSA_12_BPC; 1158 break; 1159 default: 1160 BUG(); 1161 } 1162 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1163 } 1164 } 1165 1166 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 1167 bool state) 1168 { 1169 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1170 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1171 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1172 uint32_t temp; 1173 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1174 if (state == true) 1175 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1176 else 1177 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1178 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1179 } 1180 1181 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 1182 { 1183 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1184 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1185 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1186 enum i915_pipe pipe = crtc->pipe; 1187 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1188 enum port port = intel_ddi_get_encoder_port(encoder); 1189 int type = encoder->type; 1190 uint32_t temp; 1191 1192 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1193 temp = TRANS_DDI_FUNC_ENABLE; 1194 temp |= TRANS_DDI_SELECT_PORT(port); 1195 1196 switch (crtc_state->pipe_bpp) { 1197 case 18: 1198 temp |= TRANS_DDI_BPC_6; 1199 break; 1200 case 24: 1201 temp |= TRANS_DDI_BPC_8; 1202 break; 1203 case 30: 1204 temp |= TRANS_DDI_BPC_10; 1205 break; 1206 case 36: 1207 temp |= TRANS_DDI_BPC_12; 1208 break; 1209 default: 1210 BUG(); 1211 } 1212 1213 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1214 temp |= TRANS_DDI_PVSYNC; 1215 if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1216 temp |= TRANS_DDI_PHSYNC; 1217 1218 if (cpu_transcoder == TRANSCODER_EDP) { 1219 switch (pipe) { 1220 case PIPE_A: 1221 /* On Haswell, can only use the always-on power well for 1222 * eDP when not using the panel fitter, and when not 1223 * using motion blur mitigation (which we don't 1224 * support). */ 1225 if (IS_HASWELL(dev_priv) && 1226 (crtc_state->pch_pfit.enabled || 1227 crtc_state->pch_pfit.force_thru)) 1228 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1229 else 1230 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1231 break; 1232 case PIPE_B: 1233 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1234 break; 1235 case PIPE_C: 1236 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1237 break; 1238 default: 1239 BUG(); 1240 break; 1241 } 1242 } 1243 1244 if (type == INTEL_OUTPUT_HDMI) { 1245 if (crtc_state->has_hdmi_sink) 1246 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1247 else 1248 temp |= TRANS_DDI_MODE_SELECT_DVI; 1249 1250 if (crtc_state->hdmi_scrambling) 1251 temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK; 1252 if (crtc_state->hdmi_high_tmds_clock_ratio) 1253 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1254 } else if (type == INTEL_OUTPUT_ANALOG) { 1255 temp |= TRANS_DDI_MODE_SELECT_FDI; 1256 temp |= (crtc_state->fdi_lanes - 1) << 1; 1257 } else if (type == INTEL_OUTPUT_DP || 1258 type == INTEL_OUTPUT_EDP) { 1259 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1260 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1261 } else if (type == INTEL_OUTPUT_DP_MST) { 1262 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1263 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1264 } else { 1265 WARN(1, "Invalid encoder type %d for pipe %c\n", 1266 encoder->type, pipe_name(pipe)); 1267 } 1268 1269 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1270 } 1271 1272 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1273 enum transcoder cpu_transcoder) 1274 { 1275 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1276 uint32_t val = I915_READ(reg); 1277 1278 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1279 val |= TRANS_DDI_PORT_NONE; 1280 I915_WRITE(reg, val); 1281 } 1282 1283 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1284 { 1285 struct drm_device *dev = intel_connector->base.dev; 1286 struct drm_i915_private *dev_priv = to_i915(dev); 1287 struct intel_encoder *encoder = intel_connector->encoder; 1288 int type = intel_connector->base.connector_type; 1289 enum port port = intel_ddi_get_encoder_port(encoder); 1290 enum i915_pipe pipe = 0; 1291 enum transcoder cpu_transcoder; 1292 uint32_t tmp; 1293 bool ret; 1294 1295 if (!intel_display_power_get_if_enabled(dev_priv, 1296 encoder->power_domain)) 1297 return false; 1298 1299 if (!encoder->get_hw_state(encoder, &pipe)) { 1300 ret = false; 1301 goto out; 1302 } 1303 1304 if (port == PORT_A) 1305 cpu_transcoder = TRANSCODER_EDP; 1306 else 1307 cpu_transcoder = (enum transcoder) pipe; 1308 1309 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1310 1311 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1312 case TRANS_DDI_MODE_SELECT_HDMI: 1313 case TRANS_DDI_MODE_SELECT_DVI: 1314 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1315 break; 1316 1317 case TRANS_DDI_MODE_SELECT_DP_SST: 1318 ret = type == DRM_MODE_CONNECTOR_eDP || 1319 type == DRM_MODE_CONNECTOR_DisplayPort; 1320 break; 1321 1322 case TRANS_DDI_MODE_SELECT_DP_MST: 1323 /* if the transcoder is in MST state then 1324 * connector isn't connected */ 1325 ret = false; 1326 break; 1327 1328 case TRANS_DDI_MODE_SELECT_FDI: 1329 ret = type == DRM_MODE_CONNECTOR_VGA; 1330 break; 1331 1332 default: 1333 ret = false; 1334 break; 1335 } 1336 1337 out: 1338 intel_display_power_put(dev_priv, encoder->power_domain); 1339 1340 return ret; 1341 } 1342 1343 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1344 enum i915_pipe *pipe) 1345 { 1346 struct drm_device *dev = encoder->base.dev; 1347 struct drm_i915_private *dev_priv = to_i915(dev); 1348 enum port port = intel_ddi_get_encoder_port(encoder); 1349 u32 tmp; 1350 int i; 1351 bool ret; 1352 1353 if (!intel_display_power_get_if_enabled(dev_priv, 1354 encoder->power_domain)) 1355 return false; 1356 1357 ret = false; 1358 1359 tmp = I915_READ(DDI_BUF_CTL(port)); 1360 1361 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1362 goto out; 1363 1364 if (port == PORT_A) { 1365 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1366 1367 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1368 case TRANS_DDI_EDP_INPUT_A_ON: 1369 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1370 *pipe = PIPE_A; 1371 break; 1372 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1373 *pipe = PIPE_B; 1374 break; 1375 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1376 *pipe = PIPE_C; 1377 break; 1378 } 1379 1380 ret = true; 1381 1382 goto out; 1383 } 1384 1385 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 1386 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 1387 1388 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { 1389 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 1390 TRANS_DDI_MODE_SELECT_DP_MST) 1391 goto out; 1392 1393 *pipe = i; 1394 ret = true; 1395 1396 goto out; 1397 } 1398 } 1399 1400 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 1401 1402 out: 1403 if (ret && IS_GEN9_LP(dev_priv)) { 1404 tmp = I915_READ(BXT_PHY_CTL(port)); 1405 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK | 1406 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 1407 DRM_ERROR("Port %c enabled but PHY powered down? " 1408 "(PHY_CTL %08x)\n", port_name(port), tmp); 1409 } 1410 1411 intel_display_power_put(dev_priv, encoder->power_domain); 1412 1413 return ret; 1414 } 1415 1416 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder) 1417 { 1418 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 1419 enum i915_pipe pipe; 1420 1421 if (intel_ddi_get_hw_state(encoder, &pipe)) 1422 return BIT_ULL(dig_port->ddi_io_power_domain); 1423 1424 return 0; 1425 } 1426 1427 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 1428 { 1429 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1431 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc); 1432 enum port port = intel_ddi_get_encoder_port(encoder); 1433 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1434 1435 if (cpu_transcoder != TRANSCODER_EDP) 1436 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1437 TRANS_CLK_SEL_PORT(port)); 1438 } 1439 1440 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 1441 { 1442 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); 1443 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1444 1445 if (cpu_transcoder != TRANSCODER_EDP) 1446 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1447 TRANS_CLK_SEL_DISABLED); 1448 } 1449 1450 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1451 enum port port, uint8_t iboost) 1452 { 1453 u32 tmp; 1454 1455 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); 1456 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1457 if (iboost) 1458 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1459 else 1460 tmp |= BALANCE_LEG_DISABLE(port); 1461 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); 1462 } 1463 1464 static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level) 1465 { 1466 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 1467 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 1468 enum port port = intel_dig_port->port; 1469 int type = encoder->type; 1470 const struct ddi_buf_trans *ddi_translations; 1471 uint8_t iboost; 1472 uint8_t dp_iboost, hdmi_iboost; 1473 int n_entries; 1474 1475 /* VBT may override standard boost values */ 1476 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 1477 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 1478 1479 if (type == INTEL_OUTPUT_DP) { 1480 if (dp_iboost) { 1481 iboost = dp_iboost; 1482 } else { 1483 if (IS_KABYLAKE(dev_priv)) 1484 ddi_translations = kbl_get_buf_trans_dp(dev_priv, 1485 &n_entries); 1486 else 1487 ddi_translations = skl_get_buf_trans_dp(dev_priv, 1488 &n_entries); 1489 iboost = ddi_translations[level].i_boost; 1490 } 1491 } else if (type == INTEL_OUTPUT_EDP) { 1492 if (dp_iboost) { 1493 iboost = dp_iboost; 1494 } else { 1495 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); 1496 1497 if (WARN_ON(port != PORT_A && 1498 port != PORT_E && n_entries > 9)) 1499 n_entries = 9; 1500 1501 iboost = ddi_translations[level].i_boost; 1502 } 1503 } else if (type == INTEL_OUTPUT_HDMI) { 1504 if (hdmi_iboost) { 1505 iboost = hdmi_iboost; 1506 } else { 1507 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); 1508 iboost = ddi_translations[level].i_boost; 1509 } 1510 } else { 1511 return; 1512 } 1513 1514 /* Make sure that the requested I_boost is valid */ 1515 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1516 DRM_ERROR("Invalid I_boost value %u\n", iboost); 1517 return; 1518 } 1519 1520 _skl_ddi_set_iboost(dev_priv, port, iboost); 1521 1522 if (port == PORT_A && intel_dig_port->max_lanes == 4) 1523 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1524 } 1525 1526 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, 1527 u32 level, enum port port, int type) 1528 { 1529 const struct bxt_ddi_buf_trans *ddi_translations; 1530 u32 n_entries, i; 1531 1532 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 1533 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 1534 ddi_translations = bxt_ddi_translations_edp; 1535 } else if (type == INTEL_OUTPUT_DP 1536 || type == INTEL_OUTPUT_EDP) { 1537 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 1538 ddi_translations = bxt_ddi_translations_dp; 1539 } else if (type == INTEL_OUTPUT_HDMI) { 1540 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 1541 ddi_translations = bxt_ddi_translations_hdmi; 1542 } else { 1543 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 1544 type); 1545 return; 1546 } 1547 1548 /* Check if default value has to be used */ 1549 if (level >= n_entries || 1550 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 1551 for (i = 0; i < n_entries; i++) { 1552 if (ddi_translations[i].default_index) { 1553 level = i; 1554 break; 1555 } 1556 } 1557 } 1558 1559 bxt_ddi_phy_set_signal_level(dev_priv, port, 1560 ddi_translations[level].margin, 1561 ddi_translations[level].scale, 1562 ddi_translations[level].enable, 1563 ddi_translations[level].deemphasis); 1564 } 1565 1566 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 1567 { 1568 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1569 int n_entries; 1570 1571 if (encoder->type == INTEL_OUTPUT_EDP) 1572 intel_ddi_get_buf_trans_edp(dev_priv, &n_entries); 1573 else 1574 intel_ddi_get_buf_trans_dp(dev_priv, &n_entries); 1575 1576 if (WARN_ON(n_entries < 1)) 1577 n_entries = 1; 1578 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1579 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1580 1581 return index_to_dp_signal_levels[n_entries - 1] & 1582 DP_TRAIN_VOLTAGE_SWING_MASK; 1583 } 1584 1585 static uint32_t translate_signal_level(int signal_levels) 1586 { 1587 int i; 1588 1589 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1590 if (index_to_dp_signal_levels[i] == signal_levels) 1591 return i; 1592 } 1593 1594 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1595 signal_levels); 1596 1597 return 0; 1598 } 1599 1600 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 1601 { 1602 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1603 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 1604 struct intel_encoder *encoder = &dport->base; 1605 uint8_t train_set = intel_dp->train_set[0]; 1606 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1607 DP_TRAIN_PRE_EMPHASIS_MASK); 1608 enum port port = dport->port; 1609 uint32_t level; 1610 1611 level = translate_signal_level(signal_levels); 1612 1613 if (IS_GEN9_BC(dev_priv)) 1614 skl_ddi_set_iboost(encoder, level); 1615 else if (IS_GEN9_LP(dev_priv)) 1616 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); 1617 1618 return DDI_BUF_TRANS_SELECT(level); 1619 } 1620 1621 static void intel_ddi_clk_select(struct intel_encoder *encoder, 1622 struct intel_shared_dpll *pll) 1623 { 1624 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1625 enum port port = intel_ddi_get_encoder_port(encoder); 1626 1627 if (WARN_ON(!pll)) 1628 return; 1629 1630 if (IS_GEN9_BC(dev_priv)) { 1631 uint32_t val; 1632 1633 /* DDI -> PLL mapping */ 1634 val = I915_READ(DPLL_CTRL2); 1635 1636 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 1637 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 1638 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) | 1639 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1640 1641 I915_WRITE(DPLL_CTRL2, val); 1642 1643 } else if (INTEL_INFO(dev_priv)->gen < 9) { 1644 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1645 } 1646 } 1647 1648 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 1649 int link_rate, uint32_t lane_count, 1650 struct intel_shared_dpll *pll, 1651 bool link_mst) 1652 { 1653 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1654 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1655 enum port port = intel_ddi_get_encoder_port(encoder); 1656 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 1657 1658 WARN_ON(link_mst && (port == PORT_A || port == PORT_E)); 1659 1660 intel_dp_set_link_params(intel_dp, link_rate, lane_count, 1661 link_mst); 1662 if (encoder->type == INTEL_OUTPUT_EDP) 1663 intel_edp_panel_on(intel_dp); 1664 1665 intel_ddi_clk_select(encoder, pll); 1666 1667 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 1668 1669 intel_prepare_dp_ddi_buffers(encoder); 1670 intel_ddi_init_dp_buf_reg(encoder); 1671 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1672 intel_dp_start_link_train(intel_dp); 1673 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) 1674 intel_dp_stop_link_train(intel_dp); 1675 } 1676 1677 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 1678 bool has_hdmi_sink, 1679 const struct intel_crtc_state *crtc_state, 1680 const struct drm_connector_state *conn_state, 1681 struct intel_shared_dpll *pll) 1682 { 1683 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1684 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1685 struct drm_encoder *drm_encoder = &encoder->base; 1686 enum port port = intel_ddi_get_encoder_port(encoder); 1687 int level = intel_ddi_hdmi_level(dev_priv, port); 1688 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 1689 1690 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1691 intel_ddi_clk_select(encoder, pll); 1692 1693 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 1694 1695 intel_prepare_hdmi_ddi_buffers(encoder); 1696 if (IS_GEN9_BC(dev_priv)) 1697 skl_ddi_set_iboost(encoder, level); 1698 else if (IS_GEN9_LP(dev_priv)) 1699 bxt_ddi_vswing_sequence(dev_priv, level, port, 1700 INTEL_OUTPUT_HDMI); 1701 1702 intel_hdmi->set_infoframes(drm_encoder, 1703 has_hdmi_sink, 1704 crtc_state, conn_state); 1705 } 1706 1707 static void intel_ddi_pre_enable(struct intel_encoder *encoder, 1708 struct intel_crtc_state *pipe_config, 1709 struct drm_connector_state *conn_state) 1710 { 1711 int type = encoder->type; 1712 1713 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { 1714 intel_ddi_pre_enable_dp(encoder, 1715 pipe_config->port_clock, 1716 pipe_config->lane_count, 1717 pipe_config->shared_dpll, 1718 intel_crtc_has_type(pipe_config, 1719 INTEL_OUTPUT_DP_MST)); 1720 } 1721 if (type == INTEL_OUTPUT_HDMI) { 1722 intel_ddi_pre_enable_hdmi(encoder, 1723 pipe_config->has_hdmi_sink, 1724 pipe_config, conn_state, 1725 pipe_config->shared_dpll); 1726 } 1727 } 1728 1729 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, 1730 struct intel_crtc_state *old_crtc_state, 1731 struct drm_connector_state *old_conn_state) 1732 { 1733 struct drm_encoder *encoder = &intel_encoder->base; 1734 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 1735 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1736 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1737 int type = intel_encoder->type; 1738 uint32_t val; 1739 bool wait = false; 1740 1741 /* old_crtc_state and old_conn_state are NULL when called from DP_MST */ 1742 1743 val = I915_READ(DDI_BUF_CTL(port)); 1744 if (val & DDI_BUF_CTL_ENABLE) { 1745 val &= ~DDI_BUF_CTL_ENABLE; 1746 I915_WRITE(DDI_BUF_CTL(port), val); 1747 wait = true; 1748 } 1749 1750 val = I915_READ(DP_TP_CTL(port)); 1751 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1752 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1753 I915_WRITE(DP_TP_CTL(port), val); 1754 1755 if (wait) 1756 intel_wait_ddi_buf_idle(dev_priv, port); 1757 1758 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { 1759 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1760 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1761 intel_edp_panel_vdd_on(intel_dp); 1762 intel_edp_panel_off(intel_dp); 1763 } 1764 1765 if (dig_port) 1766 intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain); 1767 1768 if (IS_GEN9_BC(dev_priv)) 1769 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 1770 DPLL_CTRL2_DDI_CLK_OFF(port))); 1771 else if (INTEL_GEN(dev_priv) < 9) 1772 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1773 1774 if (type == INTEL_OUTPUT_HDMI) { 1775 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1776 1777 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 1778 } 1779 } 1780 1781 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, 1782 struct intel_crtc_state *old_crtc_state, 1783 struct drm_connector_state *old_conn_state) 1784 { 1785 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1786 uint32_t val; 1787 1788 /* 1789 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 1790 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 1791 * step 13 is the correct place for it. Step 18 is where it was 1792 * originally before the BUN. 1793 */ 1794 val = I915_READ(FDI_RX_CTL(PIPE_A)); 1795 val &= ~FDI_RX_ENABLE; 1796 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 1797 1798 intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state); 1799 1800 val = I915_READ(FDI_RX_MISC(PIPE_A)); 1801 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1802 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1803 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 1804 1805 val = I915_READ(FDI_RX_CTL(PIPE_A)); 1806 val &= ~FDI_PCDCLK; 1807 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 1808 1809 val = I915_READ(FDI_RX_CTL(PIPE_A)); 1810 val &= ~FDI_RX_PLL_ENABLE; 1811 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 1812 } 1813 1814 static void intel_enable_ddi(struct intel_encoder *intel_encoder, 1815 struct intel_crtc_state *pipe_config, 1816 struct drm_connector_state *conn_state) 1817 { 1818 struct drm_encoder *encoder = &intel_encoder->base; 1819 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 1820 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1821 int type = intel_encoder->type; 1822 1823 if (type == INTEL_OUTPUT_HDMI) { 1824 struct intel_digital_port *intel_dig_port = 1825 enc_to_dig_port(encoder); 1826 bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio; 1827 bool scrambling = pipe_config->hdmi_scrambling; 1828 1829 intel_hdmi_handle_sink_scrambling(intel_encoder, 1830 conn_state->connector, 1831 clock_ratio, scrambling); 1832 1833 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1834 * are ignored so nothing special needs to be done besides 1835 * enabling the port. 1836 */ 1837 I915_WRITE(DDI_BUF_CTL(port), 1838 intel_dig_port->saved_port_bits | 1839 DDI_BUF_CTL_ENABLE); 1840 } else if (type == INTEL_OUTPUT_EDP) { 1841 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1842 1843 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 1844 intel_dp_stop_link_train(intel_dp); 1845 1846 intel_edp_backlight_on(intel_dp); 1847 intel_psr_enable(intel_dp); 1848 intel_edp_drrs_enable(intel_dp, pipe_config); 1849 } 1850 1851 if (pipe_config->has_audio) 1852 intel_audio_codec_enable(intel_encoder, pipe_config, conn_state); 1853 } 1854 1855 static void intel_disable_ddi(struct intel_encoder *intel_encoder, 1856 struct intel_crtc_state *old_crtc_state, 1857 struct drm_connector_state *old_conn_state) 1858 { 1859 struct drm_encoder *encoder = &intel_encoder->base; 1860 int type = intel_encoder->type; 1861 1862 if (old_crtc_state->has_audio) 1863 intel_audio_codec_disable(intel_encoder); 1864 1865 if (type == INTEL_OUTPUT_HDMI) { 1866 intel_hdmi_handle_sink_scrambling(intel_encoder, 1867 old_conn_state->connector, 1868 false, false); 1869 } 1870 1871 if (type == INTEL_OUTPUT_EDP) { 1872 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1873 1874 intel_edp_drrs_disable(intel_dp, old_crtc_state); 1875 intel_psr_disable(intel_dp); 1876 intel_edp_backlight_off(intel_dp); 1877 } 1878 } 1879 1880 static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, 1881 struct intel_crtc_state *pipe_config, 1882 struct drm_connector_state *conn_state) 1883 { 1884 uint8_t mask = pipe_config->lane_lat_optim_mask; 1885 1886 bxt_ddi_phy_set_lane_optim_mask(encoder, mask); 1887 } 1888 1889 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 1890 { 1891 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1892 struct drm_i915_private *dev_priv = 1893 to_i915(intel_dig_port->base.base.dev); 1894 enum port port = intel_dig_port->port; 1895 uint32_t val; 1896 bool wait = false; 1897 1898 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 1899 val = I915_READ(DDI_BUF_CTL(port)); 1900 if (val & DDI_BUF_CTL_ENABLE) { 1901 val &= ~DDI_BUF_CTL_ENABLE; 1902 I915_WRITE(DDI_BUF_CTL(port), val); 1903 wait = true; 1904 } 1905 1906 val = I915_READ(DP_TP_CTL(port)); 1907 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1908 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1909 I915_WRITE(DP_TP_CTL(port), val); 1910 POSTING_READ(DP_TP_CTL(port)); 1911 1912 if (wait) 1913 intel_wait_ddi_buf_idle(dev_priv, port); 1914 } 1915 1916 val = DP_TP_CTL_ENABLE | 1917 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 1918 if (intel_dp->link_mst) 1919 val |= DP_TP_CTL_MODE_MST; 1920 else { 1921 val |= DP_TP_CTL_MODE_SST; 1922 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1923 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 1924 } 1925 I915_WRITE(DP_TP_CTL(port), val); 1926 POSTING_READ(DP_TP_CTL(port)); 1927 1928 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 1929 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 1930 POSTING_READ(DDI_BUF_CTL(port)); 1931 1932 udelay(600); 1933 } 1934 1935 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 1936 struct intel_crtc *intel_crtc) 1937 { 1938 u32 temp; 1939 1940 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 1941 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 1942 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 1943 return true; 1944 } 1945 return false; 1946 } 1947 1948 void intel_ddi_get_config(struct intel_encoder *encoder, 1949 struct intel_crtc_state *pipe_config) 1950 { 1951 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1952 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1953 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1954 struct intel_hdmi *intel_hdmi; 1955 u32 temp, flags = 0; 1956 1957 /* XXX: DSI transcoder paranoia */ 1958 if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) 1959 return; 1960 1961 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1962 if (temp & TRANS_DDI_PHSYNC) 1963 flags |= DRM_MODE_FLAG_PHSYNC; 1964 else 1965 flags |= DRM_MODE_FLAG_NHSYNC; 1966 if (temp & TRANS_DDI_PVSYNC) 1967 flags |= DRM_MODE_FLAG_PVSYNC; 1968 else 1969 flags |= DRM_MODE_FLAG_NVSYNC; 1970 1971 pipe_config->base.adjusted_mode.flags |= flags; 1972 1973 switch (temp & TRANS_DDI_BPC_MASK) { 1974 case TRANS_DDI_BPC_6: 1975 pipe_config->pipe_bpp = 18; 1976 break; 1977 case TRANS_DDI_BPC_8: 1978 pipe_config->pipe_bpp = 24; 1979 break; 1980 case TRANS_DDI_BPC_10: 1981 pipe_config->pipe_bpp = 30; 1982 break; 1983 case TRANS_DDI_BPC_12: 1984 pipe_config->pipe_bpp = 36; 1985 break; 1986 default: 1987 break; 1988 } 1989 1990 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 1991 case TRANS_DDI_MODE_SELECT_HDMI: 1992 pipe_config->has_hdmi_sink = true; 1993 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1994 1995 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 1996 pipe_config->has_infoframe = true; 1997 1998 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) == 1999 TRANS_DDI_HDMI_SCRAMBLING_MASK) 2000 pipe_config->hdmi_scrambling = true; 2001 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 2002 pipe_config->hdmi_high_tmds_clock_ratio = true; 2003 /* fall through */ 2004 case TRANS_DDI_MODE_SELECT_DVI: 2005 pipe_config->lane_count = 4; 2006 break; 2007 case TRANS_DDI_MODE_SELECT_FDI: 2008 break; 2009 case TRANS_DDI_MODE_SELECT_DP_SST: 2010 case TRANS_DDI_MODE_SELECT_DP_MST: 2011 pipe_config->lane_count = 2012 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 2013 intel_dp_get_m_n(intel_crtc, pipe_config); 2014 break; 2015 default: 2016 break; 2017 } 2018 2019 pipe_config->has_audio = 2020 intel_ddi_is_audio_enabled(dev_priv, intel_crtc); 2021 2022 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 2023 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 2024 /* 2025 * This is a big fat ugly hack. 2026 * 2027 * Some machines in UEFI boot mode provide us a VBT that has 18 2028 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 2029 * unknown we fail to light up. Yet the same BIOS boots up with 2030 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 2031 * max, not what it tells us to use. 2032 * 2033 * Note: This will still be broken if the eDP panel is not lit 2034 * up by the BIOS, and thus we can't get the mode at module 2035 * load. 2036 */ 2037 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 2038 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 2039 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 2040 } 2041 2042 intel_ddi_clock_get(encoder, pipe_config); 2043 2044 if (IS_GEN9_LP(dev_priv)) 2045 pipe_config->lane_lat_optim_mask = 2046 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 2047 } 2048 2049 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 2050 struct intel_crtc_state *pipe_config, 2051 struct drm_connector_state *conn_state) 2052 { 2053 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2054 int type = encoder->type; 2055 int port = intel_ddi_get_encoder_port(encoder); 2056 int ret; 2057 2058 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 2059 2060 if (port == PORT_A) 2061 pipe_config->cpu_transcoder = TRANSCODER_EDP; 2062 2063 if (type == INTEL_OUTPUT_HDMI) 2064 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 2065 else 2066 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 2067 2068 if (IS_GEN9_LP(dev_priv) && ret) 2069 pipe_config->lane_lat_optim_mask = 2070 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder, 2071 pipe_config->lane_count); 2072 2073 return ret; 2074 2075 } 2076 2077 static const struct drm_encoder_funcs intel_ddi_funcs = { 2078 .reset = intel_dp_encoder_reset, 2079 .destroy = intel_dp_encoder_destroy, 2080 }; 2081 2082 static struct intel_connector * 2083 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 2084 { 2085 struct intel_connector *connector; 2086 enum port port = intel_dig_port->port; 2087 2088 connector = intel_connector_alloc(); 2089 if (!connector) 2090 return NULL; 2091 2092 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 2093 if (!intel_dp_init_connector(intel_dig_port, connector)) { 2094 kfree(connector); 2095 return NULL; 2096 } 2097 2098 return connector; 2099 } 2100 2101 static struct intel_connector * 2102 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 2103 { 2104 struct intel_connector *connector; 2105 enum port port = intel_dig_port->port; 2106 2107 connector = intel_connector_alloc(); 2108 if (!connector) 2109 return NULL; 2110 2111 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 2112 intel_hdmi_init_connector(intel_dig_port, connector); 2113 2114 return connector; 2115 } 2116 2117 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 2118 { 2119 struct intel_digital_port *intel_dig_port; 2120 struct intel_encoder *intel_encoder; 2121 struct drm_encoder *encoder; 2122 bool init_hdmi, init_dp, init_lspcon = false; 2123 int max_lanes; 2124 2125 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { 2126 switch (port) { 2127 case PORT_A: 2128 max_lanes = 4; 2129 break; 2130 case PORT_E: 2131 max_lanes = 0; 2132 break; 2133 default: 2134 max_lanes = 4; 2135 break; 2136 } 2137 } else { 2138 switch (port) { 2139 case PORT_A: 2140 max_lanes = 2; 2141 break; 2142 case PORT_E: 2143 max_lanes = 2; 2144 break; 2145 default: 2146 max_lanes = 4; 2147 break; 2148 } 2149 } 2150 2151 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 2152 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 2153 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 2154 2155 if (intel_bios_is_lspcon_present(dev_priv, port)) { 2156 /* 2157 * Lspcon device needs to be driven with DP connector 2158 * with special detection sequence. So make sure DP 2159 * is initialized before lspcon. 2160 */ 2161 init_dp = true; 2162 init_lspcon = true; 2163 init_hdmi = false; 2164 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); 2165 } 2166 2167 if (!init_dp && !init_hdmi) { 2168 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 2169 port_name(port)); 2170 return; 2171 } 2172 2173 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 2174 if (!intel_dig_port) 2175 return; 2176 2177 intel_encoder = &intel_dig_port->base; 2178 encoder = &intel_encoder->base; 2179 2180 drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs, 2181 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 2182 2183 intel_encoder->compute_config = intel_ddi_compute_config; 2184 intel_encoder->enable = intel_enable_ddi; 2185 if (IS_GEN9_LP(dev_priv)) 2186 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable; 2187 intel_encoder->pre_enable = intel_ddi_pre_enable; 2188 intel_encoder->disable = intel_disable_ddi; 2189 intel_encoder->post_disable = intel_ddi_post_disable; 2190 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 2191 intel_encoder->get_config = intel_ddi_get_config; 2192 intel_encoder->suspend = intel_dp_encoder_suspend; 2193 intel_encoder->get_power_domains = intel_ddi_get_power_domains; 2194 2195 intel_dig_port->port = port; 2196 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 2197 (DDI_BUF_PORT_REVERSAL | 2198 DDI_A_4_LANES); 2199 2200 switch (port) { 2201 case PORT_A: 2202 intel_dig_port->ddi_io_power_domain = 2203 POWER_DOMAIN_PORT_DDI_A_IO; 2204 break; 2205 case PORT_B: 2206 intel_dig_port->ddi_io_power_domain = 2207 POWER_DOMAIN_PORT_DDI_B_IO; 2208 break; 2209 case PORT_C: 2210 intel_dig_port->ddi_io_power_domain = 2211 POWER_DOMAIN_PORT_DDI_C_IO; 2212 break; 2213 case PORT_D: 2214 intel_dig_port->ddi_io_power_domain = 2215 POWER_DOMAIN_PORT_DDI_D_IO; 2216 break; 2217 case PORT_E: 2218 intel_dig_port->ddi_io_power_domain = 2219 POWER_DOMAIN_PORT_DDI_E_IO; 2220 break; 2221 default: 2222 MISSING_CASE(port); 2223 } 2224 2225 /* 2226 * Bspec says that DDI_A_4_LANES is the only supported configuration 2227 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP 2228 * wasn't lit up at boot. Force this bit on in our internal 2229 * configuration so that we use the proper lane count for our 2230 * calculations. 2231 */ 2232 if (IS_GEN9_LP(dev_priv) && port == PORT_A) { 2233 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { 2234 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); 2235 intel_dig_port->saved_port_bits |= DDI_A_4_LANES; 2236 max_lanes = 4; 2237 } 2238 } 2239 2240 intel_dig_port->max_lanes = max_lanes; 2241 2242 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 2243 intel_encoder->power_domain = intel_port_to_power_domain(port); 2244 intel_encoder->port = port; 2245 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2246 intel_encoder->cloneable = 0; 2247 2248 if (init_dp) { 2249 if (!intel_ddi_init_dp_connector(intel_dig_port)) 2250 goto err; 2251 2252 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 2253 dev_priv->hotplug.irq_port[port] = intel_dig_port; 2254 } 2255 2256 /* In theory we don't need the encoder->type check, but leave it just in 2257 * case we have some really bad VBTs... */ 2258 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 2259 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 2260 goto err; 2261 } 2262 2263 if (init_lspcon) { 2264 if (lspcon_init(intel_dig_port)) 2265 /* TODO: handle hdmi info frame part */ 2266 DRM_DEBUG_KMS("LSPCON init success on port %c\n", 2267 port_name(port)); 2268 else 2269 /* 2270 * LSPCON init faied, but DP init was success, so 2271 * lets try to drive as DP++ port. 2272 */ 2273 DRM_ERROR("LSPCON init failed on port %c\n", 2274 port_name(port)); 2275 } 2276 2277 return; 2278 2279 err: 2280 drm_encoder_cleanup(encoder); 2281 kfree(intel_dig_port); 2282 } 2283