1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 36 }; 37 38 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 39 * them for both DP and FDI transports, allowing those ports to 40 * automatically adapt to HDMI connections as well 41 */ 42 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 43 { 0x00FFFFFF, 0x0006000E, 0x0 }, 44 { 0x00D75FFF, 0x0005000A, 0x0 }, 45 { 0x00C30FFF, 0x00040006, 0x0 }, 46 { 0x80AAAFFF, 0x000B0000, 0x0 }, 47 { 0x00FFFFFF, 0x0005000A, 0x0 }, 48 { 0x00D75FFF, 0x000C0004, 0x0 }, 49 { 0x80C30FFF, 0x000B0000, 0x0 }, 50 { 0x00FFFFFF, 0x00040006, 0x0 }, 51 { 0x80D75FFF, 0x000B0000, 0x0 }, 52 }; 53 54 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 55 { 0x00FFFFFF, 0x0007000E, 0x0 }, 56 { 0x00D75FFF, 0x000F000A, 0x0 }, 57 { 0x00C30FFF, 0x00060006, 0x0 }, 58 { 0x00AAAFFF, 0x001E0000, 0x0 }, 59 { 0x00FFFFFF, 0x000F000A, 0x0 }, 60 { 0x00D75FFF, 0x00160004, 0x0 }, 61 { 0x00C30FFF, 0x001E0000, 0x0 }, 62 { 0x00FFFFFF, 0x00060006, 0x0 }, 63 { 0x00D75FFF, 0x001E0000, 0x0 }, 64 }; 65 66 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 67 /* Idx NT mV d T mV d db */ 68 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 69 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 70 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 71 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 72 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 73 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 74 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 75 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 76 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 77 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 78 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 79 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 80 }; 81 82 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 83 { 0x00FFFFFF, 0x00000012, 0x0 }, 84 { 0x00EBAFFF, 0x00020011, 0x0 }, 85 { 0x00C71FFF, 0x0006000F, 0x0 }, 86 { 0x00AAAFFF, 0x000E000A, 0x0 }, 87 { 0x00FFFFFF, 0x00020011, 0x0 }, 88 { 0x00DB6FFF, 0x0005000F, 0x0 }, 89 { 0x00BEEFFF, 0x000A000C, 0x0 }, 90 { 0x00FFFFFF, 0x0005000F, 0x0 }, 91 { 0x00DB6FFF, 0x000A000C, 0x0 }, 92 }; 93 94 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 95 { 0x00FFFFFF, 0x0007000E, 0x0 }, 96 { 0x00D75FFF, 0x000E000A, 0x0 }, 97 { 0x00BEFFFF, 0x00140006, 0x0 }, 98 { 0x80B2CFFF, 0x001B0002, 0x0 }, 99 { 0x00FFFFFF, 0x000E000A, 0x0 }, 100 { 0x00DB6FFF, 0x00160005, 0x0 }, 101 { 0x80C71FFF, 0x001A0002, 0x0 }, 102 { 0x00F7DFFF, 0x00180004, 0x0 }, 103 { 0x80D75FFF, 0x001B0002, 0x0 }, 104 }; 105 106 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 107 { 0x00FFFFFF, 0x0001000E, 0x0 }, 108 { 0x00D75FFF, 0x0004000A, 0x0 }, 109 { 0x00C30FFF, 0x00070006, 0x0 }, 110 { 0x00AAAFFF, 0x000C0000, 0x0 }, 111 { 0x00FFFFFF, 0x0004000A, 0x0 }, 112 { 0x00D75FFF, 0x00090004, 0x0 }, 113 { 0x00C30FFF, 0x000C0000, 0x0 }, 114 { 0x00FFFFFF, 0x00070006, 0x0 }, 115 { 0x00D75FFF, 0x000C0000, 0x0 }, 116 }; 117 118 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 119 /* Idx NT mV d T mV df db */ 120 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 121 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 122 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 123 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 124 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 125 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 126 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 127 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 128 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 129 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 130 }; 131 132 /* Skylake H and S */ 133 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 134 { 0x00002016, 0x000000A0, 0x0 }, 135 { 0x00005012, 0x0000009B, 0x0 }, 136 { 0x00007011, 0x00000088, 0x0 }, 137 { 0x80009010, 0x000000C0, 0x1 }, 138 { 0x00002016, 0x0000009B, 0x0 }, 139 { 0x00005012, 0x00000088, 0x0 }, 140 { 0x80007011, 0x000000C0, 0x1 }, 141 { 0x00002016, 0x000000DF, 0x0 }, 142 { 0x80005012, 0x000000C0, 0x1 }, 143 }; 144 145 /* Skylake U */ 146 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 147 { 0x0000201B, 0x000000A2, 0x0 }, 148 { 0x00005012, 0x00000088, 0x0 }, 149 { 0x80007011, 0x000000CD, 0x0 }, 150 { 0x80009010, 0x000000C0, 0x1 }, 151 { 0x0000201B, 0x0000009D, 0x0 }, 152 { 0x80005012, 0x000000C0, 0x1 }, 153 { 0x80007011, 0x000000C0, 0x1 }, 154 { 0x00002016, 0x00000088, 0x0 }, 155 { 0x80005012, 0x000000C0, 0x1 }, 156 }; 157 158 /* Skylake Y */ 159 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 160 { 0x00000018, 0x000000A2, 0x0 }, 161 { 0x00005012, 0x00000088, 0x0 }, 162 { 0x80007011, 0x000000CD, 0x0 }, 163 { 0x80009010, 0x000000C0, 0x3 }, 164 { 0x00000018, 0x0000009D, 0x0 }, 165 { 0x80005012, 0x000000C0, 0x3 }, 166 { 0x80007011, 0x000000C0, 0x3 }, 167 { 0x00000018, 0x00000088, 0x0 }, 168 { 0x80005012, 0x000000C0, 0x3 }, 169 }; 170 171 /* 172 * Skylake H and S 173 * eDP 1.4 low vswing translation parameters 174 */ 175 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 176 { 0x00000018, 0x000000A8, 0x0 }, 177 { 0x00004013, 0x000000A9, 0x0 }, 178 { 0x00007011, 0x000000A2, 0x0 }, 179 { 0x00009010, 0x0000009C, 0x0 }, 180 { 0x00000018, 0x000000A9, 0x0 }, 181 { 0x00006013, 0x000000A2, 0x0 }, 182 { 0x00007011, 0x000000A6, 0x0 }, 183 { 0x00000018, 0x000000AB, 0x0 }, 184 { 0x00007013, 0x0000009F, 0x0 }, 185 { 0x00000018, 0x000000DF, 0x0 }, 186 }; 187 188 /* 189 * Skylake U 190 * eDP 1.4 low vswing translation parameters 191 */ 192 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 193 { 0x00000018, 0x000000A8, 0x0 }, 194 { 0x00004013, 0x000000A9, 0x0 }, 195 { 0x00007011, 0x000000A2, 0x0 }, 196 { 0x00009010, 0x0000009C, 0x0 }, 197 { 0x00000018, 0x000000A9, 0x0 }, 198 { 0x00006013, 0x000000A2, 0x0 }, 199 { 0x00007011, 0x000000A6, 0x0 }, 200 { 0x00002016, 0x000000AB, 0x0 }, 201 { 0x00005013, 0x0000009F, 0x0 }, 202 { 0x00000018, 0x000000DF, 0x0 }, 203 }; 204 205 /* 206 * Skylake Y 207 * eDP 1.4 low vswing translation parameters 208 */ 209 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 210 { 0x00000018, 0x000000A8, 0x0 }, 211 { 0x00004013, 0x000000AB, 0x0 }, 212 { 0x00007011, 0x000000A4, 0x0 }, 213 { 0x00009010, 0x000000DF, 0x0 }, 214 { 0x00000018, 0x000000AA, 0x0 }, 215 { 0x00006013, 0x000000A4, 0x0 }, 216 { 0x00007011, 0x0000009D, 0x0 }, 217 { 0x00000018, 0x000000A0, 0x0 }, 218 { 0x00006012, 0x000000DF, 0x0 }, 219 { 0x00000018, 0x0000008A, 0x0 }, 220 }; 221 222 /* Skylake U, H and S */ 223 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 224 { 0x00000018, 0x000000AC, 0x0 }, 225 { 0x00005012, 0x0000009D, 0x0 }, 226 { 0x00007011, 0x00000088, 0x0 }, 227 { 0x00000018, 0x000000A1, 0x0 }, 228 { 0x00000018, 0x00000098, 0x0 }, 229 { 0x00004013, 0x00000088, 0x0 }, 230 { 0x80006012, 0x000000CD, 0x1 }, 231 { 0x00000018, 0x000000DF, 0x0 }, 232 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 233 { 0x80003015, 0x000000C0, 0x1 }, 234 { 0x80000018, 0x000000C0, 0x1 }, 235 }; 236 237 /* Skylake Y */ 238 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 239 { 0x00000018, 0x000000A1, 0x0 }, 240 { 0x00005012, 0x000000DF, 0x0 }, 241 { 0x80007011, 0x000000CB, 0x3 }, 242 { 0x00000018, 0x000000A4, 0x0 }, 243 { 0x00000018, 0x0000009D, 0x0 }, 244 { 0x00004013, 0x00000080, 0x0 }, 245 { 0x80006013, 0x000000C0, 0x3 }, 246 { 0x00000018, 0x0000008A, 0x0 }, 247 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 248 { 0x80003015, 0x000000C0, 0x3 }, 249 { 0x80000018, 0x000000C0, 0x3 }, 250 }; 251 252 struct bxt_ddi_buf_trans { 253 u32 margin; /* swing value */ 254 u32 scale; /* scale value */ 255 u32 enable; /* scale enable */ 256 u32 deemphasis; 257 bool default_index; /* true if the entry represents default value */ 258 }; 259 260 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 261 /* Idx NT mV diff db */ 262 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ 263 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 264 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ 265 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 266 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 267 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 268 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ 269 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 270 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 271 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 272 }; 273 274 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 275 /* Idx NT mV diff db */ 276 { 26, 0, 0, 128, false }, /* 0: 200 0 */ 277 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ 278 { 48, 0, 0, 96, false }, /* 2: 200 4 */ 279 { 54, 0, 0, 69, false }, /* 3: 200 6 */ 280 { 32, 0, 0, 128, false }, /* 4: 250 0 */ 281 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ 282 { 54, 0, 0, 85, false }, /* 6: 250 4 */ 283 { 43, 0, 0, 128, false }, /* 7: 300 0 */ 284 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ 285 { 48, 0, 0, 128, false }, /* 9: 300 0 */ 286 }; 287 288 /* BSpec has 2 recommended values - entries 0 and 8. 289 * Using the entry with higher vswing. 290 */ 291 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 292 /* Idx NT mV diff db */ 293 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ 294 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 295 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ 296 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 297 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 298 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 299 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ 300 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 301 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 302 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 303 }; 304 305 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, 306 u32 level, enum port port, int type); 307 308 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, 309 struct intel_digital_port **dig_port, 310 enum port *port) 311 { 312 struct drm_encoder *encoder = &intel_encoder->base; 313 314 *dig_port = 0; /* silence gcc warnings */ 315 *port = 0; /* silence gcc warnings */ 316 317 switch (intel_encoder->type) { 318 case INTEL_OUTPUT_DP_MST: 319 *dig_port = enc_to_mst(encoder)->primary; 320 *port = (*dig_port)->port; 321 break; 322 case INTEL_OUTPUT_DISPLAYPORT: 323 case INTEL_OUTPUT_EDP: 324 case INTEL_OUTPUT_HDMI: 325 case INTEL_OUTPUT_UNKNOWN: 326 *dig_port = enc_to_dig_port(encoder); 327 *port = (*dig_port)->port; 328 break; 329 case INTEL_OUTPUT_ANALOG: 330 *dig_port = NULL; 331 *port = PORT_E; 332 break; 333 default: 334 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type); 335 break; 336 } 337 } 338 339 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 340 { 341 struct intel_digital_port *dig_port; 342 enum port port; 343 344 ddi_get_encoder_port(intel_encoder, &dig_port, &port); 345 346 return port; 347 } 348 349 static const struct ddi_buf_trans * 350 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) 351 { 352 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 353 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 354 return skl_y_ddi_translations_dp; 355 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { 356 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 357 return skl_u_ddi_translations_dp; 358 } else { 359 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 360 return skl_ddi_translations_dp; 361 } 362 } 363 364 static const struct ddi_buf_trans * 365 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) 366 { 367 if (dev_priv->edp_low_vswing) { 368 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 369 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 370 return skl_y_ddi_translations_edp; 371 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { 372 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 373 return skl_u_ddi_translations_edp; 374 } else { 375 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 376 return skl_ddi_translations_edp; 377 } 378 } 379 380 return skl_get_buf_trans_dp(dev_priv, n_entries); 381 } 382 383 static const struct ddi_buf_trans * 384 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 385 { 386 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { 387 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 388 return skl_y_ddi_translations_hdmi; 389 } else { 390 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 391 return skl_ddi_translations_hdmi; 392 } 393 } 394 395 /* 396 * Starting with Haswell, DDI port buffers must be programmed with correct 397 * values in advance. The buffer values are different for FDI and DP modes, 398 * but the HDMI/DVI fields are shared among those. So we program the DDI 399 * in either FDI or DP modes only, as HDMI connections will work with both 400 * of those 401 */ 402 void intel_prepare_ddi_buffer(struct intel_encoder *encoder) 403 { 404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 405 u32 iboost_bit = 0; 406 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 407 size; 408 int hdmi_level; 409 enum port port; 410 const struct ddi_buf_trans *ddi_translations_fdi; 411 const struct ddi_buf_trans *ddi_translations_dp; 412 const struct ddi_buf_trans *ddi_translations_edp; 413 const struct ddi_buf_trans *ddi_translations_hdmi; 414 const struct ddi_buf_trans *ddi_translations; 415 416 port = intel_ddi_get_encoder_port(encoder); 417 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 418 419 if (IS_BROXTON(dev_priv)) { 420 if (encoder->type != INTEL_OUTPUT_HDMI) 421 return; 422 423 /* Vswing programming for HDMI */ 424 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port, 425 INTEL_OUTPUT_HDMI); 426 return; 427 } 428 429 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 430 ddi_translations_fdi = NULL; 431 ddi_translations_dp = 432 skl_get_buf_trans_dp(dev_priv, &n_dp_entries); 433 ddi_translations_edp = 434 skl_get_buf_trans_edp(dev_priv, &n_edp_entries); 435 ddi_translations_hdmi = 436 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 437 hdmi_default_entry = 8; 438 /* If we're boosting the current, set bit 31 of trans1 */ 439 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || 440 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 441 iboost_bit = 1<<31; 442 443 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && 444 port != PORT_A && port != PORT_E && 445 n_edp_entries > 9)) 446 n_edp_entries = 9; 447 } else if (IS_BROADWELL(dev_priv)) { 448 ddi_translations_fdi = bdw_ddi_translations_fdi; 449 ddi_translations_dp = bdw_ddi_translations_dp; 450 451 if (dev_priv->edp_low_vswing) { 452 ddi_translations_edp = bdw_ddi_translations_edp; 453 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 454 } else { 455 ddi_translations_edp = bdw_ddi_translations_dp; 456 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 457 } 458 459 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 460 461 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 462 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 463 hdmi_default_entry = 7; 464 } else if (IS_HASWELL(dev_priv)) { 465 ddi_translations_fdi = hsw_ddi_translations_fdi; 466 ddi_translations_dp = hsw_ddi_translations_dp; 467 ddi_translations_edp = hsw_ddi_translations_dp; 468 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 469 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 470 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 471 hdmi_default_entry = 6; 472 } else { 473 WARN(1, "ddi translation table missing\n"); 474 ddi_translations_edp = bdw_ddi_translations_dp; 475 ddi_translations_fdi = bdw_ddi_translations_fdi; 476 ddi_translations_dp = bdw_ddi_translations_dp; 477 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 478 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 479 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 480 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 481 hdmi_default_entry = 7; 482 } 483 484 switch (encoder->type) { 485 case INTEL_OUTPUT_EDP: 486 ddi_translations = ddi_translations_edp; 487 size = n_edp_entries; 488 break; 489 case INTEL_OUTPUT_DISPLAYPORT: 490 case INTEL_OUTPUT_HDMI: 491 ddi_translations = ddi_translations_dp; 492 size = n_dp_entries; 493 break; 494 case INTEL_OUTPUT_ANALOG: 495 ddi_translations = ddi_translations_fdi; 496 size = n_dp_entries; 497 break; 498 default: 499 BUG(); 500 } 501 502 for (i = 0; i < size; i++) { 503 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 504 ddi_translations[i].trans1 | iboost_bit); 505 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 506 ddi_translations[i].trans2); 507 } 508 509 if (encoder->type != INTEL_OUTPUT_HDMI) 510 return; 511 512 /* Choose a good default if VBT is badly populated */ 513 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 514 hdmi_level >= n_hdmi_entries) 515 hdmi_level = hdmi_default_entry; 516 517 /* Entry 9 is for HDMI: */ 518 I915_WRITE(DDI_BUF_TRANS_LO(port, i), 519 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); 520 I915_WRITE(DDI_BUF_TRANS_HI(port, i), 521 ddi_translations_hdmi[hdmi_level].trans2); 522 } 523 524 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 525 enum port port) 526 { 527 i915_reg_t reg = DDI_BUF_CTL(port); 528 int i; 529 530 for (i = 0; i < 16; i++) { 531 udelay(1); 532 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 533 return; 534 } 535 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 536 } 537 538 /* Starting with Haswell, different DDI ports can work in FDI mode for 539 * connection to the PCH-located connectors. For this, it is necessary to train 540 * both the DDI port and PCH receiver for the desired DDI buffer settings. 541 * 542 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 543 * please note that when FDI mode is active on DDI E, it shares 2 lines with 544 * DDI A (which is used for eDP) 545 */ 546 547 void hsw_fdi_link_train(struct drm_crtc *crtc) 548 { 549 struct drm_device *dev = crtc->dev; 550 struct drm_i915_private *dev_priv = dev->dev_private; 551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 552 struct intel_encoder *encoder; 553 u32 temp, i, rx_ctl_val; 554 555 for_each_encoder_on_crtc(dev, crtc, encoder) { 556 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); 557 intel_prepare_ddi_buffer(encoder); 558 } 559 560 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 561 * mode set "sequence for CRT port" document: 562 * - TP1 to TP2 time with the default value 563 * - FDI delay to 90h 564 * 565 * WaFDIAutoLinkSetTimingOverrride:hsw 566 */ 567 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | 568 FDI_RX_PWRDN_LANE0_VAL(2) | 569 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 570 571 /* Enable the PCH Receiver FDI PLL */ 572 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 573 FDI_RX_PLL_ENABLE | 574 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 575 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 576 POSTING_READ(FDI_RX_CTL(PIPE_A)); 577 udelay(220); 578 579 /* Switch from Rawclk to PCDclk */ 580 rx_ctl_val |= FDI_PCDCLK; 581 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 582 583 /* Configure Port Clock Select */ 584 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 585 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 586 587 /* Start the training iterating through available voltages and emphasis, 588 * testing each value twice. */ 589 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 590 /* Configure DP_TP_CTL with auto-training */ 591 I915_WRITE(DP_TP_CTL(PORT_E), 592 DP_TP_CTL_FDI_AUTOTRAIN | 593 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 594 DP_TP_CTL_LINK_TRAIN_PAT1 | 595 DP_TP_CTL_ENABLE); 596 597 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 598 * DDI E does not support port reversal, the functionality is 599 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 600 * port reversal bit */ 601 I915_WRITE(DDI_BUF_CTL(PORT_E), 602 DDI_BUF_CTL_ENABLE | 603 ((intel_crtc->config->fdi_lanes - 1) << 1) | 604 DDI_BUF_TRANS_SELECT(i / 2)); 605 POSTING_READ(DDI_BUF_CTL(PORT_E)); 606 607 udelay(600); 608 609 /* Program PCH FDI Receiver TU */ 610 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 611 612 /* Enable PCH FDI Receiver with auto-training */ 613 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 614 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 615 POSTING_READ(FDI_RX_CTL(PIPE_A)); 616 617 /* Wait for FDI receiver lane calibration */ 618 udelay(30); 619 620 /* Unset FDI_RX_MISC pwrdn lanes */ 621 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 622 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 623 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 624 POSTING_READ(FDI_RX_MISC(PIPE_A)); 625 626 /* Wait for FDI auto training time */ 627 udelay(5); 628 629 temp = I915_READ(DP_TP_STATUS(PORT_E)); 630 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 631 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 632 break; 633 } 634 635 /* 636 * Leave things enabled even if we failed to train FDI. 637 * Results in less fireworks from the state checker. 638 */ 639 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 640 DRM_ERROR("FDI link training failed!\n"); 641 break; 642 } 643 644 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 645 temp &= ~DDI_BUF_CTL_ENABLE; 646 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 647 POSTING_READ(DDI_BUF_CTL(PORT_E)); 648 649 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 650 temp = I915_READ(DP_TP_CTL(PORT_E)); 651 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 652 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 653 I915_WRITE(DP_TP_CTL(PORT_E), temp); 654 POSTING_READ(DP_TP_CTL(PORT_E)); 655 656 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 657 658 rx_ctl_val &= ~FDI_RX_ENABLE; 659 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); 660 POSTING_READ(FDI_RX_CTL(PIPE_A)); 661 662 /* Reset FDI_RX_MISC pwrdn lanes */ 663 temp = I915_READ(FDI_RX_MISC(PIPE_A)); 664 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 665 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 666 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); 667 POSTING_READ(FDI_RX_MISC(PIPE_A)); 668 } 669 670 /* Enable normal pixel sending for FDI */ 671 I915_WRITE(DP_TP_CTL(PORT_E), 672 DP_TP_CTL_FDI_AUTOTRAIN | 673 DP_TP_CTL_LINK_TRAIN_NORMAL | 674 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 675 DP_TP_CTL_ENABLE); 676 } 677 678 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 679 { 680 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 681 struct intel_digital_port *intel_dig_port = 682 enc_to_dig_port(&encoder->base); 683 684 intel_dp->DP = intel_dig_port->saved_port_bits | 685 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 686 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 687 } 688 689 static struct intel_encoder * 690 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 691 { 692 struct drm_device *dev = crtc->dev; 693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 694 struct intel_encoder *intel_encoder, *ret = NULL; 695 int num_encoders = 0; 696 697 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 698 ret = intel_encoder; 699 num_encoders++; 700 } 701 702 if (num_encoders != 1) 703 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 704 pipe_name(intel_crtc->pipe)); 705 706 BUG_ON(ret == NULL); 707 return ret; 708 } 709 710 struct intel_encoder * 711 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 712 { 713 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 714 struct intel_encoder *ret = NULL; 715 struct drm_atomic_state *state; 716 struct drm_connector *connector; 717 struct drm_connector_state *connector_state; 718 int num_encoders = 0; 719 int i; 720 721 state = crtc_state->base.state; 722 723 for_each_connector_in_state(state, connector, connector_state, i) { 724 if (connector_state->crtc != crtc_state->base.crtc) 725 continue; 726 727 ret = to_intel_encoder(connector_state->best_encoder); 728 num_encoders++; 729 } 730 731 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 732 pipe_name(crtc->pipe)); 733 734 BUG_ON(ret == NULL); 735 return ret; 736 } 737 738 #define LC_FREQ 2700 739 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 740 741 #define P_MIN 2 742 #define P_MAX 64 743 #define P_INC 2 744 745 /* Constraints for PLL good behavior */ 746 #define REF_MIN 48 747 #define REF_MAX 400 748 #define VCO_MIN 2400 749 #define VCO_MAX 4800 750 751 #define abs_diff(a, b) ({ \ 752 typeof(a) __a = (a); \ 753 typeof(b) __b = (b); \ 754 (void) (&__a == &__b); \ 755 __a > __b ? (__a - __b) : (__b - __a); }) 756 757 struct hsw_wrpll_rnp { 758 unsigned p, n2, r2; 759 }; 760 761 static unsigned hsw_wrpll_get_budget_for_freq(int clock) 762 { 763 unsigned budget; 764 765 switch (clock) { 766 case 25175000: 767 case 25200000: 768 case 27000000: 769 case 27027000: 770 case 37762500: 771 case 37800000: 772 case 40500000: 773 case 40541000: 774 case 54000000: 775 case 54054000: 776 case 59341000: 777 case 59400000: 778 case 72000000: 779 case 74176000: 780 case 74250000: 781 case 81000000: 782 case 81081000: 783 case 89012000: 784 case 89100000: 785 case 108000000: 786 case 108108000: 787 case 111264000: 788 case 111375000: 789 case 148352000: 790 case 148500000: 791 case 162000000: 792 case 162162000: 793 case 222525000: 794 case 222750000: 795 case 296703000: 796 case 297000000: 797 budget = 0; 798 break; 799 case 233500000: 800 case 245250000: 801 case 247750000: 802 case 253250000: 803 case 298000000: 804 budget = 1500; 805 break; 806 case 169128000: 807 case 169500000: 808 case 179500000: 809 case 202000000: 810 budget = 2000; 811 break; 812 case 256250000: 813 case 262500000: 814 case 270000000: 815 case 272500000: 816 case 273750000: 817 case 280750000: 818 case 281250000: 819 case 286000000: 820 case 291750000: 821 budget = 4000; 822 break; 823 case 267250000: 824 case 268500000: 825 budget = 5000; 826 break; 827 default: 828 budget = 1000; 829 break; 830 } 831 832 return budget; 833 } 834 835 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, 836 unsigned r2, unsigned n2, unsigned p, 837 struct hsw_wrpll_rnp *best) 838 { 839 uint64_t a, b, c, d, diff, diff_best; 840 841 /* No best (r,n,p) yet */ 842 if (best->p == 0) { 843 best->p = p; 844 best->n2 = n2; 845 best->r2 = r2; 846 return; 847 } 848 849 /* 850 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 851 * freq2k. 852 * 853 * delta = 1e6 * 854 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 855 * freq2k; 856 * 857 * and we would like delta <= budget. 858 * 859 * If the discrepancy is above the PPM-based budget, always prefer to 860 * improve upon the previous solution. However, if you're within the 861 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 862 */ 863 a = freq2k * budget * p * r2; 864 b = freq2k * budget * best->p * best->r2; 865 diff = abs_diff((u64)freq2k * p * r2, LC_FREQ_2K * n2); 866 diff_best = abs_diff((u64)freq2k * best->p * best->r2, 867 LC_FREQ_2K * best->n2); 868 c = 1000000 * diff; 869 d = 1000000 * diff_best; 870 871 if (a < c && b < d) { 872 /* If both are above the budget, pick the closer */ 873 if (best->p * best->r2 * diff < p * r2 * diff_best) { 874 best->p = p; 875 best->n2 = n2; 876 best->r2 = r2; 877 } 878 } else if (a >= c && b < d) { 879 /* If A is below the threshold but B is above it? Update. */ 880 best->p = p; 881 best->n2 = n2; 882 best->r2 = r2; 883 } else if (a >= c && b >= d) { 884 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 885 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 886 best->p = p; 887 best->n2 = n2; 888 best->r2 = r2; 889 } 890 } 891 /* Otherwise a < c && b >= d, do nothing */ 892 } 893 894 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, 895 i915_reg_t reg) 896 { 897 int refclk = LC_FREQ; 898 int n, p, r; 899 u32 wrpll; 900 901 wrpll = I915_READ(reg); 902 switch (wrpll & WRPLL_PLL_REF_MASK) { 903 case WRPLL_PLL_SSC: 904 case WRPLL_PLL_NON_SSC: 905 /* 906 * We could calculate spread here, but our checking 907 * code only cares about 5% accuracy, and spread is a max of 908 * 0.5% downspread. 909 */ 910 refclk = 135; 911 break; 912 case WRPLL_PLL_LCPLL: 913 refclk = LC_FREQ; 914 break; 915 default: 916 WARN(1, "bad wrpll refclk\n"); 917 return 0; 918 } 919 920 r = wrpll & WRPLL_DIVIDER_REF_MASK; 921 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 922 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 923 924 /* Convert to KHz, p & r have a fixed point portion */ 925 return (refclk * n * 100) / (p * r); 926 } 927 928 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 929 uint32_t dpll) 930 { 931 i915_reg_t cfgcr1_reg, cfgcr2_reg; 932 uint32_t cfgcr1_val, cfgcr2_val; 933 uint32_t p0, p1, p2, dco_freq; 934 935 cfgcr1_reg = DPLL_CFGCR1(dpll); 936 cfgcr2_reg = DPLL_CFGCR2(dpll); 937 938 cfgcr1_val = I915_READ(cfgcr1_reg); 939 cfgcr2_val = I915_READ(cfgcr2_reg); 940 941 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 942 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 943 944 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 945 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 946 else 947 p1 = 1; 948 949 950 switch (p0) { 951 case DPLL_CFGCR2_PDIV_1: 952 p0 = 1; 953 break; 954 case DPLL_CFGCR2_PDIV_2: 955 p0 = 2; 956 break; 957 case DPLL_CFGCR2_PDIV_3: 958 p0 = 3; 959 break; 960 case DPLL_CFGCR2_PDIV_7: 961 p0 = 7; 962 break; 963 } 964 965 switch (p2) { 966 case DPLL_CFGCR2_KDIV_5: 967 p2 = 5; 968 break; 969 case DPLL_CFGCR2_KDIV_2: 970 p2 = 2; 971 break; 972 case DPLL_CFGCR2_KDIV_3: 973 p2 = 3; 974 break; 975 case DPLL_CFGCR2_KDIV_1: 976 p2 = 1; 977 break; 978 } 979 980 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 981 982 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 983 1000) / 0x8000; 984 985 return dco_freq / (p0 * p1 * p2 * 5); 986 } 987 988 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 989 { 990 int dotclock; 991 992 if (pipe_config->has_pch_encoder) 993 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 994 &pipe_config->fdi_m_n); 995 else if (pipe_config->has_dp_encoder) 996 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 997 &pipe_config->dp_m_n); 998 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 999 dotclock = pipe_config->port_clock * 2 / 3; 1000 else 1001 dotclock = pipe_config->port_clock; 1002 1003 if (pipe_config->pixel_multiplier) 1004 dotclock /= pipe_config->pixel_multiplier; 1005 1006 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1007 } 1008 1009 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1010 struct intel_crtc_state *pipe_config) 1011 { 1012 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1013 int link_clock = 0; 1014 uint32_t dpll_ctl1, dpll; 1015 1016 dpll = pipe_config->ddi_pll_sel; 1017 1018 dpll_ctl1 = I915_READ(DPLL_CTRL1); 1019 1020 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 1021 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 1022 } else { 1023 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 1024 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 1025 1026 switch (link_clock) { 1027 case DPLL_CTRL1_LINK_RATE_810: 1028 link_clock = 81000; 1029 break; 1030 case DPLL_CTRL1_LINK_RATE_1080: 1031 link_clock = 108000; 1032 break; 1033 case DPLL_CTRL1_LINK_RATE_1350: 1034 link_clock = 135000; 1035 break; 1036 case DPLL_CTRL1_LINK_RATE_1620: 1037 link_clock = 162000; 1038 break; 1039 case DPLL_CTRL1_LINK_RATE_2160: 1040 link_clock = 216000; 1041 break; 1042 case DPLL_CTRL1_LINK_RATE_2700: 1043 link_clock = 270000; 1044 break; 1045 default: 1046 WARN(1, "Unsupported link rate\n"); 1047 break; 1048 } 1049 link_clock *= 2; 1050 } 1051 1052 pipe_config->port_clock = link_clock; 1053 1054 ddi_dotclock_get(pipe_config); 1055 } 1056 1057 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1058 struct intel_crtc_state *pipe_config) 1059 { 1060 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1061 int link_clock = 0; 1062 u32 val, pll; 1063 1064 val = pipe_config->ddi_pll_sel; 1065 switch (val & PORT_CLK_SEL_MASK) { 1066 case PORT_CLK_SEL_LCPLL_810: 1067 link_clock = 81000; 1068 break; 1069 case PORT_CLK_SEL_LCPLL_1350: 1070 link_clock = 135000; 1071 break; 1072 case PORT_CLK_SEL_LCPLL_2700: 1073 link_clock = 270000; 1074 break; 1075 case PORT_CLK_SEL_WRPLL1: 1076 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); 1077 break; 1078 case PORT_CLK_SEL_WRPLL2: 1079 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); 1080 break; 1081 case PORT_CLK_SEL_SPLL: 1082 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 1083 if (pll == SPLL_PLL_FREQ_810MHz) 1084 link_clock = 81000; 1085 else if (pll == SPLL_PLL_FREQ_1350MHz) 1086 link_clock = 135000; 1087 else if (pll == SPLL_PLL_FREQ_2700MHz) 1088 link_clock = 270000; 1089 else { 1090 WARN(1, "bad spll freq\n"); 1091 return; 1092 } 1093 break; 1094 default: 1095 WARN(1, "bad port clock sel\n"); 1096 return; 1097 } 1098 1099 pipe_config->port_clock = link_clock * 2; 1100 1101 ddi_dotclock_get(pipe_config); 1102 } 1103 1104 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 1105 enum intel_dpll_id dpll) 1106 { 1107 struct intel_shared_dpll *pll; 1108 struct intel_dpll_hw_state *state; 1109 intel_clock_t clock; 1110 1111 /* For DDI ports we always use a shared PLL. */ 1112 if (WARN_ON(dpll == DPLL_ID_PRIVATE)) 1113 return 0; 1114 1115 pll = &dev_priv->shared_dplls[dpll]; 1116 state = &pll->config.hw_state; 1117 1118 clock.m1 = 2; 1119 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; 1120 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1121 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; 1122 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1123 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1124 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1125 1126 return chv_calc_dpll_params(100000, &clock); 1127 } 1128 1129 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1130 struct intel_crtc_state *pipe_config) 1131 { 1132 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1133 enum port port = intel_ddi_get_encoder_port(encoder); 1134 uint32_t dpll = port; 1135 1136 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); 1137 1138 ddi_dotclock_get(pipe_config); 1139 } 1140 1141 void intel_ddi_clock_get(struct intel_encoder *encoder, 1142 struct intel_crtc_state *pipe_config) 1143 { 1144 struct drm_device *dev = encoder->base.dev; 1145 1146 if (INTEL_INFO(dev)->gen <= 8) 1147 hsw_ddi_clock_get(encoder, pipe_config); 1148 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1149 skl_ddi_clock_get(encoder, pipe_config); 1150 else if (IS_BROXTON(dev)) 1151 bxt_ddi_clock_get(encoder, pipe_config); 1152 } 1153 1154 static void 1155 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 1156 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 1157 { 1158 uint64_t freq2k; 1159 unsigned p, n2, r2; 1160 struct hsw_wrpll_rnp best = { 0, 0, 0 }; 1161 unsigned budget; 1162 1163 freq2k = clock / 100; 1164 1165 budget = hsw_wrpll_get_budget_for_freq(clock); 1166 1167 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 1168 * and directly pass the LC PLL to it. */ 1169 if (freq2k == 5400000) { 1170 *n2_out = 2; 1171 *p_out = 1; 1172 *r2_out = 2; 1173 return; 1174 } 1175 1176 /* 1177 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 1178 * the WR PLL. 1179 * 1180 * We want R so that REF_MIN <= Ref <= REF_MAX. 1181 * Injecting R2 = 2 * R gives: 1182 * REF_MAX * r2 > LC_FREQ * 2 and 1183 * REF_MIN * r2 < LC_FREQ * 2 1184 * 1185 * Which means the desired boundaries for r2 are: 1186 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 1187 * 1188 */ 1189 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 1190 r2 <= LC_FREQ * 2 / REF_MIN; 1191 r2++) { 1192 1193 /* 1194 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 1195 * 1196 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 1197 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 1198 * VCO_MAX * r2 > n2 * LC_FREQ and 1199 * VCO_MIN * r2 < n2 * LC_FREQ) 1200 * 1201 * Which means the desired boundaries for n2 are: 1202 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 1203 */ 1204 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 1205 n2 <= VCO_MAX * r2 / LC_FREQ; 1206 n2++) { 1207 1208 for (p = P_MIN; p <= P_MAX; p += P_INC) 1209 hsw_wrpll_update_rnp(freq2k, budget, 1210 r2, n2, p, &best); 1211 } 1212 } 1213 1214 *n2_out = best.n2; 1215 *p_out = best.p; 1216 *r2_out = best.r2; 1217 } 1218 1219 static bool 1220 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 1221 struct intel_crtc_state *crtc_state, 1222 struct intel_encoder *intel_encoder) 1223 { 1224 int clock = crtc_state->port_clock; 1225 1226 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1227 struct intel_shared_dpll *pll; 1228 uint32_t val; 1229 unsigned p, n2, r2; 1230 1231 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 1232 1233 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 1234 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 1235 WRPLL_DIVIDER_POST(p); 1236 1237 memset(&crtc_state->dpll_hw_state, 0, 1238 sizeof(crtc_state->dpll_hw_state)); 1239 1240 crtc_state->dpll_hw_state.wrpll = val; 1241 1242 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1243 if (pll == NULL) { 1244 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1245 pipe_name(intel_crtc->pipe)); 1246 return false; 1247 } 1248 1249 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1250 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { 1251 struct drm_atomic_state *state = crtc_state->base.state; 1252 struct intel_shared_dpll_config *spll = 1253 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; 1254 1255 if (spll->crtc_mask && 1256 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) 1257 return false; 1258 1259 crtc_state->shared_dpll = DPLL_ID_SPLL; 1260 spll->hw_state.spll = crtc_state->dpll_hw_state.spll; 1261 spll->crtc_mask |= 1 << intel_crtc->pipe; 1262 } 1263 1264 return true; 1265 } 1266 1267 struct skl_wrpll_context { 1268 uint64_t min_deviation; /* current minimal deviation */ 1269 uint64_t central_freq; /* chosen central freq */ 1270 uint64_t dco_freq; /* chosen dco freq */ 1271 unsigned int p; /* chosen divider */ 1272 }; 1273 1274 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) 1275 { 1276 memset(ctx, 0, sizeof(*ctx)); 1277 1278 ctx->min_deviation = U64_MAX; 1279 } 1280 1281 /* DCO freq must be within +1%/-6% of the DCO central freq */ 1282 #define SKL_DCO_MAX_PDEVIATION 100 1283 #define SKL_DCO_MAX_NDEVIATION 600 1284 1285 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, 1286 uint64_t central_freq, 1287 uint64_t dco_freq, 1288 unsigned int divider) 1289 { 1290 uint64_t deviation; 1291 1292 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), 1293 central_freq); 1294 1295 /* positive deviation */ 1296 if (dco_freq >= central_freq) { 1297 if (deviation < SKL_DCO_MAX_PDEVIATION && 1298 deviation < ctx->min_deviation) { 1299 ctx->min_deviation = deviation; 1300 ctx->central_freq = central_freq; 1301 ctx->dco_freq = dco_freq; 1302 ctx->p = divider; 1303 } 1304 /* negative deviation */ 1305 } else if (deviation < SKL_DCO_MAX_NDEVIATION && 1306 deviation < ctx->min_deviation) { 1307 ctx->min_deviation = deviation; 1308 ctx->central_freq = central_freq; 1309 ctx->dco_freq = dco_freq; 1310 ctx->p = divider; 1311 } 1312 } 1313 1314 static void skl_wrpll_get_multipliers(unsigned int p, 1315 unsigned int *p0 /* out */, 1316 unsigned int *p1 /* out */, 1317 unsigned int *p2 /* out */) 1318 { 1319 /* even dividers */ 1320 if (p % 2 == 0) { 1321 unsigned int half = p / 2; 1322 1323 if (half == 1 || half == 2 || half == 3 || half == 5) { 1324 *p0 = 2; 1325 *p1 = 1; 1326 *p2 = half; 1327 } else if (half % 2 == 0) { 1328 *p0 = 2; 1329 *p1 = half / 2; 1330 *p2 = 2; 1331 } else if (half % 3 == 0) { 1332 *p0 = 3; 1333 *p1 = half / 3; 1334 *p2 = 2; 1335 } else if (half % 7 == 0) { 1336 *p0 = 7; 1337 *p1 = half / 7; 1338 *p2 = 2; 1339 } 1340 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ 1341 *p0 = 3; 1342 *p1 = 1; 1343 *p2 = p / 3; 1344 } else if (p == 5 || p == 7) { 1345 *p0 = p; 1346 *p1 = 1; 1347 *p2 = 1; 1348 } else if (p == 15) { 1349 *p0 = 3; 1350 *p1 = 1; 1351 *p2 = 5; 1352 } else if (p == 21) { 1353 *p0 = 7; 1354 *p1 = 1; 1355 *p2 = 3; 1356 } else if (p == 35) { 1357 *p0 = 7; 1358 *p1 = 1; 1359 *p2 = 5; 1360 } 1361 } 1362 1363 struct skl_wrpll_params { 1364 uint32_t dco_fraction; 1365 uint32_t dco_integer; 1366 uint32_t qdiv_ratio; 1367 uint32_t qdiv_mode; 1368 uint32_t kdiv; 1369 uint32_t pdiv; 1370 uint32_t central_freq; 1371 }; 1372 1373 static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 1374 uint64_t afe_clock, 1375 uint64_t central_freq, 1376 uint32_t p0, uint32_t p1, uint32_t p2) 1377 { 1378 uint64_t dco_freq; 1379 1380 switch (central_freq) { 1381 case 9600000000ULL: 1382 params->central_freq = 0; 1383 break; 1384 case 9000000000ULL: 1385 params->central_freq = 1; 1386 break; 1387 case 8400000000ULL: 1388 params->central_freq = 3; 1389 } 1390 1391 switch (p0) { 1392 case 1: 1393 params->pdiv = 0; 1394 break; 1395 case 2: 1396 params->pdiv = 1; 1397 break; 1398 case 3: 1399 params->pdiv = 2; 1400 break; 1401 case 7: 1402 params->pdiv = 4; 1403 break; 1404 default: 1405 WARN(1, "Incorrect PDiv\n"); 1406 } 1407 1408 switch (p2) { 1409 case 5: 1410 params->kdiv = 0; 1411 break; 1412 case 2: 1413 params->kdiv = 1; 1414 break; 1415 case 3: 1416 params->kdiv = 2; 1417 break; 1418 case 1: 1419 params->kdiv = 3; 1420 break; 1421 default: 1422 WARN(1, "Incorrect KDiv\n"); 1423 } 1424 1425 params->qdiv_ratio = p1; 1426 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; 1427 1428 dco_freq = p0 * p1 * p2 * afe_clock; 1429 1430 /* 1431 * Intermediate values are in Hz. 1432 * Divide by MHz to match bsepc 1433 */ 1434 params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); 1435 params->dco_fraction = 1436 div_u64((div_u64(dco_freq, 24) - 1437 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); 1438 } 1439 1440 static bool 1441 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1442 struct skl_wrpll_params *wrpll_params) 1443 { 1444 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1445 uint64_t dco_central_freq[3] = {8400000000ULL, 1446 9000000000ULL, 1447 9600000000ULL}; 1448 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 1449 24, 28, 30, 32, 36, 40, 42, 44, 1450 48, 52, 54, 56, 60, 64, 66, 68, 1451 70, 72, 76, 78, 80, 84, 88, 90, 1452 92, 96, 98 }; 1453 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; 1454 static const struct { 1455 const int *list; 1456 int n_dividers; 1457 } dividers[] = { 1458 { even_dividers, ARRAY_SIZE(even_dividers) }, 1459 { odd_dividers, ARRAY_SIZE(odd_dividers) }, 1460 }; 1461 struct skl_wrpll_context ctx; 1462 unsigned int dco, d, i; 1463 unsigned int p0, p1, p2; 1464 1465 skl_wrpll_context_init(&ctx); 1466 1467 for (d = 0; d < ARRAY_SIZE(dividers); d++) { 1468 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { 1469 for (i = 0; i < dividers[d].n_dividers; i++) { 1470 unsigned int p = dividers[d].list[i]; 1471 uint64_t dco_freq = p * afe_clock; 1472 1473 skl_wrpll_try_divider(&ctx, 1474 dco_central_freq[dco], 1475 dco_freq, 1476 p); 1477 /* 1478 * Skip the remaining dividers if we're sure to 1479 * have found the definitive divider, we can't 1480 * improve a 0 deviation. 1481 */ 1482 if (ctx.min_deviation == 0) 1483 goto skip_remaining_dividers; 1484 } 1485 } 1486 1487 skip_remaining_dividers: 1488 /* 1489 * If a solution is found with an even divider, prefer 1490 * this one. 1491 */ 1492 if (d == 0 && ctx.p) 1493 break; 1494 } 1495 1496 if (!ctx.p) { 1497 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); 1498 return false; 1499 } 1500 1501 /* 1502 * gcc incorrectly analyses that these can be used without being 1503 * initialized. To be fair, it's hard to guess. 1504 */ 1505 p0 = p1 = p2 = 0; 1506 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); 1507 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, 1508 p0, p1, p2); 1509 1510 return true; 1511 } 1512 1513 static bool 1514 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1515 struct intel_crtc_state *crtc_state, 1516 struct intel_encoder *intel_encoder) 1517 { 1518 struct intel_shared_dpll *pll; 1519 uint32_t ctrl1, cfgcr1, cfgcr2; 1520 int clock = crtc_state->port_clock; 1521 1522 /* 1523 * See comment in intel_dpll_hw_state to understand why we always use 0 1524 * as the DPLL id in this function. 1525 */ 1526 1527 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1528 1529 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1530 struct skl_wrpll_params wrpll_params = { 0, }; 1531 1532 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1533 1534 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) 1535 return false; 1536 1537 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1538 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1539 wrpll_params.dco_integer; 1540 1541 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1542 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1543 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1544 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1545 wrpll_params.central_freq; 1546 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1547 intel_encoder->type == INTEL_OUTPUT_DP_MST) { 1548 switch (crtc_state->port_clock / 2) { 1549 case 81000: 1550 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1551 break; 1552 case 135000: 1553 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1554 break; 1555 case 270000: 1556 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1557 break; 1558 } 1559 1560 cfgcr1 = cfgcr2 = 0; 1561 } else if (intel_encoder->type == INTEL_OUTPUT_EDP) { 1562 return true; 1563 } else 1564 return false; 1565 1566 memset(&crtc_state->dpll_hw_state, 0, 1567 sizeof(crtc_state->dpll_hw_state)); 1568 1569 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1570 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1571 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1572 1573 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1574 if (pll == NULL) { 1575 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1576 pipe_name(intel_crtc->pipe)); 1577 return false; 1578 } 1579 1580 /* shared DPLL id 0 is DPLL 1 */ 1581 crtc_state->ddi_pll_sel = pll->id + 1; 1582 1583 return true; 1584 } 1585 1586 /* bxt clock parameters */ 1587 struct bxt_clk_div { 1588 int clock; 1589 uint32_t p1; 1590 uint32_t p2; 1591 uint32_t m2_int; 1592 uint32_t m2_frac; 1593 bool m2_frac_en; 1594 uint32_t n; 1595 }; 1596 1597 /* pre-calculated values for DP linkrates */ 1598 static const struct bxt_clk_div bxt_dp_clk_val[] = { 1599 {162000, 4, 2, 32, 1677722, 1, 1}, 1600 {270000, 4, 1, 27, 0, 0, 1}, 1601 {540000, 2, 1, 27, 0, 0, 1}, 1602 {216000, 3, 2, 32, 1677722, 1, 1}, 1603 {243000, 4, 1, 24, 1258291, 1, 1}, 1604 {324000, 4, 1, 32, 1677722, 1, 1}, 1605 {432000, 3, 1, 32, 1677722, 1, 1} 1606 }; 1607 1608 static bool 1609 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 1610 struct intel_crtc_state *crtc_state, 1611 struct intel_encoder *intel_encoder) 1612 { 1613 struct intel_shared_dpll *pll; 1614 struct bxt_clk_div clk_div = {0}; 1615 int vco = 0; 1616 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1617 uint32_t lanestagger; 1618 int clock = crtc_state->port_clock; 1619 1620 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1621 intel_clock_t best_clock; 1622 1623 /* Calculate HDMI div */ 1624 /* 1625 * FIXME: tie the following calculation into 1626 * i9xx_crtc_compute_clock 1627 */ 1628 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1629 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1630 clock, pipe_name(intel_crtc->pipe)); 1631 return false; 1632 } 1633 1634 clk_div.p1 = best_clock.p1; 1635 clk_div.p2 = best_clock.p2; 1636 WARN_ON(best_clock.m1 != 2); 1637 clk_div.n = best_clock.n; 1638 clk_div.m2_int = best_clock.m2 >> 22; 1639 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1640 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1641 1642 vco = best_clock.vco; 1643 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1644 intel_encoder->type == INTEL_OUTPUT_EDP) { 1645 int i; 1646 1647 clk_div = bxt_dp_clk_val[0]; 1648 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { 1649 if (bxt_dp_clk_val[i].clock == clock) { 1650 clk_div = bxt_dp_clk_val[i]; 1651 break; 1652 } 1653 } 1654 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1655 } 1656 1657 if (vco >= 6200000 && vco <= 6700000) { 1658 prop_coef = 4; 1659 int_coef = 9; 1660 gain_ctl = 3; 1661 targ_cnt = 8; 1662 } else if ((vco > 5400000 && vco < 6200000) || 1663 (vco >= 4800000 && vco < 5400000)) { 1664 prop_coef = 5; 1665 int_coef = 11; 1666 gain_ctl = 3; 1667 targ_cnt = 9; 1668 } else if (vco == 5400000) { 1669 prop_coef = 3; 1670 int_coef = 8; 1671 gain_ctl = 1; 1672 targ_cnt = 9; 1673 } else { 1674 DRM_ERROR("Invalid VCO\n"); 1675 return false; 1676 } 1677 1678 memset(&crtc_state->dpll_hw_state, 0, 1679 sizeof(crtc_state->dpll_hw_state)); 1680 1681 if (clock > 270000) 1682 lanestagger = 0x18; 1683 else if (clock > 135000) 1684 lanestagger = 0x0d; 1685 else if (clock > 67000) 1686 lanestagger = 0x07; 1687 else if (clock > 33000) 1688 lanestagger = 0x04; 1689 else 1690 lanestagger = 0x02; 1691 1692 crtc_state->dpll_hw_state.ebb0 = 1693 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1694 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1695 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1696 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1697 1698 if (clk_div.m2_frac_en) 1699 crtc_state->dpll_hw_state.pll3 = 1700 PORT_PLL_M2_FRAC_ENABLE; 1701 1702 crtc_state->dpll_hw_state.pll6 = 1703 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1704 crtc_state->dpll_hw_state.pll6 |= 1705 PORT_PLL_GAIN_CTL(gain_ctl); 1706 1707 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1708 1709 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; 1710 1711 crtc_state->dpll_hw_state.pll10 = 1712 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) 1713 | PORT_PLL_DCO_AMP_OVR_EN_H; 1714 1715 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; 1716 1717 crtc_state->dpll_hw_state.pcsdw12 = 1718 LANESTAGGER_STRAP_OVRD | lanestagger; 1719 1720 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1721 if (pll == NULL) { 1722 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1723 pipe_name(intel_crtc->pipe)); 1724 return false; 1725 } 1726 1727 /* shared DPLL id 0 is DPLL A */ 1728 crtc_state->ddi_pll_sel = pll->id; 1729 1730 return true; 1731 } 1732 1733 /* 1734 * Tries to find a *shared* PLL for the CRTC and store it in 1735 * intel_crtc->ddi_pll_sel. 1736 * 1737 * For private DPLLs, compute_config() should do the selection for us. This 1738 * function should be folded into compute_config() eventually. 1739 */ 1740 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1741 struct intel_crtc_state *crtc_state) 1742 { 1743 struct drm_device *dev = intel_crtc->base.dev; 1744 struct intel_encoder *intel_encoder = 1745 intel_ddi_get_crtc_new_encoder(crtc_state); 1746 1747 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 1748 return skl_ddi_pll_select(intel_crtc, crtc_state, 1749 intel_encoder); 1750 else if (IS_BROXTON(dev)) 1751 return bxt_ddi_pll_select(intel_crtc, crtc_state, 1752 intel_encoder); 1753 else 1754 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1755 intel_encoder); 1756 } 1757 1758 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1759 { 1760 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1762 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1763 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1764 int type = intel_encoder->type; 1765 uint32_t temp; 1766 1767 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1768 temp = TRANS_MSA_SYNC_CLK; 1769 switch (intel_crtc->config->pipe_bpp) { 1770 case 18: 1771 temp |= TRANS_MSA_6_BPC; 1772 break; 1773 case 24: 1774 temp |= TRANS_MSA_8_BPC; 1775 break; 1776 case 30: 1777 temp |= TRANS_MSA_10_BPC; 1778 break; 1779 case 36: 1780 temp |= TRANS_MSA_12_BPC; 1781 break; 1782 default: 1783 BUG(); 1784 } 1785 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1786 } 1787 } 1788 1789 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1790 { 1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1792 struct drm_device *dev = crtc->dev; 1793 struct drm_i915_private *dev_priv = dev->dev_private; 1794 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1795 uint32_t temp; 1796 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1797 if (state == true) 1798 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1799 else 1800 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1801 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1802 } 1803 1804 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1805 { 1806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1807 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1808 struct drm_encoder *encoder = &intel_encoder->base; 1809 struct drm_device *dev = crtc->dev; 1810 struct drm_i915_private *dev_priv = dev->dev_private; 1811 enum i915_pipe pipe = intel_crtc->pipe; 1812 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1813 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1814 int type = intel_encoder->type; 1815 uint32_t temp; 1816 1817 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1818 temp = TRANS_DDI_FUNC_ENABLE; 1819 temp |= TRANS_DDI_SELECT_PORT(port); 1820 1821 switch (intel_crtc->config->pipe_bpp) { 1822 case 18: 1823 temp |= TRANS_DDI_BPC_6; 1824 break; 1825 case 24: 1826 temp |= TRANS_DDI_BPC_8; 1827 break; 1828 case 30: 1829 temp |= TRANS_DDI_BPC_10; 1830 break; 1831 case 36: 1832 temp |= TRANS_DDI_BPC_12; 1833 break; 1834 default: 1835 BUG(); 1836 } 1837 1838 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1839 temp |= TRANS_DDI_PVSYNC; 1840 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1841 temp |= TRANS_DDI_PHSYNC; 1842 1843 if (cpu_transcoder == TRANSCODER_EDP) { 1844 switch (pipe) { 1845 case PIPE_A: 1846 /* On Haswell, can only use the always-on power well for 1847 * eDP when not using the panel fitter, and when not 1848 * using motion blur mitigation (which we don't 1849 * support). */ 1850 if (IS_HASWELL(dev) && 1851 (intel_crtc->config->pch_pfit.enabled || 1852 intel_crtc->config->pch_pfit.force_thru)) 1853 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1854 else 1855 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1856 break; 1857 case PIPE_B: 1858 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1859 break; 1860 case PIPE_C: 1861 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1862 break; 1863 default: 1864 BUG(); 1865 break; 1866 } 1867 } 1868 1869 if (type == INTEL_OUTPUT_HDMI) { 1870 if (intel_crtc->config->has_hdmi_sink) 1871 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1872 else 1873 temp |= TRANS_DDI_MODE_SELECT_DVI; 1874 1875 } else if (type == INTEL_OUTPUT_ANALOG) { 1876 temp |= TRANS_DDI_MODE_SELECT_FDI; 1877 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1878 1879 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1880 type == INTEL_OUTPUT_EDP) { 1881 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1882 1883 if (intel_dp->is_mst) { 1884 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1885 } else 1886 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1887 1888 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1889 } else if (type == INTEL_OUTPUT_DP_MST) { 1890 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1891 1892 if (intel_dp->is_mst) { 1893 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1894 } else 1895 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1896 1897 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); 1898 } else { 1899 WARN(1, "Invalid encoder type %d for pipe %c\n", 1900 intel_encoder->type, pipe_name(pipe)); 1901 } 1902 1903 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1904 } 1905 1906 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1907 enum transcoder cpu_transcoder) 1908 { 1909 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1910 uint32_t val = I915_READ(reg); 1911 1912 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1913 val |= TRANS_DDI_PORT_NONE; 1914 I915_WRITE(reg, val); 1915 } 1916 1917 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1918 { 1919 struct drm_device *dev = intel_connector->base.dev; 1920 struct drm_i915_private *dev_priv = dev->dev_private; 1921 struct intel_encoder *intel_encoder = intel_connector->encoder; 1922 int type = intel_connector->base.connector_type; 1923 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1924 enum i915_pipe pipe = 0; 1925 enum transcoder cpu_transcoder; 1926 enum intel_display_power_domain power_domain; 1927 uint32_t tmp; 1928 bool ret; 1929 1930 power_domain = intel_display_port_power_domain(intel_encoder); 1931 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 1932 return false; 1933 1934 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { 1935 ret = false; 1936 goto out; 1937 } 1938 1939 if (port == PORT_A) 1940 cpu_transcoder = TRANSCODER_EDP; 1941 else 1942 cpu_transcoder = (enum transcoder) pipe; 1943 1944 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1945 1946 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1947 case TRANS_DDI_MODE_SELECT_HDMI: 1948 case TRANS_DDI_MODE_SELECT_DVI: 1949 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1950 break; 1951 1952 case TRANS_DDI_MODE_SELECT_DP_SST: 1953 ret = type == DRM_MODE_CONNECTOR_eDP || 1954 type == DRM_MODE_CONNECTOR_DisplayPort; 1955 break; 1956 1957 case TRANS_DDI_MODE_SELECT_DP_MST: 1958 /* if the transcoder is in MST state then 1959 * connector isn't connected */ 1960 ret = false; 1961 break; 1962 1963 case TRANS_DDI_MODE_SELECT_FDI: 1964 ret = type == DRM_MODE_CONNECTOR_VGA; 1965 break; 1966 1967 default: 1968 ret = false; 1969 break; 1970 } 1971 1972 out: 1973 intel_display_power_put(dev_priv, power_domain); 1974 1975 return ret; 1976 } 1977 1978 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1979 enum i915_pipe *pipe) 1980 { 1981 struct drm_device *dev = encoder->base.dev; 1982 struct drm_i915_private *dev_priv = dev->dev_private; 1983 enum port port = intel_ddi_get_encoder_port(encoder); 1984 enum intel_display_power_domain power_domain; 1985 u32 tmp; 1986 int i; 1987 bool ret; 1988 1989 power_domain = intel_display_port_power_domain(encoder); 1990 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 1991 return false; 1992 1993 ret = false; 1994 1995 tmp = I915_READ(DDI_BUF_CTL(port)); 1996 1997 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1998 goto out; 1999 2000 if (port == PORT_A) { 2001 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 2002 2003 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 2004 case TRANS_DDI_EDP_INPUT_A_ON: 2005 case TRANS_DDI_EDP_INPUT_A_ONOFF: 2006 *pipe = PIPE_A; 2007 break; 2008 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2009 *pipe = PIPE_B; 2010 break; 2011 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2012 *pipe = PIPE_C; 2013 break; 2014 } 2015 2016 ret = true; 2017 2018 goto out; 2019 } 2020 2021 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 2022 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 2023 2024 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { 2025 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2026 TRANS_DDI_MODE_SELECT_DP_MST) 2027 goto out; 2028 2029 *pipe = i; 2030 ret = true; 2031 2032 goto out; 2033 } 2034 } 2035 2036 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 2037 2038 out: 2039 intel_display_power_put(dev_priv, power_domain); 2040 2041 return ret; 2042 } 2043 2044 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 2045 { 2046 struct drm_crtc *crtc = &intel_crtc->base; 2047 struct drm_device *dev = crtc->dev; 2048 struct drm_i915_private *dev_priv = dev->dev_private; 2049 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2050 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2051 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2052 2053 if (cpu_transcoder != TRANSCODER_EDP) 2054 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2055 TRANS_CLK_SEL_PORT(port)); 2056 } 2057 2058 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 2059 { 2060 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 2061 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2062 2063 if (cpu_transcoder != TRANSCODER_EDP) 2064 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2065 TRANS_CLK_SEL_DISABLED); 2066 } 2067 2068 static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2069 u32 level, enum port port, int type) 2070 { 2071 const struct ddi_buf_trans *ddi_translations; 2072 uint8_t iboost; 2073 uint8_t dp_iboost, hdmi_iboost; 2074 int n_entries; 2075 u32 reg; 2076 2077 /* VBT may override standard boost values */ 2078 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2079 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2080 2081 if (type == INTEL_OUTPUT_DISPLAYPORT) { 2082 if (dp_iboost) { 2083 iboost = dp_iboost; 2084 } else { 2085 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries); 2086 iboost = ddi_translations[level].i_boost; 2087 } 2088 } else if (type == INTEL_OUTPUT_EDP) { 2089 if (dp_iboost) { 2090 iboost = dp_iboost; 2091 } else { 2092 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); 2093 2094 if (WARN_ON(port != PORT_A && 2095 port != PORT_E && n_entries > 9)) 2096 n_entries = 9; 2097 2098 iboost = ddi_translations[level].i_boost; 2099 } 2100 } else if (type == INTEL_OUTPUT_HDMI) { 2101 if (hdmi_iboost) { 2102 iboost = hdmi_iboost; 2103 } else { 2104 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); 2105 iboost = ddi_translations[level].i_boost; 2106 } 2107 } else { 2108 return; 2109 } 2110 2111 /* Make sure that the requested I_boost is valid */ 2112 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2113 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2114 return; 2115 } 2116 2117 reg = I915_READ(DISPIO_CR_TX_BMU_CR0); 2118 reg &= ~BALANCE_LEG_MASK(port); 2119 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); 2120 2121 if (iboost) 2122 reg |= iboost << BALANCE_LEG_SHIFT(port); 2123 else 2124 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); 2125 2126 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); 2127 } 2128 2129 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, 2130 u32 level, enum port port, int type) 2131 { 2132 const struct bxt_ddi_buf_trans *ddi_translations; 2133 u32 n_entries, i; 2134 uint32_t val; 2135 2136 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) { 2137 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 2138 ddi_translations = bxt_ddi_translations_edp; 2139 } else if (type == INTEL_OUTPUT_DISPLAYPORT 2140 || type == INTEL_OUTPUT_EDP) { 2141 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 2142 ddi_translations = bxt_ddi_translations_dp; 2143 } else if (type == INTEL_OUTPUT_HDMI) { 2144 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 2145 ddi_translations = bxt_ddi_translations_hdmi; 2146 } else { 2147 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 2148 type); 2149 return; 2150 } 2151 2152 /* Check if default value has to be used */ 2153 if (level >= n_entries || 2154 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 2155 for (i = 0; i < n_entries; i++) { 2156 if (ddi_translations[i].default_index) { 2157 level = i; 2158 break; 2159 } 2160 } 2161 } 2162 2163 /* 2164 * While we write to the group register to program all lanes at once we 2165 * can read only lane registers and we pick lanes 0/1 for that. 2166 */ 2167 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2168 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 2169 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2170 2171 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); 2172 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 2173 val |= ddi_translations[level].margin << MARGIN_000_SHIFT | 2174 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; 2175 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); 2176 2177 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); 2178 val &= ~SCALE_DCOMP_METHOD; 2179 if (ddi_translations[level].enable) 2180 val |= SCALE_DCOMP_METHOD; 2181 2182 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 2183 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); 2184 2185 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); 2186 2187 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); 2188 val &= ~DE_EMPHASIS; 2189 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; 2190 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); 2191 2192 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2193 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 2194 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2195 } 2196 2197 static uint32_t translate_signal_level(int signal_levels) 2198 { 2199 uint32_t level; 2200 2201 switch (signal_levels) { 2202 default: 2203 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2204 signal_levels); 2205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2206 level = 0; 2207 break; 2208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2209 level = 1; 2210 break; 2211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2212 level = 2; 2213 break; 2214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: 2215 level = 3; 2216 break; 2217 2218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2219 level = 4; 2220 break; 2221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2222 level = 5; 2223 break; 2224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2225 level = 6; 2226 break; 2227 2228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2229 level = 7; 2230 break; 2231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2232 level = 8; 2233 break; 2234 2235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2236 level = 9; 2237 break; 2238 } 2239 2240 return level; 2241 } 2242 2243 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 2244 { 2245 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2246 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); 2247 struct intel_encoder *encoder = &dport->base; 2248 uint8_t train_set = intel_dp->train_set[0]; 2249 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2250 DP_TRAIN_PRE_EMPHASIS_MASK); 2251 enum port port = dport->port; 2252 uint32_t level; 2253 2254 level = translate_signal_level(signal_levels); 2255 2256 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2257 skl_ddi_set_iboost(dev_priv, level, port, encoder->type); 2258 else if (IS_BROXTON(dev_priv)) 2259 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); 2260 2261 return DDI_BUF_TRANS_SELECT(level); 2262 } 2263 2264 void intel_ddi_clk_select(struct intel_encoder *encoder, 2265 const struct intel_crtc_state *pipe_config) 2266 { 2267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2268 enum port port = intel_ddi_get_encoder_port(encoder); 2269 2270 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2271 uint32_t dpll = pipe_config->ddi_pll_sel; 2272 uint32_t val; 2273 2274 /* 2275 * DPLL0 is used for eDP and is the only "private" DPLL (as 2276 * opposed to shared) on SKL 2277 */ 2278 if (encoder->type == INTEL_OUTPUT_EDP) { 2279 WARN_ON(dpll != SKL_DPLL0); 2280 2281 val = I915_READ(DPLL_CTRL1); 2282 2283 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 2284 DPLL_CTRL1_SSC(dpll) | 2285 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2286 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6); 2287 2288 I915_WRITE(DPLL_CTRL1, val); 2289 POSTING_READ(DPLL_CTRL1); 2290 } 2291 2292 /* DDI -> PLL mapping */ 2293 val = I915_READ(DPLL_CTRL2); 2294 2295 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2296 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2297 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 2298 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2299 2300 I915_WRITE(DPLL_CTRL2, val); 2301 2302 } else if (INTEL_INFO(dev_priv)->gen < 9) { 2303 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE); 2304 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel); 2305 } 2306 } 2307 2308 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 2309 { 2310 struct drm_encoder *encoder = &intel_encoder->base; 2311 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 2312 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 2313 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2314 int type = intel_encoder->type; 2315 2316 intel_prepare_ddi_buffer(intel_encoder); 2317 2318 if (type == INTEL_OUTPUT_EDP) { 2319 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2320 intel_edp_panel_on(intel_dp); 2321 } 2322 2323 intel_ddi_clk_select(intel_encoder, crtc->config); 2324 2325 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2326 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2327 2328 intel_dp_set_link_params(intel_dp, crtc->config); 2329 2330 intel_ddi_init_dp_buf_reg(intel_encoder); 2331 2332 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2333 intel_dp_start_link_train(intel_dp); 2334 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9) 2335 intel_dp_stop_link_train(intel_dp); 2336 } else if (type == INTEL_OUTPUT_HDMI) { 2337 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2338 2339 intel_hdmi->set_infoframes(encoder, 2340 crtc->config->has_hdmi_sink, 2341 &crtc->config->base.adjusted_mode); 2342 } 2343 } 2344 2345 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 2346 { 2347 struct drm_encoder *encoder = &intel_encoder->base; 2348 struct drm_device *dev = encoder->dev; 2349 struct drm_i915_private *dev_priv = dev->dev_private; 2350 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2351 int type = intel_encoder->type; 2352 uint32_t val; 2353 bool wait = false; 2354 2355 val = I915_READ(DDI_BUF_CTL(port)); 2356 if (val & DDI_BUF_CTL_ENABLE) { 2357 val &= ~DDI_BUF_CTL_ENABLE; 2358 I915_WRITE(DDI_BUF_CTL(port), val); 2359 wait = true; 2360 } 2361 2362 val = I915_READ(DP_TP_CTL(port)); 2363 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2364 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2365 I915_WRITE(DP_TP_CTL(port), val); 2366 2367 if (wait) 2368 intel_wait_ddi_buf_idle(dev_priv, port); 2369 2370 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2371 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2372 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2373 intel_edp_panel_vdd_on(intel_dp); 2374 intel_edp_panel_off(intel_dp); 2375 } 2376 2377 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 2378 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 2379 DPLL_CTRL2_DDI_CLK_OFF(port))); 2380 else if (INTEL_INFO(dev)->gen < 9) 2381 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2382 } 2383 2384 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 2385 { 2386 struct drm_encoder *encoder = &intel_encoder->base; 2387 struct drm_crtc *crtc = encoder->crtc; 2388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2389 struct drm_device *dev = encoder->dev; 2390 struct drm_i915_private *dev_priv = dev->dev_private; 2391 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2392 int type = intel_encoder->type; 2393 2394 if (type == INTEL_OUTPUT_HDMI) { 2395 struct intel_digital_port *intel_dig_port = 2396 enc_to_dig_port(encoder); 2397 2398 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2399 * are ignored so nothing special needs to be done besides 2400 * enabling the port. 2401 */ 2402 I915_WRITE(DDI_BUF_CTL(port), 2403 intel_dig_port->saved_port_bits | 2404 DDI_BUF_CTL_ENABLE); 2405 } else if (type == INTEL_OUTPUT_EDP) { 2406 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2407 2408 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 2409 intel_dp_stop_link_train(intel_dp); 2410 2411 intel_edp_backlight_on(intel_dp); 2412 intel_psr_enable(intel_dp); 2413 intel_edp_drrs_enable(intel_dp); 2414 } 2415 2416 if (intel_crtc->config->has_audio) { 2417 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 2418 intel_audio_codec_enable(intel_encoder); 2419 } 2420 } 2421 2422 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 2423 { 2424 struct drm_encoder *encoder = &intel_encoder->base; 2425 struct drm_crtc *crtc = encoder->crtc; 2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2427 int type = intel_encoder->type; 2428 struct drm_device *dev = encoder->dev; 2429 struct drm_i915_private *dev_priv = dev->dev_private; 2430 2431 if (intel_crtc->config->has_audio) { 2432 intel_audio_codec_disable(intel_encoder); 2433 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 2434 } 2435 2436 if (type == INTEL_OUTPUT_EDP) { 2437 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2438 2439 intel_edp_drrs_disable(intel_dp); 2440 intel_psr_disable(intel_dp); 2441 intel_edp_backlight_off(intel_dp); 2442 } 2443 } 2444 2445 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, 2446 struct intel_shared_dpll *pll) 2447 { 2448 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 2449 POSTING_READ(WRPLL_CTL(pll->id)); 2450 udelay(20); 2451 } 2452 2453 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, 2454 struct intel_shared_dpll *pll) 2455 { 2456 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); 2457 POSTING_READ(SPLL_CTL); 2458 udelay(20); 2459 } 2460 2461 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 2462 struct intel_shared_dpll *pll) 2463 { 2464 uint32_t val; 2465 2466 val = I915_READ(WRPLL_CTL(pll->id)); 2467 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 2468 POSTING_READ(WRPLL_CTL(pll->id)); 2469 } 2470 2471 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 2472 struct intel_shared_dpll *pll) 2473 { 2474 uint32_t val; 2475 2476 val = I915_READ(SPLL_CTL); 2477 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 2478 POSTING_READ(SPLL_CTL); 2479 } 2480 2481 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, 2482 struct intel_shared_dpll *pll, 2483 struct intel_dpll_hw_state *hw_state) 2484 { 2485 uint32_t val; 2486 2487 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2488 return false; 2489 2490 val = I915_READ(WRPLL_CTL(pll->id)); 2491 hw_state->wrpll = val; 2492 2493 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 2494 2495 return val & WRPLL_PLL_ENABLE; 2496 } 2497 2498 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 2499 struct intel_shared_dpll *pll, 2500 struct intel_dpll_hw_state *hw_state) 2501 { 2502 uint32_t val; 2503 2504 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2505 return false; 2506 2507 val = I915_READ(SPLL_CTL); 2508 hw_state->spll = val; 2509 2510 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 2511 2512 return val & SPLL_PLL_ENABLE; 2513 } 2514 2515 2516 static const char * const hsw_ddi_pll_names[] = { 2517 "WRPLL 1", 2518 "WRPLL 2", 2519 "SPLL" 2520 }; 2521 2522 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 2523 { 2524 int i; 2525 2526 dev_priv->num_shared_dpll = 3; 2527 2528 for (i = 0; i < 2; i++) { 2529 dev_priv->shared_dplls[i].id = i; 2530 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2531 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; 2532 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; 2533 dev_priv->shared_dplls[i].get_hw_state = 2534 hsw_ddi_wrpll_get_hw_state; 2535 } 2536 2537 /* SPLL is special, but needs to be initialized anyway.. */ 2538 dev_priv->shared_dplls[i].id = i; 2539 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2540 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; 2541 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; 2542 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; 2543 2544 } 2545 2546 static const char * const skl_ddi_pll_names[] = { 2547 "DPLL 1", 2548 "DPLL 2", 2549 "DPLL 3", 2550 }; 2551 2552 struct skl_dpll_regs { 2553 i915_reg_t ctl, cfgcr1, cfgcr2; 2554 }; 2555 2556 /* this array is indexed by the *shared* pll id */ 2557 static const struct skl_dpll_regs skl_dpll_regs[3] = { 2558 { 2559 /* DPLL 1 */ 2560 .ctl = LCPLL2_CTL, 2561 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), 2562 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), 2563 }, 2564 { 2565 /* DPLL 2 */ 2566 .ctl = WRPLL_CTL(0), 2567 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), 2568 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), 2569 }, 2570 { 2571 /* DPLL 3 */ 2572 .ctl = WRPLL_CTL(1), 2573 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), 2574 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), 2575 }, 2576 }; 2577 2578 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 2579 struct intel_shared_dpll *pll) 2580 { 2581 uint32_t val; 2582 unsigned int dpll; 2583 const struct skl_dpll_regs *regs = skl_dpll_regs; 2584 2585 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2586 dpll = pll->id + 1; 2587 2588 val = I915_READ(DPLL_CTRL1); 2589 2590 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 2591 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2592 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 2593 2594 I915_WRITE(DPLL_CTRL1, val); 2595 POSTING_READ(DPLL_CTRL1); 2596 2597 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 2598 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 2599 POSTING_READ(regs[pll->id].cfgcr1); 2600 POSTING_READ(regs[pll->id].cfgcr2); 2601 2602 /* the enable bit is always bit 31 */ 2603 I915_WRITE(regs[pll->id].ctl, 2604 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 2605 2606 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 2607 DRM_ERROR("DPLL %d not locked\n", dpll); 2608 } 2609 2610 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 2611 struct intel_shared_dpll *pll) 2612 { 2613 const struct skl_dpll_regs *regs = skl_dpll_regs; 2614 2615 /* the enable bit is always bit 31 */ 2616 I915_WRITE(regs[pll->id].ctl, 2617 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 2618 POSTING_READ(regs[pll->id].ctl); 2619 } 2620 2621 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2622 struct intel_shared_dpll *pll, 2623 struct intel_dpll_hw_state *hw_state) 2624 { 2625 uint32_t val; 2626 unsigned int dpll; 2627 const struct skl_dpll_regs *regs = skl_dpll_regs; 2628 bool ret; 2629 2630 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2631 return false; 2632 2633 ret = false; 2634 2635 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2636 dpll = pll->id + 1; 2637 2638 val = I915_READ(regs[pll->id].ctl); 2639 if (!(val & LCPLL_PLL_ENABLE)) 2640 goto out; 2641 2642 val = I915_READ(DPLL_CTRL1); 2643 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 2644 2645 /* avoid reading back stale values if HDMI mode is not enabled */ 2646 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 2647 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 2648 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 2649 } 2650 ret = true; 2651 2652 out: 2653 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 2654 2655 return ret; 2656 } 2657 2658 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 2659 { 2660 int i; 2661 2662 dev_priv->num_shared_dpll = 3; 2663 2664 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2665 dev_priv->shared_dplls[i].id = i; 2666 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 2667 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 2668 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 2669 dev_priv->shared_dplls[i].get_hw_state = 2670 skl_ddi_pll_get_hw_state; 2671 } 2672 } 2673 2674 static void broxton_phy_init(struct drm_i915_private *dev_priv, 2675 enum dpio_phy phy) 2676 { 2677 enum port port; 2678 uint32_t val; 2679 2680 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 2681 val |= GT_DISPLAY_POWER_ON(phy); 2682 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 2683 2684 /* Considering 10ms timeout until BSpec is updated */ 2685 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) 2686 DRM_ERROR("timeout during PHY%d power on\n", phy); 2687 2688 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); 2689 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { 2690 int lane; 2691 2692 for (lane = 0; lane < 4; lane++) { 2693 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); 2694 /* 2695 * Note that on CHV this flag is called UPAR, but has 2696 * the same function. 2697 */ 2698 val &= ~LATENCY_OPTIM; 2699 if (lane != 1) 2700 val |= LATENCY_OPTIM; 2701 2702 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); 2703 } 2704 } 2705 2706 /* Program PLL Rcomp code offset */ 2707 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 2708 val &= ~IREF0RC_OFFSET_MASK; 2709 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 2710 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 2711 2712 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 2713 val &= ~IREF1RC_OFFSET_MASK; 2714 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 2715 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 2716 2717 /* Program power gating */ 2718 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 2719 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 2720 SUS_CLK_CONFIG; 2721 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 2722 2723 if (phy == DPIO_PHY0) { 2724 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); 2725 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 2726 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); 2727 } 2728 2729 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); 2730 val &= ~OCL2_LDOFUSE_PWR_DIS; 2731 /* 2732 * On PHY1 disable power on the second channel, since no port is 2733 * connected there. On PHY0 both channels have a port, so leave it 2734 * enabled. 2735 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should 2736 * power down the second channel on PHY0 as well. 2737 */ 2738 if (phy == DPIO_PHY1) 2739 val |= OCL2_LDOFUSE_PWR_DIS; 2740 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); 2741 2742 if (phy == DPIO_PHY0) { 2743 uint32_t grc_code; 2744 /* 2745 * PHY0 isn't connected to an RCOMP resistor so copy over 2746 * the corresponding calibrated value from PHY1, and disable 2747 * the automatic calibration on PHY0. 2748 */ 2749 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, 2750 10)) 2751 DRM_ERROR("timeout waiting for PHY1 GRC\n"); 2752 2753 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); 2754 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 2755 grc_code = val << GRC_CODE_FAST_SHIFT | 2756 val << GRC_CODE_SLOW_SHIFT | 2757 val; 2758 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); 2759 2760 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); 2761 val |= GRC_DIS | GRC_RDY_OVRD; 2762 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); 2763 } 2764 2765 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2766 val |= COMMON_RESET_DIS; 2767 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2768 } 2769 2770 void broxton_ddi_phy_init(struct drm_device *dev) 2771 { 2772 /* Enable PHY1 first since it provides Rcomp for PHY0 */ 2773 broxton_phy_init(dev->dev_private, DPIO_PHY1); 2774 broxton_phy_init(dev->dev_private, DPIO_PHY0); 2775 } 2776 2777 static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 2778 enum dpio_phy phy) 2779 { 2780 uint32_t val; 2781 2782 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2783 val &= ~COMMON_RESET_DIS; 2784 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2785 } 2786 2787 void broxton_ddi_phy_uninit(struct drm_device *dev) 2788 { 2789 struct drm_i915_private *dev_priv = dev->dev_private; 2790 2791 broxton_phy_uninit(dev_priv, DPIO_PHY1); 2792 broxton_phy_uninit(dev_priv, DPIO_PHY0); 2793 2794 /* FIXME: do this in broxton_phy_uninit per phy */ 2795 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); 2796 } 2797 2798 static const char * const bxt_ddi_pll_names[] = { 2799 "PORT PLL A", 2800 "PORT PLL B", 2801 "PORT PLL C", 2802 }; 2803 2804 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 2805 struct intel_shared_dpll *pll) 2806 { 2807 uint32_t temp; 2808 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2809 2810 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2811 temp &= ~PORT_PLL_REF_SEL; 2812 /* Non-SSC reference */ 2813 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2814 2815 /* Disable 10 bit clock */ 2816 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2817 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2818 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2819 2820 /* Write P1 & P2 */ 2821 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2822 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 2823 temp |= pll->config.hw_state.ebb0; 2824 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 2825 2826 /* Write M2 integer */ 2827 temp = I915_READ(BXT_PORT_PLL(port, 0)); 2828 temp &= ~PORT_PLL_M2_MASK; 2829 temp |= pll->config.hw_state.pll0; 2830 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 2831 2832 /* Write N */ 2833 temp = I915_READ(BXT_PORT_PLL(port, 1)); 2834 temp &= ~PORT_PLL_N_MASK; 2835 temp |= pll->config.hw_state.pll1; 2836 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 2837 2838 /* Write M2 fraction */ 2839 temp = I915_READ(BXT_PORT_PLL(port, 2)); 2840 temp &= ~PORT_PLL_M2_FRAC_MASK; 2841 temp |= pll->config.hw_state.pll2; 2842 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 2843 2844 /* Write M2 fraction enable */ 2845 temp = I915_READ(BXT_PORT_PLL(port, 3)); 2846 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 2847 temp |= pll->config.hw_state.pll3; 2848 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 2849 2850 /* Write coeff */ 2851 temp = I915_READ(BXT_PORT_PLL(port, 6)); 2852 temp &= ~PORT_PLL_PROP_COEFF_MASK; 2853 temp &= ~PORT_PLL_INT_COEFF_MASK; 2854 temp &= ~PORT_PLL_GAIN_CTL_MASK; 2855 temp |= pll->config.hw_state.pll6; 2856 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 2857 2858 /* Write calibration val */ 2859 temp = I915_READ(BXT_PORT_PLL(port, 8)); 2860 temp &= ~PORT_PLL_TARGET_CNT_MASK; 2861 temp |= pll->config.hw_state.pll8; 2862 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 2863 2864 temp = I915_READ(BXT_PORT_PLL(port, 9)); 2865 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 2866 temp |= pll->config.hw_state.pll9; 2867 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 2868 2869 temp = I915_READ(BXT_PORT_PLL(port, 10)); 2870 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 2871 temp &= ~PORT_PLL_DCO_AMP_MASK; 2872 temp |= pll->config.hw_state.pll10; 2873 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 2874 2875 /* Recalibrate with new settings */ 2876 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2877 temp |= PORT_PLL_RECALIBRATE; 2878 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2879 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2880 temp |= pll->config.hw_state.ebb4; 2881 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2882 2883 /* Enable PLL */ 2884 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2885 temp |= PORT_PLL_ENABLE; 2886 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2887 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2888 2889 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & 2890 PORT_PLL_LOCK), 200)) 2891 DRM_ERROR("PLL %d not locked\n", port); 2892 2893 /* 2894 * While we write to the group register to program all lanes at once we 2895 * can read only lane registers and we pick lanes 0/1 for that. 2896 */ 2897 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2898 temp &= ~LANE_STAGGER_MASK; 2899 temp &= ~LANESTAGGER_STRAP_OVRD; 2900 temp |= pll->config.hw_state.pcsdw12; 2901 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 2902 } 2903 2904 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 2905 struct intel_shared_dpll *pll) 2906 { 2907 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2908 uint32_t temp; 2909 2910 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2911 temp &= ~PORT_PLL_ENABLE; 2912 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2913 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2914 } 2915 2916 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2917 struct intel_shared_dpll *pll, 2918 struct intel_dpll_hw_state *hw_state) 2919 { 2920 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2921 uint32_t val; 2922 bool ret; 2923 2924 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2925 return false; 2926 2927 ret = false; 2928 2929 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2930 if (!(val & PORT_PLL_ENABLE)) 2931 goto out; 2932 2933 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2934 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; 2935 2936 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2937 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; 2938 2939 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 2940 hw_state->pll0 &= PORT_PLL_M2_MASK; 2941 2942 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 2943 hw_state->pll1 &= PORT_PLL_N_MASK; 2944 2945 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 2946 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; 2947 2948 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 2949 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; 2950 2951 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 2952 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | 2953 PORT_PLL_INT_COEFF_MASK | 2954 PORT_PLL_GAIN_CTL_MASK; 2955 2956 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 2957 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; 2958 2959 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); 2960 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; 2961 2962 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 2963 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | 2964 PORT_PLL_DCO_AMP_MASK; 2965 2966 /* 2967 * While we write to the group register to program all lanes at once we 2968 * can read only lane registers. We configure all lanes the same way, so 2969 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 2970 */ 2971 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2972 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) 2973 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 2974 hw_state->pcsdw12, 2975 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 2976 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; 2977 2978 ret = true; 2979 2980 out: 2981 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); 2982 2983 return ret; 2984 } 2985 2986 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) 2987 { 2988 int i; 2989 2990 dev_priv->num_shared_dpll = 3; 2991 2992 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2993 dev_priv->shared_dplls[i].id = i; 2994 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; 2995 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; 2996 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; 2997 dev_priv->shared_dplls[i].get_hw_state = 2998 bxt_ddi_pll_get_hw_state; 2999 } 3000 } 3001 3002 void intel_ddi_pll_init(struct drm_device *dev) 3003 { 3004 struct drm_i915_private *dev_priv = dev->dev_private; 3005 uint32_t val = I915_READ(LCPLL_CTL); 3006 3007 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 3008 skl_shared_dplls_init(dev_priv); 3009 else if (IS_BROXTON(dev)) 3010 bxt_shared_dplls_init(dev_priv); 3011 else 3012 hsw_shared_dplls_init(dev_priv); 3013 3014 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 3015 int cdclk_freq; 3016 3017 cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 3018 dev_priv->skl_boot_cdclk = cdclk_freq; 3019 if (skl_sanitize_cdclk(dev_priv)) 3020 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); 3021 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 3022 DRM_ERROR("LCPLL1 is disabled\n"); 3023 } else if (IS_BROXTON(dev)) { 3024 broxton_init_cdclk(dev); 3025 broxton_ddi_phy_init(dev); 3026 } else { 3027 /* 3028 * The LCPLL register should be turned on by the BIOS. For now 3029 * let's just check its state and print errors in case 3030 * something is wrong. Don't even try to turn it on. 3031 */ 3032 3033 if (val & LCPLL_CD_SOURCE_FCLK) 3034 DRM_ERROR("CDCLK source is not LCPLL\n"); 3035 3036 if (val & LCPLL_PLL_DISABLE) 3037 DRM_ERROR("LCPLL is disabled\n"); 3038 } 3039 } 3040 3041 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 3042 { 3043 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3044 struct drm_i915_private *dev_priv = 3045 to_i915(intel_dig_port->base.base.dev); 3046 enum port port = intel_dig_port->port; 3047 uint32_t val; 3048 bool wait = false; 3049 3050 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 3051 val = I915_READ(DDI_BUF_CTL(port)); 3052 if (val & DDI_BUF_CTL_ENABLE) { 3053 val &= ~DDI_BUF_CTL_ENABLE; 3054 I915_WRITE(DDI_BUF_CTL(port), val); 3055 wait = true; 3056 } 3057 3058 val = I915_READ(DP_TP_CTL(port)); 3059 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3060 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3061 I915_WRITE(DP_TP_CTL(port), val); 3062 POSTING_READ(DP_TP_CTL(port)); 3063 3064 if (wait) 3065 intel_wait_ddi_buf_idle(dev_priv, port); 3066 } 3067 3068 val = DP_TP_CTL_ENABLE | 3069 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 3070 if (intel_dp->is_mst) 3071 val |= DP_TP_CTL_MODE_MST; 3072 else { 3073 val |= DP_TP_CTL_MODE_SST; 3074 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3075 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3076 } 3077 I915_WRITE(DP_TP_CTL(port), val); 3078 POSTING_READ(DP_TP_CTL(port)); 3079 3080 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3081 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 3082 POSTING_READ(DDI_BUF_CTL(port)); 3083 3084 udelay(600); 3085 } 3086 3087 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 3088 { 3089 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 3090 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 3091 uint32_t val; 3092 3093 intel_ddi_post_disable(intel_encoder); 3094 3095 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3096 val &= ~FDI_RX_ENABLE; 3097 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3098 3099 val = I915_READ(FDI_RX_MISC(PIPE_A)); 3100 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3101 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3102 I915_WRITE(FDI_RX_MISC(PIPE_A), val); 3103 3104 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3105 val &= ~FDI_PCDCLK; 3106 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3107 3108 val = I915_READ(FDI_RX_CTL(PIPE_A)); 3109 val &= ~FDI_RX_PLL_ENABLE; 3110 I915_WRITE(FDI_RX_CTL(PIPE_A), val); 3111 } 3112 3113 void intel_ddi_get_config(struct intel_encoder *encoder, 3114 struct intel_crtc_state *pipe_config) 3115 { 3116 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 3117 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 3118 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3119 struct intel_hdmi *intel_hdmi; 3120 u32 temp, flags = 0; 3121 3122 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3123 if (temp & TRANS_DDI_PHSYNC) 3124 flags |= DRM_MODE_FLAG_PHSYNC; 3125 else 3126 flags |= DRM_MODE_FLAG_NHSYNC; 3127 if (temp & TRANS_DDI_PVSYNC) 3128 flags |= DRM_MODE_FLAG_PVSYNC; 3129 else 3130 flags |= DRM_MODE_FLAG_NVSYNC; 3131 3132 pipe_config->base.adjusted_mode.flags |= flags; 3133 3134 switch (temp & TRANS_DDI_BPC_MASK) { 3135 case TRANS_DDI_BPC_6: 3136 pipe_config->pipe_bpp = 18; 3137 break; 3138 case TRANS_DDI_BPC_8: 3139 pipe_config->pipe_bpp = 24; 3140 break; 3141 case TRANS_DDI_BPC_10: 3142 pipe_config->pipe_bpp = 30; 3143 break; 3144 case TRANS_DDI_BPC_12: 3145 pipe_config->pipe_bpp = 36; 3146 break; 3147 default: 3148 break; 3149 } 3150 3151 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3152 case TRANS_DDI_MODE_SELECT_HDMI: 3153 pipe_config->has_hdmi_sink = true; 3154 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 3155 3156 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) 3157 pipe_config->has_infoframe = true; 3158 break; 3159 case TRANS_DDI_MODE_SELECT_DVI: 3160 case TRANS_DDI_MODE_SELECT_FDI: 3161 break; 3162 case TRANS_DDI_MODE_SELECT_DP_SST: 3163 case TRANS_DDI_MODE_SELECT_DP_MST: 3164 pipe_config->has_dp_encoder = true; 3165 pipe_config->lane_count = 3166 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3167 intel_dp_get_m_n(intel_crtc, pipe_config); 3168 break; 3169 default: 3170 break; 3171 } 3172 3173 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 3174 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 3175 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 3176 pipe_config->has_audio = true; 3177 } 3178 3179 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 3180 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 3181 /* 3182 * This is a big fat ugly hack. 3183 * 3184 * Some machines in UEFI boot mode provide us a VBT that has 18 3185 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3186 * unknown we fail to light up. Yet the same BIOS boots up with 3187 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3188 * max, not what it tells us to use. 3189 * 3190 * Note: This will still be broken if the eDP panel is not lit 3191 * up by the BIOS, and thus we can't get the mode at module 3192 * load. 3193 */ 3194 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3195 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 3196 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 3197 } 3198 3199 intel_ddi_clock_get(encoder, pipe_config); 3200 } 3201 3202 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 3203 struct intel_crtc_state *pipe_config) 3204 { 3205 int type = encoder->type; 3206 int port = intel_ddi_get_encoder_port(encoder); 3207 3208 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 3209 3210 if (port == PORT_A) 3211 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3212 3213 if (type == INTEL_OUTPUT_HDMI) 3214 return intel_hdmi_compute_config(encoder, pipe_config); 3215 else 3216 return intel_dp_compute_config(encoder, pipe_config); 3217 } 3218 3219 static const struct drm_encoder_funcs intel_ddi_funcs = { 3220 .reset = intel_dp_encoder_reset, 3221 .destroy = intel_dp_encoder_destroy, 3222 }; 3223 3224 static struct intel_connector * 3225 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 3226 { 3227 struct intel_connector *connector; 3228 enum port port = intel_dig_port->port; 3229 3230 connector = intel_connector_alloc(); 3231 if (!connector) 3232 return NULL; 3233 3234 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 3235 if (!intel_dp_init_connector(intel_dig_port, connector)) { 3236 kfree(connector); 3237 return NULL; 3238 } 3239 3240 return connector; 3241 } 3242 3243 static struct intel_connector * 3244 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 3245 { 3246 struct intel_connector *connector; 3247 enum port port = intel_dig_port->port; 3248 3249 connector = intel_connector_alloc(); 3250 if (!connector) 3251 return NULL; 3252 3253 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 3254 intel_hdmi_init_connector(intel_dig_port, connector); 3255 3256 return connector; 3257 } 3258 3259 void intel_ddi_init(struct drm_device *dev, enum port port) 3260 { 3261 struct drm_i915_private *dev_priv = dev->dev_private; 3262 struct intel_digital_port *intel_dig_port; 3263 struct intel_encoder *intel_encoder; 3264 struct drm_encoder *encoder; 3265 bool init_hdmi, init_dp; 3266 int max_lanes; 3267 3268 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { 3269 switch (port) { 3270 case PORT_A: 3271 max_lanes = 4; 3272 break; 3273 case PORT_E: 3274 max_lanes = 0; 3275 break; 3276 default: 3277 max_lanes = 4; 3278 break; 3279 } 3280 } else { 3281 switch (port) { 3282 case PORT_A: 3283 max_lanes = 2; 3284 break; 3285 case PORT_E: 3286 max_lanes = 2; 3287 break; 3288 default: 3289 max_lanes = 4; 3290 break; 3291 } 3292 } 3293 3294 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 3295 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 3296 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 3297 if (!init_dp && !init_hdmi) { 3298 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 3299 port_name(port)); 3300 return; 3301 } 3302 3303 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3304 if (!intel_dig_port) 3305 return; 3306 3307 intel_encoder = &intel_dig_port->base; 3308 encoder = &intel_encoder->base; 3309 3310 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 3311 DRM_MODE_ENCODER_TMDS, NULL); 3312 3313 intel_encoder->compute_config = intel_ddi_compute_config; 3314 intel_encoder->enable = intel_enable_ddi; 3315 intel_encoder->pre_enable = intel_ddi_pre_enable; 3316 intel_encoder->disable = intel_disable_ddi; 3317 intel_encoder->post_disable = intel_ddi_post_disable; 3318 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 3319 intel_encoder->get_config = intel_ddi_get_config; 3320 intel_encoder->suspend = intel_dp_encoder_suspend; 3321 3322 intel_dig_port->port = port; 3323 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 3324 (DDI_BUF_PORT_REVERSAL | 3325 DDI_A_4_LANES); 3326 3327 /* 3328 * Bspec says that DDI_A_4_LANES is the only supported configuration 3329 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP 3330 * wasn't lit up at boot. Force this bit on in our internal 3331 * configuration so that we use the proper lane count for our 3332 * calculations. 3333 */ 3334 if (IS_BROXTON(dev) && port == PORT_A) { 3335 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { 3336 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); 3337 intel_dig_port->saved_port_bits |= DDI_A_4_LANES; 3338 max_lanes = 4; 3339 } 3340 } 3341 3342 intel_dig_port->max_lanes = max_lanes; 3343 3344 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 3345 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3346 intel_encoder->cloneable = 0; 3347 3348 if (init_dp) { 3349 if (!intel_ddi_init_dp_connector(intel_dig_port)) 3350 goto err; 3351 3352 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 3353 /* 3354 * On BXT A0/A1, sw needs to activate DDIA HPD logic and 3355 * interrupts to check the external panel connection. 3356 */ 3357 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) 3358 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; 3359 else 3360 dev_priv->hotplug.irq_port[port] = intel_dig_port; 3361 } 3362 3363 /* In theory we don't need the encoder->type check, but leave it just in 3364 * case we have some really bad VBTs... */ 3365 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 3366 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 3367 goto err; 3368 } 3369 3370 return; 3371 3372 err: 3373 drm_encoder_cleanup(encoder); 3374 kfree(intel_dig_port); 3375 } 3376