1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drmP.h> 29 #include <drm/i915_drm.h> 30 #include "i915_drv.h" 31 #include "intel_drv.h" 32 33 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 34 * them for both DP and FDI transports, allowing those ports to 35 * automatically adapt to HDMI connections as well 36 */ 37 static const u32 hsw_ddi_translations_dp[] = { 38 0x00FFFFFF, 0x0006000E, /* DP parameters */ 39 0x00D75FFF, 0x0005000A, 40 0x00C30FFF, 0x00040006, 41 0x80AAAFFF, 0x000B0000, 42 0x00FFFFFF, 0x0005000A, 43 0x00D75FFF, 0x000C0004, 44 0x80C30FFF, 0x000B0000, 45 0x00FFFFFF, 0x00040006, 46 0x80D75FFF, 0x000B0000, 47 0x00FFFFFF, 0x00040006 /* HDMI parameters */ 48 }; 49 50 static const u32 hsw_ddi_translations_fdi[] = { 51 0x00FFFFFF, 0x0007000E, /* FDI parameters */ 52 0x00D75FFF, 0x000F000A, 53 0x00C30FFF, 0x00060006, 54 0x00AAAFFF, 0x001E0000, 55 0x00FFFFFF, 0x000F000A, 56 0x00D75FFF, 0x00160004, 57 0x00C30FFF, 0x001E0000, 58 0x00FFFFFF, 0x00060006, 59 0x00D75FFF, 0x001E0000, 60 0x00FFFFFF, 0x00040006 /* HDMI parameters */ 61 }; 62 63 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 64 { 65 struct drm_encoder *encoder = &intel_encoder->base; 66 int type = intel_encoder->type; 67 68 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || 69 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { 70 struct intel_digital_port *intel_dig_port = 71 enc_to_dig_port(encoder); 72 return intel_dig_port->port; 73 74 } else if (type == INTEL_OUTPUT_ANALOG) { 75 return PORT_E; 76 77 } else { 78 DRM_ERROR("Invalid DDI encoder type %d\n", type); 79 BUG(); 80 } 81 } 82 83 /* On Haswell, DDI port buffers must be programmed with correct values 84 * in advance. The buffer values are different for FDI and DP modes, 85 * but the HDMI/DVI fields are shared among those. So we program the DDI 86 * in either FDI or DP modes only, as HDMI connections will work with both 87 * of those 88 */ 89 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode) 90 { 91 struct drm_i915_private *dev_priv = dev->dev_private; 92 u32 reg; 93 int i; 94 const u32 *ddi_translations = ((use_fdi_mode) ? 95 hsw_ddi_translations_fdi : 96 hsw_ddi_translations_dp); 97 98 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n", 99 port_name(port), 100 use_fdi_mode ? "FDI" : "DP"); 101 102 WARN((use_fdi_mode && (port != PORT_E)), 103 "Programming port %c in FDI mode, this probably will not work.\n", 104 port_name(port)); 105 106 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { 107 I915_WRITE(reg, ddi_translations[i]); 108 reg += 4; 109 } 110 } 111 112 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 113 * mode and port E for FDI. 114 */ 115 void intel_prepare_ddi(struct drm_device *dev) 116 { 117 int port; 118 119 if (IS_HASWELL(dev)) { 120 for (port = PORT_A; port < PORT_E; port++) 121 intel_prepare_ddi_buffers(dev, port, false); 122 123 /* DDI E is the suggested one to work in FDI mode, so program is as such by 124 * default. It will have to be re-programmed in case a digital DP output 125 * will be detected on it 126 */ 127 intel_prepare_ddi_buffers(dev, PORT_E, true); 128 } 129 } 130 131 static const long hsw_ddi_buf_ctl_values[] = { 132 DDI_BUF_EMP_400MV_0DB_HSW, 133 DDI_BUF_EMP_400MV_3_5DB_HSW, 134 DDI_BUF_EMP_400MV_6DB_HSW, 135 DDI_BUF_EMP_400MV_9_5DB_HSW, 136 DDI_BUF_EMP_600MV_0DB_HSW, 137 DDI_BUF_EMP_600MV_3_5DB_HSW, 138 DDI_BUF_EMP_600MV_6DB_HSW, 139 DDI_BUF_EMP_800MV_0DB_HSW, 140 DDI_BUF_EMP_800MV_3_5DB_HSW 141 }; 142 143 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 144 enum port port) 145 { 146 uint32_t reg = DDI_BUF_CTL(port); 147 int i; 148 149 for (i = 0; i < 8; i++) { 150 udelay(1); 151 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 152 return; 153 } 154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 155 } 156 157 /* Starting with Haswell, different DDI ports can work in FDI mode for 158 * connection to the PCH-located connectors. For this, it is necessary to train 159 * both the DDI port and PCH receiver for the desired DDI buffer settings. 160 * 161 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 162 * please note that when FDI mode is active on DDI E, it shares 2 lines with 163 * DDI A (which is used for eDP) 164 */ 165 166 void hsw_fdi_link_train(struct drm_crtc *crtc) 167 { 168 struct drm_device *dev = crtc->dev; 169 struct drm_i915_private *dev_priv = dev->dev_private; 170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 171 u32 temp, i, rx_ctl_val; 172 173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 174 * mode set "sequence for CRT port" document: 175 * - TP1 to TP2 time with the default value 176 * - FDI delay to 90h 177 */ 178 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | 179 FDI_RX_PWRDN_LANE0_VAL(2) | 180 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 181 182 /* Enable the PCH Receiver FDI PLL */ 183 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 184 FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19); 185 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 186 POSTING_READ(_FDI_RXA_CTL); 187 udelay(220); 188 189 /* Switch from Rawclk to PCDclk */ 190 rx_ctl_val |= FDI_PCDCLK; 191 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 192 193 /* Configure Port Clock Select */ 194 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); 195 196 /* Start the training iterating through available voltages and emphasis, 197 * testing each value twice. */ 198 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { 199 /* Configure DP_TP_CTL with auto-training */ 200 I915_WRITE(DP_TP_CTL(PORT_E), 201 DP_TP_CTL_FDI_AUTOTRAIN | 202 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 203 DP_TP_CTL_LINK_TRAIN_PAT1 | 204 DP_TP_CTL_ENABLE); 205 206 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 207 * DDI E does not support port reversal, the functionality is 208 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 209 * port reversal bit */ 210 I915_WRITE(DDI_BUF_CTL(PORT_E), 211 DDI_BUF_CTL_ENABLE | 212 ((intel_crtc->fdi_lanes - 1) << 1) | 213 hsw_ddi_buf_ctl_values[i / 2]); 214 POSTING_READ(DDI_BUF_CTL(PORT_E)); 215 216 udelay(600); 217 218 /* Program PCH FDI Receiver TU */ 219 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); 220 221 /* Enable PCH FDI Receiver with auto-training */ 222 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 223 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 224 POSTING_READ(_FDI_RXA_CTL); 225 226 /* Wait for FDI receiver lane calibration */ 227 udelay(30); 228 229 /* Unset FDI_RX_MISC pwrdn lanes */ 230 temp = I915_READ(_FDI_RXA_MISC); 231 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 232 I915_WRITE(_FDI_RXA_MISC, temp); 233 POSTING_READ(_FDI_RXA_MISC); 234 235 /* Wait for FDI auto training time */ 236 udelay(5); 237 238 temp = I915_READ(DP_TP_STATUS(PORT_E)); 239 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 240 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 241 242 /* Enable normal pixel sending for FDI */ 243 I915_WRITE(DP_TP_CTL(PORT_E), 244 DP_TP_CTL_FDI_AUTOTRAIN | 245 DP_TP_CTL_LINK_TRAIN_NORMAL | 246 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 247 DP_TP_CTL_ENABLE); 248 249 return; 250 } 251 252 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 253 temp &= ~DDI_BUF_CTL_ENABLE; 254 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 255 POSTING_READ(DDI_BUF_CTL(PORT_E)); 256 257 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 258 temp = I915_READ(DP_TP_CTL(PORT_E)); 259 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 260 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 261 I915_WRITE(DP_TP_CTL(PORT_E), temp); 262 POSTING_READ(DP_TP_CTL(PORT_E)); 263 264 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 265 266 rx_ctl_val &= ~FDI_RX_ENABLE; 267 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 268 POSTING_READ(_FDI_RXA_CTL); 269 270 /* Reset FDI_RX_MISC pwrdn lanes */ 271 temp = I915_READ(_FDI_RXA_MISC); 272 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 273 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 274 I915_WRITE(_FDI_RXA_MISC, temp); 275 POSTING_READ(_FDI_RXA_MISC); 276 } 277 278 DRM_ERROR("FDI link training failed!\n"); 279 } 280 281 /* WRPLL clock dividers */ 282 struct wrpll_tmds_clock { 283 u32 clock; 284 u16 p; /* Post divider */ 285 u16 n2; /* Feedback divider */ 286 u16 r2; /* Reference divider */ 287 }; 288 289 /* Table of matching values for WRPLL clocks programming for each frequency. 290 * The code assumes this table is sorted. */ 291 static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = { 292 {19750, 38, 25, 18}, 293 {20000, 48, 32, 18}, 294 {21000, 36, 21, 15}, 295 {21912, 42, 29, 17}, 296 {22000, 36, 22, 15}, 297 {23000, 36, 23, 15}, 298 {23500, 40, 40, 23}, 299 {23750, 26, 16, 14}, 300 {24000, 36, 24, 15}, 301 {25000, 36, 25, 15}, 302 {25175, 26, 40, 33}, 303 {25200, 30, 21, 15}, 304 {26000, 36, 26, 15}, 305 {27000, 30, 21, 14}, 306 {27027, 18, 100, 111}, 307 {27500, 30, 29, 19}, 308 {28000, 34, 30, 17}, 309 {28320, 26, 30, 22}, 310 {28322, 32, 42, 25}, 311 {28750, 24, 23, 18}, 312 {29000, 30, 29, 18}, 313 {29750, 32, 30, 17}, 314 {30000, 30, 25, 15}, 315 {30750, 30, 41, 24}, 316 {31000, 30, 31, 18}, 317 {31500, 30, 28, 16}, 318 {32000, 30, 32, 18}, 319 {32500, 28, 32, 19}, 320 {33000, 24, 22, 15}, 321 {34000, 28, 30, 17}, 322 {35000, 26, 32, 19}, 323 {35500, 24, 30, 19}, 324 {36000, 26, 26, 15}, 325 {36750, 26, 46, 26}, 326 {37000, 24, 23, 14}, 327 {37762, 22, 40, 26}, 328 {37800, 20, 21, 15}, 329 {38000, 24, 27, 16}, 330 {38250, 24, 34, 20}, 331 {39000, 24, 26, 15}, 332 {40000, 24, 32, 18}, 333 {40500, 20, 21, 14}, 334 {40541, 22, 147, 89}, 335 {40750, 18, 19, 14}, 336 {41000, 16, 17, 14}, 337 {41500, 22, 44, 26}, 338 {41540, 22, 44, 26}, 339 {42000, 18, 21, 15}, 340 {42500, 22, 45, 26}, 341 {43000, 20, 43, 27}, 342 {43163, 20, 24, 15}, 343 {44000, 18, 22, 15}, 344 {44900, 20, 108, 65}, 345 {45000, 20, 25, 15}, 346 {45250, 20, 52, 31}, 347 {46000, 18, 23, 15}, 348 {46750, 20, 45, 26}, 349 {47000, 20, 40, 23}, 350 {48000, 18, 24, 15}, 351 {49000, 18, 49, 30}, 352 {49500, 16, 22, 15}, 353 {50000, 18, 25, 15}, 354 {50500, 18, 32, 19}, 355 {51000, 18, 34, 20}, 356 {52000, 18, 26, 15}, 357 {52406, 14, 34, 25}, 358 {53000, 16, 22, 14}, 359 {54000, 16, 24, 15}, 360 {54054, 16, 173, 108}, 361 {54500, 14, 24, 17}, 362 {55000, 12, 22, 18}, 363 {56000, 14, 45, 31}, 364 {56250, 16, 25, 15}, 365 {56750, 14, 25, 17}, 366 {57000, 16, 27, 16}, 367 {58000, 16, 43, 25}, 368 {58250, 16, 38, 22}, 369 {58750, 16, 40, 23}, 370 {59000, 14, 26, 17}, 371 {59341, 14, 40, 26}, 372 {59400, 16, 44, 25}, 373 {60000, 16, 32, 18}, 374 {60500, 12, 39, 29}, 375 {61000, 14, 49, 31}, 376 {62000, 14, 37, 23}, 377 {62250, 14, 42, 26}, 378 {63000, 12, 21, 15}, 379 {63500, 14, 28, 17}, 380 {64000, 12, 27, 19}, 381 {65000, 14, 32, 19}, 382 {65250, 12, 29, 20}, 383 {65500, 12, 32, 22}, 384 {66000, 12, 22, 15}, 385 {66667, 14, 38, 22}, 386 {66750, 10, 21, 17}, 387 {67000, 14, 33, 19}, 388 {67750, 14, 58, 33}, 389 {68000, 14, 30, 17}, 390 {68179, 14, 46, 26}, 391 {68250, 14, 46, 26}, 392 {69000, 12, 23, 15}, 393 {70000, 12, 28, 18}, 394 {71000, 12, 30, 19}, 395 {72000, 12, 24, 15}, 396 {73000, 10, 23, 17}, 397 {74000, 12, 23, 14}, 398 {74176, 8, 100, 91}, 399 {74250, 10, 22, 16}, 400 {74481, 12, 43, 26}, 401 {74500, 10, 29, 21}, 402 {75000, 12, 25, 15}, 403 {75250, 10, 39, 28}, 404 {76000, 12, 27, 16}, 405 {77000, 12, 53, 31}, 406 {78000, 12, 26, 15}, 407 {78750, 12, 28, 16}, 408 {79000, 10, 38, 26}, 409 {79500, 10, 28, 19}, 410 {80000, 12, 32, 18}, 411 {81000, 10, 21, 14}, 412 {81081, 6, 100, 111}, 413 {81624, 8, 29, 24}, 414 {82000, 8, 17, 14}, 415 {83000, 10, 40, 26}, 416 {83950, 10, 28, 18}, 417 {84000, 10, 28, 18}, 418 {84750, 6, 16, 17}, 419 {85000, 6, 17, 18}, 420 {85250, 10, 30, 19}, 421 {85750, 10, 27, 17}, 422 {86000, 10, 43, 27}, 423 {87000, 10, 29, 18}, 424 {88000, 10, 44, 27}, 425 {88500, 10, 41, 25}, 426 {89000, 10, 28, 17}, 427 {89012, 6, 90, 91}, 428 {89100, 10, 33, 20}, 429 {90000, 10, 25, 15}, 430 {91000, 10, 32, 19}, 431 {92000, 10, 46, 27}, 432 {93000, 10, 31, 18}, 433 {94000, 10, 40, 23}, 434 {94500, 10, 28, 16}, 435 {95000, 10, 44, 25}, 436 {95654, 10, 39, 22}, 437 {95750, 10, 39, 22}, 438 {96000, 10, 32, 18}, 439 {97000, 8, 23, 16}, 440 {97750, 8, 42, 29}, 441 {98000, 8, 45, 31}, 442 {99000, 8, 22, 15}, 443 {99750, 8, 34, 23}, 444 {100000, 6, 20, 18}, 445 {100500, 6, 19, 17}, 446 {101000, 6, 37, 33}, 447 {101250, 8, 21, 14}, 448 {102000, 6, 17, 15}, 449 {102250, 6, 25, 22}, 450 {103000, 8, 29, 19}, 451 {104000, 8, 37, 24}, 452 {105000, 8, 28, 18}, 453 {106000, 8, 22, 14}, 454 {107000, 8, 46, 29}, 455 {107214, 8, 27, 17}, 456 {108000, 8, 24, 15}, 457 {108108, 8, 173, 108}, 458 {109000, 6, 23, 19}, 459 {110000, 6, 22, 18}, 460 {110013, 6, 22, 18}, 461 {110250, 8, 49, 30}, 462 {110500, 8, 36, 22}, 463 {111000, 8, 23, 14}, 464 {111264, 8, 150, 91}, 465 {111375, 8, 33, 20}, 466 {112000, 8, 63, 38}, 467 {112500, 8, 25, 15}, 468 {113100, 8, 57, 34}, 469 {113309, 8, 42, 25}, 470 {114000, 8, 27, 16}, 471 {115000, 6, 23, 18}, 472 {116000, 8, 43, 25}, 473 {117000, 8, 26, 15}, 474 {117500, 8, 40, 23}, 475 {118000, 6, 38, 29}, 476 {119000, 8, 30, 17}, 477 {119500, 8, 46, 26}, 478 {119651, 8, 39, 22}, 479 {120000, 8, 32, 18}, 480 {121000, 6, 39, 29}, 481 {121250, 6, 31, 23}, 482 {121750, 6, 23, 17}, 483 {122000, 6, 42, 31}, 484 {122614, 6, 30, 22}, 485 {123000, 6, 41, 30}, 486 {123379, 6, 37, 27}, 487 {124000, 6, 51, 37}, 488 {125000, 6, 25, 18}, 489 {125250, 4, 13, 14}, 490 {125750, 4, 27, 29}, 491 {126000, 6, 21, 15}, 492 {127000, 6, 24, 17}, 493 {127250, 6, 41, 29}, 494 {128000, 6, 27, 19}, 495 {129000, 6, 43, 30}, 496 {129859, 4, 25, 26}, 497 {130000, 6, 26, 18}, 498 {130250, 6, 42, 29}, 499 {131000, 6, 32, 22}, 500 {131500, 6, 38, 26}, 501 {131850, 6, 41, 28}, 502 {132000, 6, 22, 15}, 503 {132750, 6, 28, 19}, 504 {133000, 6, 34, 23}, 505 {133330, 6, 37, 25}, 506 {134000, 6, 61, 41}, 507 {135000, 6, 21, 14}, 508 {135250, 6, 167, 111}, 509 {136000, 6, 62, 41}, 510 {137000, 6, 35, 23}, 511 {138000, 6, 23, 15}, 512 {138500, 6, 40, 26}, 513 {138750, 6, 37, 24}, 514 {139000, 6, 34, 22}, 515 {139050, 6, 34, 22}, 516 {139054, 6, 34, 22}, 517 {140000, 6, 28, 18}, 518 {141000, 6, 36, 23}, 519 {141500, 6, 22, 14}, 520 {142000, 6, 30, 19}, 521 {143000, 6, 27, 17}, 522 {143472, 4, 17, 16}, 523 {144000, 6, 24, 15}, 524 {145000, 6, 29, 18}, 525 {146000, 6, 47, 29}, 526 {146250, 6, 26, 16}, 527 {147000, 6, 49, 30}, 528 {147891, 6, 23, 14}, 529 {148000, 6, 23, 14}, 530 {148250, 6, 28, 17}, 531 {148352, 4, 100, 91}, 532 {148500, 6, 33, 20}, 533 {149000, 6, 48, 29}, 534 {150000, 6, 25, 15}, 535 {151000, 4, 19, 17}, 536 {152000, 6, 27, 16}, 537 {152280, 6, 44, 26}, 538 {153000, 6, 34, 20}, 539 {154000, 6, 53, 31}, 540 {155000, 6, 31, 18}, 541 {155250, 6, 50, 29}, 542 {155750, 6, 45, 26}, 543 {156000, 6, 26, 15}, 544 {157000, 6, 61, 35}, 545 {157500, 6, 28, 16}, 546 {158000, 6, 65, 37}, 547 {158250, 6, 44, 25}, 548 {159000, 6, 53, 30}, 549 {159500, 6, 39, 22}, 550 {160000, 6, 32, 18}, 551 {161000, 4, 31, 26}, 552 {162000, 4, 18, 15}, 553 {162162, 4, 131, 109}, 554 {162500, 4, 53, 44}, 555 {163000, 4, 29, 24}, 556 {164000, 4, 17, 14}, 557 {165000, 4, 22, 18}, 558 {166000, 4, 32, 26}, 559 {167000, 4, 26, 21}, 560 {168000, 4, 46, 37}, 561 {169000, 4, 104, 83}, 562 {169128, 4, 64, 51}, 563 {169500, 4, 39, 31}, 564 {170000, 4, 34, 27}, 565 {171000, 4, 19, 15}, 566 {172000, 4, 51, 40}, 567 {172750, 4, 32, 25}, 568 {172800, 4, 32, 25}, 569 {173000, 4, 41, 32}, 570 {174000, 4, 49, 38}, 571 {174787, 4, 22, 17}, 572 {175000, 4, 35, 27}, 573 {176000, 4, 30, 23}, 574 {177000, 4, 38, 29}, 575 {178000, 4, 29, 22}, 576 {178500, 4, 37, 28}, 577 {179000, 4, 53, 40}, 578 {179500, 4, 73, 55}, 579 {180000, 4, 20, 15}, 580 {181000, 4, 55, 41}, 581 {182000, 4, 31, 23}, 582 {183000, 4, 42, 31}, 583 {184000, 4, 30, 22}, 584 {184750, 4, 26, 19}, 585 {185000, 4, 37, 27}, 586 {186000, 4, 51, 37}, 587 {187000, 4, 36, 26}, 588 {188000, 4, 32, 23}, 589 {189000, 4, 21, 15}, 590 {190000, 4, 38, 27}, 591 {190960, 4, 41, 29}, 592 {191000, 4, 41, 29}, 593 {192000, 4, 27, 19}, 594 {192250, 4, 37, 26}, 595 {193000, 4, 20, 14}, 596 {193250, 4, 53, 37}, 597 {194000, 4, 23, 16}, 598 {194208, 4, 23, 16}, 599 {195000, 4, 26, 18}, 600 {196000, 4, 45, 31}, 601 {197000, 4, 35, 24}, 602 {197750, 4, 41, 28}, 603 {198000, 4, 22, 15}, 604 {198500, 4, 25, 17}, 605 {199000, 4, 28, 19}, 606 {200000, 4, 37, 25}, 607 {201000, 4, 61, 41}, 608 {202000, 4, 112, 75}, 609 {202500, 4, 21, 14}, 610 {203000, 4, 146, 97}, 611 {204000, 4, 62, 41}, 612 {204750, 4, 44, 29}, 613 {205000, 4, 38, 25}, 614 {206000, 4, 29, 19}, 615 {207000, 4, 23, 15}, 616 {207500, 4, 40, 26}, 617 {208000, 4, 37, 24}, 618 {208900, 4, 48, 31}, 619 {209000, 4, 48, 31}, 620 {209250, 4, 31, 20}, 621 {210000, 4, 28, 18}, 622 {211000, 4, 25, 16}, 623 {212000, 4, 22, 14}, 624 {213000, 4, 30, 19}, 625 {213750, 4, 38, 24}, 626 {214000, 4, 46, 29}, 627 {214750, 4, 35, 22}, 628 {215000, 4, 43, 27}, 629 {216000, 4, 24, 15}, 630 {217000, 4, 37, 23}, 631 {218000, 4, 42, 26}, 632 {218250, 4, 42, 26}, 633 {218750, 4, 34, 21}, 634 {219000, 4, 47, 29}, 635 {220000, 4, 44, 27}, 636 {220640, 4, 49, 30}, 637 {220750, 4, 36, 22}, 638 {221000, 4, 36, 22}, 639 {222000, 4, 23, 14}, 640 {222525, 4, 28, 17}, 641 {222750, 4, 33, 20}, 642 {227000, 4, 37, 22}, 643 {230250, 4, 29, 17}, 644 {233500, 4, 38, 22}, 645 {235000, 4, 40, 23}, 646 {238000, 4, 30, 17}, 647 {241500, 2, 17, 19}, 648 {245250, 2, 20, 22}, 649 {247750, 2, 22, 24}, 650 {253250, 2, 15, 16}, 651 {256250, 2, 18, 19}, 652 {262500, 2, 31, 32}, 653 {267250, 2, 66, 67}, 654 {268500, 2, 94, 95}, 655 {270000, 2, 14, 14}, 656 {272500, 2, 77, 76}, 657 {273750, 2, 57, 56}, 658 {280750, 2, 24, 23}, 659 {281250, 2, 23, 22}, 660 {286000, 2, 17, 16}, 661 {291750, 2, 26, 24}, 662 {296703, 2, 56, 51}, 663 {297000, 2, 22, 20}, 664 {298000, 2, 21, 19}, 665 }; 666 667 static void intel_ddi_mode_set(struct drm_encoder *encoder, 668 struct drm_display_mode *mode, 669 struct drm_display_mode *adjusted_mode) 670 { 671 struct drm_crtc *crtc = encoder->crtc; 672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 673 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 674 int port = intel_ddi_get_encoder_port(intel_encoder); 675 int pipe = intel_crtc->pipe; 676 int type = intel_encoder->type; 677 678 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n", 679 port_name(port), pipe_name(pipe)); 680 681 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 682 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 683 struct intel_digital_port *intel_dig_port = 684 enc_to_dig_port(encoder); 685 686 intel_dp->DP = intel_dig_port->port_reversal | 687 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; 688 switch (intel_dp->lane_count) { 689 case 1: 690 intel_dp->DP |= DDI_PORT_WIDTH_X1; 691 break; 692 case 2: 693 intel_dp->DP |= DDI_PORT_WIDTH_X2; 694 break; 695 case 4: 696 intel_dp->DP |= DDI_PORT_WIDTH_X4; 697 break; 698 default: 699 intel_dp->DP |= DDI_PORT_WIDTH_X4; 700 WARN(1, "Unexpected DP lane count %d\n", 701 intel_dp->lane_count); 702 break; 703 } 704 705 if (intel_dp->has_audio) { 706 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n", 707 pipe_name(intel_crtc->pipe)); 708 709 /* write eld */ 710 DRM_DEBUG_DRIVER("DP audio: write eld information\n"); 711 intel_write_eld(encoder, adjusted_mode); 712 } 713 714 intel_dp_init_link_config(intel_dp); 715 716 } else if (type == INTEL_OUTPUT_HDMI) { 717 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 718 719 if (intel_hdmi->has_audio) { 720 /* Proper support for digital audio needs a new logic 721 * and a new set of registers, so we leave it for future 722 * patch bombing. 723 */ 724 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", 725 pipe_name(intel_crtc->pipe)); 726 727 /* write eld */ 728 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); 729 intel_write_eld(encoder, adjusted_mode); 730 } 731 732 intel_hdmi->set_infoframes(encoder, adjusted_mode); 733 } 734 } 735 736 static struct intel_encoder * 737 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 738 { 739 struct drm_device *dev = crtc->dev; 740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 741 struct intel_encoder *intel_encoder, *ret = NULL; 742 int num_encoders = 0; 743 744 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 745 ret = intel_encoder; 746 num_encoders++; 747 } 748 749 if (num_encoders != 1) 750 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders, 751 intel_crtc->pipe); 752 753 BUG_ON(ret == NULL); 754 return ret; 755 } 756 757 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) 758 { 759 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 760 struct intel_ddi_plls *plls = &dev_priv->ddi_plls; 761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 762 uint32_t val; 763 764 switch (intel_crtc->ddi_pll_sel) { 765 case PORT_CLK_SEL_SPLL: 766 plls->spll_refcount--; 767 if (plls->spll_refcount == 0) { 768 DRM_DEBUG_KMS("Disabling SPLL\n"); 769 val = I915_READ(SPLL_CTL); 770 WARN_ON(!(val & SPLL_PLL_ENABLE)); 771 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 772 POSTING_READ(SPLL_CTL); 773 } 774 break; 775 case PORT_CLK_SEL_WRPLL1: 776 plls->wrpll1_refcount--; 777 if (plls->wrpll1_refcount == 0) { 778 DRM_DEBUG_KMS("Disabling WRPLL 1\n"); 779 val = I915_READ(WRPLL_CTL1); 780 WARN_ON(!(val & WRPLL_PLL_ENABLE)); 781 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); 782 POSTING_READ(WRPLL_CTL1); 783 } 784 break; 785 case PORT_CLK_SEL_WRPLL2: 786 plls->wrpll2_refcount--; 787 if (plls->wrpll2_refcount == 0) { 788 DRM_DEBUG_KMS("Disabling WRPLL 2\n"); 789 val = I915_READ(WRPLL_CTL2); 790 WARN_ON(!(val & WRPLL_PLL_ENABLE)); 791 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); 792 POSTING_READ(WRPLL_CTL2); 793 } 794 break; 795 } 796 797 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); 798 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); 799 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); 800 801 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; 802 } 803 804 static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2) 805 { 806 u32 i; 807 808 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++) 809 if (clock <= wrpll_tmds_clock_table[i].clock) 810 break; 811 812 if (i == ARRAY_SIZE(wrpll_tmds_clock_table)) 813 i--; 814 815 *p = wrpll_tmds_clock_table[i].p; 816 *n2 = wrpll_tmds_clock_table[i].n2; 817 *r2 = wrpll_tmds_clock_table[i].r2; 818 819 if (wrpll_tmds_clock_table[i].clock != clock) 820 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n", 821 wrpll_tmds_clock_table[i].clock, clock); 822 823 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n", 824 clock, *p, *n2, *r2); 825 } 826 827 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) 828 { 829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 830 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 831 struct drm_encoder *encoder = &intel_encoder->base; 832 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 833 struct intel_ddi_plls *plls = &dev_priv->ddi_plls; 834 int type = intel_encoder->type; 835 enum i915_pipe pipe = intel_crtc->pipe; 836 uint32_t reg, val; 837 838 /* TODO: reuse PLLs when possible (compare values) */ 839 840 intel_ddi_put_crtc_pll(crtc); 841 842 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 843 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 844 845 switch (intel_dp->link_bw) { 846 case DP_LINK_BW_1_62: 847 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; 848 break; 849 case DP_LINK_BW_2_7: 850 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; 851 break; 852 case DP_LINK_BW_5_4: 853 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; 854 break; 855 default: 856 DRM_ERROR("Link bandwidth %d unsupported\n", 857 intel_dp->link_bw); 858 return false; 859 } 860 861 /* We don't need to turn any PLL on because we'll use LCPLL. */ 862 return true; 863 864 } else if (type == INTEL_OUTPUT_HDMI) { 865 int p, n2, r2; 866 867 if (plls->wrpll1_refcount == 0) { 868 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", 869 pipe_name(pipe)); 870 plls->wrpll1_refcount++; 871 reg = WRPLL_CTL1; 872 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; 873 } else if (plls->wrpll2_refcount == 0) { 874 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", 875 pipe_name(pipe)); 876 plls->wrpll2_refcount++; 877 reg = WRPLL_CTL2; 878 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; 879 } else { 880 DRM_ERROR("No WRPLLs available!\n"); 881 return false; 882 } 883 884 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, 885 "WRPLL already enabled\n"); 886 887 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2); 888 889 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | 890 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 891 WRPLL_DIVIDER_POST(p); 892 893 } else if (type == INTEL_OUTPUT_ANALOG) { 894 if (plls->spll_refcount == 0) { 895 DRM_DEBUG_KMS("Using SPLL on pipe %c\n", 896 pipe_name(pipe)); 897 plls->spll_refcount++; 898 reg = SPLL_CTL; 899 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; 900 } 901 902 WARN(I915_READ(reg) & SPLL_PLL_ENABLE, 903 "SPLL already enabled\n"); 904 905 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; 906 907 } else { 908 WARN(1, "Invalid DDI encoder type %d\n", type); 909 return false; 910 } 911 912 I915_WRITE(reg, val); 913 udelay(20); 914 915 return true; 916 } 917 918 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 919 { 920 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 922 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 923 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 924 int type = intel_encoder->type; 925 uint32_t temp; 926 927 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 928 929 temp = TRANS_MSA_SYNC_CLK; 930 switch (intel_crtc->bpp) { 931 case 18: 932 temp |= TRANS_MSA_6_BPC; 933 break; 934 case 24: 935 temp |= TRANS_MSA_8_BPC; 936 break; 937 case 30: 938 temp |= TRANS_MSA_10_BPC; 939 break; 940 case 36: 941 temp |= TRANS_MSA_12_BPC; 942 break; 943 default: 944 temp |= TRANS_MSA_8_BPC; 945 WARN(1, "%d bpp unsupported by DDI function\n", 946 intel_crtc->bpp); 947 } 948 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 949 } 950 } 951 952 void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) 953 { 954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 955 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 956 struct drm_encoder *encoder = &intel_encoder->base; 957 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 958 enum i915_pipe pipe = intel_crtc->pipe; 959 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 960 enum port port = intel_ddi_get_encoder_port(intel_encoder); 961 int type = intel_encoder->type; 962 uint32_t temp; 963 964 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 965 temp = TRANS_DDI_FUNC_ENABLE; 966 temp |= TRANS_DDI_SELECT_PORT(port); 967 968 switch (intel_crtc->bpp) { 969 case 18: 970 temp |= TRANS_DDI_BPC_6; 971 break; 972 case 24: 973 temp |= TRANS_DDI_BPC_8; 974 break; 975 case 30: 976 temp |= TRANS_DDI_BPC_10; 977 break; 978 case 36: 979 temp |= TRANS_DDI_BPC_12; 980 break; 981 default: 982 WARN(1, "%d bpp unsupported by transcoder DDI function\n", 983 intel_crtc->bpp); 984 } 985 986 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 987 temp |= TRANS_DDI_PVSYNC; 988 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 989 temp |= TRANS_DDI_PHSYNC; 990 991 if (cpu_transcoder == TRANSCODER_EDP) { 992 switch (pipe) { 993 case PIPE_A: 994 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 995 break; 996 case PIPE_B: 997 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 998 break; 999 case PIPE_C: 1000 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1001 break; 1002 default: 1003 BUG(); 1004 break; 1005 } 1006 } 1007 1008 if (type == INTEL_OUTPUT_HDMI) { 1009 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1010 1011 if (intel_hdmi->has_hdmi_sink) 1012 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1013 else 1014 temp |= TRANS_DDI_MODE_SELECT_DVI; 1015 1016 } else if (type == INTEL_OUTPUT_ANALOG) { 1017 temp |= TRANS_DDI_MODE_SELECT_FDI; 1018 temp |= (intel_crtc->fdi_lanes - 1) << 1; 1019 1020 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1021 type == INTEL_OUTPUT_EDP) { 1022 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1023 1024 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1025 1026 switch (intel_dp->lane_count) { 1027 case 1: 1028 temp |= TRANS_DDI_PORT_WIDTH_X1; 1029 break; 1030 case 2: 1031 temp |= TRANS_DDI_PORT_WIDTH_X2; 1032 break; 1033 case 4: 1034 temp |= TRANS_DDI_PORT_WIDTH_X4; 1035 break; 1036 default: 1037 temp |= TRANS_DDI_PORT_WIDTH_X4; 1038 WARN(1, "Unsupported lane count %d\n", 1039 intel_dp->lane_count); 1040 } 1041 1042 } else { 1043 WARN(1, "Invalid encoder type %d for pipe %d\n", 1044 intel_encoder->type, pipe); 1045 } 1046 1047 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1048 } 1049 1050 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1051 enum transcoder cpu_transcoder) 1052 { 1053 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1054 uint32_t val = I915_READ(reg); 1055 1056 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); 1057 val |= TRANS_DDI_PORT_NONE; 1058 I915_WRITE(reg, val); 1059 } 1060 1061 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1062 { 1063 struct drm_device *dev = intel_connector->base.dev; 1064 struct drm_i915_private *dev_priv = dev->dev_private; 1065 struct intel_encoder *intel_encoder = intel_connector->encoder; 1066 int type = intel_connector->base.connector_type; 1067 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1068 enum i915_pipe pipe = 0; 1069 enum transcoder cpu_transcoder; 1070 uint32_t tmp; 1071 1072 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1073 return false; 1074 1075 if (port == PORT_A) 1076 cpu_transcoder = TRANSCODER_EDP; 1077 else 1078 cpu_transcoder = pipe; 1079 1080 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1081 1082 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1083 case TRANS_DDI_MODE_SELECT_HDMI: 1084 case TRANS_DDI_MODE_SELECT_DVI: 1085 return (type == DRM_MODE_CONNECTOR_HDMIA); 1086 1087 case TRANS_DDI_MODE_SELECT_DP_SST: 1088 if (type == DRM_MODE_CONNECTOR_eDP) 1089 return true; 1090 case TRANS_DDI_MODE_SELECT_DP_MST: 1091 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1092 1093 case TRANS_DDI_MODE_SELECT_FDI: 1094 return (type == DRM_MODE_CONNECTOR_VGA); 1095 1096 default: 1097 return false; 1098 } 1099 } 1100 1101 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1102 enum i915_pipe *pipe) 1103 { 1104 struct drm_device *dev = encoder->base.dev; 1105 struct drm_i915_private *dev_priv = dev->dev_private; 1106 enum port port = intel_ddi_get_encoder_port(encoder); 1107 u32 tmp; 1108 int i; 1109 1110 tmp = I915_READ(DDI_BUF_CTL(port)); 1111 1112 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1113 return false; 1114 1115 if (port == PORT_A) { 1116 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1117 1118 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1119 case TRANS_DDI_EDP_INPUT_A_ON: 1120 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1121 *pipe = PIPE_A; 1122 break; 1123 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1124 *pipe = PIPE_B; 1125 break; 1126 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1127 *pipe = PIPE_C; 1128 break; 1129 } 1130 1131 return true; 1132 } else { 1133 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 1134 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 1135 1136 if ((tmp & TRANS_DDI_PORT_MASK) 1137 == TRANS_DDI_SELECT_PORT(port)) { 1138 *pipe = i; 1139 return true; 1140 } 1141 } 1142 } 1143 1144 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); 1145 1146 return true; 1147 } 1148 1149 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, 1150 enum i915_pipe pipe) 1151 { 1152 uint32_t temp, ret; 1153 enum port port = I915_MAX_PORTS; 1154 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1155 pipe); 1156 int i; 1157 1158 if (cpu_transcoder == TRANSCODER_EDP) { 1159 port = PORT_A; 1160 } else { 1161 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1162 temp &= TRANS_DDI_PORT_MASK; 1163 1164 for (i = PORT_B; i <= PORT_E; i++) 1165 if (temp == TRANS_DDI_SELECT_PORT(i)) 1166 port = i; 1167 } 1168 1169 ret = I915_READ(PORT_CLK_SEL(port)); 1170 1171 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n", 1172 pipe_name(pipe), port_name(port), ret); 1173 1174 return ret; 1175 } 1176 1177 void intel_ddi_setup_hw_pll_state(struct drm_device *dev) 1178 { 1179 struct drm_i915_private *dev_priv = dev->dev_private; 1180 enum i915_pipe pipe; 1181 struct intel_crtc *intel_crtc; 1182 1183 for_each_pipe(pipe) { 1184 intel_crtc = 1185 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 1186 1187 if (!intel_crtc->active) 1188 continue; 1189 1190 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, 1191 pipe); 1192 1193 switch (intel_crtc->ddi_pll_sel) { 1194 case PORT_CLK_SEL_SPLL: 1195 dev_priv->ddi_plls.spll_refcount++; 1196 break; 1197 case PORT_CLK_SEL_WRPLL1: 1198 dev_priv->ddi_plls.wrpll1_refcount++; 1199 break; 1200 case PORT_CLK_SEL_WRPLL2: 1201 dev_priv->ddi_plls.wrpll2_refcount++; 1202 break; 1203 } 1204 } 1205 } 1206 1207 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 1208 { 1209 struct drm_crtc *crtc = &intel_crtc->base; 1210 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1211 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1212 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1213 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 1214 1215 if (cpu_transcoder != TRANSCODER_EDP) 1216 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1217 TRANS_CLK_SEL_PORT(port)); 1218 } 1219 1220 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 1221 { 1222 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1223 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 1224 1225 if (cpu_transcoder != TRANSCODER_EDP) 1226 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1227 TRANS_CLK_SEL_DISABLED); 1228 } 1229 1230 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 1231 { 1232 struct drm_encoder *encoder = &intel_encoder->base; 1233 struct drm_crtc *crtc = encoder->crtc; 1234 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1236 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1237 int type = intel_encoder->type; 1238 1239 if (type == INTEL_OUTPUT_EDP) { 1240 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1241 ironlake_edp_panel_vdd_on(intel_dp); 1242 ironlake_edp_panel_on(intel_dp); 1243 ironlake_edp_panel_vdd_off(intel_dp, true); 1244 } 1245 1246 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); 1247 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); 1248 1249 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1250 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1251 1252 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1253 intel_dp_start_link_train(intel_dp); 1254 intel_dp_complete_link_train(intel_dp); 1255 } 1256 } 1257 1258 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 1259 { 1260 struct drm_encoder *encoder = &intel_encoder->base; 1261 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1262 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1263 int type = intel_encoder->type; 1264 uint32_t val; 1265 bool wait = false; 1266 1267 val = I915_READ(DDI_BUF_CTL(port)); 1268 if (val & DDI_BUF_CTL_ENABLE) { 1269 val &= ~DDI_BUF_CTL_ENABLE; 1270 I915_WRITE(DDI_BUF_CTL(port), val); 1271 wait = true; 1272 } 1273 1274 val = I915_READ(DP_TP_CTL(port)); 1275 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1276 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1277 I915_WRITE(DP_TP_CTL(port), val); 1278 1279 if (wait) 1280 intel_wait_ddi_buf_idle(dev_priv, port); 1281 1282 if (type == INTEL_OUTPUT_EDP) { 1283 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1284 ironlake_edp_panel_vdd_on(intel_dp); 1285 ironlake_edp_panel_off(intel_dp); 1286 } 1287 1288 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1289 } 1290 1291 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 1292 { 1293 struct drm_encoder *encoder = &intel_encoder->base; 1294 struct drm_device *dev = encoder->dev; 1295 struct drm_i915_private *dev_priv = dev->dev_private; 1296 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1297 int type = intel_encoder->type; 1298 1299 if (type == INTEL_OUTPUT_HDMI) { 1300 struct intel_digital_port *intel_dig_port = 1301 enc_to_dig_port(encoder); 1302 1303 /* In HDMI/DVI mode, the port width, and swing/emphasis values 1304 * are ignored so nothing special needs to be done besides 1305 * enabling the port. 1306 */ 1307 I915_WRITE(DDI_BUF_CTL(port), 1308 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE); 1309 } else if (type == INTEL_OUTPUT_EDP) { 1310 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1311 1312 ironlake_edp_backlight_on(intel_dp); 1313 } 1314 } 1315 1316 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 1317 { 1318 struct drm_encoder *encoder = &intel_encoder->base; 1319 int type = intel_encoder->type; 1320 1321 if (type == INTEL_OUTPUT_EDP) { 1322 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1323 1324 ironlake_edp_backlight_off(intel_dp); 1325 } 1326 } 1327 1328 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) 1329 { 1330 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) 1331 return 450; 1332 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) == 1333 LCPLL_CLK_FREQ_450) 1334 return 450; 1335 else if (IS_ULT(dev_priv->dev)) 1336 return 338; 1337 else 1338 return 540; 1339 } 1340 1341 void intel_ddi_pll_init(struct drm_device *dev) 1342 { 1343 struct drm_i915_private *dev_priv = dev->dev_private; 1344 uint32_t val = I915_READ(LCPLL_CTL); 1345 1346 /* The LCPLL register should be turned on by the BIOS. For now let's 1347 * just check its state and print errors in case something is wrong. 1348 * Don't even try to turn it on. 1349 */ 1350 1351 DRM_DEBUG_KMS("CDCLK running at %dMHz\n", 1352 intel_ddi_get_cdclk_freq(dev_priv)); 1353 1354 if (val & LCPLL_CD_SOURCE_FCLK) 1355 DRM_ERROR("CDCLK source is not LCPLL\n"); 1356 1357 if (val & LCPLL_PLL_DISABLE) 1358 DRM_ERROR("LCPLL is disabled\n"); 1359 } 1360 1361 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 1362 { 1363 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1364 struct intel_dp *intel_dp = &intel_dig_port->dp; 1365 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 1366 enum port port = intel_dig_port->port; 1367 bool wait = false; 1368 uint32_t val; 1369 1370 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 1371 val = I915_READ(DDI_BUF_CTL(port)); 1372 if (val & DDI_BUF_CTL_ENABLE) { 1373 val &= ~DDI_BUF_CTL_ENABLE; 1374 I915_WRITE(DDI_BUF_CTL(port), val); 1375 wait = true; 1376 } 1377 1378 val = I915_READ(DP_TP_CTL(port)); 1379 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1380 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 1381 I915_WRITE(DP_TP_CTL(port), val); 1382 POSTING_READ(DP_TP_CTL(port)); 1383 1384 if (wait) 1385 intel_wait_ddi_buf_idle(dev_priv, port); 1386 } 1387 1388 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | 1389 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 1390 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 1391 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 1392 I915_WRITE(DP_TP_CTL(port), val); 1393 POSTING_READ(DP_TP_CTL(port)); 1394 1395 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 1396 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 1397 POSTING_READ(DDI_BUF_CTL(port)); 1398 1399 udelay(600); 1400 } 1401 1402 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 1403 { 1404 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1405 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1406 uint32_t val; 1407 1408 intel_ddi_post_disable(intel_encoder); 1409 1410 val = I915_READ(_FDI_RXA_CTL); 1411 val &= ~FDI_RX_ENABLE; 1412 I915_WRITE(_FDI_RXA_CTL, val); 1413 1414 val = I915_READ(_FDI_RXA_MISC); 1415 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1416 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1417 I915_WRITE(_FDI_RXA_MISC, val); 1418 1419 val = I915_READ(_FDI_RXA_CTL); 1420 val &= ~FDI_PCDCLK; 1421 I915_WRITE(_FDI_RXA_CTL, val); 1422 1423 val = I915_READ(_FDI_RXA_CTL); 1424 val &= ~FDI_RX_PLL_ENABLE; 1425 I915_WRITE(_FDI_RXA_CTL, val); 1426 } 1427 1428 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) 1429 { 1430 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 1431 int type = intel_encoder->type; 1432 1433 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) 1434 intel_dp_check_link_status(intel_dp); 1435 } 1436 1437 static void intel_ddi_destroy(struct drm_encoder *encoder) 1438 { 1439 /* HDMI has nothing special to destroy, so we can go with this. */ 1440 intel_dp_encoder_destroy(encoder); 1441 } 1442 1443 static bool intel_ddi_mode_fixup(struct drm_encoder *encoder, 1444 const struct drm_display_mode *mode, 1445 struct drm_display_mode *adjusted_mode) 1446 { 1447 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1448 int type = intel_encoder->type; 1449 1450 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n"); 1451 1452 if (type == INTEL_OUTPUT_HDMI) 1453 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode); 1454 else 1455 return intel_dp_mode_fixup(encoder, mode, adjusted_mode); 1456 } 1457 1458 static const struct drm_encoder_funcs intel_ddi_funcs = { 1459 .destroy = intel_ddi_destroy, 1460 }; 1461 1462 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = { 1463 .mode_fixup = intel_ddi_mode_fixup, 1464 .mode_set = intel_ddi_mode_set, 1465 .disable = intel_encoder_noop, 1466 }; 1467 1468 void intel_ddi_init(struct drm_device *dev, enum port port) 1469 { 1470 struct drm_i915_private *dev_priv = dev->dev_private; 1471 struct intel_digital_port *intel_dig_port; 1472 struct intel_encoder *intel_encoder; 1473 struct drm_encoder *encoder; 1474 struct intel_connector *hdmi_connector = NULL; 1475 struct intel_connector *dp_connector = NULL; 1476 1477 intel_dig_port = kmalloc(sizeof(struct intel_digital_port), 1478 DRM_MEM_KMS, M_WAITOK | M_ZERO); 1479 if (!intel_dig_port) 1480 return; 1481 1482 dp_connector = kmalloc(sizeof(struct intel_connector), 1483 DRM_MEM_KMS, M_WAITOK | M_ZERO); 1484 if (!dp_connector) { 1485 kfree(intel_dig_port, DRM_MEM_KMS); 1486 return; 1487 } 1488 1489 if (port != PORT_A) { 1490 hdmi_connector = kmalloc(sizeof(struct intel_connector), 1491 DRM_MEM_KMS, M_WAITOK | M_ZERO); 1492 if (!hdmi_connector) { 1493 kfree(dp_connector, DRM_MEM_KMS); 1494 kfree(intel_dig_port, DRM_MEM_KMS); 1495 return; 1496 } 1497 } 1498 1499 intel_encoder = &intel_dig_port->base; 1500 encoder = &intel_encoder->base; 1501 1502 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 1503 DRM_MODE_ENCODER_TMDS); 1504 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs); 1505 1506 intel_encoder->enable = intel_enable_ddi; 1507 intel_encoder->pre_enable = intel_ddi_pre_enable; 1508 intel_encoder->disable = intel_disable_ddi; 1509 intel_encoder->post_disable = intel_ddi_post_disable; 1510 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 1511 1512 intel_dig_port->port = port; 1513 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & 1514 DDI_BUF_PORT_REVERSAL; 1515 if (hdmi_connector) 1516 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port); 1517 else 1518 intel_dig_port->hdmi.sdvox_reg = 0; 1519 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 1520 1521 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 1522 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1523 intel_encoder->cloneable = false; 1524 intel_encoder->hot_plug = intel_ddi_hot_plug; 1525 1526 if (hdmi_connector) 1527 intel_hdmi_init_connector(intel_dig_port, hdmi_connector); 1528 intel_dp_init_connector(intel_dig_port, dp_connector); 1529 } 1530