1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include "i915_drv.h" 26 27 #define PLATFORM_NAME(x) [INTEL_##x] = #x 28 static const char * const platform_names[] = { 29 PLATFORM_NAME(I830), 30 PLATFORM_NAME(I845G), 31 PLATFORM_NAME(I85X), 32 PLATFORM_NAME(I865G), 33 PLATFORM_NAME(I915G), 34 PLATFORM_NAME(I915GM), 35 PLATFORM_NAME(I945G), 36 PLATFORM_NAME(I945GM), 37 PLATFORM_NAME(G33), 38 PLATFORM_NAME(PINEVIEW), 39 PLATFORM_NAME(I965G), 40 PLATFORM_NAME(I965GM), 41 PLATFORM_NAME(G45), 42 PLATFORM_NAME(GM45), 43 PLATFORM_NAME(IRONLAKE), 44 PLATFORM_NAME(SANDYBRIDGE), 45 PLATFORM_NAME(IVYBRIDGE), 46 PLATFORM_NAME(VALLEYVIEW), 47 PLATFORM_NAME(HASWELL), 48 PLATFORM_NAME(BROADWELL), 49 PLATFORM_NAME(CHERRYVIEW), 50 PLATFORM_NAME(SKYLAKE), 51 PLATFORM_NAME(BROXTON), 52 PLATFORM_NAME(KABYLAKE), 53 PLATFORM_NAME(GEMINILAKE), 54 }; 55 #undef PLATFORM_NAME 56 57 const char *intel_platform_name(enum intel_platform platform) 58 { 59 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 60 61 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 62 platform_names[platform] == NULL)) 63 return "<unknown>"; 64 65 return platform_names[platform]; 66 } 67 68 void intel_device_info_dump(struct drm_i915_private *dev_priv) 69 { 70 const struct intel_device_info *info = &dev_priv->info; 71 72 DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x", 73 intel_platform_name(info->platform), 74 info->gen, 75 dev_priv->drm.pdev->device, 76 dev_priv->drm.pdev->revision); 77 #define PRINT_FLAG(name) \ 78 DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name)) 79 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 80 #undef PRINT_FLAG 81 } 82 83 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) 84 { 85 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; 86 u32 fuse, eu_dis; 87 88 fuse = I915_READ(CHV_FUSE_GT); 89 90 sseu->slice_mask = BIT(0); 91 92 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 93 sseu->subslice_mask |= BIT(0); 94 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | 95 CHV_FGT_EU_DIS_SS0_R1_MASK); 96 sseu->eu_total += 8 - hweight32(eu_dis); 97 } 98 99 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 100 sseu->subslice_mask |= BIT(1); 101 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | 102 CHV_FGT_EU_DIS_SS1_R1_MASK); 103 sseu->eu_total += 8 - hweight32(eu_dis); 104 } 105 106 /* 107 * CHV expected to always have a uniform distribution of EU 108 * across subslices. 109 */ 110 sseu->eu_per_subslice = sseu_subslice_total(sseu) ? 111 sseu->eu_total / sseu_subslice_total(sseu) : 112 0; 113 /* 114 * CHV supports subslice power gating on devices with more than 115 * one subslice, and supports EU power gating on devices with 116 * more than one EU pair per subslice. 117 */ 118 sseu->has_slice_pg = 0; 119 sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; 120 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 121 } 122 123 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) 124 { 125 struct intel_device_info *info = mkwrite_device_info(dev_priv); 126 struct sseu_dev_info *sseu = &info->sseu; 127 int s_max = 3, ss_max = 4, eu_max = 8; 128 int s, ss; 129 u32 fuse2, eu_disable; 130 u8 eu_mask = 0xff; 131 132 fuse2 = I915_READ(GEN8_FUSE2); 133 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 134 135 /* 136 * The subslice disable field is global, i.e. it applies 137 * to each of the enabled slices. 138 */ 139 sseu->subslice_mask = (1 << ss_max) - 1; 140 sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 141 GEN9_F2_SS_DIS_SHIFT); 142 143 /* 144 * Iterate through enabled slices and subslices to 145 * count the total enabled EU. 146 */ 147 for (s = 0; s < s_max; s++) { 148 if (!(sseu->slice_mask & BIT(s))) 149 /* skip disabled slice */ 150 continue; 151 152 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); 153 for (ss = 0; ss < ss_max; ss++) { 154 int eu_per_ss; 155 156 if (!(sseu->subslice_mask & BIT(ss))) 157 /* skip disabled subslice */ 158 continue; 159 160 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & 161 eu_mask); 162 163 /* 164 * Record which subslice(s) has(have) 7 EUs. we 165 * can tune the hash used to spread work among 166 * subslices if they are unbalanced. 167 */ 168 if (eu_per_ss == 7) 169 sseu->subslice_7eu[s] |= BIT(ss); 170 171 sseu->eu_total += eu_per_ss; 172 } 173 } 174 175 /* 176 * SKL is expected to always have a uniform distribution 177 * of EU across subslices with the exception that any one 178 * EU in any one subslice may be fused off for die 179 * recovery. BXT is expected to be perfectly uniform in EU 180 * distribution. 181 */ 182 sseu->eu_per_subslice = sseu_subslice_total(sseu) ? 183 DIV_ROUND_UP(sseu->eu_total, 184 sseu_subslice_total(sseu)) : 0; 185 /* 186 * SKL supports slice power gating on devices with more than 187 * one slice, and supports EU power gating on devices with 188 * more than one EU pair per subslice. BXT supports subslice 189 * power gating on devices with more than one subslice, and 190 * supports EU power gating on devices with more than one EU 191 * pair per subslice. 192 */ 193 sseu->has_slice_pg = 194 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 195 hweight8(sseu->slice_mask) > 1; 196 sseu->has_subslice_pg = 197 IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; 198 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 199 200 if (IS_GEN9_LP(dev_priv)) { 201 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss))) 202 info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3; 203 204 /* 205 * There is a HW issue in 2x6 fused down parts that requires 206 * Pooled EU to be enabled as a WA. The pool configuration 207 * changes depending upon which subslice is fused down. This 208 * doesn't affect if the device has all 3 subslices enabled. 209 */ 210 /* WaEnablePooledEuFor2x6:bxt */ 211 info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 && 212 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST)); 213 214 sseu->min_eu_in_pool = 0; 215 if (info->has_pooled_eu) { 216 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 217 sseu->min_eu_in_pool = 3; 218 else if (IS_SS_DISABLED(1)) 219 sseu->min_eu_in_pool = 6; 220 else 221 sseu->min_eu_in_pool = 9; 222 } 223 #undef IS_SS_DISABLED 224 } 225 } 226 227 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) 228 { 229 struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; 230 const int s_max = 3, ss_max = 3, eu_max = 8; 231 int s, ss; 232 u32 fuse2, eu_disable[3]; /* s_max */ 233 234 fuse2 = I915_READ(GEN8_FUSE2); 235 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 236 /* 237 * The subslice disable field is global, i.e. it applies 238 * to each of the enabled slices. 239 */ 240 sseu->subslice_mask = GENMASK(ss_max - 1, 0); 241 sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 242 GEN8_F2_SS_DIS_SHIFT); 243 244 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; 245 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | 246 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << 247 (32 - GEN8_EU_DIS0_S1_SHIFT)); 248 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | 249 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << 250 (32 - GEN8_EU_DIS1_S2_SHIFT)); 251 252 /* 253 * Iterate through enabled slices and subslices to 254 * count the total enabled EU. 255 */ 256 for (s = 0; s < s_max; s++) { 257 if (!(sseu->slice_mask & BIT(s))) 258 /* skip disabled slice */ 259 continue; 260 261 for (ss = 0; ss < ss_max; ss++) { 262 u32 n_disabled; 263 264 if (!(sseu->subslice_mask & BIT(ss))) 265 /* skip disabled subslice */ 266 continue; 267 268 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); 269 270 /* 271 * Record which subslices have 7 EUs. 272 */ 273 if (eu_max - n_disabled == 7) 274 sseu->subslice_7eu[s] |= 1 << ss; 275 276 sseu->eu_total += eu_max - n_disabled; 277 } 278 } 279 280 /* 281 * BDW is expected to always have a uniform distribution of EU across 282 * subslices with the exception that any one EU in any one subslice may 283 * be fused off for die recovery. 284 */ 285 sseu->eu_per_subslice = sseu_subslice_total(sseu) ? 286 DIV_ROUND_UP(sseu->eu_total, 287 sseu_subslice_total(sseu)) : 0; 288 289 /* 290 * BDW supports slice power gating on devices with more than 291 * one slice. 292 */ 293 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 294 sseu->has_subslice_pg = 0; 295 sseu->has_eu_pg = 0; 296 } 297 298 /* 299 * Determine various intel_device_info fields at runtime. 300 * 301 * Use it when either: 302 * - it's judged too laborious to fill n static structures with the limit 303 * when a simple if statement does the job, 304 * - run-time checks (eg read fuse/strap registers) are needed. 305 * 306 * This function needs to be called: 307 * - after the MMIO has been setup as we are reading registers, 308 * - after the PCH has been detected, 309 * - before the first usage of the fields it can tweak. 310 */ 311 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 312 { 313 struct intel_device_info *info = mkwrite_device_info(dev_priv); 314 enum i915_pipe pipe; 315 316 if (INTEL_GEN(dev_priv) >= 9) { 317 info->num_scalers[PIPE_A] = 2; 318 info->num_scalers[PIPE_B] = 2; 319 info->num_scalers[PIPE_C] = 1; 320 } 321 322 /* 323 * Skylake and Broxton currently don't expose the topmost plane as its 324 * use is exclusive with the legacy cursor and we only want to expose 325 * one of those, not both. Until we can safely expose the topmost plane 326 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, 327 * we don't expose the topmost plane at all to prevent ABI breakage 328 * down the line. 329 */ 330 if (IS_GEMINILAKE(dev_priv)) 331 for_each_pipe(dev_priv, pipe) 332 info->num_sprites[pipe] = 3; 333 else if (IS_BROXTON(dev_priv)) { 334 info->num_sprites[PIPE_A] = 2; 335 info->num_sprites[PIPE_B] = 2; 336 info->num_sprites[PIPE_C] = 1; 337 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 338 for_each_pipe(dev_priv, pipe) 339 info->num_sprites[pipe] = 2; 340 } else if (INTEL_GEN(dev_priv) >= 5) { 341 for_each_pipe(dev_priv, pipe) 342 info->num_sprites[pipe] = 1; 343 } 344 345 if (i915.disable_display) { 346 DRM_INFO("Display disabled (module parameter)\n"); 347 info->num_pipes = 0; 348 } else if (info->num_pipes > 0 && 349 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && 350 HAS_PCH_SPLIT(dev_priv)) { 351 u32 fuse_strap = I915_READ(FUSE_STRAP); 352 u32 sfuse_strap = I915_READ(SFUSE_STRAP); 353 354 /* 355 * SFUSE_STRAP is supposed to have a bit signalling the display 356 * is fused off. Unfortunately it seems that, at least in 357 * certain cases, fused off display means that PCH display 358 * reads don't land anywhere. In that case, we read 0s. 359 * 360 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK 361 * should be set when taking over after the firmware. 362 */ 363 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || 364 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 365 (dev_priv->pch_type == PCH_CPT && 366 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 367 DRM_INFO("Display fused off, disabling\n"); 368 info->num_pipes = 0; 369 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 370 DRM_INFO("PipeC fused off\n"); 371 info->num_pipes -= 1; 372 } 373 } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { 374 u32 dfsm = I915_READ(SKL_DFSM); 375 u8 disabled_mask = 0; 376 bool invalid; 377 int num_bits; 378 379 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) 380 disabled_mask |= BIT(PIPE_A); 381 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) 382 disabled_mask |= BIT(PIPE_B); 383 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) 384 disabled_mask |= BIT(PIPE_C); 385 386 num_bits = hweight8(disabled_mask); 387 388 switch (disabled_mask) { 389 case BIT(PIPE_A): 390 case BIT(PIPE_B): 391 case BIT(PIPE_A) | BIT(PIPE_B): 392 case BIT(PIPE_A) | BIT(PIPE_C): 393 invalid = true; 394 break; 395 default: 396 invalid = false; 397 } 398 399 if (num_bits > info->num_pipes || invalid) 400 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", 401 disabled_mask); 402 else 403 info->num_pipes -= num_bits; 404 } 405 406 /* Initialize slice/subslice/EU info */ 407 if (IS_CHERRYVIEW(dev_priv)) 408 cherryview_sseu_info_init(dev_priv); 409 else if (IS_BROADWELL(dev_priv)) 410 broadwell_sseu_info_init(dev_priv); 411 else if (INTEL_INFO(dev_priv)->gen >= 9) 412 gen9_sseu_info_init(dev_priv); 413 414 info->has_snoop = !info->has_llc; 415 416 DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask); 417 DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask)); 418 DRM_DEBUG_DRIVER("subslice total: %u\n", 419 sseu_subslice_total(&info->sseu)); 420 DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask); 421 DRM_DEBUG_DRIVER("subslice per slice: %u\n", 422 hweight8(info->sseu.subslice_mask)); 423 DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total); 424 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice); 425 DRM_DEBUG_DRIVER("has slice power gating: %s\n", 426 info->sseu.has_slice_pg ? "y" : "n"); 427 DRM_DEBUG_DRIVER("has subslice power gating: %s\n", 428 info->sseu.has_subslice_pg ? "y" : "n"); 429 DRM_DEBUG_DRIVER("has EU power gating: %s\n", 430 info->sseu.has_eu_pg ? "y" : "n"); 431 } 432