1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * $FreeBSD: src/sys/dev/drm2/i915/intel_display.c,v 1.2 2012/05/24 19:13:54 dim Exp $ 27 */ 28 29 #include <ddb/ddb.h> 30 #include <sys/limits.h> 31 32 #include <drm/drmP.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_crtc_helper.h> 39 40 #include <linux/err.h> 41 42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 43 44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type); 45 static void intel_increase_pllclock(struct drm_crtc *crtc); 46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 47 48 typedef struct { 49 /* given values */ 50 int n; 51 int m1, m2; 52 int p1, p2; 53 /* derived values */ 54 int dot; 55 int vco; 56 int m; 57 int p; 58 } intel_clock_t; 59 60 typedef struct { 61 int min, max; 62 } intel_range_t; 63 64 typedef struct { 65 int dot_limit; 66 int p2_slow, p2_fast; 67 } intel_p2_t; 68 69 #define INTEL_P2_NUM 2 70 typedef struct intel_limit intel_limit_t; 71 struct intel_limit { 72 intel_range_t dot, vco, n, m, m1, m2, p, p1; 73 intel_p2_t p2; 74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 75 int, int, intel_clock_t *, intel_clock_t *); 76 }; 77 78 /* FDI */ 79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ 80 81 static bool 82 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 83 int target, int refclk, intel_clock_t *match_clock, 84 intel_clock_t *best_clock); 85 static bool 86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 87 int target, int refclk, intel_clock_t *match_clock, 88 intel_clock_t *best_clock); 89 90 static bool 91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 92 int target, int refclk, intel_clock_t *match_clock, 93 intel_clock_t *best_clock); 94 static bool 95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, 96 int target, int refclk, intel_clock_t *match_clock, 97 intel_clock_t *best_clock); 98 99 static inline u32 /* units of 100MHz */ 100 intel_fdi_link_freq(struct drm_device *dev) 101 { 102 if (IS_GEN5(dev)) { 103 struct drm_i915_private *dev_priv = dev->dev_private; 104 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; 105 } else 106 return 27; 107 } 108 109 static const intel_limit_t intel_limits_i8xx_dvo = { 110 .dot = { .min = 25000, .max = 350000 }, 111 .vco = { .min = 930000, .max = 1400000 }, 112 .n = { .min = 3, .max = 16 }, 113 .m = { .min = 96, .max = 140 }, 114 .m1 = { .min = 18, .max = 26 }, 115 .m2 = { .min = 6, .max = 16 }, 116 .p = { .min = 4, .max = 128 }, 117 .p1 = { .min = 2, .max = 33 }, 118 .p2 = { .dot_limit = 165000, 119 .p2_slow = 4, .p2_fast = 2 }, 120 .find_pll = intel_find_best_PLL, 121 }; 122 123 static const intel_limit_t intel_limits_i8xx_lvds = { 124 .dot = { .min = 25000, .max = 350000 }, 125 .vco = { .min = 930000, .max = 1400000 }, 126 .n = { .min = 3, .max = 16 }, 127 .m = { .min = 96, .max = 140 }, 128 .m1 = { .min = 18, .max = 26 }, 129 .m2 = { .min = 6, .max = 16 }, 130 .p = { .min = 4, .max = 128 }, 131 .p1 = { .min = 1, .max = 6 }, 132 .p2 = { .dot_limit = 165000, 133 .p2_slow = 14, .p2_fast = 7 }, 134 .find_pll = intel_find_best_PLL, 135 }; 136 137 static const intel_limit_t intel_limits_i9xx_sdvo = { 138 .dot = { .min = 20000, .max = 400000 }, 139 .vco = { .min = 1400000, .max = 2800000 }, 140 .n = { .min = 1, .max = 6 }, 141 .m = { .min = 70, .max = 120 }, 142 .m1 = { .min = 10, .max = 22 }, 143 .m2 = { .min = 5, .max = 9 }, 144 .p = { .min = 5, .max = 80 }, 145 .p1 = { .min = 1, .max = 8 }, 146 .p2 = { .dot_limit = 200000, 147 .p2_slow = 10, .p2_fast = 5 }, 148 .find_pll = intel_find_best_PLL, 149 }; 150 151 static const intel_limit_t intel_limits_i9xx_lvds = { 152 .dot = { .min = 20000, .max = 400000 }, 153 .vco = { .min = 1400000, .max = 2800000 }, 154 .n = { .min = 1, .max = 6 }, 155 .m = { .min = 70, .max = 120 }, 156 .m1 = { .min = 10, .max = 22 }, 157 .m2 = { .min = 5, .max = 9 }, 158 .p = { .min = 7, .max = 98 }, 159 .p1 = { .min = 1, .max = 8 }, 160 .p2 = { .dot_limit = 112000, 161 .p2_slow = 14, .p2_fast = 7 }, 162 .find_pll = intel_find_best_PLL, 163 }; 164 165 166 static const intel_limit_t intel_limits_g4x_sdvo = { 167 .dot = { .min = 25000, .max = 270000 }, 168 .vco = { .min = 1750000, .max = 3500000}, 169 .n = { .min = 1, .max = 4 }, 170 .m = { .min = 104, .max = 138 }, 171 .m1 = { .min = 17, .max = 23 }, 172 .m2 = { .min = 5, .max = 11 }, 173 .p = { .min = 10, .max = 30 }, 174 .p1 = { .min = 1, .max = 3}, 175 .p2 = { .dot_limit = 270000, 176 .p2_slow = 10, 177 .p2_fast = 10 178 }, 179 .find_pll = intel_g4x_find_best_PLL, 180 }; 181 182 static const intel_limit_t intel_limits_g4x_hdmi = { 183 .dot = { .min = 22000, .max = 400000 }, 184 .vco = { .min = 1750000, .max = 3500000}, 185 .n = { .min = 1, .max = 4 }, 186 .m = { .min = 104, .max = 138 }, 187 .m1 = { .min = 16, .max = 23 }, 188 .m2 = { .min = 5, .max = 11 }, 189 .p = { .min = 5, .max = 80 }, 190 .p1 = { .min = 1, .max = 8}, 191 .p2 = { .dot_limit = 165000, 192 .p2_slow = 10, .p2_fast = 5 }, 193 .find_pll = intel_g4x_find_best_PLL, 194 }; 195 196 static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 197 .dot = { .min = 20000, .max = 115000 }, 198 .vco = { .min = 1750000, .max = 3500000 }, 199 .n = { .min = 1, .max = 3 }, 200 .m = { .min = 104, .max = 138 }, 201 .m1 = { .min = 17, .max = 23 }, 202 .m2 = { .min = 5, .max = 11 }, 203 .p = { .min = 28, .max = 112 }, 204 .p1 = { .min = 2, .max = 8 }, 205 .p2 = { .dot_limit = 0, 206 .p2_slow = 14, .p2_fast = 14 207 }, 208 .find_pll = intel_g4x_find_best_PLL, 209 }; 210 211 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 212 .dot = { .min = 80000, .max = 224000 }, 213 .vco = { .min = 1750000, .max = 3500000 }, 214 .n = { .min = 1, .max = 3 }, 215 .m = { .min = 104, .max = 138 }, 216 .m1 = { .min = 17, .max = 23 }, 217 .m2 = { .min = 5, .max = 11 }, 218 .p = { .min = 14, .max = 42 }, 219 .p1 = { .min = 2, .max = 6 }, 220 .p2 = { .dot_limit = 0, 221 .p2_slow = 7, .p2_fast = 7 222 }, 223 .find_pll = intel_g4x_find_best_PLL, 224 }; 225 226 static const intel_limit_t intel_limits_g4x_display_port = { 227 .dot = { .min = 161670, .max = 227000 }, 228 .vco = { .min = 1750000, .max = 3500000}, 229 .n = { .min = 1, .max = 2 }, 230 .m = { .min = 97, .max = 108 }, 231 .m1 = { .min = 0x10, .max = 0x12 }, 232 .m2 = { .min = 0x05, .max = 0x06 }, 233 .p = { .min = 10, .max = 20 }, 234 .p1 = { .min = 1, .max = 2}, 235 .p2 = { .dot_limit = 0, 236 .p2_slow = 10, .p2_fast = 10 }, 237 .find_pll = intel_find_pll_g4x_dp, 238 }; 239 240 static const intel_limit_t intel_limits_pineview_sdvo = { 241 .dot = { .min = 20000, .max = 400000}, 242 .vco = { .min = 1700000, .max = 3500000 }, 243 /* Pineview's Ncounter is a ring counter */ 244 .n = { .min = 3, .max = 6 }, 245 .m = { .min = 2, .max = 256 }, 246 /* Pineview only has one combined m divider, which we treat as m2. */ 247 .m1 = { .min = 0, .max = 0 }, 248 .m2 = { .min = 0, .max = 254 }, 249 .p = { .min = 5, .max = 80 }, 250 .p1 = { .min = 1, .max = 8 }, 251 .p2 = { .dot_limit = 200000, 252 .p2_slow = 10, .p2_fast = 5 }, 253 .find_pll = intel_find_best_PLL, 254 }; 255 256 static const intel_limit_t intel_limits_pineview_lvds = { 257 .dot = { .min = 20000, .max = 400000 }, 258 .vco = { .min = 1700000, .max = 3500000 }, 259 .n = { .min = 3, .max = 6 }, 260 .m = { .min = 2, .max = 256 }, 261 .m1 = { .min = 0, .max = 0 }, 262 .m2 = { .min = 0, .max = 254 }, 263 .p = { .min = 7, .max = 112 }, 264 .p1 = { .min = 1, .max = 8 }, 265 .p2 = { .dot_limit = 112000, 266 .p2_slow = 14, .p2_fast = 14 }, 267 .find_pll = intel_find_best_PLL, 268 }; 269 270 /* Ironlake / Sandybridge 271 * 272 * We calculate clock using (register_value + 2) for N/M1/M2, so here 273 * the range value for them is (actual_value - 2). 274 */ 275 static const intel_limit_t intel_limits_ironlake_dac = { 276 .dot = { .min = 25000, .max = 350000 }, 277 .vco = { .min = 1760000, .max = 3510000 }, 278 .n = { .min = 1, .max = 5 }, 279 .m = { .min = 79, .max = 127 }, 280 .m1 = { .min = 12, .max = 22 }, 281 .m2 = { .min = 5, .max = 9 }, 282 .p = { .min = 5, .max = 80 }, 283 .p1 = { .min = 1, .max = 8 }, 284 .p2 = { .dot_limit = 225000, 285 .p2_slow = 10, .p2_fast = 5 }, 286 .find_pll = intel_g4x_find_best_PLL, 287 }; 288 289 static const intel_limit_t intel_limits_ironlake_single_lvds = { 290 .dot = { .min = 25000, .max = 350000 }, 291 .vco = { .min = 1760000, .max = 3510000 }, 292 .n = { .min = 1, .max = 3 }, 293 .m = { .min = 79, .max = 118 }, 294 .m1 = { .min = 12, .max = 22 }, 295 .m2 = { .min = 5, .max = 9 }, 296 .p = { .min = 28, .max = 112 }, 297 .p1 = { .min = 2, .max = 8 }, 298 .p2 = { .dot_limit = 225000, 299 .p2_slow = 14, .p2_fast = 14 }, 300 .find_pll = intel_g4x_find_best_PLL, 301 }; 302 303 static const intel_limit_t intel_limits_ironlake_dual_lvds = { 304 .dot = { .min = 25000, .max = 350000 }, 305 .vco = { .min = 1760000, .max = 3510000 }, 306 .n = { .min = 1, .max = 3 }, 307 .m = { .min = 79, .max = 127 }, 308 .m1 = { .min = 12, .max = 22 }, 309 .m2 = { .min = 5, .max = 9 }, 310 .p = { .min = 14, .max = 56 }, 311 .p1 = { .min = 2, .max = 8 }, 312 .p2 = { .dot_limit = 225000, 313 .p2_slow = 7, .p2_fast = 7 }, 314 .find_pll = intel_g4x_find_best_PLL, 315 }; 316 317 /* LVDS 100mhz refclk limits. */ 318 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { 319 .dot = { .min = 25000, .max = 350000 }, 320 .vco = { .min = 1760000, .max = 3510000 }, 321 .n = { .min = 1, .max = 2 }, 322 .m = { .min = 79, .max = 126 }, 323 .m1 = { .min = 12, .max = 22 }, 324 .m2 = { .min = 5, .max = 9 }, 325 .p = { .min = 28, .max = 112 }, 326 .p1 = { .min = 2, .max = 8 }, 327 .p2 = { .dot_limit = 225000, 328 .p2_slow = 14, .p2_fast = 14 }, 329 .find_pll = intel_g4x_find_best_PLL, 330 }; 331 332 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 333 .dot = { .min = 25000, .max = 350000 }, 334 .vco = { .min = 1760000, .max = 3510000 }, 335 .n = { .min = 1, .max = 3 }, 336 .m = { .min = 79, .max = 126 }, 337 .m1 = { .min = 12, .max = 22 }, 338 .m2 = { .min = 5, .max = 9 }, 339 .p = { .min = 14, .max = 42 }, 340 .p1 = { .min = 2, .max = 6 }, 341 .p2 = { .dot_limit = 225000, 342 .p2_slow = 7, .p2_fast = 7 }, 343 .find_pll = intel_g4x_find_best_PLL, 344 }; 345 346 static const intel_limit_t intel_limits_ironlake_display_port = { 347 .dot = { .min = 25000, .max = 350000 }, 348 .vco = { .min = 1760000, .max = 3510000}, 349 .n = { .min = 1, .max = 2 }, 350 .m = { .min = 81, .max = 90 }, 351 .m1 = { .min = 12, .max = 22 }, 352 .m2 = { .min = 5, .max = 9 }, 353 .p = { .min = 10, .max = 20 }, 354 .p1 = { .min = 1, .max = 2}, 355 .p2 = { .dot_limit = 0, 356 .p2_slow = 10, .p2_fast = 10 }, 357 .find_pll = intel_find_pll_ironlake_dp, 358 }; 359 360 static void vlv_init_dpio(struct drm_device *dev) 361 { 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 364 /* Reset the DPIO config */ 365 I915_WRITE(DPIO_CTL, 0); 366 POSTING_READ(DPIO_CTL); 367 I915_WRITE(DPIO_CTL, 1); 368 POSTING_READ(DPIO_CTL); 369 } 370 371 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 372 int refclk) 373 { 374 struct drm_device *dev = crtc->dev; 375 struct drm_i915_private *dev_priv = dev->dev_private; 376 const intel_limit_t *limit; 377 378 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 379 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == 380 LVDS_CLKB_POWER_UP) { 381 /* LVDS dual channel */ 382 if (refclk == 100000) 383 limit = &intel_limits_ironlake_dual_lvds_100m; 384 else 385 limit = &intel_limits_ironlake_dual_lvds; 386 } else { 387 if (refclk == 100000) 388 limit = &intel_limits_ironlake_single_lvds_100m; 389 else 390 limit = &intel_limits_ironlake_single_lvds; 391 } 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 393 HAS_eDP) 394 limit = &intel_limits_ironlake_display_port; 395 else 396 limit = &intel_limits_ironlake_dac; 397 398 return limit; 399 } 400 401 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) 402 { 403 struct drm_device *dev = crtc->dev; 404 struct drm_i915_private *dev_priv = dev->dev_private; 405 const intel_limit_t *limit; 406 407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 408 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 409 LVDS_CLKB_POWER_UP) 410 /* LVDS with dual channel */ 411 limit = &intel_limits_g4x_dual_channel_lvds; 412 else 413 /* LVDS with dual channel */ 414 limit = &intel_limits_g4x_single_channel_lvds; 415 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || 416 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 417 limit = &intel_limits_g4x_hdmi; 418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 419 limit = &intel_limits_g4x_sdvo; 420 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 421 limit = &intel_limits_g4x_display_port; 422 } else /* The option is for other outputs */ 423 limit = &intel_limits_i9xx_sdvo; 424 425 return limit; 426 } 427 428 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) 429 { 430 struct drm_device *dev = crtc->dev; 431 const intel_limit_t *limit; 432 433 if (HAS_PCH_SPLIT(dev)) 434 limit = intel_ironlake_limit(crtc, refclk); 435 else if (IS_G4X(dev)) { 436 limit = intel_g4x_limit(crtc); 437 } else if (IS_PINEVIEW(dev)) { 438 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 439 limit = &intel_limits_pineview_lvds; 440 else 441 limit = &intel_limits_pineview_sdvo; 442 } else if (!IS_GEN2(dev)) { 443 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 444 limit = &intel_limits_i9xx_lvds; 445 else 446 limit = &intel_limits_i9xx_sdvo; 447 } else { 448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 449 limit = &intel_limits_i8xx_lvds; 450 else 451 limit = &intel_limits_i8xx_dvo; 452 } 453 return limit; 454 } 455 456 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 457 static void pineview_clock(int refclk, intel_clock_t *clock) 458 { 459 clock->m = clock->m2 + 2; 460 clock->p = clock->p1 * clock->p2; 461 clock->vco = refclk * clock->m / clock->n; 462 clock->dot = clock->vco / clock->p; 463 } 464 465 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 466 { 467 if (IS_PINEVIEW(dev)) { 468 pineview_clock(refclk, clock); 469 return; 470 } 471 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 472 clock->p = clock->p1 * clock->p2; 473 clock->vco = refclk * clock->m / (clock->n + 2); 474 clock->dot = clock->vco / clock->p; 475 } 476 477 /** 478 * Returns whether any output on the specified pipe is of the specified type 479 */ 480 bool intel_pipe_has_type(struct drm_crtc *crtc, int type) 481 { 482 struct drm_device *dev = crtc->dev; 483 struct drm_mode_config *mode_config = &dev->mode_config; 484 struct intel_encoder *encoder; 485 486 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 487 if (encoder->base.crtc == crtc && encoder->type == type) 488 return true; 489 490 return false; 491 } 492 493 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 494 /** 495 * Returns whether the given set of divisors are valid for a given refclk with 496 * the given connectors. 497 */ 498 499 static bool intel_PLL_is_valid(struct drm_device *dev, 500 const intel_limit_t *limit, 501 const intel_clock_t *clock) 502 { 503 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 504 INTELPllInvalid("p1 out of range\n"); 505 if (clock->p < limit->p.min || limit->p.max < clock->p) 506 INTELPllInvalid("p out of range\n"); 507 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 508 INTELPllInvalid("m2 out of range\n"); 509 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 510 INTELPllInvalid("m1 out of range\n"); 511 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) 512 INTELPllInvalid("m1 <= m2\n"); 513 if (clock->m < limit->m.min || limit->m.max < clock->m) 514 INTELPllInvalid("m out of range\n"); 515 if (clock->n < limit->n.min || limit->n.max < clock->n) 516 INTELPllInvalid("n out of range\n"); 517 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 518 INTELPllInvalid("vco out of range\n"); 519 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 520 * connector, etc., rather than just a single range. 521 */ 522 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 523 INTELPllInvalid("dot out of range\n"); 524 525 return true; 526 } 527 528 static bool 529 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 530 int target, int refclk, intel_clock_t *match_clock, 531 intel_clock_t *best_clock) 532 533 { 534 struct drm_device *dev = crtc->dev; 535 struct drm_i915_private *dev_priv = dev->dev_private; 536 intel_clock_t clock; 537 int err = target; 538 539 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 540 (I915_READ(LVDS)) != 0) { 541 /* 542 * For LVDS, if the panel is on, just rely on its current 543 * settings for dual-channel. We haven't figured out how to 544 * reliably set up different single/dual channel state, if we 545 * even can. 546 */ 547 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 548 LVDS_CLKB_POWER_UP) 549 clock.p2 = limit->p2.p2_fast; 550 else 551 clock.p2 = limit->p2.p2_slow; 552 } else { 553 if (target < limit->p2.dot_limit) 554 clock.p2 = limit->p2.p2_slow; 555 else 556 clock.p2 = limit->p2.p2_fast; 557 } 558 559 memset(best_clock, 0, sizeof(*best_clock)); 560 561 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 562 clock.m1++) { 563 for (clock.m2 = limit->m2.min; 564 clock.m2 <= limit->m2.max; clock.m2++) { 565 /* m1 is always 0 in Pineview */ 566 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) 567 break; 568 for (clock.n = limit->n.min; 569 clock.n <= limit->n.max; clock.n++) { 570 for (clock.p1 = limit->p1.min; 571 clock.p1 <= limit->p1.max; clock.p1++) { 572 int this_err; 573 574 intel_clock(dev, refclk, &clock); 575 if (!intel_PLL_is_valid(dev, limit, 576 &clock)) 577 continue; 578 if (match_clock && 579 clock.p != match_clock->p) 580 continue; 581 582 this_err = abs(clock.dot - target); 583 if (this_err < err) { 584 *best_clock = clock; 585 err = this_err; 586 } 587 } 588 } 589 } 590 } 591 592 return (err != target); 593 } 594 595 static bool 596 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 597 int target, int refclk, intel_clock_t *match_clock, 598 intel_clock_t *best_clock) 599 { 600 struct drm_device *dev = crtc->dev; 601 struct drm_i915_private *dev_priv = dev->dev_private; 602 intel_clock_t clock; 603 int max_n; 604 bool found; 605 /* approximately equals target * 0.00585 */ 606 int err_most = (target >> 8) + (target >> 9); 607 found = false; 608 609 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 610 int lvds_reg; 611 612 if (HAS_PCH_SPLIT(dev)) 613 lvds_reg = PCH_LVDS; 614 else 615 lvds_reg = LVDS; 616 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == 617 LVDS_CLKB_POWER_UP) 618 clock.p2 = limit->p2.p2_fast; 619 else 620 clock.p2 = limit->p2.p2_slow; 621 } else { 622 if (target < limit->p2.dot_limit) 623 clock.p2 = limit->p2.p2_slow; 624 else 625 clock.p2 = limit->p2.p2_fast; 626 } 627 628 memset(best_clock, 0, sizeof(*best_clock)); 629 max_n = limit->n.max; 630 /* based on hardware requirement, prefer smaller n to precision */ 631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 632 /* based on hardware requirement, prefere larger m1,m2 */ 633 for (clock.m1 = limit->m1.max; 634 clock.m1 >= limit->m1.min; clock.m1--) { 635 for (clock.m2 = limit->m2.max; 636 clock.m2 >= limit->m2.min; clock.m2--) { 637 for (clock.p1 = limit->p1.max; 638 clock.p1 >= limit->p1.min; clock.p1--) { 639 int this_err; 640 641 intel_clock(dev, refclk, &clock); 642 if (!intel_PLL_is_valid(dev, limit, 643 &clock)) 644 continue; 645 if (match_clock && 646 clock.p != match_clock->p) 647 continue; 648 649 this_err = abs(clock.dot - target); 650 if (this_err < err_most) { 651 *best_clock = clock; 652 err_most = this_err; 653 max_n = clock.n; 654 found = true; 655 } 656 } 657 } 658 } 659 } 660 return found; 661 } 662 663 static bool 664 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 665 int target, int refclk, intel_clock_t *match_clock, 666 intel_clock_t *best_clock) 667 { 668 struct drm_device *dev = crtc->dev; 669 intel_clock_t clock; 670 671 if (target < 200000) { 672 clock.n = 1; 673 clock.p1 = 2; 674 clock.p2 = 10; 675 clock.m1 = 12; 676 clock.m2 = 9; 677 } else { 678 clock.n = 2; 679 clock.p1 = 1; 680 clock.p2 = 10; 681 clock.m1 = 14; 682 clock.m2 = 8; 683 } 684 intel_clock(dev, refclk, &clock); 685 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 686 return true; 687 } 688 689 /* DisplayPort has only two frequencies, 162MHz and 270MHz */ 690 static bool 691 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 692 int target, int refclk, intel_clock_t *match_clock, 693 intel_clock_t *best_clock) 694 { 695 intel_clock_t clock; 696 if (target < 200000) { 697 clock.p1 = 2; 698 clock.p2 = 10; 699 clock.n = 2; 700 clock.m1 = 23; 701 clock.m2 = 8; 702 } else { 703 clock.p1 = 1; 704 clock.p2 = 10; 705 clock.n = 1; 706 clock.m1 = 14; 707 clock.m2 = 2; 708 } 709 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); 710 clock.p = (clock.p1 * clock.p2); 711 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; 712 clock.vco = 0; 713 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 714 return true; 715 } 716 717 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 718 enum i915_pipe pipe) 719 { 720 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 722 723 return intel_crtc->cpu_transcoder; 724 } 725 726 /** 727 * intel_wait_for_vblank - wait for vblank on a given pipe 728 * @dev: drm device 729 * @pipe: pipe to wait for 730 * 731 * Wait for vblank to occur on a given pipe. Needed for various bits of 732 * mode setting code. 733 */ 734 void intel_wait_for_vblank(struct drm_device *dev, int pipe) 735 { 736 struct drm_i915_private *dev_priv = dev->dev_private; 737 int pipestat_reg = PIPESTAT(pipe); 738 739 /* Clear existing vblank status. Note this will clear any other 740 * sticky status fields as well. 741 * 742 * This races with i915_driver_irq_handler() with the result 743 * that either function could miss a vblank event. Here it is not 744 * fatal, as we will either wait upon the next vblank interrupt or 745 * timeout. Generally speaking intel_wait_for_vblank() is only 746 * called during modeset at which time the GPU should be idle and 747 * should *not* be performing page flips and thus not waiting on 748 * vblanks... 749 * Currently, the result of us stealing a vblank from the irq 750 * handler is that a single frame will be skipped during swapbuffers. 751 */ 752 I915_WRITE(pipestat_reg, 753 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); 754 755 /* Wait for vblank interrupt bit to set */ 756 if (_intel_wait_for(dev, 757 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS, 758 50, 1, "915vbl")) 759 DRM_DEBUG_KMS("vblank wait timed out\n"); 760 } 761 762 /* 763 * intel_wait_for_pipe_off - wait for pipe to turn off 764 * @dev: drm device 765 * @pipe: pipe to wait for 766 * 767 * After disabling a pipe, we can't wait for vblank in the usual way, 768 * spinning on the vblank interrupt status bit, since we won't actually 769 * see an interrupt when the pipe is disabled. 770 * 771 * On Gen4 and above: 772 * wait for the pipe register state bit to turn off 773 * 774 * Otherwise: 775 * wait for the display line value to settle (it usually 776 * ends up stopping at the start of the next frame). 777 * 778 */ 779 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) 780 { 781 struct drm_i915_private *dev_priv = dev->dev_private; 782 783 if (INTEL_INFO(dev)->gen >= 4) { 784 int reg = PIPECONF(pipe); 785 786 /* Wait for the Pipe State to go off */ 787 if (_intel_wait_for(dev, 788 (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100, 789 1, "915pip")) 790 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 791 } else { 792 u32 last_line, line_mask; 793 int reg = PIPEDSL(pipe); 794 unsigned long timeout = jiffies + msecs_to_jiffies(100); 795 796 if (IS_GEN2(dev)) 797 line_mask = DSL_LINEMASK_GEN2; 798 else 799 line_mask = DSL_LINEMASK_GEN3; 800 801 /* Wait for the display line to settle */ 802 do { 803 last_line = I915_READ(reg) & line_mask; 804 DELAY(5000); 805 } while (((I915_READ(reg) & line_mask) != last_line) && 806 time_after(timeout, jiffies)); 807 if (time_after(jiffies, timeout)) 808 DRM_DEBUG_KMS("pipe_off wait timed out\n"); 809 } 810 } 811 812 static const char *state_string(bool enabled) 813 { 814 return enabled ? "on" : "off"; 815 } 816 817 /* Only for pre-ILK configs */ 818 static void assert_pll(struct drm_i915_private *dev_priv, 819 enum i915_pipe pipe, bool state) 820 { 821 int reg; 822 u32 val; 823 bool cur_state; 824 825 reg = DPLL(pipe); 826 val = I915_READ(reg); 827 cur_state = !!(val & DPLL_VCO_ENABLE); 828 if (cur_state != state) 829 kprintf("PLL state assertion failure (expected %s, current %s)\n", 830 state_string(state), state_string(cur_state)); 831 } 832 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 833 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 834 835 /* For ILK+ */ 836 static void assert_pch_pll(struct drm_i915_private *dev_priv, 837 enum i915_pipe pipe, bool state) 838 { 839 int reg; 840 u32 val; 841 bool cur_state; 842 843 if (HAS_PCH_CPT(dev_priv->dev)) { 844 u32 pch_dpll; 845 846 pch_dpll = I915_READ(PCH_DPLL_SEL); 847 848 /* Make sure the selected PLL is enabled to the transcoder */ 849 KASSERT(((pch_dpll >> (4 * pipe)) & 8) != 0, 850 ("transcoder %d PLL not enabled\n", pipe)); 851 852 /* Convert the transcoder pipe number to a pll pipe number */ 853 pipe = (pch_dpll >> (4 * pipe)) & 1; 854 } 855 856 reg = _PCH_DPLL(pipe); 857 val = I915_READ(reg); 858 cur_state = !!(val & DPLL_VCO_ENABLE); 859 if (cur_state != state) 860 kprintf("PCH PLL state assertion failure (expected %s, current %s)\n", 861 state_string(state), state_string(cur_state)); 862 } 863 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) 864 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) 865 866 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 867 enum i915_pipe pipe, bool state) 868 { 869 int reg; 870 u32 val; 871 bool cur_state; 872 873 reg = FDI_TX_CTL(pipe); 874 val = I915_READ(reg); 875 cur_state = !!(val & FDI_TX_ENABLE); 876 if (cur_state != state) 877 kprintf("FDI TX state assertion failure (expected %s, current %s)\n", 878 state_string(state), state_string(cur_state)); 879 } 880 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) 881 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) 882 883 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 884 enum i915_pipe pipe, bool state) 885 { 886 int reg; 887 u32 val; 888 bool cur_state; 889 890 reg = FDI_RX_CTL(pipe); 891 val = I915_READ(reg); 892 cur_state = !!(val & FDI_RX_ENABLE); 893 if (cur_state != state) 894 kprintf("FDI RX state assertion failure (expected %s, current %s)\n", 895 state_string(state), state_string(cur_state)); 896 } 897 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) 898 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) 899 900 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 901 enum i915_pipe pipe) 902 { 903 int reg; 904 u32 val; 905 906 /* ILK FDI PLL is always enabled */ 907 if (dev_priv->info->gen == 5) 908 return; 909 910 reg = FDI_TX_CTL(pipe); 911 val = I915_READ(reg); 912 if (!(val & FDI_TX_PLL_ENABLE)) 913 kprintf("FDI TX PLL assertion failure, should be active but is disabled\n"); 914 } 915 916 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, 917 enum i915_pipe pipe) 918 { 919 int reg; 920 u32 val; 921 922 reg = FDI_RX_CTL(pipe); 923 val = I915_READ(reg); 924 if (!(val & FDI_RX_PLL_ENABLE)) 925 kprintf("FDI RX PLL assertion failure, should be active but is disabled\n"); 926 } 927 928 static void assert_panel_unlocked(struct drm_i915_private *dev_priv, 929 enum i915_pipe pipe) 930 { 931 int pp_reg, lvds_reg; 932 u32 val; 933 enum i915_pipe panel_pipe = PIPE_A; 934 bool locked = true; 935 936 if (HAS_PCH_SPLIT(dev_priv->dev)) { 937 pp_reg = PCH_PP_CONTROL; 938 lvds_reg = PCH_LVDS; 939 } else { 940 pp_reg = PP_CONTROL; 941 lvds_reg = LVDS; 942 } 943 944 val = I915_READ(pp_reg); 945 if (!(val & PANEL_POWER_ON) || 946 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) 947 locked = false; 948 949 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) 950 panel_pipe = PIPE_B; 951 952 if (panel_pipe == pipe && locked) 953 kprintf("panel assertion failure, pipe %c regs locked\n", 954 pipe_name(pipe)); 955 } 956 957 void assert_pipe(struct drm_i915_private *dev_priv, 958 enum i915_pipe pipe, bool state) 959 { 960 int reg; 961 u32 val; 962 bool cur_state; 963 964 /* if we need the pipe A quirk it must be always on */ 965 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 966 state = true; 967 968 reg = PIPECONF(pipe); 969 val = I915_READ(reg); 970 cur_state = !!(val & PIPECONF_ENABLE); 971 if (cur_state != state) 972 kprintf("pipe %c assertion failure (expected %s, current %s)\n", 973 pipe_name(pipe), state_string(state), state_string(cur_state)); 974 } 975 976 static void assert_plane(struct drm_i915_private *dev_priv, 977 enum plane plane, bool state) 978 { 979 int reg; 980 u32 val; 981 bool cur_state; 982 983 reg = DSPCNTR(plane); 984 val = I915_READ(reg); 985 cur_state = !!(val & DISPLAY_PLANE_ENABLE); 986 if (cur_state != state) 987 kprintf("plane %c assertion failure, (expected %s, current %s)\n", 988 plane_name(plane), state_string(state), state_string(cur_state)); 989 } 990 991 #define assert_plane_enabled(d, p) assert_plane(d, p, true) 992 #define assert_plane_disabled(d, p) assert_plane(d, p, false) 993 994 static void assert_planes_disabled(struct drm_i915_private *dev_priv, 995 enum i915_pipe pipe) 996 { 997 int reg, i; 998 u32 val; 999 int cur_pipe; 1000 1001 /* Planes are fixed to pipes on ILK+ */ 1002 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1003 reg = DSPCNTR(pipe); 1004 val = I915_READ(reg); 1005 if ((val & DISPLAY_PLANE_ENABLE) != 0) 1006 kprintf("plane %c assertion failure, should be disabled but not\n", 1007 plane_name(pipe)); 1008 return; 1009 } 1010 1011 /* Need to check both planes against the pipe */ 1012 for (i = 0; i < 2; i++) { 1013 reg = DSPCNTR(i); 1014 val = I915_READ(reg); 1015 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1016 DISPPLANE_SEL_PIPE_SHIFT; 1017 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe) 1018 kprintf("plane %c assertion failure, should be off on pipe %c but is still active\n", 1019 plane_name(i), pipe_name(pipe)); 1020 } 1021 } 1022 1023 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1024 { 1025 u32 val; 1026 bool enabled; 1027 1028 val = I915_READ(PCH_DREF_CONTROL); 1029 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 1030 DREF_SUPERSPREAD_SOURCE_MASK)); 1031 if (!enabled) 1032 kprintf("PCH refclk assertion failure, should be active but is disabled\n"); 1033 } 1034 1035 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, 1036 enum i915_pipe pipe) 1037 { 1038 int reg; 1039 u32 val; 1040 bool enabled; 1041 1042 reg = TRANSCONF(pipe); 1043 val = I915_READ(reg); 1044 enabled = !!(val & TRANS_ENABLE); 1045 if (enabled) 1046 kprintf("transcoder assertion failed, should be off on pipe %c but is still active\n", 1047 pipe_name(pipe)); 1048 } 1049 1050 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1051 enum i915_pipe pipe, u32 val) 1052 { 1053 if ((val & PORT_ENABLE) == 0) 1054 return false; 1055 1056 if (HAS_PCH_CPT(dev_priv->dev)) { 1057 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1058 return false; 1059 } else { 1060 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) 1061 return false; 1062 } 1063 return true; 1064 } 1065 1066 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, 1067 enum i915_pipe pipe, u32 val) 1068 { 1069 if ((val & LVDS_PORT_EN) == 0) 1070 return false; 1071 1072 if (HAS_PCH_CPT(dev_priv->dev)) { 1073 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1074 return false; 1075 } else { 1076 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) 1077 return false; 1078 } 1079 return true; 1080 } 1081 1082 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, 1083 enum i915_pipe pipe, u32 val) 1084 { 1085 if ((val & ADPA_DAC_ENABLE) == 0) 1086 return false; 1087 if (HAS_PCH_CPT(dev_priv->dev)) { 1088 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1089 return false; 1090 } else { 1091 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) 1092 return false; 1093 } 1094 return true; 1095 } 1096 1097 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 1098 enum i915_pipe pipe, u32 port_sel, u32 val) 1099 { 1100 if ((val & DP_PORT_EN) == 0) 1101 return false; 1102 1103 if (HAS_PCH_CPT(dev_priv->dev)) { 1104 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); 1105 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); 1106 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) 1107 return false; 1108 } else { 1109 if ((val & DP_PIPE_MASK) != (pipe << 30)) 1110 return false; 1111 } 1112 return true; 1113 } 1114 1115 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1116 enum i915_pipe pipe, int reg, u32 port_sel) 1117 { 1118 u32 val = I915_READ(reg); 1119 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) 1120 kprintf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1121 reg, pipe_name(pipe)); 1122 } 1123 1124 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1125 enum i915_pipe pipe, int reg) 1126 { 1127 u32 val = I915_READ(reg); 1128 if (hdmi_pipe_enabled(dev_priv, val, pipe)) 1129 kprintf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1130 reg, pipe_name(pipe)); 1131 } 1132 1133 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1134 enum i915_pipe pipe) 1135 { 1136 int reg; 1137 u32 val; 1138 1139 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1140 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1141 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1142 1143 reg = PCH_ADPA; 1144 val = I915_READ(reg); 1145 if (adpa_pipe_enabled(dev_priv, val, pipe)) 1146 kprintf("PCH VGA enabled on transcoder %c, should be disabled\n", 1147 pipe_name(pipe)); 1148 1149 reg = PCH_LVDS; 1150 val = I915_READ(reg); 1151 if (lvds_pipe_enabled(dev_priv, val, pipe)) 1152 kprintf("PCH LVDS enabled on transcoder %c, should be disabled\n", 1153 pipe_name(pipe)); 1154 1155 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); 1156 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); 1157 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); 1158 } 1159 1160 /** 1161 * intel_enable_pll - enable a PLL 1162 * @dev_priv: i915 private structure 1163 * @pipe: pipe PLL to enable 1164 * 1165 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to 1166 * make sure the PLL reg is writable first though, since the panel write 1167 * protect mechanism may be enabled. 1168 * 1169 * Note! This is for pre-ILK only. 1170 */ 1171 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1172 { 1173 int reg; 1174 u32 val; 1175 1176 /* No really, not for ILK+ */ 1177 KASSERT(dev_priv->info->gen < 5, ("Wrong device gen")); 1178 1179 /* PLL is protected by panel, make sure we can write it */ 1180 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) 1181 assert_panel_unlocked(dev_priv, pipe); 1182 1183 reg = DPLL(pipe); 1184 val = I915_READ(reg); 1185 val |= DPLL_VCO_ENABLE; 1186 1187 /* We do this three times for luck */ 1188 I915_WRITE(reg, val); 1189 POSTING_READ(reg); 1190 DELAY(150); /* wait for warmup */ 1191 I915_WRITE(reg, val); 1192 POSTING_READ(reg); 1193 DELAY(150); /* wait for warmup */ 1194 I915_WRITE(reg, val); 1195 POSTING_READ(reg); 1196 DELAY(150); /* wait for warmup */ 1197 } 1198 1199 /** 1200 * intel_disable_pll - disable a PLL 1201 * @dev_priv: i915 private structure 1202 * @pipe: pipe PLL to disable 1203 * 1204 * Disable the PLL for @pipe, making sure the pipe is off first. 1205 * 1206 * Note! This is for pre-ILK only. 1207 */ 1208 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1209 { 1210 int reg; 1211 u32 val; 1212 1213 /* Don't disable pipe A or pipe A PLLs if needed */ 1214 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1215 return; 1216 1217 /* Make sure the pipe isn't still relying on us */ 1218 assert_pipe_disabled(dev_priv, pipe); 1219 1220 reg = DPLL(pipe); 1221 val = I915_READ(reg); 1222 val &= ~DPLL_VCO_ENABLE; 1223 I915_WRITE(reg, val); 1224 POSTING_READ(reg); 1225 } 1226 1227 /** 1228 * intel_enable_pch_pll - enable PCH PLL 1229 * @dev_priv: i915 private structure 1230 * @pipe: pipe PLL to enable 1231 * 1232 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1233 * drives the transcoder clock. 1234 */ 1235 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, 1236 enum i915_pipe pipe) 1237 { 1238 int reg; 1239 u32 val; 1240 1241 if (pipe > 1) 1242 return; 1243 1244 /* PCH only available on ILK+ */ 1245 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1246 1247 /* PCH refclock must be enabled first */ 1248 assert_pch_refclk_enabled(dev_priv); 1249 1250 reg = _PCH_DPLL(pipe); 1251 val = I915_READ(reg); 1252 val |= DPLL_VCO_ENABLE; 1253 I915_WRITE(reg, val); 1254 POSTING_READ(reg); 1255 DELAY(200); 1256 } 1257 1258 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, 1259 enum i915_pipe pipe) 1260 { 1261 int reg; 1262 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, 1263 pll_sel = TRANSC_DPLL_ENABLE; 1264 1265 if (pipe > 1) 1266 return; 1267 1268 /* PCH only available on ILK+ */ 1269 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1270 1271 /* Make sure transcoder isn't still depending on us */ 1272 assert_transcoder_disabled(dev_priv, pipe); 1273 1274 if (pipe == 0) 1275 pll_sel |= TRANSC_DPLLA_SEL; 1276 else if (pipe == 1) 1277 pll_sel |= TRANSC_DPLLB_SEL; 1278 1279 1280 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) 1281 return; 1282 1283 reg = _PCH_DPLL(pipe); 1284 val = I915_READ(reg); 1285 val &= ~DPLL_VCO_ENABLE; 1286 I915_WRITE(reg, val); 1287 POSTING_READ(reg); 1288 DELAY(200); 1289 } 1290 1291 static void intel_enable_transcoder(struct drm_i915_private *dev_priv, 1292 enum i915_pipe pipe) 1293 { 1294 int reg; 1295 u32 val, pipeconf_val; 1296 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1297 1298 /* PCH only available on ILK+ */ 1299 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen")); 1300 1301 /* Make sure PCH DPLL is enabled */ 1302 assert_pch_pll_enabled(dev_priv, pipe); 1303 1304 /* FDI must be feeding us bits for PCH ports */ 1305 assert_fdi_tx_enabled(dev_priv, pipe); 1306 assert_fdi_rx_enabled(dev_priv, pipe); 1307 1308 1309 reg = TRANSCONF(pipe); 1310 val = I915_READ(reg); 1311 pipeconf_val = I915_READ(PIPECONF(pipe)); 1312 1313 if (HAS_PCH_IBX(dev_priv->dev)) { 1314 /* 1315 * make the BPC in transcoder be consistent with 1316 * that in pipeconf reg. 1317 */ 1318 val &= ~PIPE_BPC_MASK; 1319 val |= pipeconf_val & PIPE_BPC_MASK; 1320 } 1321 1322 val &= ~TRANS_INTERLACE_MASK; 1323 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1324 if (HAS_PCH_IBX(dev_priv->dev) && 1325 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) 1326 val |= TRANS_LEGACY_INTERLACED_ILK; 1327 else 1328 val |= TRANS_INTERLACED; 1329 else 1330 val |= TRANS_PROGRESSIVE; 1331 1332 I915_WRITE(reg, val | TRANS_ENABLE); 1333 if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE, 1334 100, 1, "915trc")) 1335 DRM_ERROR("failed to enable transcoder %d\n", pipe); 1336 } 1337 1338 static void intel_disable_transcoder(struct drm_i915_private *dev_priv, 1339 enum i915_pipe pipe) 1340 { 1341 int reg; 1342 u32 val; 1343 1344 /* FDI relies on the transcoder */ 1345 assert_fdi_tx_disabled(dev_priv, pipe); 1346 assert_fdi_rx_disabled(dev_priv, pipe); 1347 1348 /* Ports must be off as well */ 1349 assert_pch_ports_disabled(dev_priv, pipe); 1350 1351 reg = TRANSCONF(pipe); 1352 val = I915_READ(reg); 1353 val &= ~TRANS_ENABLE; 1354 I915_WRITE(reg, val); 1355 /* wait for PCH transcoder off, transcoder state */ 1356 if (_intel_wait_for(dev_priv->dev, 1357 (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50, 1358 1, "915trd")) 1359 DRM_ERROR("failed to disable transcoder %d\n", pipe); 1360 } 1361 1362 /** 1363 * intel_enable_pipe - enable a pipe, asserting requirements 1364 * @dev_priv: i915 private structure 1365 * @pipe: pipe to enable 1366 * @pch_port: on ILK+, is this pipe driving a PCH port or not 1367 * 1368 * Enable @pipe, making sure that various hardware specific requirements 1369 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1370 * 1371 * @pipe should be %PIPE_A or %PIPE_B. 1372 * 1373 * Will wait until the pipe is actually running (i.e. first vblank) before 1374 * returning. 1375 */ 1376 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 1377 bool pch_port) 1378 { 1379 int reg; 1380 u32 val; 1381 1382 /* 1383 * A pipe without a PLL won't actually be able to drive bits from 1384 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 1385 * need the check. 1386 */ 1387 if (!HAS_PCH_SPLIT(dev_priv->dev)) 1388 assert_pll_enabled(dev_priv, pipe); 1389 else { 1390 if (pch_port) { 1391 /* if driving the PCH, we need FDI enabled */ 1392 assert_fdi_rx_pll_enabled(dev_priv, pipe); 1393 assert_fdi_tx_pll_enabled(dev_priv, pipe); 1394 } 1395 /* FIXME: assert CPU port conditions for SNB+ */ 1396 } 1397 1398 reg = PIPECONF(pipe); 1399 val = I915_READ(reg); 1400 if (val & PIPECONF_ENABLE) 1401 return; 1402 1403 I915_WRITE(reg, val | PIPECONF_ENABLE); 1404 intel_wait_for_vblank(dev_priv->dev, pipe); 1405 } 1406 1407 /** 1408 * intel_disable_pipe - disable a pipe, asserting requirements 1409 * @dev_priv: i915 private structure 1410 * @pipe: pipe to disable 1411 * 1412 * Disable @pipe, making sure that various hardware specific requirements 1413 * are met, if applicable, e.g. plane disabled, panel fitter off, etc. 1414 * 1415 * @pipe should be %PIPE_A or %PIPE_B. 1416 * 1417 * Will wait until the pipe has shut down before returning. 1418 */ 1419 static void intel_disable_pipe(struct drm_i915_private *dev_priv, 1420 enum i915_pipe pipe) 1421 { 1422 int reg; 1423 u32 val; 1424 1425 /* 1426 * Make sure planes won't keep trying to pump pixels to us, 1427 * or we might hang the display. 1428 */ 1429 assert_planes_disabled(dev_priv, pipe); 1430 1431 /* Don't disable pipe A or pipe A PLLs if needed */ 1432 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1433 return; 1434 1435 reg = PIPECONF(pipe); 1436 val = I915_READ(reg); 1437 if ((val & PIPECONF_ENABLE) == 0) 1438 return; 1439 1440 I915_WRITE(reg, val & ~PIPECONF_ENABLE); 1441 intel_wait_for_pipe_off(dev_priv->dev, pipe); 1442 } 1443 1444 /* 1445 * Plane regs are double buffered, going from enabled->disabled needs a 1446 * trigger in order to latch. The display address reg provides this. 1447 */ 1448 void intel_flush_display_plane(struct drm_i915_private *dev_priv, 1449 enum plane plane) 1450 { 1451 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); 1452 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); 1453 } 1454 1455 /** 1456 * intel_enable_plane - enable a display plane on a given pipe 1457 * @dev_priv: i915 private structure 1458 * @plane: plane to enable 1459 * @pipe: pipe being fed 1460 * 1461 * Enable @plane on @pipe, making sure that @pipe is running first. 1462 */ 1463 static void intel_enable_plane(struct drm_i915_private *dev_priv, 1464 enum plane plane, enum i915_pipe pipe) 1465 { 1466 int reg; 1467 u32 val; 1468 1469 /* If the pipe isn't enabled, we can't pump pixels and may hang */ 1470 assert_pipe_enabled(dev_priv, pipe); 1471 1472 reg = DSPCNTR(plane); 1473 val = I915_READ(reg); 1474 if (val & DISPLAY_PLANE_ENABLE) 1475 return; 1476 1477 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); 1478 intel_flush_display_plane(dev_priv, plane); 1479 intel_wait_for_vblank(dev_priv->dev, pipe); 1480 } 1481 1482 /** 1483 * intel_disable_plane - disable a display plane 1484 * @dev_priv: i915 private structure 1485 * @plane: plane to disable 1486 * @pipe: pipe consuming the data 1487 * 1488 * Disable @plane; should be an independent operation. 1489 */ 1490 static void intel_disable_plane(struct drm_i915_private *dev_priv, 1491 enum plane plane, enum i915_pipe pipe) 1492 { 1493 int reg; 1494 u32 val; 1495 1496 reg = DSPCNTR(plane); 1497 val = I915_READ(reg); 1498 if ((val & DISPLAY_PLANE_ENABLE) == 0) 1499 return; 1500 1501 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); 1502 intel_flush_display_plane(dev_priv, plane); 1503 intel_wait_for_vblank(dev_priv->dev, pipe); 1504 } 1505 1506 static void disable_pch_dp(struct drm_i915_private *dev_priv, 1507 enum i915_pipe pipe, int reg, u32 port_sel) 1508 { 1509 u32 val = I915_READ(reg); 1510 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { 1511 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); 1512 I915_WRITE(reg, val & ~DP_PORT_EN); 1513 } 1514 } 1515 1516 static void disable_pch_hdmi(struct drm_i915_private *dev_priv, 1517 enum i915_pipe pipe, int reg) 1518 { 1519 u32 val = I915_READ(reg); 1520 if (hdmi_pipe_enabled(dev_priv, val, pipe)) { 1521 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", 1522 reg, pipe); 1523 I915_WRITE(reg, val & ~PORT_ENABLE); 1524 } 1525 } 1526 1527 /* Disable any ports connected to this transcoder */ 1528 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, 1529 enum i915_pipe pipe) 1530 { 1531 u32 reg, val; 1532 1533 val = I915_READ(PCH_PP_CONTROL); 1534 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); 1535 1536 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1537 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1538 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1539 1540 reg = PCH_ADPA; 1541 val = I915_READ(reg); 1542 if (adpa_pipe_enabled(dev_priv, val, pipe)) 1543 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); 1544 1545 reg = PCH_LVDS; 1546 val = I915_READ(reg); 1547 if (lvds_pipe_enabled(dev_priv, val, pipe)) { 1548 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); 1549 I915_WRITE(reg, val & ~LVDS_PORT_EN); 1550 POSTING_READ(reg); 1551 DELAY(100); 1552 } 1553 1554 disable_pch_hdmi(dev_priv, pipe, HDMIB); 1555 disable_pch_hdmi(dev_priv, pipe, HDMIC); 1556 disable_pch_hdmi(dev_priv, pipe, HDMID); 1557 } 1558 1559 int 1560 intel_pin_and_fence_fb_obj(struct drm_device *dev, 1561 struct drm_i915_gem_object *obj, 1562 struct intel_ring_buffer *pipelined) 1563 { 1564 struct drm_i915_private *dev_priv = dev->dev_private; 1565 u32 alignment; 1566 int ret; 1567 1568 alignment = 0; /* shut gcc */ 1569 switch (obj->tiling_mode) { 1570 case I915_TILING_NONE: 1571 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) 1572 alignment = 128 * 1024; 1573 else if (INTEL_INFO(dev)->gen >= 4) 1574 alignment = 4 * 1024; 1575 else 1576 alignment = 64 * 1024; 1577 break; 1578 case I915_TILING_X: 1579 /* pin() will align the object as required by fence */ 1580 alignment = 0; 1581 break; 1582 case I915_TILING_Y: 1583 /* FIXME: Is this true? */ 1584 DRM_ERROR("Y tiled not allowed for scan out buffers\n"); 1585 return -EINVAL; 1586 default: 1587 KASSERT(0, ("Wrong tiling for fb obj")); 1588 } 1589 1590 dev_priv->mm.interruptible = false; 1591 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); 1592 if (ret) 1593 goto err_interruptible; 1594 1595 /* Install a fence for tiled scan-out. Pre-i965 always needs a 1596 * fence, whereas 965+ only requires a fence if using 1597 * framebuffer compression. For simplicity, we always install 1598 * a fence as the cost is not that onerous. 1599 */ 1600 if (obj->tiling_mode != I915_TILING_NONE) { 1601 ret = i915_gem_object_get_fence(obj); 1602 if (ret) 1603 goto err_unpin; 1604 1605 i915_gem_object_pin_fence(obj); 1606 } 1607 1608 dev_priv->mm.interruptible = true; 1609 return 0; 1610 1611 err_unpin: 1612 i915_gem_object_unpin(obj); 1613 err_interruptible: 1614 dev_priv->mm.interruptible = true; 1615 return ret; 1616 } 1617 1618 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) 1619 { 1620 i915_gem_object_unpin_fence(obj); 1621 i915_gem_object_unpin(obj); 1622 } 1623 1624 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel 1625 * is assumed to be a power-of-two. */ 1626 unsigned long intel_gen4_compute_page_offset(int *x, int *y, 1627 unsigned int tiling_mode, 1628 unsigned int cpp, 1629 unsigned int pitch) 1630 { 1631 if (tiling_mode != I915_TILING_NONE) { 1632 unsigned int tile_rows, tiles; 1633 1634 tile_rows = *y / 8; 1635 *y %= 8; 1636 1637 tiles = *x / (512/cpp); 1638 *x %= 512/cpp; 1639 1640 return tile_rows * pitch * 8 + tiles * 4096; 1641 } else { 1642 unsigned int offset; 1643 1644 offset = *y * pitch + *x * cpp; 1645 *y = 0; 1646 *x = (offset & 4095) / cpp; 1647 return offset & -4096; 1648 } 1649 } 1650 1651 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1652 int x, int y) 1653 { 1654 struct drm_device *dev = crtc->dev; 1655 struct drm_i915_private *dev_priv = dev->dev_private; 1656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1657 struct intel_framebuffer *intel_fb; 1658 struct drm_i915_gem_object *obj; 1659 int plane = intel_crtc->plane; 1660 unsigned long Start, Offset; 1661 u32 dspcntr; 1662 u32 reg; 1663 1664 switch (plane) { 1665 case 0: 1666 case 1: 1667 break; 1668 default: 1669 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1670 return -EINVAL; 1671 } 1672 1673 intel_fb = to_intel_framebuffer(fb); 1674 obj = intel_fb->obj; 1675 1676 reg = DSPCNTR(plane); 1677 dspcntr = I915_READ(reg); 1678 /* Mask out pixel format bits in case we change it */ 1679 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1680 switch (fb->bits_per_pixel) { 1681 case 8: 1682 dspcntr |= DISPPLANE_8BPP; 1683 break; 1684 case 16: 1685 if (fb->depth == 15) 1686 dspcntr |= DISPPLANE_BGRX555; 1687 else 1688 dspcntr |= DISPPLANE_BGRX565; 1689 break; 1690 case 24: 1691 case 32: 1692 dspcntr |= DISPPLANE_BGRX888; 1693 break; 1694 default: 1695 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); 1696 return -EINVAL; 1697 } 1698 if (INTEL_INFO(dev)->gen >= 4) { 1699 if (obj->tiling_mode != I915_TILING_NONE) 1700 dspcntr |= DISPPLANE_TILED; 1701 else 1702 dspcntr &= ~DISPPLANE_TILED; 1703 } 1704 1705 I915_WRITE(reg, dspcntr); 1706 1707 Start = obj->gtt_offset; 1708 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1709 1710 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 1711 Start, Offset, x, y, fb->pitches[0]); 1712 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1713 if (INTEL_INFO(dev)->gen >= 4) { 1714 I915_WRITE(DSPSURF(plane), Start); 1715 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1716 I915_WRITE(DSPADDR(plane), Offset); 1717 } else 1718 I915_WRITE(DSPADDR(plane), Start + Offset); 1719 POSTING_READ(reg); 1720 1721 return (0); 1722 } 1723 1724 static int ironlake_update_plane(struct drm_crtc *crtc, 1725 struct drm_framebuffer *fb, int x, int y) 1726 { 1727 struct drm_device *dev = crtc->dev; 1728 struct drm_i915_private *dev_priv = dev->dev_private; 1729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1730 struct intel_framebuffer *intel_fb; 1731 struct drm_i915_gem_object *obj; 1732 int plane = intel_crtc->plane; 1733 unsigned long Start, Offset; 1734 u32 dspcntr; 1735 u32 reg; 1736 1737 switch (plane) { 1738 case 0: 1739 case 1: 1740 case 2: 1741 break; 1742 default: 1743 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 1744 return -EINVAL; 1745 } 1746 1747 intel_fb = to_intel_framebuffer(fb); 1748 obj = intel_fb->obj; 1749 1750 reg = DSPCNTR(plane); 1751 dspcntr = I915_READ(reg); 1752 /* Mask out pixel format bits in case we change it */ 1753 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 1754 switch (fb->bits_per_pixel) { 1755 case 8: 1756 dspcntr |= DISPPLANE_8BPP; 1757 break; 1758 case 16: 1759 if (fb->depth != 16) { 1760 DRM_ERROR("bpp 16, depth %d\n", fb->depth); 1761 return -EINVAL; 1762 } 1763 1764 dspcntr |= DISPPLANE_BGRX565; 1765 break; 1766 case 24: 1767 case 32: 1768 if (fb->depth == 24) 1769 dspcntr |= DISPPLANE_BGRX888; 1770 else if (fb->depth == 30) 1771 dspcntr |= DISPPLANE_BGRX101010; 1772 else { 1773 DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel, 1774 fb->depth); 1775 return -EINVAL; 1776 } 1777 break; 1778 default: 1779 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); 1780 return -EINVAL; 1781 } 1782 1783 if (obj->tiling_mode != I915_TILING_NONE) 1784 dspcntr |= DISPPLANE_TILED; 1785 else 1786 dspcntr &= ~DISPPLANE_TILED; 1787 1788 /* must disable */ 1789 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1790 1791 I915_WRITE(reg, dspcntr); 1792 1793 Start = obj->gtt_offset; 1794 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 1795 1796 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 1797 Start, Offset, x, y, fb->pitches[0]); 1798 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 1799 I915_WRITE(DSPSURF(plane), Start); 1800 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 1801 I915_WRITE(DSPADDR(plane), Offset); 1802 POSTING_READ(reg); 1803 1804 return 0; 1805 } 1806 1807 /* Assume fb object is pinned & idle & fenced and just update base pointers */ 1808 static int 1809 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1810 int x, int y, enum mode_set_atomic state) 1811 { 1812 struct drm_device *dev = crtc->dev; 1813 struct drm_i915_private *dev_priv = dev->dev_private; 1814 1815 if (dev_priv->display.disable_fbc) 1816 dev_priv->display.disable_fbc(dev); 1817 intel_increase_pllclock(crtc); 1818 1819 return dev_priv->display.update_plane(crtc, fb, x, y); 1820 } 1821 1822 static int 1823 intel_finish_fb(struct drm_framebuffer *old_fb) 1824 { 1825 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; 1826 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1827 bool was_interruptible = dev_priv->mm.interruptible; 1828 int ret; 1829 1830 wait_event(dev_priv->pending_flip_queue, 1831 atomic_read(&dev_priv->mm.wedged) || 1832 atomic_read(&obj->pending_flip) == 0); 1833 1834 /* Big Hammer, we also need to ensure that any pending 1835 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 1836 * current scanout is retired before unpinning the old 1837 * framebuffer. 1838 * 1839 * This should only fail upon a hung GPU, in which case we 1840 * can safely continue. 1841 */ 1842 dev_priv->mm.interruptible = false; 1843 ret = i915_gem_object_finish_gpu(obj); 1844 dev_priv->mm.interruptible = was_interruptible; 1845 1846 return ret; 1847 } 1848 1849 static int 1850 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 1851 struct drm_framebuffer *old_fb) 1852 { 1853 struct drm_device *dev = crtc->dev; 1854 #if 0 1855 struct drm_i915_master_private *master_priv; 1856 #else 1857 drm_i915_private_t *dev_priv = dev->dev_private; 1858 #endif 1859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1860 int ret; 1861 1862 /* no fb bound */ 1863 if (!crtc->fb) { 1864 DRM_ERROR("No FB bound\n"); 1865 return 0; 1866 } 1867 1868 switch (intel_crtc->plane) { 1869 case 0: 1870 case 1: 1871 break; 1872 case 2: 1873 if (IS_IVYBRIDGE(dev)) 1874 break; 1875 /* fall through otherwise */ 1876 default: 1877 DRM_ERROR("no plane for crtc\n"); 1878 return -EINVAL; 1879 } 1880 1881 DRM_LOCK(dev); 1882 ret = intel_pin_and_fence_fb_obj(dev, 1883 to_intel_framebuffer(crtc->fb)->obj, 1884 NULL); 1885 if (ret != 0) { 1886 DRM_UNLOCK(dev); 1887 DRM_ERROR("pin & fence failed\n"); 1888 return ret; 1889 } 1890 1891 if (old_fb) 1892 intel_finish_fb(old_fb); 1893 1894 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, 1895 LEAVE_ATOMIC_MODE_SET); 1896 if (ret) { 1897 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 1898 DRM_UNLOCK(dev); 1899 DRM_ERROR("failed to update base address\n"); 1900 return ret; 1901 } 1902 1903 if (old_fb) { 1904 intel_wait_for_vblank(dev, intel_crtc->pipe); 1905 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 1906 } 1907 1908 DRM_UNLOCK(dev); 1909 1910 #if 0 1911 if (!dev->primary->master) 1912 return 0; 1913 1914 master_priv = dev->primary->master->driver_priv; 1915 if (!master_priv->sarea_priv) 1916 return 0; 1917 1918 if (intel_crtc->pipe) { 1919 master_priv->sarea_priv->pipeB_x = x; 1920 master_priv->sarea_priv->pipeB_y = y; 1921 } else { 1922 master_priv->sarea_priv->pipeA_x = x; 1923 master_priv->sarea_priv->pipeA_y = y; 1924 } 1925 #else 1926 1927 if (!dev_priv->sarea_priv) 1928 return 0; 1929 1930 if (intel_crtc->pipe) { 1931 dev_priv->sarea_priv->planeB_x = x; 1932 dev_priv->sarea_priv->planeB_y = y; 1933 } else { 1934 dev_priv->sarea_priv->planeA_x = x; 1935 dev_priv->sarea_priv->planeA_y = y; 1936 } 1937 #endif 1938 1939 return 0; 1940 } 1941 1942 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) 1943 { 1944 struct drm_device *dev = crtc->dev; 1945 struct drm_i915_private *dev_priv = dev->dev_private; 1946 u32 dpa_ctl; 1947 1948 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); 1949 dpa_ctl = I915_READ(DP_A); 1950 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1951 1952 if (clock < 200000) { 1953 u32 temp; 1954 dpa_ctl |= DP_PLL_FREQ_160MHZ; 1955 /* workaround for 160Mhz: 1956 1) program 0x4600c bits 15:0 = 0x8124 1957 2) program 0x46010 bit 0 = 1 1958 3) program 0x46034 bit 24 = 1 1959 4) program 0x64000 bit 14 = 1 1960 */ 1961 temp = I915_READ(0x4600c); 1962 temp &= 0xffff0000; 1963 I915_WRITE(0x4600c, temp | 0x8124); 1964 1965 temp = I915_READ(0x46010); 1966 I915_WRITE(0x46010, temp | 1); 1967 1968 temp = I915_READ(0x46034); 1969 I915_WRITE(0x46034, temp | (1 << 24)); 1970 } else { 1971 dpa_ctl |= DP_PLL_FREQ_270MHZ; 1972 } 1973 I915_WRITE(DP_A, dpa_ctl); 1974 1975 POSTING_READ(DP_A); 1976 DELAY(500); 1977 } 1978 1979 static void intel_fdi_normal_train(struct drm_crtc *crtc) 1980 { 1981 struct drm_device *dev = crtc->dev; 1982 struct drm_i915_private *dev_priv = dev->dev_private; 1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1984 int pipe = intel_crtc->pipe; 1985 u32 reg, temp; 1986 1987 /* enable normal train */ 1988 reg = FDI_TX_CTL(pipe); 1989 temp = I915_READ(reg); 1990 if (IS_IVYBRIDGE(dev)) { 1991 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 1992 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 1993 } else { 1994 temp &= ~FDI_LINK_TRAIN_NONE; 1995 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 1996 } 1997 I915_WRITE(reg, temp); 1998 1999 reg = FDI_RX_CTL(pipe); 2000 temp = I915_READ(reg); 2001 if (HAS_PCH_CPT(dev)) { 2002 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2003 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 2004 } else { 2005 temp &= ~FDI_LINK_TRAIN_NONE; 2006 temp |= FDI_LINK_TRAIN_NONE; 2007 } 2008 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 2009 2010 /* wait one idle pattern time */ 2011 POSTING_READ(reg); 2012 DELAY(1000); 2013 2014 /* IVB wants error correction enabled */ 2015 if (IS_IVYBRIDGE(dev)) 2016 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | 2017 FDI_FE_ERRC_ENABLE); 2018 } 2019 2020 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) 2021 { 2022 struct drm_i915_private *dev_priv = dev->dev_private; 2023 u32 flags = I915_READ(SOUTH_CHICKEN1); 2024 2025 flags |= FDI_PHASE_SYNC_OVR(pipe); 2026 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ 2027 flags |= FDI_PHASE_SYNC_EN(pipe); 2028 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ 2029 POSTING_READ(SOUTH_CHICKEN1); 2030 } 2031 2032 /* The FDI link training functions for ILK/Ibexpeak. */ 2033 static void ironlake_fdi_link_train(struct drm_crtc *crtc) 2034 { 2035 struct drm_device *dev = crtc->dev; 2036 struct drm_i915_private *dev_priv = dev->dev_private; 2037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2038 int pipe = intel_crtc->pipe; 2039 int plane = intel_crtc->plane; 2040 u32 reg, temp, tries; 2041 2042 /* FDI needs bits from pipe & plane first */ 2043 assert_pipe_enabled(dev_priv, pipe); 2044 assert_plane_enabled(dev_priv, plane); 2045 2046 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2047 for train result */ 2048 reg = FDI_RX_IMR(pipe); 2049 temp = I915_READ(reg); 2050 temp &= ~FDI_RX_SYMBOL_LOCK; 2051 temp &= ~FDI_RX_BIT_LOCK; 2052 I915_WRITE(reg, temp); 2053 I915_READ(reg); 2054 DELAY(150); 2055 2056 /* enable CPU FDI TX and PCH FDI RX */ 2057 reg = FDI_TX_CTL(pipe); 2058 temp = I915_READ(reg); 2059 temp &= ~(7 << 19); 2060 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2061 temp &= ~FDI_LINK_TRAIN_NONE; 2062 temp |= FDI_LINK_TRAIN_PATTERN_1; 2063 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2064 2065 reg = FDI_RX_CTL(pipe); 2066 temp = I915_READ(reg); 2067 temp &= ~FDI_LINK_TRAIN_NONE; 2068 temp |= FDI_LINK_TRAIN_PATTERN_1; 2069 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2070 2071 POSTING_READ(reg); 2072 DELAY(150); 2073 2074 /* Ironlake workaround, enable clock pointer after FDI enable*/ 2075 if (HAS_PCH_IBX(dev)) { 2076 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2077 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | 2078 FDI_RX_PHASE_SYNC_POINTER_EN); 2079 } 2080 2081 reg = FDI_RX_IIR(pipe); 2082 for (tries = 0; tries < 5; tries++) { 2083 temp = I915_READ(reg); 2084 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2085 2086 if ((temp & FDI_RX_BIT_LOCK)) { 2087 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2088 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2089 break; 2090 } 2091 } 2092 if (tries == 5) 2093 DRM_ERROR("FDI train 1 fail!\n"); 2094 2095 /* Train 2 */ 2096 reg = FDI_TX_CTL(pipe); 2097 temp = I915_READ(reg); 2098 temp &= ~FDI_LINK_TRAIN_NONE; 2099 temp |= FDI_LINK_TRAIN_PATTERN_2; 2100 I915_WRITE(reg, temp); 2101 2102 reg = FDI_RX_CTL(pipe); 2103 temp = I915_READ(reg); 2104 temp &= ~FDI_LINK_TRAIN_NONE; 2105 temp |= FDI_LINK_TRAIN_PATTERN_2; 2106 I915_WRITE(reg, temp); 2107 2108 POSTING_READ(reg); 2109 DELAY(150); 2110 2111 reg = FDI_RX_IIR(pipe); 2112 for (tries = 0; tries < 5; tries++) { 2113 temp = I915_READ(reg); 2114 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2115 2116 if (temp & FDI_RX_SYMBOL_LOCK) { 2117 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2118 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2119 break; 2120 } 2121 } 2122 if (tries == 5) 2123 DRM_ERROR("FDI train 2 fail!\n"); 2124 2125 DRM_DEBUG_KMS("FDI train done\n"); 2126 2127 } 2128 2129 static const int snb_b_fdi_train_param[] = { 2130 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 2131 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 2132 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 2133 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 2134 }; 2135 2136 /* The FDI link training functions for SNB/Cougarpoint. */ 2137 static void gen6_fdi_link_train(struct drm_crtc *crtc) 2138 { 2139 struct drm_device *dev = crtc->dev; 2140 struct drm_i915_private *dev_priv = dev->dev_private; 2141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2142 int pipe = intel_crtc->pipe; 2143 u32 reg, temp, i; 2144 2145 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2146 for train result */ 2147 reg = FDI_RX_IMR(pipe); 2148 temp = I915_READ(reg); 2149 temp &= ~FDI_RX_SYMBOL_LOCK; 2150 temp &= ~FDI_RX_BIT_LOCK; 2151 I915_WRITE(reg, temp); 2152 2153 POSTING_READ(reg); 2154 DELAY(150); 2155 2156 /* enable CPU FDI TX and PCH FDI RX */ 2157 reg = FDI_TX_CTL(pipe); 2158 temp = I915_READ(reg); 2159 temp &= ~(7 << 19); 2160 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2161 temp &= ~FDI_LINK_TRAIN_NONE; 2162 temp |= FDI_LINK_TRAIN_PATTERN_1; 2163 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2164 /* SNB-B */ 2165 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2166 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2167 2168 reg = FDI_RX_CTL(pipe); 2169 temp = I915_READ(reg); 2170 if (HAS_PCH_CPT(dev)) { 2171 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2172 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2173 } else { 2174 temp &= ~FDI_LINK_TRAIN_NONE; 2175 temp |= FDI_LINK_TRAIN_PATTERN_1; 2176 } 2177 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2178 2179 POSTING_READ(reg); 2180 DELAY(150); 2181 2182 if (HAS_PCH_CPT(dev)) 2183 cpt_phase_pointer_enable(dev, pipe); 2184 2185 for (i = 0; i < 4; i++) { 2186 reg = FDI_TX_CTL(pipe); 2187 temp = I915_READ(reg); 2188 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2189 temp |= snb_b_fdi_train_param[i]; 2190 I915_WRITE(reg, temp); 2191 2192 POSTING_READ(reg); 2193 DELAY(500); 2194 2195 reg = FDI_RX_IIR(pipe); 2196 temp = I915_READ(reg); 2197 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2198 2199 if (temp & FDI_RX_BIT_LOCK) { 2200 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2201 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2202 break; 2203 } 2204 } 2205 if (i == 4) 2206 DRM_ERROR("FDI train 1 fail!\n"); 2207 2208 /* Train 2 */ 2209 reg = FDI_TX_CTL(pipe); 2210 temp = I915_READ(reg); 2211 temp &= ~FDI_LINK_TRAIN_NONE; 2212 temp |= FDI_LINK_TRAIN_PATTERN_2; 2213 if (IS_GEN6(dev)) { 2214 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2215 /* SNB-B */ 2216 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2217 } 2218 I915_WRITE(reg, temp); 2219 2220 reg = FDI_RX_CTL(pipe); 2221 temp = I915_READ(reg); 2222 if (HAS_PCH_CPT(dev)) { 2223 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2224 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2225 } else { 2226 temp &= ~FDI_LINK_TRAIN_NONE; 2227 temp |= FDI_LINK_TRAIN_PATTERN_2; 2228 } 2229 I915_WRITE(reg, temp); 2230 2231 POSTING_READ(reg); 2232 DELAY(150); 2233 2234 for (i = 0; i < 4; i++) { 2235 reg = FDI_TX_CTL(pipe); 2236 temp = I915_READ(reg); 2237 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2238 temp |= snb_b_fdi_train_param[i]; 2239 I915_WRITE(reg, temp); 2240 2241 POSTING_READ(reg); 2242 DELAY(500); 2243 2244 reg = FDI_RX_IIR(pipe); 2245 temp = I915_READ(reg); 2246 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2247 2248 if (temp & FDI_RX_SYMBOL_LOCK) { 2249 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2250 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2251 break; 2252 } 2253 } 2254 if (i == 4) 2255 DRM_ERROR("FDI train 2 fail!\n"); 2256 2257 DRM_DEBUG_KMS("FDI train done.\n"); 2258 } 2259 2260 /* Manual link training for Ivy Bridge A0 parts */ 2261 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 2262 { 2263 struct drm_device *dev = crtc->dev; 2264 struct drm_i915_private *dev_priv = dev->dev_private; 2265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2266 int pipe = intel_crtc->pipe; 2267 u32 reg, temp, i; 2268 2269 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2270 for train result */ 2271 reg = FDI_RX_IMR(pipe); 2272 temp = I915_READ(reg); 2273 temp &= ~FDI_RX_SYMBOL_LOCK; 2274 temp &= ~FDI_RX_BIT_LOCK; 2275 I915_WRITE(reg, temp); 2276 2277 POSTING_READ(reg); 2278 DELAY(150); 2279 2280 /* enable CPU FDI TX and PCH FDI RX */ 2281 reg = FDI_TX_CTL(pipe); 2282 temp = I915_READ(reg); 2283 temp &= ~(7 << 19); 2284 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2285 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 2286 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 2287 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2288 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2289 temp |= FDI_COMPOSITE_SYNC; 2290 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2291 2292 reg = FDI_RX_CTL(pipe); 2293 temp = I915_READ(reg); 2294 temp &= ~FDI_LINK_TRAIN_AUTO; 2295 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2296 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2297 temp |= FDI_COMPOSITE_SYNC; 2298 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2299 2300 POSTING_READ(reg); 2301 DELAY(150); 2302 2303 for (i = 0; i < 4; i++) { 2304 reg = FDI_TX_CTL(pipe); 2305 temp = I915_READ(reg); 2306 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2307 temp |= snb_b_fdi_train_param[i]; 2308 I915_WRITE(reg, temp); 2309 2310 POSTING_READ(reg); 2311 DELAY(500); 2312 2313 reg = FDI_RX_IIR(pipe); 2314 temp = I915_READ(reg); 2315 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2316 2317 if (temp & FDI_RX_BIT_LOCK || 2318 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { 2319 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2320 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2321 break; 2322 } 2323 } 2324 if (i == 4) 2325 DRM_ERROR("FDI train 1 fail!\n"); 2326 2327 /* Train 2 */ 2328 reg = FDI_TX_CTL(pipe); 2329 temp = I915_READ(reg); 2330 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 2331 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; 2332 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2333 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2334 I915_WRITE(reg, temp); 2335 2336 reg = FDI_RX_CTL(pipe); 2337 temp = I915_READ(reg); 2338 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2339 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2340 I915_WRITE(reg, temp); 2341 2342 POSTING_READ(reg); 2343 DELAY(150); 2344 2345 for (i = 0; i < 4; i++ ) { 2346 reg = FDI_TX_CTL(pipe); 2347 temp = I915_READ(reg); 2348 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2349 temp |= snb_b_fdi_train_param[i]; 2350 I915_WRITE(reg, temp); 2351 2352 POSTING_READ(reg); 2353 DELAY(500); 2354 2355 reg = FDI_RX_IIR(pipe); 2356 temp = I915_READ(reg); 2357 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2358 2359 if (temp & FDI_RX_SYMBOL_LOCK) { 2360 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2361 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2362 break; 2363 } 2364 } 2365 if (i == 4) 2366 DRM_ERROR("FDI train 2 fail!\n"); 2367 2368 DRM_DEBUG_KMS("FDI train done.\n"); 2369 } 2370 2371 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) 2372 { 2373 struct drm_device *dev = crtc->dev; 2374 struct drm_i915_private *dev_priv = dev->dev_private; 2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2376 int pipe = intel_crtc->pipe; 2377 u32 reg, temp; 2378 2379 /* Write the TU size bits so error detection works */ 2380 I915_WRITE(FDI_RX_TUSIZE1(pipe), 2381 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 2382 2383 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 2384 reg = FDI_RX_CTL(pipe); 2385 temp = I915_READ(reg); 2386 temp &= ~((0x7 << 19) | (0x7 << 16)); 2387 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2388 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2389 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 2390 2391 POSTING_READ(reg); 2392 DELAY(200); 2393 2394 /* Switch from Rawclk to PCDclk */ 2395 temp = I915_READ(reg); 2396 I915_WRITE(reg, temp | FDI_PCDCLK); 2397 2398 POSTING_READ(reg); 2399 DELAY(200); 2400 2401 /* Enable CPU FDI TX PLL, always on for Ironlake */ 2402 reg = FDI_TX_CTL(pipe); 2403 temp = I915_READ(reg); 2404 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 2405 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 2406 2407 POSTING_READ(reg); 2408 DELAY(100); 2409 } 2410 } 2411 2412 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) 2413 { 2414 struct drm_i915_private *dev_priv = dev->dev_private; 2415 u32 flags = I915_READ(SOUTH_CHICKEN1); 2416 2417 flags &= ~(FDI_PHASE_SYNC_EN(pipe)); 2418 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ 2419 flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); 2420 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ 2421 POSTING_READ(SOUTH_CHICKEN1); 2422 } 2423 2424 static void ironlake_fdi_disable(struct drm_crtc *crtc) 2425 { 2426 struct drm_device *dev = crtc->dev; 2427 struct drm_i915_private *dev_priv = dev->dev_private; 2428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2429 int pipe = intel_crtc->pipe; 2430 u32 reg, temp; 2431 2432 /* disable CPU FDI tx and PCH FDI rx */ 2433 reg = FDI_TX_CTL(pipe); 2434 temp = I915_READ(reg); 2435 I915_WRITE(reg, temp & ~FDI_TX_ENABLE); 2436 POSTING_READ(reg); 2437 2438 reg = FDI_RX_CTL(pipe); 2439 temp = I915_READ(reg); 2440 temp &= ~(0x7 << 16); 2441 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2442 I915_WRITE(reg, temp & ~FDI_RX_ENABLE); 2443 2444 POSTING_READ(reg); 2445 DELAY(100); 2446 2447 /* Ironlake workaround, disable clock pointer after downing FDI */ 2448 if (HAS_PCH_IBX(dev)) { 2449 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2450 I915_WRITE(FDI_RX_CHICKEN(pipe), 2451 I915_READ(FDI_RX_CHICKEN(pipe) & 2452 ~FDI_RX_PHASE_SYNC_POINTER_EN)); 2453 } else if (HAS_PCH_CPT(dev)) { 2454 cpt_phase_pointer_disable(dev, pipe); 2455 } 2456 2457 /* still set train pattern 1 */ 2458 reg = FDI_TX_CTL(pipe); 2459 temp = I915_READ(reg); 2460 temp &= ~FDI_LINK_TRAIN_NONE; 2461 temp |= FDI_LINK_TRAIN_PATTERN_1; 2462 I915_WRITE(reg, temp); 2463 2464 reg = FDI_RX_CTL(pipe); 2465 temp = I915_READ(reg); 2466 if (HAS_PCH_CPT(dev)) { 2467 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2468 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2469 } else { 2470 temp &= ~FDI_LINK_TRAIN_NONE; 2471 temp |= FDI_LINK_TRAIN_PATTERN_1; 2472 } 2473 /* BPC in FDI rx is consistent with that in PIPECONF */ 2474 temp &= ~(0x07 << 16); 2475 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; 2476 I915_WRITE(reg, temp); 2477 2478 POSTING_READ(reg); 2479 DELAY(100); 2480 } 2481 2482 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) 2483 { 2484 struct drm_device *dev = crtc->dev; 2485 struct drm_i915_private *dev_priv = dev->dev_private; 2486 bool pending; 2487 2488 if (atomic_read(&dev_priv->mm.wedged)) 2489 return false; 2490 2491 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 2492 pending = to_intel_crtc(crtc)->unpin_work != NULL; 2493 lockmgr(&dev->event_lock, LK_RELEASE); 2494 2495 return pending; 2496 } 2497 2498 /* 2499 * When we disable a pipe, we need to clear any pending scanline wait events 2500 * to avoid hanging the ring, which we assume we are waiting on. 2501 */ 2502 static void intel_clear_scanline_wait(struct drm_device *dev) 2503 { 2504 struct drm_i915_private *dev_priv = dev->dev_private; 2505 struct intel_ring_buffer *ring; 2506 u32 tmp; 2507 2508 if (IS_GEN2(dev)) 2509 /* Can't break the hang on i8xx */ 2510 return; 2511 2512 ring = LP_RING(dev_priv); 2513 tmp = I915_READ_CTL(ring); 2514 if (tmp & RING_WAIT) 2515 I915_WRITE_CTL(ring, tmp); 2516 } 2517 2518 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 2519 { 2520 struct drm_device *dev = crtc->dev; 2521 struct drm_i915_private *dev_priv = dev->dev_private; 2522 2523 if (crtc->fb == NULL) 2524 return; 2525 2526 wait_event(dev_priv->pending_flip_queue, 2527 !intel_crtc_has_pending_flip(crtc)); 2528 2529 DRM_LOCK(dev); 2530 intel_finish_fb(crtc->fb); 2531 DRM_UNLOCK(dev); 2532 } 2533 2534 static bool intel_crtc_driving_pch(struct drm_crtc *crtc) 2535 { 2536 struct drm_device *dev = crtc->dev; 2537 struct drm_mode_config *mode_config = &dev->mode_config; 2538 struct intel_encoder *encoder; 2539 2540 /* 2541 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that 2542 * must be driven by its own crtc; no sharing is possible. 2543 */ 2544 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 2545 if (encoder->base.crtc != crtc) 2546 continue; 2547 2548 switch (encoder->type) { 2549 case INTEL_OUTPUT_EDP: 2550 if (!intel_encoder_is_pch_edp(&encoder->base)) 2551 return false; 2552 continue; 2553 } 2554 } 2555 2556 return true; 2557 } 2558 2559 /* 2560 * Enable PCH resources required for PCH ports: 2561 * - PCH PLLs 2562 * - FDI training & RX/TX 2563 * - update transcoder timings 2564 * - DP transcoding bits 2565 * - transcoder 2566 */ 2567 static void ironlake_pch_enable(struct drm_crtc *crtc) 2568 { 2569 struct drm_device *dev = crtc->dev; 2570 struct drm_i915_private *dev_priv = dev->dev_private; 2571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2572 int pipe = intel_crtc->pipe; 2573 u32 reg, temp, transc_sel; 2574 2575 /* For PCH output, training FDI link */ 2576 dev_priv->display.fdi_link_train(crtc); 2577 2578 intel_enable_pch_pll(dev_priv, pipe); 2579 2580 if (HAS_PCH_CPT(dev)) { 2581 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : 2582 TRANSC_DPLLB_SEL; 2583 2584 /* Be sure PCH DPLL SEL is set */ 2585 temp = I915_READ(PCH_DPLL_SEL); 2586 if (pipe == 0) { 2587 temp &= ~(TRANSA_DPLLB_SEL); 2588 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); 2589 } else if (pipe == 1) { 2590 temp &= ~(TRANSB_DPLLB_SEL); 2591 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2592 } else if (pipe == 2) { 2593 temp &= ~(TRANSC_DPLLB_SEL); 2594 temp |= (TRANSC_DPLL_ENABLE | transc_sel); 2595 } 2596 I915_WRITE(PCH_DPLL_SEL, temp); 2597 } 2598 2599 /* set transcoder timing, panel must allow it */ 2600 assert_panel_unlocked(dev_priv, pipe); 2601 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 2602 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); 2603 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); 2604 2605 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); 2606 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); 2607 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); 2608 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); 2609 2610 intel_fdi_normal_train(crtc); 2611 2612 /* For PCH DP, enable TRANS_DP_CTL */ 2613 if (HAS_PCH_CPT(dev) && 2614 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 2615 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 2616 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; 2617 reg = TRANS_DP_CTL(pipe); 2618 temp = I915_READ(reg); 2619 temp &= ~(TRANS_DP_PORT_SEL_MASK | 2620 TRANS_DP_SYNC_MASK | 2621 TRANS_DP_BPC_MASK); 2622 temp |= (TRANS_DP_OUTPUT_ENABLE | 2623 TRANS_DP_ENH_FRAMING); 2624 temp |= bpc << 9; /* same format but at 11:9 */ 2625 2626 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2627 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2628 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 2629 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 2630 2631 switch (intel_trans_dp_port_sel(crtc)) { 2632 case PCH_DP_B: 2633 temp |= TRANS_DP_PORT_SEL_B; 2634 break; 2635 case PCH_DP_C: 2636 temp |= TRANS_DP_PORT_SEL_C; 2637 break; 2638 case PCH_DP_D: 2639 temp |= TRANS_DP_PORT_SEL_D; 2640 break; 2641 default: 2642 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); 2643 temp |= TRANS_DP_PORT_SEL_B; 2644 break; 2645 } 2646 2647 I915_WRITE(reg, temp); 2648 } 2649 2650 intel_enable_transcoder(dev_priv, pipe); 2651 } 2652 2653 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) 2654 { 2655 struct drm_i915_private *dev_priv = dev->dev_private; 2656 int dslreg = PIPEDSL(pipe); 2657 u32 temp; 2658 2659 temp = I915_READ(dslreg); 2660 udelay(500); 2661 if (wait_for(I915_READ(dslreg) != temp, 5)) { 2662 if (wait_for(I915_READ(dslreg) != temp, 5)) 2663 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); 2664 } 2665 } 2666 2667 static void ironlake_crtc_enable(struct drm_crtc *crtc) 2668 { 2669 struct drm_device *dev = crtc->dev; 2670 struct drm_i915_private *dev_priv = dev->dev_private; 2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2672 int pipe = intel_crtc->pipe; 2673 int plane = intel_crtc->plane; 2674 u32 temp; 2675 bool is_pch_port; 2676 2677 if (intel_crtc->active) 2678 return; 2679 2680 intel_crtc->active = true; 2681 intel_update_watermarks(dev); 2682 2683 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 2684 temp = I915_READ(PCH_LVDS); 2685 if ((temp & LVDS_PORT_EN) == 0) 2686 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); 2687 } 2688 2689 is_pch_port = intel_crtc_driving_pch(crtc); 2690 2691 if (is_pch_port) 2692 ironlake_fdi_pll_enable(crtc); 2693 else 2694 ironlake_fdi_disable(crtc); 2695 2696 /* Enable panel fitting for LVDS */ 2697 if (dev_priv->pch_pf_size && 2698 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { 2699 /* Force use of hard-coded filter coefficients 2700 * as some pre-programmed values are broken, 2701 * e.g. x201. 2702 */ 2703 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 2704 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); 2705 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); 2706 } 2707 2708 intel_enable_pipe(dev_priv, pipe, is_pch_port); 2709 intel_enable_plane(dev_priv, plane, pipe); 2710 2711 if (is_pch_port) 2712 ironlake_pch_enable(crtc); 2713 2714 intel_crtc_load_lut(crtc); 2715 2716 DRM_LOCK(dev); 2717 intel_update_fbc(dev); 2718 DRM_UNLOCK(dev); 2719 2720 intel_crtc_update_cursor(crtc, true); 2721 } 2722 2723 static void ironlake_crtc_disable(struct drm_crtc *crtc) 2724 { 2725 struct drm_device *dev = crtc->dev; 2726 struct drm_i915_private *dev_priv = dev->dev_private; 2727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2728 int pipe = intel_crtc->pipe; 2729 int plane = intel_crtc->plane; 2730 u32 reg, temp; 2731 2732 if (!intel_crtc->active) 2733 return; 2734 2735 intel_crtc_wait_for_pending_flips(crtc); 2736 drm_vblank_off(dev, pipe); 2737 intel_crtc_update_cursor(crtc, false); 2738 2739 intel_disable_plane(dev_priv, plane, pipe); 2740 2741 if (dev_priv->cfb_plane == plane) 2742 intel_disable_fbc(dev); 2743 2744 intel_disable_pipe(dev_priv, pipe); 2745 2746 /* Disable PF */ 2747 I915_WRITE(PF_CTL(pipe), 0); 2748 I915_WRITE(PF_WIN_SZ(pipe), 0); 2749 2750 ironlake_fdi_disable(crtc); 2751 2752 /* This is a horrible layering violation; we should be doing this in 2753 * the connector/encoder ->prepare instead, but we don't always have 2754 * enough information there about the config to know whether it will 2755 * actually be necessary or just cause undesired flicker. 2756 */ 2757 intel_disable_pch_ports(dev_priv, pipe); 2758 2759 intel_disable_transcoder(dev_priv, pipe); 2760 2761 if (HAS_PCH_CPT(dev)) { 2762 /* disable TRANS_DP_CTL */ 2763 reg = TRANS_DP_CTL(pipe); 2764 temp = I915_READ(reg); 2765 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); 2766 temp |= TRANS_DP_PORT_SEL_NONE; 2767 I915_WRITE(reg, temp); 2768 2769 /* disable DPLL_SEL */ 2770 temp = I915_READ(PCH_DPLL_SEL); 2771 switch (pipe) { 2772 case 0: 2773 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 2774 break; 2775 case 1: 2776 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 2777 break; 2778 case 2: 2779 /* C shares PLL A or B */ 2780 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); 2781 break; 2782 default: 2783 KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */ 2784 } 2785 I915_WRITE(PCH_DPLL_SEL, temp); 2786 } 2787 2788 /* disable PCH DPLL */ 2789 if (!intel_crtc->no_pll) 2790 intel_disable_pch_pll(dev_priv, pipe); 2791 2792 /* Switch from PCDclk to Rawclk */ 2793 reg = FDI_RX_CTL(pipe); 2794 temp = I915_READ(reg); 2795 I915_WRITE(reg, temp & ~FDI_PCDCLK); 2796 2797 /* Disable CPU FDI TX PLL */ 2798 reg = FDI_TX_CTL(pipe); 2799 temp = I915_READ(reg); 2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); 2801 2802 POSTING_READ(reg); 2803 DELAY(100); 2804 2805 reg = FDI_RX_CTL(pipe); 2806 temp = I915_READ(reg); 2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); 2808 2809 /* Wait for the clocks to turn off. */ 2810 POSTING_READ(reg); 2811 DELAY(100); 2812 2813 intel_crtc->active = false; 2814 intel_update_watermarks(dev); 2815 2816 DRM_LOCK(dev); 2817 intel_update_fbc(dev); 2818 intel_clear_scanline_wait(dev); 2819 DRM_UNLOCK(dev); 2820 } 2821 2822 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 2823 { 2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2825 int pipe = intel_crtc->pipe; 2826 int plane = intel_crtc->plane; 2827 2828 /* XXX: When our outputs are all unaware of DPMS modes other than off 2829 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 2830 */ 2831 switch (mode) { 2832 case DRM_MODE_DPMS_ON: 2833 case DRM_MODE_DPMS_STANDBY: 2834 case DRM_MODE_DPMS_SUSPEND: 2835 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); 2836 ironlake_crtc_enable(crtc); 2837 break; 2838 2839 case DRM_MODE_DPMS_OFF: 2840 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); 2841 ironlake_crtc_disable(crtc); 2842 break; 2843 } 2844 } 2845 2846 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) 2847 { 2848 if (!enable && intel_crtc->overlay) { 2849 struct drm_device *dev = intel_crtc->base.dev; 2850 struct drm_i915_private *dev_priv = dev->dev_private; 2851 2852 DRM_LOCK(dev); 2853 dev_priv->mm.interruptible = false; 2854 (void) intel_overlay_switch_off(intel_crtc->overlay); 2855 dev_priv->mm.interruptible = true; 2856 DRM_UNLOCK(dev); 2857 } 2858 2859 /* Let userspace switch the overlay on again. In most cases userspace 2860 * has to recompute where to put it anyway. 2861 */ 2862 } 2863 2864 static void i9xx_crtc_enable(struct drm_crtc *crtc) 2865 { 2866 struct drm_device *dev = crtc->dev; 2867 struct drm_i915_private *dev_priv = dev->dev_private; 2868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2869 int pipe = intel_crtc->pipe; 2870 int plane = intel_crtc->plane; 2871 2872 if (intel_crtc->active) 2873 return; 2874 2875 intel_crtc->active = true; 2876 intel_update_watermarks(dev); 2877 2878 intel_enable_pll(dev_priv, pipe); 2879 intel_enable_pipe(dev_priv, pipe, false); 2880 intel_enable_plane(dev_priv, plane, pipe); 2881 2882 intel_crtc_load_lut(crtc); 2883 intel_update_fbc(dev); 2884 2885 /* Give the overlay scaler a chance to enable if it's on this pipe */ 2886 intel_crtc_dpms_overlay(intel_crtc, true); 2887 intel_crtc_update_cursor(crtc, true); 2888 } 2889 2890 static void i9xx_crtc_disable(struct drm_crtc *crtc) 2891 { 2892 struct drm_device *dev = crtc->dev; 2893 struct drm_i915_private *dev_priv = dev->dev_private; 2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2895 int pipe = intel_crtc->pipe; 2896 int plane = intel_crtc->plane; 2897 2898 if (!intel_crtc->active) 2899 return; 2900 2901 /* Give the overlay scaler a chance to disable if it's on this pipe */ 2902 intel_crtc_wait_for_pending_flips(crtc); 2903 drm_vblank_off(dev, pipe); 2904 intel_crtc_dpms_overlay(intel_crtc, false); 2905 intel_crtc_update_cursor(crtc, false); 2906 2907 if (dev_priv->cfb_plane == plane) 2908 intel_disable_fbc(dev); 2909 2910 intel_disable_plane(dev_priv, plane, pipe); 2911 intel_disable_pipe(dev_priv, pipe); 2912 intel_disable_pll(dev_priv, pipe); 2913 2914 intel_crtc->active = false; 2915 intel_update_fbc(dev); 2916 intel_update_watermarks(dev); 2917 intel_clear_scanline_wait(dev); 2918 } 2919 2920 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 2921 { 2922 /* XXX: When our outputs are all unaware of DPMS modes other than off 2923 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 2924 */ 2925 switch (mode) { 2926 case DRM_MODE_DPMS_ON: 2927 case DRM_MODE_DPMS_STANDBY: 2928 case DRM_MODE_DPMS_SUSPEND: 2929 i9xx_crtc_enable(crtc); 2930 break; 2931 case DRM_MODE_DPMS_OFF: 2932 i9xx_crtc_disable(crtc); 2933 break; 2934 } 2935 } 2936 2937 /** 2938 * Sets the power management mode of the pipe and plane. 2939 */ 2940 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 2941 { 2942 struct drm_device *dev = crtc->dev; 2943 struct drm_i915_private *dev_priv = dev->dev_private; 2944 #if 0 2945 struct drm_i915_master_private *master_priv; 2946 #endif 2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2948 int pipe = intel_crtc->pipe; 2949 bool enabled; 2950 2951 if (intel_crtc->dpms_mode == mode) 2952 return; 2953 2954 intel_crtc->dpms_mode = mode; 2955 2956 dev_priv->display.dpms(crtc, mode); 2957 2958 #if 0 2959 if (!dev->primary->master) 2960 return; 2961 2962 master_priv = dev->primary->master->driver_priv; 2963 if (!master_priv->sarea_priv) 2964 return; 2965 #else 2966 if (!dev_priv->sarea_priv) 2967 return; 2968 #endif 2969 2970 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; 2971 2972 switch (pipe) { 2973 case 0: 2974 #if 0 2975 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; 2976 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; 2977 #else 2978 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0; 2979 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0; 2980 #endif 2981 break; 2982 case 1: 2983 #if 0 2984 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; 2985 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; 2986 #else 2987 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0; 2988 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0; 2989 #endif 2990 break; 2991 default: 2992 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); 2993 break; 2994 } 2995 } 2996 2997 static void intel_crtc_disable(struct drm_crtc *crtc) 2998 { 2999 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 3000 struct drm_device *dev = crtc->dev; 3001 3002 /* Flush any pending WAITs before we disable the pipe. Note that 3003 * we need to drop the struct_mutex in order to acquire it again 3004 * during the lowlevel dpms routines around a couple of the 3005 * operations. It does not look trivial nor desirable to move 3006 * that locking higher. So instead we leave a window for the 3007 * submission of further commands on the fb before we can actually 3008 * disable it. This race with userspace exists anyway, and we can 3009 * only rely on the pipe being disabled by userspace after it 3010 * receives the hotplug notification and has flushed any pending 3011 * batches. 3012 */ 3013 if (crtc->fb) { 3014 DRM_LOCK(dev); 3015 intel_finish_fb(crtc->fb); 3016 DRM_UNLOCK(dev); 3017 } 3018 3019 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 3020 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); 3021 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); 3022 3023 if (crtc->fb) { 3024 DRM_LOCK(dev); 3025 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 3026 DRM_UNLOCK(dev); 3027 } 3028 } 3029 3030 /* Prepare for a mode set. 3031 * 3032 * Note we could be a lot smarter here. We need to figure out which outputs 3033 * will be enabled, which disabled (in short, how the config will changes) 3034 * and perform the minimum necessary steps to accomplish that, e.g. updating 3035 * watermarks, FBC configuration, making sure PLLs are programmed correctly, 3036 * panel fitting is in the proper state, etc. 3037 */ 3038 static void i9xx_crtc_prepare(struct drm_crtc *crtc) 3039 { 3040 i9xx_crtc_disable(crtc); 3041 } 3042 3043 static void i9xx_crtc_commit(struct drm_crtc *crtc) 3044 { 3045 i9xx_crtc_enable(crtc); 3046 } 3047 3048 static void ironlake_crtc_prepare(struct drm_crtc *crtc) 3049 { 3050 ironlake_crtc_disable(crtc); 3051 } 3052 3053 static void ironlake_crtc_commit(struct drm_crtc *crtc) 3054 { 3055 ironlake_crtc_enable(crtc); 3056 } 3057 3058 void intel_encoder_prepare(struct drm_encoder *encoder) 3059 { 3060 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3061 /* lvds has its own version of prepare see intel_lvds_prepare */ 3062 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 3063 } 3064 3065 void intel_encoder_commit(struct drm_encoder *encoder) 3066 { 3067 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 3068 struct drm_device *dev = encoder->dev; 3069 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3070 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); 3071 3072 /* lvds has its own version of commit see intel_lvds_commit */ 3073 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 3074 3075 if (HAS_PCH_CPT(dev)) 3076 intel_cpt_verify_modeset(dev, intel_crtc->pipe); 3077 } 3078 3079 void intel_encoder_destroy(struct drm_encoder *encoder) 3080 { 3081 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3082 3083 drm_encoder_cleanup(encoder); 3084 drm_free(intel_encoder, DRM_MEM_KMS); 3085 } 3086 3087 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 3088 const struct drm_display_mode *mode, 3089 struct drm_display_mode *adjusted_mode) 3090 { 3091 struct drm_device *dev = crtc->dev; 3092 3093 if (HAS_PCH_SPLIT(dev)) { 3094 /* FDI link clock is fixed at 2.7G */ 3095 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) 3096 return false; 3097 } 3098 3099 /* All interlaced capable intel hw wants timings in frames. Note though 3100 * that intel_lvds_mode_fixup does some funny tricks with the crtc 3101 * timings, so we need to be careful not to clobber these.*/ 3102 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) 3103 drm_mode_set_crtcinfo(adjusted_mode, 0); 3104 3105 return true; 3106 } 3107 3108 static int valleyview_get_display_clock_speed(struct drm_device *dev) 3109 { 3110 return 400000; /* FIXME */ 3111 } 3112 3113 static int i945_get_display_clock_speed(struct drm_device *dev) 3114 { 3115 return 400000; 3116 } 3117 3118 static int i915_get_display_clock_speed(struct drm_device *dev) 3119 { 3120 return 333000; 3121 } 3122 3123 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) 3124 { 3125 return 200000; 3126 } 3127 3128 static int i915gm_get_display_clock_speed(struct drm_device *dev) 3129 { 3130 u16 gcfgc = 0; 3131 3132 gcfgc = pci_read_config(dev->dev, GCFGC, 2); 3133 3134 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) 3135 return 133000; 3136 else { 3137 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 3138 case GC_DISPLAY_CLOCK_333_MHZ: 3139 return 333000; 3140 default: 3141 case GC_DISPLAY_CLOCK_190_200_MHZ: 3142 return 190000; 3143 } 3144 } 3145 } 3146 3147 static int i865_get_display_clock_speed(struct drm_device *dev) 3148 { 3149 return 266000; 3150 } 3151 3152 static int i855_get_display_clock_speed(struct drm_device *dev) 3153 { 3154 u16 hpllcc = 0; 3155 /* Assume that the hardware is in the high speed state. This 3156 * should be the default. 3157 */ 3158 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 3159 case GC_CLOCK_133_200: 3160 case GC_CLOCK_100_200: 3161 return 200000; 3162 case GC_CLOCK_166_250: 3163 return 250000; 3164 case GC_CLOCK_100_133: 3165 return 133000; 3166 } 3167 3168 /* Shouldn't happen */ 3169 return 0; 3170 } 3171 3172 static int i830_get_display_clock_speed(struct drm_device *dev) 3173 { 3174 return 133000; 3175 } 3176 3177 struct fdi_m_n { 3178 u32 tu; 3179 u32 gmch_m; 3180 u32 gmch_n; 3181 u32 link_m; 3182 u32 link_n; 3183 }; 3184 3185 static void 3186 fdi_reduce_ratio(u32 *num, u32 *den) 3187 { 3188 while (*num > 0xffffff || *den > 0xffffff) { 3189 *num >>= 1; 3190 *den >>= 1; 3191 } 3192 } 3193 3194 static void 3195 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, 3196 int link_clock, struct fdi_m_n *m_n) 3197 { 3198 m_n->tu = 64; /* default size */ 3199 3200 /* BUG_ON(pixel_clock > INT_MAX / 36); */ 3201 m_n->gmch_m = bits_per_pixel * pixel_clock; 3202 m_n->gmch_n = link_clock * nlanes * 8; 3203 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 3204 3205 m_n->link_m = pixel_clock; 3206 m_n->link_n = link_clock; 3207 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); 3208 } 3209 3210 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 3211 { 3212 if (i915_panel_use_ssc >= 0) 3213 return i915_panel_use_ssc != 0; 3214 return dev_priv->lvds_use_ssc 3215 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 3216 } 3217 3218 /** 3219 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send 3220 * @crtc: CRTC structure 3221 * @mode: requested mode 3222 * 3223 * A pipe may be connected to one or more outputs. Based on the depth of the 3224 * attached framebuffer, choose a good color depth to use on the pipe. 3225 * 3226 * If possible, match the pipe depth to the fb depth. In some cases, this 3227 * isn't ideal, because the connected output supports a lesser or restricted 3228 * set of depths. Resolve that here: 3229 * LVDS typically supports only 6bpc, so clamp down in that case 3230 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc 3231 * Displays may support a restricted set as well, check EDID and clamp as 3232 * appropriate. 3233 * DP may want to dither down to 6bpc to fit larger modes 3234 * 3235 * RETURNS: 3236 * Dithering requirement (i.e. false if display bpc and pipe bpc match, 3237 * true if they don't match). 3238 */ 3239 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, 3240 unsigned int *pipe_bpp, 3241 struct drm_display_mode *mode) 3242 { 3243 struct drm_device *dev = crtc->dev; 3244 struct drm_i915_private *dev_priv = dev->dev_private; 3245 struct drm_encoder *encoder; 3246 struct drm_connector *connector; 3247 unsigned int display_bpc = UINT_MAX, bpc; 3248 3249 /* Walk the encoders & connectors on this crtc, get min bpc */ 3250 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3251 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3252 3253 if (encoder->crtc != crtc) 3254 continue; 3255 3256 if (intel_encoder->type == INTEL_OUTPUT_LVDS) { 3257 unsigned int lvds_bpc; 3258 3259 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == 3260 LVDS_A3_POWER_UP) 3261 lvds_bpc = 8; 3262 else 3263 lvds_bpc = 6; 3264 3265 if (lvds_bpc < display_bpc) { 3266 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); 3267 display_bpc = lvds_bpc; 3268 } 3269 continue; 3270 } 3271 3272 if (intel_encoder->type == INTEL_OUTPUT_EDP) { 3273 /* Use VBT settings if we have an eDP panel */ 3274 unsigned int edp_bpc = dev_priv->edp.bpp / 3; 3275 3276 if (edp_bpc < display_bpc) { 3277 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); 3278 display_bpc = edp_bpc; 3279 } 3280 continue; 3281 } 3282 3283 /* Not one of the known troublemakers, check the EDID */ 3284 list_for_each_entry(connector, &dev->mode_config.connector_list, 3285 head) { 3286 if (connector->encoder != encoder) 3287 continue; 3288 3289 /* Don't use an invalid EDID bpc value */ 3290 if (connector->display_info.bpc && 3291 connector->display_info.bpc < display_bpc) { 3292 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); 3293 display_bpc = connector->display_info.bpc; 3294 } 3295 } 3296 3297 /* 3298 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 3299 * through, clamp it down. (Note: >12bpc will be caught below.) 3300 */ 3301 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 3302 if (display_bpc > 8 && display_bpc < 12) { 3303 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); 3304 display_bpc = 12; 3305 } else { 3306 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); 3307 display_bpc = 8; 3308 } 3309 } 3310 } 3311 3312 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 3313 DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); 3314 display_bpc = 6; 3315 } 3316 3317 /* 3318 * We could just drive the pipe at the highest bpc all the time and 3319 * enable dithering as needed, but that costs bandwidth. So choose 3320 * the minimum value that expresses the full color range of the fb but 3321 * also stays within the max display bpc discovered above. 3322 */ 3323 3324 switch (crtc->fb->depth) { 3325 case 8: 3326 bpc = 8; /* since we go through a colormap */ 3327 break; 3328 case 15: 3329 case 16: 3330 bpc = 6; /* min is 18bpp */ 3331 break; 3332 case 24: 3333 bpc = 8; 3334 break; 3335 case 30: 3336 bpc = 10; 3337 break; 3338 case 48: 3339 bpc = 12; 3340 break; 3341 default: 3342 DRM_DEBUG("unsupported depth, assuming 24 bits\n"); 3343 bpc = min((unsigned int)8, display_bpc); 3344 break; 3345 } 3346 3347 display_bpc = min(display_bpc, bpc); 3348 3349 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", 3350 bpc, display_bpc); 3351 3352 *pipe_bpp = display_bpc * 3; 3353 3354 return display_bpc != bpc; 3355 } 3356 3357 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) 3358 { 3359 struct drm_device *dev = crtc->dev; 3360 struct drm_i915_private *dev_priv = dev->dev_private; 3361 int refclk; 3362 3363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 3364 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 3365 refclk = dev_priv->lvds_ssc_freq * 1000; 3366 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 3367 refclk / 1000); 3368 } else if (!IS_GEN2(dev)) { 3369 refclk = 96000; 3370 } else { 3371 refclk = 48000; 3372 } 3373 3374 return refclk; 3375 } 3376 3377 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, 3378 intel_clock_t *clock) 3379 { 3380 /* SDVO TV has fixed PLL values depend on its clock range, 3381 this mirrors vbios setting. */ 3382 if (adjusted_mode->clock >= 100000 3383 && adjusted_mode->clock < 140500) { 3384 clock->p1 = 2; 3385 clock->p2 = 10; 3386 clock->n = 3; 3387 clock->m1 = 16; 3388 clock->m2 = 8; 3389 } else if (adjusted_mode->clock >= 140500 3390 && adjusted_mode->clock <= 200000) { 3391 clock->p1 = 1; 3392 clock->p2 = 10; 3393 clock->n = 6; 3394 clock->m1 = 12; 3395 clock->m2 = 8; 3396 } 3397 } 3398 3399 static void i9xx_update_pll_dividers(struct drm_crtc *crtc, 3400 intel_clock_t *clock, 3401 intel_clock_t *reduced_clock) 3402 { 3403 struct drm_device *dev = crtc->dev; 3404 struct drm_i915_private *dev_priv = dev->dev_private; 3405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3406 int pipe = intel_crtc->pipe; 3407 u32 fp, fp2 = 0; 3408 3409 if (IS_PINEVIEW(dev)) { 3410 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; 3411 if (reduced_clock) 3412 fp2 = (1 << reduced_clock->n) << 16 | 3413 reduced_clock->m1 << 8 | reduced_clock->m2; 3414 } else { 3415 fp = clock->n << 16 | clock->m1 << 8 | clock->m2; 3416 if (reduced_clock) 3417 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | 3418 reduced_clock->m2; 3419 } 3420 3421 I915_WRITE(FP0(pipe), fp); 3422 3423 intel_crtc->lowfreq_avail = false; 3424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 3425 reduced_clock && i915_powersave) { 3426 I915_WRITE(FP1(pipe), fp2); 3427 intel_crtc->lowfreq_avail = true; 3428 } else { 3429 I915_WRITE(FP1(pipe), fp); 3430 } 3431 } 3432 3433 static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 3434 struct drm_display_mode *mode, 3435 struct drm_display_mode *adjusted_mode, 3436 int x, int y, 3437 struct drm_framebuffer *old_fb) 3438 { 3439 struct drm_device *dev = crtc->dev; 3440 struct drm_i915_private *dev_priv = dev->dev_private; 3441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3442 int pipe = intel_crtc->pipe; 3443 int plane = intel_crtc->plane; 3444 int refclk, num_connectors = 0; 3445 intel_clock_t clock, reduced_clock; 3446 u32 dpll, dspcntr, pipeconf, vsyncshift; 3447 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3448 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3449 struct drm_mode_config *mode_config = &dev->mode_config; 3450 struct intel_encoder *encoder; 3451 const intel_limit_t *limit; 3452 int ret; 3453 u32 temp; 3454 u32 lvds_sync = 0; 3455 3456 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3457 if (encoder->base.crtc != crtc) 3458 continue; 3459 3460 switch (encoder->type) { 3461 case INTEL_OUTPUT_LVDS: 3462 is_lvds = true; 3463 break; 3464 case INTEL_OUTPUT_SDVO: 3465 case INTEL_OUTPUT_HDMI: 3466 is_sdvo = true; 3467 if (encoder->needs_tv_clock) 3468 is_tv = true; 3469 break; 3470 case INTEL_OUTPUT_DVO: 3471 is_dvo = true; 3472 break; 3473 case INTEL_OUTPUT_TVOUT: 3474 is_tv = true; 3475 break; 3476 case INTEL_OUTPUT_ANALOG: 3477 is_crt = true; 3478 break; 3479 case INTEL_OUTPUT_DISPLAYPORT: 3480 is_dp = true; 3481 break; 3482 } 3483 3484 num_connectors++; 3485 } 3486 3487 refclk = i9xx_get_refclk(crtc, num_connectors); 3488 3489 /* 3490 * Returns a set of divisors for the desired target clock with the given 3491 * refclk, or false. The returned values represent the clock equation: 3492 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 3493 */ 3494 limit = intel_limit(crtc, refclk); 3495 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 3496 &clock); 3497 if (!ok) { 3498 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 3499 return -EINVAL; 3500 } 3501 3502 /* Ensure that the cursor is valid for the new mode before changing... */ 3503 intel_crtc_update_cursor(crtc, true); 3504 3505 if (is_lvds && dev_priv->lvds_downclock_avail) { 3506 /* 3507 * Ensure we match the reduced clock's P to the target clock. 3508 * If the clocks don't match, we can't switch the display clock 3509 * by using the FP0/FP1. In such case we will disable the LVDS 3510 * downclock feature. 3511 */ 3512 has_reduced_clock = limit->find_pll(limit, crtc, 3513 dev_priv->lvds_downclock, 3514 refclk, 3515 &clock, 3516 &reduced_clock); 3517 } 3518 3519 if (is_sdvo && is_tv) 3520 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); 3521 3522 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? 3523 &reduced_clock : NULL); 3524 3525 dpll = DPLL_VGA_MODE_DIS; 3526 3527 if (!IS_GEN2(dev)) { 3528 if (is_lvds) 3529 dpll |= DPLLB_MODE_LVDS; 3530 else 3531 dpll |= DPLLB_MODE_DAC_SERIAL; 3532 if (is_sdvo) { 3533 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 3534 if (pixel_multiplier > 1) { 3535 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 3536 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 3537 } 3538 dpll |= DPLL_DVO_HIGH_SPEED; 3539 } 3540 if (is_dp) 3541 dpll |= DPLL_DVO_HIGH_SPEED; 3542 3543 /* compute bitmask from p1 value */ 3544 if (IS_PINEVIEW(dev)) 3545 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 3546 else { 3547 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3548 if (IS_G4X(dev) && has_reduced_clock) 3549 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 3550 } 3551 switch (clock.p2) { 3552 case 5: 3553 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 3554 break; 3555 case 7: 3556 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 3557 break; 3558 case 10: 3559 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 3560 break; 3561 case 14: 3562 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 3563 break; 3564 } 3565 if (INTEL_INFO(dev)->gen >= 4) 3566 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 3567 } else { 3568 if (is_lvds) { 3569 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3570 } else { 3571 if (clock.p1 == 2) 3572 dpll |= PLL_P1_DIVIDE_BY_TWO; 3573 else 3574 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 3575 if (clock.p2 == 4) 3576 dpll |= PLL_P2_DIVIDE_BY_4; 3577 } 3578 } 3579 3580 if (is_sdvo && is_tv) 3581 dpll |= PLL_REF_INPUT_TVCLKINBC; 3582 else if (is_tv) 3583 /* XXX: just matching BIOS for now */ 3584 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 3585 dpll |= 3; 3586 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 3587 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 3588 else 3589 dpll |= PLL_REF_INPUT_DREFCLK; 3590 3591 /* setup pipeconf */ 3592 pipeconf = I915_READ(PIPECONF(pipe)); 3593 3594 /* Set up the display plane register */ 3595 dspcntr = DISPPLANE_GAMMA_ENABLE; 3596 3597 if (pipe == 0) 3598 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 3599 else 3600 dspcntr |= DISPPLANE_SEL_PIPE_B; 3601 3602 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { 3603 /* Enable pixel doubling when the dot clock is > 90% of the (display) 3604 * core speed. 3605 * 3606 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the 3607 * pipe == 0 check? 3608 */ 3609 if (mode->clock > 3610 dev_priv->display.get_display_clock_speed(dev) * 9 / 10) 3611 pipeconf |= PIPECONF_DOUBLE_WIDE; 3612 else 3613 pipeconf &= ~PIPECONF_DOUBLE_WIDE; 3614 } 3615 3616 /* default to 8bpc */ 3617 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); 3618 if (is_dp) { 3619 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 3620 pipeconf |= PIPECONF_BPP_6 | 3621 PIPECONF_DITHER_EN | 3622 PIPECONF_DITHER_TYPE_SP; 3623 } 3624 } 3625 3626 dpll |= DPLL_VCO_ENABLE; 3627 3628 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 3629 drm_mode_debug_printmodeline(mode); 3630 3631 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 3632 3633 POSTING_READ(DPLL(pipe)); 3634 DELAY(150); 3635 3636 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 3637 * This is an exception to the general rule that mode_set doesn't turn 3638 * things on. 3639 */ 3640 if (is_lvds) { 3641 temp = I915_READ(LVDS); 3642 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 3643 if (pipe == 1) { 3644 temp |= LVDS_PIPEB_SELECT; 3645 } else { 3646 temp &= ~LVDS_PIPEB_SELECT; 3647 } 3648 /* set the corresponsding LVDS_BORDER bit */ 3649 temp |= dev_priv->lvds_border_bits; 3650 /* Set the B0-B3 data pairs corresponding to whether we're going to 3651 * set the DPLLs for dual-channel mode or not. 3652 */ 3653 if (clock.p2 == 7) 3654 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 3655 else 3656 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 3657 3658 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 3659 * appropriately here, but we need to look more thoroughly into how 3660 * panels behave in the two modes. 3661 */ 3662 /* set the dithering flag on LVDS as needed */ 3663 if (INTEL_INFO(dev)->gen >= 4) { 3664 if (dev_priv->lvds_dither) 3665 temp |= LVDS_ENABLE_DITHER; 3666 else 3667 temp &= ~LVDS_ENABLE_DITHER; 3668 } 3669 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 3670 lvds_sync |= LVDS_HSYNC_POLARITY; 3671 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 3672 lvds_sync |= LVDS_VSYNC_POLARITY; 3673 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) 3674 != lvds_sync) { 3675 char flags[2] = "-+"; 3676 DRM_INFO("Changing LVDS panel from " 3677 "(%chsync, %cvsync) to (%chsync, %cvsync)\n", 3678 flags[!(temp & LVDS_HSYNC_POLARITY)], 3679 flags[!(temp & LVDS_VSYNC_POLARITY)], 3680 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], 3681 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); 3682 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 3683 temp |= lvds_sync; 3684 } 3685 I915_WRITE(LVDS, temp); 3686 } 3687 3688 if (is_dp) { 3689 intel_dp_set_m_n(crtc, mode, adjusted_mode); 3690 } 3691 3692 I915_WRITE(DPLL(pipe), dpll); 3693 3694 /* Wait for the clocks to stabilize. */ 3695 POSTING_READ(DPLL(pipe)); 3696 DELAY(150); 3697 3698 if (INTEL_INFO(dev)->gen >= 4) { 3699 temp = 0; 3700 if (is_sdvo) { 3701 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 3702 if (temp > 1) 3703 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 3704 else 3705 temp = 0; 3706 } 3707 I915_WRITE(DPLL_MD(pipe), temp); 3708 } else { 3709 /* The pixel multiplier can only be updated once the 3710 * DPLL is enabled and the clocks are stable. 3711 * 3712 * So write it again. 3713 */ 3714 I915_WRITE(DPLL(pipe), dpll); 3715 } 3716 3717 if (HAS_PIPE_CXSR(dev)) { 3718 if (intel_crtc->lowfreq_avail) { 3719 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 3720 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 3721 } else { 3722 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 3723 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 3724 } 3725 } 3726 3727 pipeconf &= ~PIPECONF_INTERLACE_MASK; 3728 if (!IS_GEN2(dev) && 3729 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 3730 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 3731 /* the chip adds 2 halflines automatically */ 3732 adjusted_mode->crtc_vtotal -= 1; 3733 adjusted_mode->crtc_vblank_end -= 1; 3734 vsyncshift = adjusted_mode->crtc_hsync_start 3735 - adjusted_mode->crtc_htotal/2; 3736 } else { 3737 pipeconf |= PIPECONF_PROGRESSIVE; 3738 vsyncshift = 0; 3739 } 3740 3741 if (!IS_GEN3(dev)) 3742 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); 3743 3744 I915_WRITE(HTOTAL(pipe), 3745 (adjusted_mode->crtc_hdisplay - 1) | 3746 ((adjusted_mode->crtc_htotal - 1) << 16)); 3747 I915_WRITE(HBLANK(pipe), 3748 (adjusted_mode->crtc_hblank_start - 1) | 3749 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 3750 I915_WRITE(HSYNC(pipe), 3751 (adjusted_mode->crtc_hsync_start - 1) | 3752 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 3753 3754 I915_WRITE(VTOTAL(pipe), 3755 (adjusted_mode->crtc_vdisplay - 1) | 3756 ((adjusted_mode->crtc_vtotal - 1) << 16)); 3757 I915_WRITE(VBLANK(pipe), 3758 (adjusted_mode->crtc_vblank_start - 1) | 3759 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 3760 I915_WRITE(VSYNC(pipe), 3761 (adjusted_mode->crtc_vsync_start - 1) | 3762 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 3763 3764 /* pipesrc and dspsize control the size that is scaled from, 3765 * which should always be the user's requested size. 3766 */ 3767 I915_WRITE(DSPSIZE(plane), 3768 ((mode->vdisplay - 1) << 16) | 3769 (mode->hdisplay - 1)); 3770 I915_WRITE(DSPPOS(plane), 0); 3771 I915_WRITE(PIPESRC(pipe), 3772 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 3773 3774 I915_WRITE(PIPECONF(pipe), pipeconf); 3775 POSTING_READ(PIPECONF(pipe)); 3776 intel_enable_pipe(dev_priv, pipe, false); 3777 3778 intel_wait_for_vblank(dev, pipe); 3779 3780 I915_WRITE(DSPCNTR(plane), dspcntr); 3781 POSTING_READ(DSPCNTR(plane)); 3782 intel_enable_plane(dev_priv, plane, pipe); 3783 3784 ret = intel_pipe_set_base(crtc, x, y, old_fb); 3785 3786 intel_update_watermarks(dev); 3787 3788 return ret; 3789 } 3790 3791 /* 3792 * Initialize reference clocks when the driver loads 3793 */ 3794 void ironlake_init_pch_refclk(struct drm_device *dev) 3795 { 3796 struct drm_i915_private *dev_priv = dev->dev_private; 3797 struct drm_mode_config *mode_config = &dev->mode_config; 3798 struct intel_encoder *encoder; 3799 u32 temp; 3800 bool has_lvds = false; 3801 bool has_cpu_edp = false; 3802 bool has_pch_edp = false; 3803 bool has_panel = false; 3804 bool has_ck505 = false; 3805 bool can_ssc = false; 3806 3807 /* We need to take the global config into account */ 3808 list_for_each_entry(encoder, &mode_config->encoder_list, 3809 base.head) { 3810 switch (encoder->type) { 3811 case INTEL_OUTPUT_LVDS: 3812 has_panel = true; 3813 has_lvds = true; 3814 break; 3815 case INTEL_OUTPUT_EDP: 3816 has_panel = true; 3817 if (intel_encoder_is_pch_edp(&encoder->base)) 3818 has_pch_edp = true; 3819 else 3820 has_cpu_edp = true; 3821 break; 3822 } 3823 } 3824 3825 if (HAS_PCH_IBX(dev)) { 3826 has_ck505 = dev_priv->display_clock_mode; 3827 can_ssc = has_ck505; 3828 } else { 3829 has_ck505 = false; 3830 can_ssc = true; 3831 } 3832 3833 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", 3834 has_panel, has_lvds, has_pch_edp, has_cpu_edp, 3835 has_ck505); 3836 3837 /* Ironlake: try to setup display ref clock before DPLL 3838 * enabling. This is only under driver's control after 3839 * PCH B stepping, previous chipset stepping should be 3840 * ignoring this setting. 3841 */ 3842 temp = I915_READ(PCH_DREF_CONTROL); 3843 /* Always enable nonspread source */ 3844 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 3845 3846 if (has_ck505) 3847 temp |= DREF_NONSPREAD_CK505_ENABLE; 3848 else 3849 temp |= DREF_NONSPREAD_SOURCE_ENABLE; 3850 3851 if (has_panel) { 3852 temp &= ~DREF_SSC_SOURCE_MASK; 3853 temp |= DREF_SSC_SOURCE_ENABLE; 3854 3855 /* SSC must be turned on before enabling the CPU output */ 3856 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 3857 DRM_DEBUG_KMS("Using SSC on panel\n"); 3858 temp |= DREF_SSC1_ENABLE; 3859 } else 3860 temp &= ~DREF_SSC1_ENABLE; 3861 3862 /* Get SSC going before enabling the outputs */ 3863 I915_WRITE(PCH_DREF_CONTROL, temp); 3864 POSTING_READ(PCH_DREF_CONTROL); 3865 DELAY(200); 3866 3867 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 3868 3869 /* Enable CPU source on CPU attached eDP */ 3870 if (has_cpu_edp) { 3871 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 3872 DRM_DEBUG_KMS("Using SSC on eDP\n"); 3873 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 3874 } 3875 else 3876 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 3877 } else 3878 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 3879 3880 I915_WRITE(PCH_DREF_CONTROL, temp); 3881 POSTING_READ(PCH_DREF_CONTROL); 3882 DELAY(200); 3883 } else { 3884 DRM_DEBUG_KMS("Disabling SSC entirely\n"); 3885 3886 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 3887 3888 /* Turn off CPU output */ 3889 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 3890 3891 I915_WRITE(PCH_DREF_CONTROL, temp); 3892 POSTING_READ(PCH_DREF_CONTROL); 3893 DELAY(200); 3894 3895 /* Turn off the SSC source */ 3896 temp &= ~DREF_SSC_SOURCE_MASK; 3897 temp |= DREF_SSC_SOURCE_DISABLE; 3898 3899 /* Turn off SSC1 */ 3900 temp &= ~ DREF_SSC1_ENABLE; 3901 3902 I915_WRITE(PCH_DREF_CONTROL, temp); 3903 POSTING_READ(PCH_DREF_CONTROL); 3904 DELAY(200); 3905 } 3906 } 3907 3908 static int ironlake_get_refclk(struct drm_crtc *crtc) 3909 { 3910 struct drm_device *dev = crtc->dev; 3911 struct drm_i915_private *dev_priv = dev->dev_private; 3912 struct intel_encoder *encoder; 3913 struct drm_mode_config *mode_config = &dev->mode_config; 3914 struct intel_encoder *edp_encoder = NULL; 3915 int num_connectors = 0; 3916 bool is_lvds = false; 3917 3918 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3919 if (encoder->base.crtc != crtc) 3920 continue; 3921 3922 switch (encoder->type) { 3923 case INTEL_OUTPUT_LVDS: 3924 is_lvds = true; 3925 break; 3926 case INTEL_OUTPUT_EDP: 3927 edp_encoder = encoder; 3928 break; 3929 } 3930 num_connectors++; 3931 } 3932 3933 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 3934 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 3935 dev_priv->lvds_ssc_freq); 3936 return dev_priv->lvds_ssc_freq * 1000; 3937 } 3938 3939 return 120000; 3940 } 3941 3942 static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 3943 struct drm_display_mode *mode, 3944 struct drm_display_mode *adjusted_mode, 3945 int x, int y, 3946 struct drm_framebuffer *old_fb) 3947 { 3948 struct drm_device *dev = crtc->dev; 3949 struct drm_i915_private *dev_priv = dev->dev_private; 3950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3951 int pipe = intel_crtc->pipe; 3952 int plane = intel_crtc->plane; 3953 int refclk, num_connectors = 0; 3954 intel_clock_t clock, reduced_clock; 3955 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; 3956 bool ok, has_reduced_clock = false, is_sdvo = false; 3957 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3958 struct intel_encoder *has_edp_encoder = NULL; 3959 struct drm_mode_config *mode_config = &dev->mode_config; 3960 struct intel_encoder *encoder; 3961 const intel_limit_t *limit; 3962 int ret; 3963 struct fdi_m_n m_n = {0}; 3964 u32 temp; 3965 u32 lvds_sync = 0; 3966 int target_clock, pixel_multiplier, lane, link_bw, factor; 3967 unsigned int pipe_bpp; 3968 bool dither; 3969 3970 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 3971 if (encoder->base.crtc != crtc) 3972 continue; 3973 3974 switch (encoder->type) { 3975 case INTEL_OUTPUT_LVDS: 3976 is_lvds = true; 3977 break; 3978 case INTEL_OUTPUT_SDVO: 3979 case INTEL_OUTPUT_HDMI: 3980 is_sdvo = true; 3981 if (encoder->needs_tv_clock) 3982 is_tv = true; 3983 break; 3984 case INTEL_OUTPUT_TVOUT: 3985 is_tv = true; 3986 break; 3987 case INTEL_OUTPUT_ANALOG: 3988 is_crt = true; 3989 break; 3990 case INTEL_OUTPUT_DISPLAYPORT: 3991 is_dp = true; 3992 break; 3993 case INTEL_OUTPUT_EDP: 3994 has_edp_encoder = encoder; 3995 break; 3996 } 3997 3998 num_connectors++; 3999 } 4000 4001 refclk = ironlake_get_refclk(crtc); 4002 4003 /* 4004 * Returns a set of divisors for the desired target clock with the given 4005 * refclk, or false. The returned values represent the clock equation: 4006 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 4007 */ 4008 limit = intel_limit(crtc, refclk); 4009 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 4010 &clock); 4011 if (!ok) { 4012 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 4013 return -EINVAL; 4014 } 4015 4016 /* Ensure that the cursor is valid for the new mode before changing... */ 4017 intel_crtc_update_cursor(crtc, true); 4018 4019 if (is_lvds && dev_priv->lvds_downclock_avail) { 4020 /* 4021 * Ensure we match the reduced clock's P to the target clock. 4022 * If the clocks don't match, we can't switch the display clock 4023 * by using the FP0/FP1. In such case we will disable the LVDS 4024 * downclock feature. 4025 */ 4026 has_reduced_clock = limit->find_pll(limit, crtc, 4027 dev_priv->lvds_downclock, 4028 refclk, 4029 &clock, 4030 &reduced_clock); 4031 } 4032 /* SDVO TV has fixed PLL values depend on its clock range, 4033 this mirrors vbios setting. */ 4034 if (is_sdvo && is_tv) { 4035 if (adjusted_mode->clock >= 100000 4036 && adjusted_mode->clock < 140500) { 4037 clock.p1 = 2; 4038 clock.p2 = 10; 4039 clock.n = 3; 4040 clock.m1 = 16; 4041 clock.m2 = 8; 4042 } else if (adjusted_mode->clock >= 140500 4043 && adjusted_mode->clock <= 200000) { 4044 clock.p1 = 1; 4045 clock.p2 = 10; 4046 clock.n = 6; 4047 clock.m1 = 12; 4048 clock.m2 = 8; 4049 } 4050 } 4051 4052 /* FDI link */ 4053 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4054 lane = 0; 4055 /* CPU eDP doesn't require FDI link, so just set DP M/N 4056 according to current link config */ 4057 if (has_edp_encoder && 4058 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4059 target_clock = mode->clock; 4060 intel_edp_link_config(has_edp_encoder, 4061 &lane, &link_bw); 4062 } else { 4063 /* [e]DP over FDI requires target mode clock 4064 instead of link clock */ 4065 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4066 target_clock = mode->clock; 4067 else 4068 target_clock = adjusted_mode->clock; 4069 4070 /* FDI is a binary signal running at ~2.7GHz, encoding 4071 * each output octet as 10 bits. The actual frequency 4072 * is stored as a divider into a 100MHz clock, and the 4073 * mode pixel clock is stored in units of 1KHz. 4074 * Hence the bw of each lane in terms of the mode signal 4075 * is: 4076 */ 4077 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; 4078 } 4079 4080 /* determine panel color depth */ 4081 temp = I915_READ(PIPECONF(pipe)); 4082 temp &= ~PIPE_BPC_MASK; 4083 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); 4084 switch (pipe_bpp) { 4085 case 18: 4086 temp |= PIPE_6BPC; 4087 break; 4088 case 24: 4089 temp |= PIPE_8BPC; 4090 break; 4091 case 30: 4092 temp |= PIPE_10BPC; 4093 break; 4094 case 36: 4095 temp |= PIPE_12BPC; 4096 break; 4097 default: 4098 kprintf("intel_choose_pipe_bpp returned invalid value %d\n", 4099 pipe_bpp); 4100 temp |= PIPE_8BPC; 4101 pipe_bpp = 24; 4102 break; 4103 } 4104 4105 intel_crtc->bpp = pipe_bpp; 4106 I915_WRITE(PIPECONF(pipe), temp); 4107 4108 if (!lane) { 4109 /* 4110 * Account for spread spectrum to avoid 4111 * oversubscribing the link. Max center spread 4112 * is 2.5%; use 5% for safety's sake. 4113 */ 4114 u32 bps = target_clock * intel_crtc->bpp * 21 / 20; 4115 lane = bps / (link_bw * 8) + 1; 4116 } 4117 4118 intel_crtc->fdi_lanes = lane; 4119 4120 if (pixel_multiplier > 1) 4121 link_bw *= pixel_multiplier; 4122 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, 4123 &m_n); 4124 4125 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 4126 if (has_reduced_clock) 4127 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | 4128 reduced_clock.m2; 4129 4130 /* Enable autotuning of the PLL clock (if permissible) */ 4131 factor = 21; 4132 if (is_lvds) { 4133 if ((intel_panel_use_ssc(dev_priv) && 4134 dev_priv->lvds_ssc_freq == 100) || 4135 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) 4136 factor = 25; 4137 } else if (is_sdvo && is_tv) 4138 factor = 20; 4139 4140 if (clock.m < factor * clock.n) 4141 fp |= FP_CB_TUNE; 4142 4143 dpll = 0; 4144 4145 if (is_lvds) 4146 dpll |= DPLLB_MODE_LVDS; 4147 else 4148 dpll |= DPLLB_MODE_DAC_SERIAL; 4149 if (is_sdvo) { 4150 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4151 if (pixel_multiplier > 1) { 4152 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 4153 } 4154 dpll |= DPLL_DVO_HIGH_SPEED; 4155 } 4156 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4157 dpll |= DPLL_DVO_HIGH_SPEED; 4158 4159 /* compute bitmask from p1 value */ 4160 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4161 /* also FPA1 */ 4162 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 4163 4164 switch (clock.p2) { 4165 case 5: 4166 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 4167 break; 4168 case 7: 4169 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 4170 break; 4171 case 10: 4172 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 4173 break; 4174 case 14: 4175 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 4176 break; 4177 } 4178 4179 if (is_sdvo && is_tv) 4180 dpll |= PLL_REF_INPUT_TVCLKINBC; 4181 else if (is_tv) 4182 /* XXX: just matching BIOS for now */ 4183 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4184 dpll |= 3; 4185 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4186 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4187 else 4188 dpll |= PLL_REF_INPUT_DREFCLK; 4189 4190 /* setup pipeconf */ 4191 pipeconf = I915_READ(PIPECONF(pipe)); 4192 4193 /* Set up the display plane register */ 4194 dspcntr = DISPPLANE_GAMMA_ENABLE; 4195 4196 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 4197 drm_mode_debug_printmodeline(mode); 4198 4199 /* PCH eDP needs FDI, but CPU eDP does not */ 4200 if (!intel_crtc->no_pll) { 4201 if (!has_edp_encoder || 4202 intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4203 I915_WRITE(_PCH_FP0(pipe), fp); 4204 I915_WRITE(_PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4205 4206 POSTING_READ(_PCH_DPLL(pipe)); 4207 DELAY(150); 4208 } 4209 } else { 4210 if (dpll == (I915_READ(_PCH_DPLL(0)) & 0x7fffffff) && 4211 fp == I915_READ(_PCH_FP0(0))) { 4212 intel_crtc->use_pll_a = true; 4213 DRM_DEBUG_KMS("using pipe a dpll\n"); 4214 } else if (dpll == (I915_READ(_PCH_DPLL(1)) & 0x7fffffff) && 4215 fp == I915_READ(_PCH_FP0(1))) { 4216 intel_crtc->use_pll_a = false; 4217 DRM_DEBUG_KMS("using pipe b dpll\n"); 4218 } else { 4219 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); 4220 return -EINVAL; 4221 } 4222 } 4223 4224 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 4225 * This is an exception to the general rule that mode_set doesn't turn 4226 * things on. 4227 */ 4228 if (is_lvds) { 4229 temp = I915_READ(PCH_LVDS); 4230 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 4231 if (HAS_PCH_CPT(dev)) { 4232 temp &= ~PORT_TRANS_SEL_MASK; 4233 temp |= PORT_TRANS_SEL_CPT(pipe); 4234 } else { 4235 if (pipe == 1) 4236 temp |= LVDS_PIPEB_SELECT; 4237 else 4238 temp &= ~LVDS_PIPEB_SELECT; 4239 } 4240 4241 /* set the corresponsding LVDS_BORDER bit */ 4242 temp |= dev_priv->lvds_border_bits; 4243 /* Set the B0-B3 data pairs corresponding to whether we're going to 4244 * set the DPLLs for dual-channel mode or not. 4245 */ 4246 if (clock.p2 == 7) 4247 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 4248 else 4249 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 4250 4251 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 4252 * appropriately here, but we need to look more thoroughly into how 4253 * panels behave in the two modes. 4254 */ 4255 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 4256 lvds_sync |= LVDS_HSYNC_POLARITY; 4257 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 4258 lvds_sync |= LVDS_VSYNC_POLARITY; 4259 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) 4260 != lvds_sync) { 4261 char flags[2] = "-+"; 4262 DRM_INFO("Changing LVDS panel from " 4263 "(%chsync, %cvsync) to (%chsync, %cvsync)\n", 4264 flags[!(temp & LVDS_HSYNC_POLARITY)], 4265 flags[!(temp & LVDS_VSYNC_POLARITY)], 4266 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], 4267 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); 4268 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 4269 temp |= lvds_sync; 4270 } 4271 I915_WRITE(PCH_LVDS, temp); 4272 } 4273 4274 pipeconf &= ~PIPECONF_DITHER_EN; 4275 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; 4276 if ((is_lvds && dev_priv->lvds_dither) || dither) { 4277 pipeconf |= PIPECONF_DITHER_EN; 4278 pipeconf |= PIPECONF_DITHER_TYPE_SP; 4279 } 4280 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4281 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4282 } else { 4283 /* For non-DP output, clear any trans DP clock recovery setting.*/ 4284 I915_WRITE(TRANSDATA_M1(pipe), 0); 4285 I915_WRITE(TRANSDATA_N1(pipe), 0); 4286 I915_WRITE(TRANSDPLINK_M1(pipe), 0); 4287 I915_WRITE(TRANSDPLINK_N1(pipe), 0); 4288 } 4289 4290 if (!intel_crtc->no_pll && 4291 (!has_edp_encoder || 4292 intel_encoder_is_pch_edp(&has_edp_encoder->base))) { 4293 I915_WRITE(_PCH_DPLL(pipe), dpll); 4294 4295 /* Wait for the clocks to stabilize. */ 4296 POSTING_READ(_PCH_DPLL(pipe)); 4297 DELAY(150); 4298 4299 /* The pixel multiplier can only be updated once the 4300 * DPLL is enabled and the clocks are stable. 4301 * 4302 * So write it again. 4303 */ 4304 I915_WRITE(_PCH_DPLL(pipe), dpll); 4305 } 4306 4307 intel_crtc->lowfreq_avail = false; 4308 if (!intel_crtc->no_pll) { 4309 if (is_lvds && has_reduced_clock && i915_powersave) { 4310 I915_WRITE(_PCH_FP1(pipe), fp2); 4311 intel_crtc->lowfreq_avail = true; 4312 if (HAS_PIPE_CXSR(dev)) { 4313 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 4314 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4315 } 4316 } else { 4317 I915_WRITE(_PCH_FP1(pipe), fp); 4318 if (HAS_PIPE_CXSR(dev)) { 4319 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4320 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 4321 } 4322 } 4323 } 4324 4325 pipeconf &= ~PIPECONF_INTERLACE_MASK; 4326 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 4327 pipeconf |= PIPECONF_INTERLACED_ILK; 4328 /* the chip adds 2 halflines automatically */ 4329 adjusted_mode->crtc_vtotal -= 1; 4330 adjusted_mode->crtc_vblank_end -= 1; 4331 I915_WRITE(VSYNCSHIFT(pipe), 4332 adjusted_mode->crtc_hsync_start 4333 - adjusted_mode->crtc_htotal/2); 4334 } else { 4335 pipeconf |= PIPECONF_PROGRESSIVE; 4336 I915_WRITE(VSYNCSHIFT(pipe), 0); 4337 } 4338 4339 I915_WRITE(HTOTAL(pipe), 4340 (adjusted_mode->crtc_hdisplay - 1) | 4341 ((adjusted_mode->crtc_htotal - 1) << 16)); 4342 I915_WRITE(HBLANK(pipe), 4343 (adjusted_mode->crtc_hblank_start - 1) | 4344 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 4345 I915_WRITE(HSYNC(pipe), 4346 (adjusted_mode->crtc_hsync_start - 1) | 4347 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 4348 4349 I915_WRITE(VTOTAL(pipe), 4350 (adjusted_mode->crtc_vdisplay - 1) | 4351 ((adjusted_mode->crtc_vtotal - 1) << 16)); 4352 I915_WRITE(VBLANK(pipe), 4353 (adjusted_mode->crtc_vblank_start - 1) | 4354 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 4355 I915_WRITE(VSYNC(pipe), 4356 (adjusted_mode->crtc_vsync_start - 1) | 4357 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 4358 4359 /* pipesrc controls the size that is scaled from, which should 4360 * always be the user's requested size. 4361 */ 4362 I915_WRITE(PIPESRC(pipe), 4363 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4364 4365 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 4366 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); 4367 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); 4368 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); 4369 4370 if (has_edp_encoder && 4371 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 4372 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4373 } 4374 4375 I915_WRITE(PIPECONF(pipe), pipeconf); 4376 POSTING_READ(PIPECONF(pipe)); 4377 4378 intel_wait_for_vblank(dev, pipe); 4379 4380 I915_WRITE(DSPCNTR(plane), dspcntr); 4381 POSTING_READ(DSPCNTR(plane)); 4382 4383 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4384 4385 intel_update_watermarks(dev); 4386 4387 return ret; 4388 } 4389 4390 static int intel_crtc_mode_set(struct drm_crtc *crtc, 4391 struct drm_display_mode *mode, 4392 struct drm_display_mode *adjusted_mode, 4393 int x, int y, 4394 struct drm_framebuffer *old_fb) 4395 { 4396 struct drm_device *dev = crtc->dev; 4397 struct drm_i915_private *dev_priv = dev->dev_private; 4398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4399 int pipe = intel_crtc->pipe; 4400 int ret; 4401 4402 drm_vblank_pre_modeset(dev, pipe); 4403 4404 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, 4405 x, y, old_fb); 4406 drm_vblank_post_modeset(dev, pipe); 4407 4408 if (ret) 4409 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 4410 else 4411 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; 4412 4413 return ret; 4414 } 4415 4416 static bool intel_eld_uptodate(struct drm_connector *connector, 4417 int reg_eldv, uint32_t bits_eldv, 4418 int reg_elda, uint32_t bits_elda, 4419 int reg_edid) 4420 { 4421 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4422 uint8_t *eld = connector->eld; 4423 uint32_t i; 4424 4425 i = I915_READ(reg_eldv); 4426 i &= bits_eldv; 4427 4428 if (!eld[0]) 4429 return !i; 4430 4431 if (!i) 4432 return false; 4433 4434 i = I915_READ(reg_elda); 4435 i &= ~bits_elda; 4436 I915_WRITE(reg_elda, i); 4437 4438 for (i = 0; i < eld[2]; i++) 4439 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 4440 return false; 4441 4442 return true; 4443 } 4444 4445 static void g4x_write_eld(struct drm_connector *connector, 4446 struct drm_crtc *crtc) 4447 { 4448 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4449 uint8_t *eld = connector->eld; 4450 uint32_t eldv; 4451 uint32_t len; 4452 uint32_t i; 4453 4454 i = I915_READ(G4X_AUD_VID_DID); 4455 4456 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) 4457 eldv = G4X_ELDV_DEVCL_DEVBLC; 4458 else 4459 eldv = G4X_ELDV_DEVCTG; 4460 4461 if (intel_eld_uptodate(connector, 4462 G4X_AUD_CNTL_ST, eldv, 4463 G4X_AUD_CNTL_ST, G4X_ELD_ADDR, 4464 G4X_HDMIW_HDMIEDID)) 4465 return; 4466 4467 i = I915_READ(G4X_AUD_CNTL_ST); 4468 i &= ~(eldv | G4X_ELD_ADDR); 4469 len = (i >> 9) & 0x1f; /* ELD buffer size */ 4470 I915_WRITE(G4X_AUD_CNTL_ST, i); 4471 4472 if (!eld[0]) 4473 return; 4474 4475 if (eld[2] < (uint8_t)len) 4476 len = eld[2]; 4477 DRM_DEBUG_KMS("ELD size %d\n", len); 4478 for (i = 0; i < len; i++) 4479 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 4480 4481 i = I915_READ(G4X_AUD_CNTL_ST); 4482 i |= eldv; 4483 I915_WRITE(G4X_AUD_CNTL_ST, i); 4484 } 4485 4486 static void ironlake_write_eld(struct drm_connector *connector, 4487 struct drm_crtc *crtc) 4488 { 4489 struct drm_i915_private *dev_priv = connector->dev->dev_private; 4490 uint8_t *eld = connector->eld; 4491 uint32_t eldv; 4492 uint32_t i; 4493 int len; 4494 int hdmiw_hdmiedid; 4495 int aud_config; 4496 int aud_cntl_st; 4497 int aud_cntrl_st2; 4498 4499 if (HAS_PCH_IBX(connector->dev)) { 4500 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; 4501 aud_config = IBX_AUD_CONFIG_A; 4502 aud_cntl_st = IBX_AUD_CNTL_ST_A; 4503 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 4504 } else { 4505 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; 4506 aud_config = CPT_AUD_CONFIG_A; 4507 aud_cntl_st = CPT_AUD_CNTL_ST_A; 4508 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 4509 } 4510 4511 i = to_intel_crtc(crtc)->pipe; 4512 hdmiw_hdmiedid += i * 0x100; 4513 aud_cntl_st += i * 0x100; 4514 aud_config += i * 0x100; 4515 4516 DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i)); 4517 4518 i = I915_READ(aud_cntl_st); 4519 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ 4520 if (!i) { 4521 DRM_DEBUG_KMS("Audio directed to unknown port\n"); 4522 /* operate blindly on all ports */ 4523 eldv = IBX_ELD_VALIDB; 4524 eldv |= IBX_ELD_VALIDB << 4; 4525 eldv |= IBX_ELD_VALIDB << 8; 4526 } else { 4527 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i); 4528 eldv = IBX_ELD_VALIDB << ((i - 1) * 4); 4529 } 4530 4531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 4532 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); 4533 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ 4534 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ 4535 } else 4536 I915_WRITE(aud_config, 0); 4537 4538 if (intel_eld_uptodate(connector, 4539 aud_cntrl_st2, eldv, 4540 aud_cntl_st, IBX_ELD_ADDRESS, 4541 hdmiw_hdmiedid)) 4542 return; 4543 4544 i = I915_READ(aud_cntrl_st2); 4545 i &= ~eldv; 4546 I915_WRITE(aud_cntrl_st2, i); 4547 4548 if (!eld[0]) 4549 return; 4550 4551 i = I915_READ(aud_cntl_st); 4552 i &= ~IBX_ELD_ADDRESS; 4553 I915_WRITE(aud_cntl_st, i); 4554 4555 /* 84 bytes of hw ELD buffer */ 4556 len = 21; 4557 if (eld[2] < (uint8_t)len) 4558 len = eld[2]; 4559 DRM_DEBUG_KMS("ELD size %d\n", len); 4560 for (i = 0; i < len; i++) 4561 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 4562 4563 i = I915_READ(aud_cntrl_st2); 4564 i |= eldv; 4565 I915_WRITE(aud_cntrl_st2, i); 4566 } 4567 4568 void intel_write_eld(struct drm_encoder *encoder, 4569 struct drm_display_mode *mode) 4570 { 4571 struct drm_crtc *crtc = encoder->crtc; 4572 struct drm_connector *connector; 4573 struct drm_device *dev = encoder->dev; 4574 struct drm_i915_private *dev_priv = dev->dev_private; 4575 4576 connector = drm_select_eld(encoder, mode); 4577 if (!connector) 4578 return; 4579 4580 DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 4581 connector->base.id, 4582 drm_get_connector_name(connector), 4583 connector->encoder->base.id, 4584 drm_get_encoder_name(connector->encoder)); 4585 4586 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; 4587 4588 if (dev_priv->display.write_eld) 4589 dev_priv->display.write_eld(connector, crtc); 4590 } 4591 4592 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 4593 void intel_crtc_load_lut(struct drm_crtc *crtc) 4594 { 4595 struct drm_device *dev = crtc->dev; 4596 struct drm_i915_private *dev_priv = dev->dev_private; 4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4598 int palreg = PALETTE(intel_crtc->pipe); 4599 int i; 4600 4601 /* The clocks have to be on to load the palette. */ 4602 if (!crtc->enabled || !intel_crtc->active) 4603 return; 4604 4605 /* use legacy palette for Ironlake */ 4606 if (HAS_PCH_SPLIT(dev)) 4607 palreg = LGC_PALETTE(intel_crtc->pipe); 4608 4609 for (i = 0; i < 256; i++) { 4610 I915_WRITE(palreg + 4 * i, 4611 (intel_crtc->lut_r[i] << 16) | 4612 (intel_crtc->lut_g[i] << 8) | 4613 intel_crtc->lut_b[i]); 4614 } 4615 } 4616 4617 static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 4618 { 4619 struct drm_device *dev = crtc->dev; 4620 struct drm_i915_private *dev_priv = dev->dev_private; 4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4622 bool visible = base != 0; 4623 u32 cntl; 4624 4625 if (intel_crtc->cursor_visible == visible) 4626 return; 4627 4628 cntl = I915_READ(_CURACNTR); 4629 if (visible) { 4630 /* On these chipsets we can only modify the base whilst 4631 * the cursor is disabled. 4632 */ 4633 I915_WRITE(_CURABASE, base); 4634 4635 cntl &= ~(CURSOR_FORMAT_MASK); 4636 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 4637 cntl |= CURSOR_ENABLE | 4638 CURSOR_GAMMA_ENABLE | 4639 CURSOR_FORMAT_ARGB; 4640 } else 4641 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 4642 I915_WRITE(_CURACNTR, cntl); 4643 4644 intel_crtc->cursor_visible = visible; 4645 } 4646 4647 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 4648 { 4649 struct drm_device *dev = crtc->dev; 4650 struct drm_i915_private *dev_priv = dev->dev_private; 4651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4652 int pipe = intel_crtc->pipe; 4653 bool visible = base != 0; 4654 4655 if (intel_crtc->cursor_visible != visible) { 4656 uint32_t cntl = I915_READ(CURCNTR(pipe)); 4657 if (base) { 4658 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 4659 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4660 cntl |= pipe << 28; /* Connect to correct pipe */ 4661 } else { 4662 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4663 cntl |= CURSOR_MODE_DISABLE; 4664 } 4665 I915_WRITE(CURCNTR(pipe), cntl); 4666 4667 intel_crtc->cursor_visible = visible; 4668 } 4669 /* and commit changes on next vblank */ 4670 I915_WRITE(CURBASE(pipe), base); 4671 } 4672 4673 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 4674 { 4675 struct drm_device *dev = crtc->dev; 4676 struct drm_i915_private *dev_priv = dev->dev_private; 4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4678 int pipe = intel_crtc->pipe; 4679 bool visible = base != 0; 4680 4681 if (intel_crtc->cursor_visible != visible) { 4682 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); 4683 if (base) { 4684 cntl &= ~CURSOR_MODE; 4685 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 4686 } else { 4687 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 4688 cntl |= CURSOR_MODE_DISABLE; 4689 } 4690 I915_WRITE(CURCNTR_IVB(pipe), cntl); 4691 4692 intel_crtc->cursor_visible = visible; 4693 } 4694 /* and commit changes on next vblank */ 4695 I915_WRITE(CURBASE_IVB(pipe), base); 4696 } 4697 4698 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 4699 static void intel_crtc_update_cursor(struct drm_crtc *crtc, 4700 bool on) 4701 { 4702 struct drm_device *dev = crtc->dev; 4703 struct drm_i915_private *dev_priv = dev->dev_private; 4704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4705 int pipe = intel_crtc->pipe; 4706 int x = intel_crtc->cursor_x; 4707 int y = intel_crtc->cursor_y; 4708 u32 base, pos; 4709 bool visible; 4710 4711 pos = 0; 4712 4713 if (on && crtc->enabled && crtc->fb) { 4714 base = intel_crtc->cursor_addr; 4715 if (x > (int) crtc->fb->width) 4716 base = 0; 4717 4718 if (y > (int) crtc->fb->height) 4719 base = 0; 4720 } else 4721 base = 0; 4722 4723 if (x < 0) { 4724 if (x + intel_crtc->cursor_width < 0) 4725 base = 0; 4726 4727 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 4728 x = -x; 4729 } 4730 pos |= x << CURSOR_X_SHIFT; 4731 4732 if (y < 0) { 4733 if (y + intel_crtc->cursor_height < 0) 4734 base = 0; 4735 4736 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 4737 y = -y; 4738 } 4739 pos |= y << CURSOR_Y_SHIFT; 4740 4741 visible = base != 0; 4742 if (!visible && !intel_crtc->cursor_visible) 4743 return; 4744 4745 if (IS_IVYBRIDGE(dev)) { 4746 I915_WRITE(CURPOS_IVB(pipe), pos); 4747 ivb_update_cursor(crtc, base); 4748 } else { 4749 I915_WRITE(CURPOS(pipe), pos); 4750 if (IS_845G(dev) || IS_I865G(dev)) 4751 i845_update_cursor(crtc, base); 4752 else 4753 i9xx_update_cursor(crtc, base); 4754 } 4755 } 4756 4757 static int intel_crtc_cursor_set(struct drm_crtc *crtc, 4758 struct drm_file *file, 4759 uint32_t handle, 4760 uint32_t width, uint32_t height) 4761 { 4762 struct drm_device *dev = crtc->dev; 4763 struct drm_i915_private *dev_priv = dev->dev_private; 4764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4765 struct drm_i915_gem_object *obj; 4766 uint32_t addr; 4767 int ret; 4768 4769 DRM_DEBUG_KMS("\n"); 4770 4771 /* if we want to turn off the cursor ignore width and height */ 4772 if (!handle) { 4773 DRM_DEBUG_KMS("cursor off\n"); 4774 addr = 0; 4775 obj = NULL; 4776 DRM_LOCK(dev); 4777 goto finish; 4778 } 4779 4780 /* Currently we only support 64x64 cursors */ 4781 if (width != 64 || height != 64) { 4782 DRM_ERROR("we currently only support 64x64 cursors\n"); 4783 return -EINVAL; 4784 } 4785 4786 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); 4787 if (&obj->base == NULL) 4788 return -ENOENT; 4789 4790 if (obj->base.size < width * height * 4) { 4791 DRM_ERROR("buffer is to small\n"); 4792 ret = -ENOMEM; 4793 goto fail; 4794 } 4795 4796 /* we only need to pin inside GTT if cursor is non-phy */ 4797 DRM_LOCK(dev); 4798 if (!dev_priv->info->cursor_needs_physical) { 4799 if (obj->tiling_mode) { 4800 DRM_ERROR("cursor cannot be tiled\n"); 4801 ret = -EINVAL; 4802 goto fail_locked; 4803 } 4804 4805 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); 4806 if (ret) { 4807 DRM_ERROR("failed to move cursor bo into the GTT\n"); 4808 goto fail_locked; 4809 } 4810 4811 ret = i915_gem_object_put_fence(obj); 4812 if (ret) { 4813 DRM_ERROR("failed to release fence for cursor\n"); 4814 goto fail_unpin; 4815 } 4816 4817 addr = obj->gtt_offset; 4818 } else { 4819 int align = IS_I830(dev) ? 16 * 1024 : 256; 4820 ret = i915_gem_attach_phys_object(dev, obj, 4821 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, 4822 align); 4823 if (ret) { 4824 DRM_ERROR("failed to attach phys object\n"); 4825 goto fail_locked; 4826 } 4827 addr = obj->phys_obj->handle->busaddr; 4828 } 4829 4830 if (IS_GEN2(dev)) 4831 I915_WRITE(CURSIZE, (height << 12) | width); 4832 4833 finish: 4834 if (intel_crtc->cursor_bo) { 4835 if (dev_priv->info->cursor_needs_physical) { 4836 if (intel_crtc->cursor_bo != obj) 4837 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 4838 } else 4839 i915_gem_object_unpin(intel_crtc->cursor_bo); 4840 drm_gem_object_unreference(&intel_crtc->cursor_bo->base); 4841 } 4842 4843 DRM_UNLOCK(dev); 4844 4845 intel_crtc->cursor_addr = addr; 4846 intel_crtc->cursor_bo = obj; 4847 intel_crtc->cursor_width = width; 4848 intel_crtc->cursor_height = height; 4849 4850 intel_crtc_update_cursor(crtc, true); 4851 4852 return 0; 4853 fail_unpin: 4854 i915_gem_object_unpin(obj); 4855 fail_locked: 4856 DRM_UNLOCK(dev); 4857 fail: 4858 drm_gem_object_unreference_unlocked(&obj->base); 4859 return ret; 4860 } 4861 4862 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 4863 { 4864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4865 4866 intel_crtc->cursor_x = x; 4867 intel_crtc->cursor_y = y; 4868 4869 intel_crtc_update_cursor(crtc, true); 4870 4871 return 0; 4872 } 4873 4874 /** Sets the color ramps on behalf of RandR */ 4875 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 4876 u16 blue, int regno) 4877 { 4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4879 4880 intel_crtc->lut_r[regno] = red >> 8; 4881 intel_crtc->lut_g[regno] = green >> 8; 4882 intel_crtc->lut_b[regno] = blue >> 8; 4883 } 4884 4885 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 4886 u16 *blue, int regno) 4887 { 4888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4889 4890 *red = intel_crtc->lut_r[regno] << 8; 4891 *green = intel_crtc->lut_g[regno] << 8; 4892 *blue = intel_crtc->lut_b[regno] << 8; 4893 } 4894 4895 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 4896 u16 *blue, uint32_t start, uint32_t size) 4897 { 4898 int end = (start + size > 256) ? 256 : start + size, i; 4899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4900 4901 for (i = start; i < end; i++) { 4902 intel_crtc->lut_r[i] = red[i] >> 8; 4903 intel_crtc->lut_g[i] = green[i] >> 8; 4904 intel_crtc->lut_b[i] = blue[i] >> 8; 4905 } 4906 4907 intel_crtc_load_lut(crtc); 4908 } 4909 4910 /** 4911 * Get a pipe with a simple mode set on it for doing load-based monitor 4912 * detection. 4913 * 4914 * It will be up to the load-detect code to adjust the pipe as appropriate for 4915 * its requirements. The pipe will be connected to no other encoders. 4916 * 4917 * Currently this code will only succeed if there is a pipe with no encoders 4918 * configured for it. In the future, it could choose to temporarily disable 4919 * some outputs to free up a pipe for its use. 4920 * 4921 * \return crtc, or NULL if no pipes are available. 4922 */ 4923 4924 /* VESA 640x480x72Hz mode to set on the pipe */ 4925 static struct drm_display_mode load_detect_mode = { 4926 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 4927 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 4928 }; 4929 4930 static struct drm_framebuffer * 4931 intel_framebuffer_create(struct drm_device *dev, 4932 struct drm_mode_fb_cmd2 *mode_cmd, 4933 struct drm_i915_gem_object *obj) 4934 { 4935 struct intel_framebuffer *intel_fb; 4936 int ret; 4937 4938 intel_fb = kmalloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO); 4939 if (!intel_fb) { 4940 drm_gem_object_unreference_unlocked(&obj->base); 4941 return ERR_PTR(-ENOMEM); 4942 } 4943 4944 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 4945 if (ret) { 4946 drm_gem_object_unreference_unlocked(&obj->base); 4947 kfree(intel_fb, DRM_MEM_KMS); 4948 return ERR_PTR(ret); 4949 } 4950 4951 return &intel_fb->base; 4952 } 4953 4954 static u32 4955 intel_framebuffer_pitch_for_width(int width, int bpp) 4956 { 4957 u32 pitch = howmany(width * bpp, 8); 4958 return roundup2(pitch, 64); 4959 } 4960 4961 static u32 4962 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 4963 { 4964 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 4965 return roundup2(pitch * mode->vdisplay, PAGE_SIZE); 4966 } 4967 4968 static struct drm_framebuffer * 4969 intel_framebuffer_create_for_mode(struct drm_device *dev, 4970 struct drm_display_mode *mode, 4971 int depth, int bpp) 4972 { 4973 struct drm_i915_gem_object *obj; 4974 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 4975 4976 obj = i915_gem_alloc_object(dev, 4977 intel_framebuffer_size_for_mode(mode, bpp)); 4978 if (obj == NULL) 4979 return ERR_PTR(-ENOMEM); 4980 4981 mode_cmd.width = mode->hdisplay; 4982 mode_cmd.height = mode->vdisplay; 4983 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, 4984 bpp); 4985 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); 4986 4987 return intel_framebuffer_create(dev, &mode_cmd, obj); 4988 } 4989 4990 static int 4991 mode_fits_in_fbdev(struct drm_device *dev, 4992 struct drm_display_mode *mode, struct drm_framebuffer **res) 4993 { 4994 struct drm_i915_private *dev_priv = dev->dev_private; 4995 struct drm_i915_gem_object *obj; 4996 struct drm_framebuffer *fb; 4997 4998 if (dev_priv->fbdev == NULL) { 4999 *res = NULL; 5000 return (0); 5001 } 5002 5003 obj = dev_priv->fbdev->ifb.obj; 5004 if (obj == NULL) { 5005 *res = NULL; 5006 return (0); 5007 } 5008 5009 fb = &dev_priv->fbdev->ifb.base; 5010 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 5011 fb->bits_per_pixel)) { 5012 *res = NULL; 5013 return (0); 5014 } 5015 5016 if (obj->base.size < mode->vdisplay * fb->pitches[0]) { 5017 *res = NULL; 5018 return (0); 5019 } 5020 5021 *res = fb; 5022 return (0); 5023 } 5024 5025 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 5026 struct drm_connector *connector, 5027 struct drm_display_mode *mode, 5028 struct intel_load_detect_pipe *old) 5029 { 5030 struct intel_crtc *intel_crtc; 5031 struct drm_crtc *possible_crtc; 5032 struct drm_encoder *encoder = &intel_encoder->base; 5033 struct drm_crtc *crtc = NULL; 5034 struct drm_device *dev = encoder->dev; 5035 struct drm_framebuffer *old_fb; 5036 int i = -1, r; 5037 5038 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 5039 connector->base.id, drm_get_connector_name(connector), 5040 encoder->base.id, drm_get_encoder_name(encoder)); 5041 5042 /* 5043 * Algorithm gets a little messy: 5044 * 5045 * - if the connector already has an assigned crtc, use it (but make 5046 * sure it's on first) 5047 * 5048 * - try to find the first unused crtc that can drive this connector, 5049 * and use that if we find one 5050 */ 5051 5052 /* See if we already have a CRTC for this connector */ 5053 if (encoder->crtc) { 5054 crtc = encoder->crtc; 5055 5056 intel_crtc = to_intel_crtc(crtc); 5057 old->dpms_mode = intel_crtc->dpms_mode; 5058 old->load_detect_temp = false; 5059 5060 /* Make sure the crtc and connector are running */ 5061 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { 5062 struct drm_encoder_helper_funcs *encoder_funcs; 5063 struct drm_crtc_helper_funcs *crtc_funcs; 5064 5065 crtc_funcs = crtc->helper_private; 5066 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 5067 5068 encoder_funcs = encoder->helper_private; 5069 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 5070 } 5071 5072 return true; 5073 } 5074 5075 /* Find an unused one (if possible) */ 5076 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { 5077 i++; 5078 if (!(encoder->possible_crtcs & (1 << i))) 5079 continue; 5080 if (!possible_crtc->enabled) { 5081 crtc = possible_crtc; 5082 break; 5083 } 5084 } 5085 5086 /* 5087 * If we didn't find an unused CRTC, don't use any. 5088 */ 5089 if (!crtc) { 5090 DRM_DEBUG_KMS("no pipe available for load-detect\n"); 5091 return false; 5092 } 5093 5094 encoder->crtc = crtc; 5095 connector->encoder = encoder; 5096 5097 intel_crtc = to_intel_crtc(crtc); 5098 old->dpms_mode = intel_crtc->dpms_mode; 5099 old->load_detect_temp = true; 5100 old->release_fb = NULL; 5101 5102 if (!mode) 5103 mode = &load_detect_mode; 5104 5105 old_fb = crtc->fb; 5106 5107 /* We need a framebuffer large enough to accommodate all accesses 5108 * that the plane may generate whilst we perform load detection. 5109 * We can not rely on the fbcon either being present (we get called 5110 * during its initialisation to detect all boot displays, or it may 5111 * not even exist) or that it is large enough to satisfy the 5112 * requested mode. 5113 */ 5114 r = mode_fits_in_fbdev(dev, mode, &crtc->fb); 5115 if (crtc->fb == NULL) { 5116 DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); 5117 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); 5118 old->release_fb = crtc->fb; 5119 } else 5120 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); 5121 if (IS_ERR(crtc->fb)) { 5122 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); 5123 return false; 5124 } 5125 5126 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { 5127 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); 5128 if (old->release_fb) 5129 old->release_fb->funcs->destroy(old->release_fb); 5130 crtc->fb = old_fb; 5131 return false; 5132 } 5133 5134 /* let the connector get through one full cycle before testing */ 5135 intel_wait_for_vblank(dev, intel_crtc->pipe); 5136 5137 return true; 5138 } 5139 5140 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, 5141 struct drm_connector *connector, 5142 struct intel_load_detect_pipe *old) 5143 { 5144 struct drm_encoder *encoder = &intel_encoder->base; 5145 struct drm_device *dev = encoder->dev; 5146 struct drm_crtc *crtc = encoder->crtc; 5147 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 5148 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 5149 5150 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 5151 connector->base.id, drm_get_connector_name(connector), 5152 encoder->base.id, drm_get_encoder_name(encoder)); 5153 5154 if (old->load_detect_temp) { 5155 connector->encoder = NULL; 5156 drm_helper_disable_unused_functions(dev); 5157 5158 if (old->release_fb) 5159 old->release_fb->funcs->destroy(old->release_fb); 5160 5161 return; 5162 } 5163 5164 /* Switch crtc and encoder back off if necessary */ 5165 if (old->dpms_mode != DRM_MODE_DPMS_ON) { 5166 encoder_funcs->dpms(encoder, old->dpms_mode); 5167 crtc_funcs->dpms(crtc, old->dpms_mode); 5168 } 5169 } 5170 5171 /* Returns the clock of the currently programmed mode of the given pipe. */ 5172 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) 5173 { 5174 struct drm_i915_private *dev_priv = dev->dev_private; 5175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5176 int pipe = intel_crtc->pipe; 5177 u32 dpll = I915_READ(DPLL(pipe)); 5178 u32 fp; 5179 intel_clock_t clock; 5180 5181 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 5182 fp = I915_READ(FP0(pipe)); 5183 else 5184 fp = I915_READ(FP1(pipe)); 5185 5186 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 5187 if (IS_PINEVIEW(dev)) { 5188 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 5189 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 5190 } else { 5191 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 5192 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 5193 } 5194 5195 if (!IS_GEN2(dev)) { 5196 if (IS_PINEVIEW(dev)) 5197 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 5198 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 5199 else 5200 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 5201 DPLL_FPA01_P1_POST_DIV_SHIFT); 5202 5203 switch (dpll & DPLL_MODE_MASK) { 5204 case DPLLB_MODE_DAC_SERIAL: 5205 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5206 5 : 10; 5207 break; 5208 case DPLLB_MODE_LVDS: 5209 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 5210 7 : 14; 5211 break; 5212 default: 5213 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " 5214 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 5215 return 0; 5216 } 5217 5218 /* XXX: Handle the 100Mhz refclk */ 5219 intel_clock(dev, 96000, &clock); 5220 } else { 5221 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 5222 5223 if (is_lvds) { 5224 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 5225 DPLL_FPA01_P1_POST_DIV_SHIFT); 5226 clock.p2 = 14; 5227 5228 if ((dpll & PLL_REF_INPUT_MASK) == 5229 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 5230 /* XXX: might not be 66MHz */ 5231 intel_clock(dev, 66000, &clock); 5232 } else 5233 intel_clock(dev, 48000, &clock); 5234 } else { 5235 if (dpll & PLL_P1_DIVIDE_BY_TWO) 5236 clock.p1 = 2; 5237 else { 5238 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 5239 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 5240 } 5241 if (dpll & PLL_P2_DIVIDE_BY_4) 5242 clock.p2 = 4; 5243 else 5244 clock.p2 = 2; 5245 5246 intel_clock(dev, 48000, &clock); 5247 } 5248 } 5249 5250 /* XXX: It would be nice to validate the clocks, but we can't reuse 5251 * i830PllIsValid() because it relies on the xf86_config connector 5252 * configuration being accurate, which it isn't necessarily. 5253 */ 5254 5255 return clock.dot; 5256 } 5257 5258 /** Returns the currently programmed mode of the given pipe. */ 5259 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 5260 struct drm_crtc *crtc) 5261 { 5262 struct drm_i915_private *dev_priv = dev->dev_private; 5263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5264 int pipe = intel_crtc->pipe; 5265 struct drm_display_mode *mode; 5266 int htot = I915_READ(HTOTAL(pipe)); 5267 int hsync = I915_READ(HSYNC(pipe)); 5268 int vtot = I915_READ(VTOTAL(pipe)); 5269 int vsync = I915_READ(VSYNC(pipe)); 5270 5271 mode = kmalloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO); 5272 5273 mode->clock = intel_crtc_clock_get(dev, crtc); 5274 mode->hdisplay = (htot & 0xffff) + 1; 5275 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 5276 mode->hsync_start = (hsync & 0xffff) + 1; 5277 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 5278 mode->vdisplay = (vtot & 0xffff) + 1; 5279 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 5280 mode->vsync_start = (vsync & 0xffff) + 1; 5281 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 5282 5283 drm_mode_set_name(mode); 5284 drm_mode_set_crtcinfo(mode, 0); 5285 5286 return mode; 5287 } 5288 5289 static void intel_increase_pllclock(struct drm_crtc *crtc) 5290 { 5291 struct drm_device *dev = crtc->dev; 5292 drm_i915_private_t *dev_priv = dev->dev_private; 5293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5294 int pipe = intel_crtc->pipe; 5295 int dpll_reg = DPLL(pipe); 5296 int dpll; 5297 5298 if (HAS_PCH_SPLIT(dev)) 5299 return; 5300 5301 if (!dev_priv->lvds_downclock_avail) 5302 return; 5303 5304 dpll = I915_READ(dpll_reg); 5305 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 5306 DRM_DEBUG_DRIVER("upclocking LVDS\n"); 5307 5308 assert_panel_unlocked(dev_priv, pipe); 5309 5310 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 5311 I915_WRITE(dpll_reg, dpll); 5312 intel_wait_for_vblank(dev, pipe); 5313 5314 dpll = I915_READ(dpll_reg); 5315 if (dpll & DISPLAY_RATE_SELECT_FPA1) 5316 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 5317 } 5318 } 5319 5320 static void intel_decrease_pllclock(struct drm_crtc *crtc) 5321 { 5322 struct drm_device *dev = crtc->dev; 5323 drm_i915_private_t *dev_priv = dev->dev_private; 5324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5325 5326 if (HAS_PCH_SPLIT(dev)) 5327 return; 5328 5329 if (!dev_priv->lvds_downclock_avail) 5330 return; 5331 5332 /* 5333 * Since this is called by a timer, we should never get here in 5334 * the manual case. 5335 */ 5336 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 5337 int pipe = intel_crtc->pipe; 5338 int dpll_reg = DPLL(pipe); 5339 u32 dpll; 5340 5341 DRM_DEBUG_DRIVER("downclocking LVDS\n"); 5342 5343 assert_panel_unlocked(dev_priv, pipe); 5344 5345 dpll = I915_READ(dpll_reg); 5346 dpll |= DISPLAY_RATE_SELECT_FPA1; 5347 I915_WRITE(dpll_reg, dpll); 5348 intel_wait_for_vblank(dev, pipe); 5349 dpll = I915_READ(dpll_reg); 5350 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 5351 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 5352 } 5353 } 5354 5355 void intel_mark_busy(struct drm_device *dev) 5356 { 5357 i915_update_gfx_val(dev->dev_private); 5358 } 5359 5360 void intel_mark_idle(struct drm_device *dev) 5361 { 5362 struct drm_crtc *crtc; 5363 5364 if (!i915_powersave) 5365 return; 5366 5367 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5368 if (!crtc->fb) 5369 continue; 5370 5371 intel_decrease_pllclock(crtc); 5372 } 5373 } 5374 5375 static void intel_crtc_destroy(struct drm_crtc *crtc) 5376 { 5377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5378 struct drm_device *dev = crtc->dev; 5379 struct intel_unpin_work *work; 5380 5381 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5382 work = intel_crtc->unpin_work; 5383 intel_crtc->unpin_work = NULL; 5384 lockmgr(&dev->event_lock, LK_RELEASE); 5385 5386 if (work) { 5387 cancel_work_sync(&work->work); 5388 kfree(work, DRM_MEM_KMS); 5389 } 5390 5391 drm_crtc_cleanup(crtc); 5392 5393 drm_free(intel_crtc, DRM_MEM_KMS); 5394 } 5395 5396 static void intel_unpin_work_fn(struct work_struct *__work) 5397 { 5398 struct intel_unpin_work *work = 5399 container_of(__work, struct intel_unpin_work, work); 5400 struct drm_device *dev; 5401 5402 dev = work->dev; 5403 DRM_LOCK(dev); 5404 intel_unpin_fb_obj(work->old_fb_obj); 5405 drm_gem_object_unreference(&work->pending_flip_obj->base); 5406 drm_gem_object_unreference(&work->old_fb_obj->base); 5407 5408 intel_update_fbc(work->dev); 5409 DRM_UNLOCK(dev); 5410 drm_free(work, DRM_MEM_KMS); 5411 } 5412 5413 static void do_intel_finish_page_flip(struct drm_device *dev, 5414 struct drm_crtc *crtc) 5415 { 5416 drm_i915_private_t *dev_priv = dev->dev_private; 5417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5418 struct intel_unpin_work *work; 5419 struct drm_i915_gem_object *obj; 5420 5421 /* Ignore early vblank irqs */ 5422 if (intel_crtc == NULL) 5423 return; 5424 5425 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5426 work = intel_crtc->unpin_work; 5427 5428 /* Ensure we don't miss a work->pending update ... */ 5429 cpu_lfence(); 5430 5431 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 5432 lockmgr(&dev->event_lock, LK_RELEASE); 5433 return; 5434 } 5435 5436 /* and that the unpin work is consistent wrt ->pending. */ 5437 cpu_lfence(); 5438 5439 intel_crtc->unpin_work = NULL; 5440 5441 if (work->event) 5442 drm_send_vblank_event(dev, intel_crtc->pipe, work->event); 5443 5444 drm_vblank_put(dev, intel_crtc->pipe); 5445 5446 lockmgr(&dev->event_lock, LK_RELEASE); 5447 5448 obj = work->old_fb_obj; 5449 5450 atomic_clear_mask(1 << intel_crtc->plane, 5451 &obj->pending_flip.counter); 5452 wake_up(&dev_priv->pending_flip_queue); 5453 5454 queue_work(dev_priv->wq, &work->work); 5455 } 5456 5457 void intel_finish_page_flip(struct drm_device *dev, int pipe) 5458 { 5459 drm_i915_private_t *dev_priv = dev->dev_private; 5460 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 5461 5462 do_intel_finish_page_flip(dev, crtc); 5463 } 5464 5465 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) 5466 { 5467 drm_i915_private_t *dev_priv = dev->dev_private; 5468 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; 5469 5470 do_intel_finish_page_flip(dev, crtc); 5471 } 5472 5473 void intel_prepare_page_flip(struct drm_device *dev, int plane) 5474 { 5475 drm_i915_private_t *dev_priv = dev->dev_private; 5476 struct intel_crtc *intel_crtc = 5477 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); 5478 5479 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5480 if (intel_crtc->unpin_work) 5481 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); 5482 lockmgr(&dev->event_lock, LK_RELEASE); 5483 } 5484 5485 static int intel_gen2_queue_flip(struct drm_device *dev, 5486 struct drm_crtc *crtc, 5487 struct drm_framebuffer *fb, 5488 struct drm_i915_gem_object *obj) 5489 { 5490 struct drm_i915_private *dev_priv = dev->dev_private; 5491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5492 unsigned long offset; 5493 u32 flip_mask; 5494 int ret; 5495 5496 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5497 if (ret) 5498 goto out; 5499 5500 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5501 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 5502 5503 ret = BEGIN_LP_RING(6); 5504 if (ret) 5505 goto out; 5506 5507 /* Can't queue multiple flips, so wait for the previous 5508 * one to finish before executing the next. 5509 */ 5510 if (intel_crtc->plane) 5511 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5512 else 5513 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 5514 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5515 OUT_RING(MI_NOOP); 5516 OUT_RING(MI_DISPLAY_FLIP | 5517 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5518 OUT_RING(fb->pitches[0]); 5519 OUT_RING(obj->gtt_offset + offset); 5520 OUT_RING(0); /* aux display base address, unused */ 5521 ADVANCE_LP_RING(); 5522 out: 5523 return ret; 5524 } 5525 5526 static int intel_gen3_queue_flip(struct drm_device *dev, 5527 struct drm_crtc *crtc, 5528 struct drm_framebuffer *fb, 5529 struct drm_i915_gem_object *obj) 5530 { 5531 struct drm_i915_private *dev_priv = dev->dev_private; 5532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5533 unsigned long offset; 5534 u32 flip_mask; 5535 int ret; 5536 5537 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5538 if (ret) 5539 goto out; 5540 5541 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5542 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; 5543 5544 ret = BEGIN_LP_RING(6); 5545 if (ret) 5546 goto out; 5547 5548 if (intel_crtc->plane) 5549 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 5550 else 5551 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 5552 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); 5553 OUT_RING(MI_NOOP); 5554 OUT_RING(MI_DISPLAY_FLIP_I915 | 5555 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5556 OUT_RING(fb->pitches[0]); 5557 OUT_RING(obj->gtt_offset + offset); 5558 OUT_RING(MI_NOOP); 5559 5560 ADVANCE_LP_RING(); 5561 out: 5562 return ret; 5563 } 5564 5565 static int intel_gen4_queue_flip(struct drm_device *dev, 5566 struct drm_crtc *crtc, 5567 struct drm_framebuffer *fb, 5568 struct drm_i915_gem_object *obj) 5569 { 5570 struct drm_i915_private *dev_priv = dev->dev_private; 5571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5572 uint32_t pf, pipesrc; 5573 int ret; 5574 5575 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5576 if (ret) 5577 goto out; 5578 5579 ret = BEGIN_LP_RING(4); 5580 if (ret) 5581 goto out; 5582 5583 /* i965+ uses the linear or tiled offsets from the 5584 * Display Registers (which do not change across a page-flip) 5585 * so we need only reprogram the base address. 5586 */ 5587 OUT_RING(MI_DISPLAY_FLIP | 5588 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5589 OUT_RING(fb->pitches[0]); 5590 OUT_RING(obj->gtt_offset | obj->tiling_mode); 5591 5592 /* XXX Enabling the panel-fitter across page-flip is so far 5593 * untested on non-native modes, so ignore it for now. 5594 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 5595 */ 5596 pf = 0; 5597 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 5598 OUT_RING(pf | pipesrc); 5599 ADVANCE_LP_RING(); 5600 out: 5601 return ret; 5602 } 5603 5604 static int intel_gen6_queue_flip(struct drm_device *dev, 5605 struct drm_crtc *crtc, 5606 struct drm_framebuffer *fb, 5607 struct drm_i915_gem_object *obj) 5608 { 5609 struct drm_i915_private *dev_priv = dev->dev_private; 5610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5611 uint32_t pf, pipesrc; 5612 int ret; 5613 5614 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); 5615 if (ret) 5616 goto out; 5617 5618 ret = BEGIN_LP_RING(4); 5619 if (ret) 5620 goto out; 5621 5622 OUT_RING(MI_DISPLAY_FLIP | 5623 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5624 OUT_RING(fb->pitches[0] | obj->tiling_mode); 5625 OUT_RING(obj->gtt_offset); 5626 5627 /* Contrary to the suggestions in the documentation, 5628 * "Enable Panel Fitter" does not seem to be required when page 5629 * flipping with a non-native mode, and worse causes a normal 5630 * modeset to fail. 5631 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 5632 */ 5633 pf = 0; 5634 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 5635 OUT_RING(pf | pipesrc); 5636 ADVANCE_LP_RING(); 5637 out: 5638 return ret; 5639 } 5640 5641 /* 5642 * On gen7 we currently use the blit ring because (in early silicon at least) 5643 * the render ring doesn't give us interrpts for page flip completion, which 5644 * means clients will hang after the first flip is queued. Fortunately the 5645 * blit ring generates interrupts properly, so use it instead. 5646 */ 5647 static int intel_gen7_queue_flip(struct drm_device *dev, 5648 struct drm_crtc *crtc, 5649 struct drm_framebuffer *fb, 5650 struct drm_i915_gem_object *obj) 5651 { 5652 struct drm_i915_private *dev_priv = dev->dev_private; 5653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5654 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 5655 int ret; 5656 5657 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 5658 if (ret) 5659 goto out; 5660 5661 ret = intel_ring_begin(ring, 4); 5662 if (ret) 5663 goto out; 5664 5665 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); 5666 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 5667 intel_ring_emit(ring, (obj->gtt_offset)); 5668 intel_ring_emit(ring, (MI_NOOP)); 5669 intel_ring_advance(ring); 5670 out: 5671 return ret; 5672 } 5673 5674 static int intel_default_queue_flip(struct drm_device *dev, 5675 struct drm_crtc *crtc, 5676 struct drm_framebuffer *fb, 5677 struct drm_i915_gem_object *obj) 5678 { 5679 return -ENODEV; 5680 } 5681 5682 static int intel_crtc_page_flip(struct drm_crtc *crtc, 5683 struct drm_framebuffer *fb, 5684 struct drm_pending_vblank_event *event) 5685 { 5686 struct drm_device *dev = crtc->dev; 5687 struct drm_i915_private *dev_priv = dev->dev_private; 5688 struct intel_framebuffer *intel_fb; 5689 struct drm_i915_gem_object *obj; 5690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5691 struct intel_unpin_work *work; 5692 int ret; 5693 5694 work = kmalloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO); 5695 5696 work->event = event; 5697 work->dev = crtc->dev; 5698 intel_fb = to_intel_framebuffer(crtc->fb); 5699 work->old_fb_obj = intel_fb->obj; 5700 INIT_WORK(&work->work, intel_unpin_work_fn); 5701 5702 ret = drm_vblank_get(dev, intel_crtc->pipe); 5703 if (ret) 5704 goto free_work; 5705 5706 /* We borrow the event spin lock for protecting unpin_work */ 5707 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5708 if (intel_crtc->unpin_work) { 5709 lockmgr(&dev->event_lock, LK_RELEASE); 5710 drm_free(work, DRM_MEM_KMS); 5711 drm_vblank_put(dev, intel_crtc->pipe); 5712 5713 DRM_DEBUG("flip queue: crtc already busy\n"); 5714 return -EBUSY; 5715 } 5716 intel_crtc->unpin_work = work; 5717 lockmgr(&dev->event_lock, LK_RELEASE); 5718 5719 intel_fb = to_intel_framebuffer(fb); 5720 obj = intel_fb->obj; 5721 5722 DRM_LOCK(dev); 5723 5724 /* Reference the objects for the scheduled work. */ 5725 drm_gem_object_reference(&work->old_fb_obj->base); 5726 drm_gem_object_reference(&obj->base); 5727 5728 crtc->fb = fb; 5729 5730 work->pending_flip_obj = obj; 5731 5732 work->enable_stall_check = true; 5733 5734 /* Block clients from rendering to the new back buffer until 5735 * the flip occurs and the object is no longer visible. 5736 */ 5737 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 5738 5739 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); 5740 if (ret) 5741 goto cleanup_pending; 5742 intel_disable_fbc(dev); 5743 DRM_UNLOCK(dev); 5744 5745 return 0; 5746 5747 cleanup_pending: 5748 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); 5749 drm_gem_object_unreference(&work->old_fb_obj->base); 5750 drm_gem_object_unreference(&obj->base); 5751 DRM_UNLOCK(dev); 5752 5753 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 5754 intel_crtc->unpin_work = NULL; 5755 lockmgr(&dev->event_lock, LK_RELEASE); 5756 5757 drm_vblank_put(dev, intel_crtc->pipe); 5758 free_work: 5759 drm_free(work, DRM_MEM_KMS); 5760 5761 return ret; 5762 } 5763 5764 static void intel_sanitize_modesetting(struct drm_device *dev, 5765 int pipe, int plane) 5766 { 5767 struct drm_i915_private *dev_priv = dev->dev_private; 5768 u32 reg, val; 5769 5770 /* Clear any frame start delays used for debugging left by the BIOS */ 5771 for_each_pipe(pipe) { 5772 reg = PIPECONF(pipe); 5773 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 5774 } 5775 5776 if (HAS_PCH_SPLIT(dev)) 5777 return; 5778 5779 /* Who knows what state these registers were left in by the BIOS or 5780 * grub? 5781 * 5782 * If we leave the registers in a conflicting state (e.g. with the 5783 * display plane reading from the other pipe than the one we intend 5784 * to use) then when we attempt to teardown the active mode, we will 5785 * not disable the pipes and planes in the correct order -- leaving 5786 * a plane reading from a disabled pipe and possibly leading to 5787 * undefined behaviour. 5788 */ 5789 5790 reg = DSPCNTR(plane); 5791 val = I915_READ(reg); 5792 5793 if ((val & DISPLAY_PLANE_ENABLE) == 0) 5794 return; 5795 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) 5796 return; 5797 5798 /* This display plane is active and attached to the other CPU pipe. */ 5799 pipe = !pipe; 5800 5801 /* Disable the plane and wait for it to stop reading from the pipe. */ 5802 intel_disable_plane(dev_priv, plane, pipe); 5803 intel_disable_pipe(dev_priv, pipe); 5804 } 5805 5806 static void intel_crtc_reset(struct drm_crtc *crtc) 5807 { 5808 struct drm_device *dev = crtc->dev; 5809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5810 5811 /* Reset flags back to the 'unknown' status so that they 5812 * will be correctly set on the initial modeset. 5813 */ 5814 intel_crtc->dpms_mode = -1; 5815 5816 /* We need to fix up any BIOS configuration that conflicts with 5817 * our expectations. 5818 */ 5819 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); 5820 } 5821 5822 static struct drm_crtc_helper_funcs intel_helper_funcs = { 5823 .dpms = intel_crtc_dpms, 5824 .mode_fixup = intel_crtc_mode_fixup, 5825 .mode_set = intel_crtc_mode_set, 5826 .mode_set_base = intel_pipe_set_base, 5827 .mode_set_base_atomic = intel_pipe_set_base_atomic, 5828 .load_lut = intel_crtc_load_lut, 5829 .disable = intel_crtc_disable, 5830 }; 5831 5832 static const struct drm_crtc_funcs intel_crtc_funcs = { 5833 .reset = intel_crtc_reset, 5834 .cursor_set = intel_crtc_cursor_set, 5835 .cursor_move = intel_crtc_cursor_move, 5836 .gamma_set = intel_crtc_gamma_set, 5837 .set_config = drm_crtc_helper_set_config, 5838 .destroy = intel_crtc_destroy, 5839 .page_flip = intel_crtc_page_flip, 5840 }; 5841 5842 static void intel_cpu_pll_init(struct drm_device *dev) 5843 { 5844 #if 0 5845 if (IS_HASWELL(dev)) 5846 intel_ddi_pll_init(dev); 5847 #endif 5848 } 5849 5850 static void intel_pch_pll_init(struct drm_device *dev) 5851 { 5852 drm_i915_private_t *dev_priv = dev->dev_private; 5853 int i; 5854 5855 if (dev_priv->num_pch_pll == 0) { 5856 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); 5857 return; 5858 } 5859 5860 for (i = 0; i < dev_priv->num_pch_pll; i++) { 5861 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); 5862 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); 5863 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); 5864 } 5865 } 5866 5867 static void intel_crtc_init(struct drm_device *dev, int pipe) 5868 { 5869 drm_i915_private_t *dev_priv = dev->dev_private; 5870 struct intel_crtc *intel_crtc; 5871 int i; 5872 5873 intel_crtc = kmalloc(sizeof(struct intel_crtc) + 5874 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 5875 DRM_MEM_KMS, M_WAITOK | M_ZERO); 5876 5877 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); 5878 5879 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); 5880 for (i = 0; i < 256; i++) { 5881 intel_crtc->lut_r[i] = i; 5882 intel_crtc->lut_g[i] = i; 5883 intel_crtc->lut_b[i] = i; 5884 } 5885 5886 /* Swap pipes & planes for FBC on pre-965 */ 5887 intel_crtc->pipe = pipe; 5888 intel_crtc->plane = pipe; 5889 intel_crtc->cpu_transcoder = pipe; 5890 if (IS_MOBILE(dev) && IS_GEN3(dev)) { 5891 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); 5892 intel_crtc->plane = !pipe; 5893 } 5894 5895 KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) && 5896 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL, 5897 ("plane_to_crtc is already initialized")); 5898 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 5899 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5900 5901 intel_crtc_reset(&intel_crtc->base); 5902 intel_crtc->active = true; /* force the pipe off on setup_init_config */ 5903 intel_crtc->bpp = 24; /* default for pre-Ironlake */ 5904 5905 if (HAS_PCH_SPLIT(dev)) { 5906 if (pipe == 2 && IS_IVYBRIDGE(dev)) 5907 intel_crtc->no_pll = true; 5908 intel_helper_funcs.prepare = ironlake_crtc_prepare; 5909 intel_helper_funcs.commit = ironlake_crtc_commit; 5910 } else { 5911 intel_helper_funcs.prepare = i9xx_crtc_prepare; 5912 intel_helper_funcs.commit = i9xx_crtc_commit; 5913 } 5914 5915 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 5916 5917 intel_crtc->busy = false; 5918 5919 callout_init_mp(&intel_crtc->idle_callout); 5920 } 5921 5922 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 5923 struct drm_file *file) 5924 { 5925 drm_i915_private_t *dev_priv = dev->dev_private; 5926 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 5927 struct drm_mode_object *drmmode_obj; 5928 struct intel_crtc *crtc; 5929 5930 if (!dev_priv) { 5931 DRM_ERROR("called with no initialization\n"); 5932 return -EINVAL; 5933 } 5934 5935 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 5936 DRM_MODE_OBJECT_CRTC); 5937 5938 if (!drmmode_obj) { 5939 DRM_ERROR("no such CRTC id\n"); 5940 return -EINVAL; 5941 } 5942 5943 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); 5944 pipe_from_crtc_id->pipe = crtc->pipe; 5945 5946 return 0; 5947 } 5948 5949 static int intel_encoder_clones(struct drm_device *dev, int type_mask) 5950 { 5951 struct intel_encoder *encoder; 5952 int index_mask = 0; 5953 int entry = 0; 5954 5955 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 5956 if (type_mask & encoder->clone_mask) 5957 index_mask |= (1 << entry); 5958 entry++; 5959 } 5960 5961 return index_mask; 5962 } 5963 5964 static bool has_edp_a(struct drm_device *dev) 5965 { 5966 struct drm_i915_private *dev_priv = dev->dev_private; 5967 5968 if (!IS_MOBILE(dev)) 5969 return false; 5970 5971 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 5972 return false; 5973 5974 if (IS_GEN5(dev) && 5975 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) 5976 return false; 5977 5978 return true; 5979 } 5980 5981 static void intel_setup_outputs(struct drm_device *dev) 5982 { 5983 struct drm_i915_private *dev_priv = dev->dev_private; 5984 struct intel_encoder *encoder; 5985 bool dpd_is_edp = false; 5986 bool has_lvds; 5987 5988 has_lvds = intel_lvds_init(dev); 5989 if (!has_lvds && !HAS_PCH_SPLIT(dev)) { 5990 /* disable the panel fitter on everything but LVDS */ 5991 I915_WRITE(PFIT_CONTROL, 0); 5992 } 5993 5994 if (HAS_PCH_SPLIT(dev)) { 5995 dpd_is_edp = intel_dpd_is_edp(dev); 5996 5997 if (has_edp_a(dev)) 5998 intel_dp_init(dev, DP_A); 5999 6000 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) 6001 intel_dp_init(dev, PCH_DP_D); 6002 } 6003 6004 intel_crt_init(dev); 6005 6006 if (HAS_PCH_SPLIT(dev)) { 6007 int found; 6008 6009 DRM_DEBUG_KMS( 6010 "HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n", 6011 (I915_READ(HDMIB) & PORT_DETECTED) != 0, 6012 (I915_READ(PCH_DP_B) & DP_DETECTED) != 0, 6013 (I915_READ(HDMIC) & PORT_DETECTED) != 0, 6014 (I915_READ(HDMID) & PORT_DETECTED) != 0, 6015 (I915_READ(PCH_DP_C) & DP_DETECTED) != 0, 6016 (I915_READ(PCH_DP_D) & DP_DETECTED) != 0, 6017 (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0); 6018 6019 if (I915_READ(HDMIB) & PORT_DETECTED) { 6020 /* PCH SDVOB multiplex with HDMIB */ 6021 found = intel_sdvo_init(dev, PCH_SDVOB); 6022 if (!found) 6023 intel_hdmi_init(dev, HDMIB); 6024 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 6025 intel_dp_init(dev, PCH_DP_B); 6026 } 6027 6028 if (I915_READ(HDMIC) & PORT_DETECTED) 6029 intel_hdmi_init(dev, HDMIC); 6030 6031 if (I915_READ(HDMID) & PORT_DETECTED) 6032 intel_hdmi_init(dev, HDMID); 6033 6034 if (I915_READ(PCH_DP_C) & DP_DETECTED) 6035 intel_dp_init(dev, PCH_DP_C); 6036 6037 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) 6038 intel_dp_init(dev, PCH_DP_D); 6039 6040 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { 6041 bool found = false; 6042 6043 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6044 DRM_DEBUG_KMS("probing SDVOB\n"); 6045 found = intel_sdvo_init(dev, SDVOB); 6046 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { 6047 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 6048 intel_hdmi_init(dev, SDVOB); 6049 } 6050 6051 if (!found && SUPPORTS_INTEGRATED_DP(dev)) { 6052 DRM_DEBUG_KMS("probing DP_B\n"); 6053 intel_dp_init(dev, DP_B); 6054 } 6055 } 6056 6057 /* Before G4X SDVOC doesn't have its own detect register */ 6058 6059 if (I915_READ(SDVOB) & SDVO_DETECTED) { 6060 DRM_DEBUG_KMS("probing SDVOC\n"); 6061 found = intel_sdvo_init(dev, SDVOC); 6062 } 6063 6064 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 6065 6066 if (SUPPORTS_INTEGRATED_HDMI(dev)) { 6067 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 6068 intel_hdmi_init(dev, SDVOC); 6069 } 6070 if (SUPPORTS_INTEGRATED_DP(dev)) { 6071 DRM_DEBUG_KMS("probing DP_C\n"); 6072 intel_dp_init(dev, DP_C); 6073 } 6074 } 6075 6076 if (SUPPORTS_INTEGRATED_DP(dev) && 6077 (I915_READ(DP_D) & DP_DETECTED)) { 6078 DRM_DEBUG_KMS("probing DP_D\n"); 6079 intel_dp_init(dev, DP_D); 6080 } 6081 } else if (IS_GEN2(dev)) { 6082 #if 1 6083 KIB_NOTYET(); 6084 #else 6085 intel_dvo_init(dev); 6086 #endif 6087 } 6088 6089 if (SUPPORTS_TV(dev)) 6090 intel_tv_init(dev); 6091 6092 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 6093 encoder->base.possible_crtcs = encoder->crtc_mask; 6094 encoder->base.possible_clones = 6095 intel_encoder_clones(dev, encoder->clone_mask); 6096 } 6097 6098 /* disable all the possible outputs/crtcs before entering KMS mode */ 6099 drm_helper_disable_unused_functions(dev); 6100 6101 if (HAS_PCH_SPLIT(dev)) 6102 ironlake_init_pch_refclk(dev); 6103 } 6104 6105 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 6106 { 6107 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 6108 6109 drm_framebuffer_cleanup(fb); 6110 drm_gem_object_unreference_unlocked(&intel_fb->obj->base); 6111 6112 drm_free(intel_fb, DRM_MEM_KMS); 6113 } 6114 6115 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 6116 struct drm_file *file, 6117 unsigned int *handle) 6118 { 6119 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 6120 struct drm_i915_gem_object *obj = intel_fb->obj; 6121 6122 return drm_gem_handle_create(file, &obj->base, handle); 6123 } 6124 6125 static const struct drm_framebuffer_funcs intel_fb_funcs = { 6126 .destroy = intel_user_framebuffer_destroy, 6127 .create_handle = intel_user_framebuffer_create_handle, 6128 }; 6129 6130 int intel_framebuffer_init(struct drm_device *dev, 6131 struct intel_framebuffer *intel_fb, 6132 struct drm_mode_fb_cmd2 *mode_cmd, 6133 struct drm_i915_gem_object *obj) 6134 { 6135 int ret; 6136 6137 if (obj->tiling_mode == I915_TILING_Y) 6138 return -EINVAL; 6139 6140 if (mode_cmd->pitches[0] & 63) 6141 return -EINVAL; 6142 6143 switch (mode_cmd->pixel_format) { 6144 case DRM_FORMAT_RGB332: 6145 case DRM_FORMAT_RGB565: 6146 case DRM_FORMAT_XRGB8888: 6147 case DRM_FORMAT_XBGR8888: 6148 case DRM_FORMAT_ARGB8888: 6149 case DRM_FORMAT_XRGB2101010: 6150 case DRM_FORMAT_ARGB2101010: 6151 /* RGB formats are common across chipsets */ 6152 break; 6153 case DRM_FORMAT_YUYV: 6154 case DRM_FORMAT_UYVY: 6155 case DRM_FORMAT_YVYU: 6156 case DRM_FORMAT_VYUY: 6157 break; 6158 default: 6159 DRM_DEBUG_KMS("unsupported pixel format %u\n", 6160 mode_cmd->pixel_format); 6161 return -EINVAL; 6162 } 6163 6164 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 6165 if (ret) { 6166 DRM_ERROR("framebuffer init failed %d\n", ret); 6167 return ret; 6168 } 6169 6170 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 6171 intel_fb->obj = obj; 6172 return 0; 6173 } 6174 6175 static struct drm_framebuffer * 6176 intel_user_framebuffer_create(struct drm_device *dev, 6177 struct drm_file *filp, 6178 struct drm_mode_fb_cmd2 *mode_cmd) 6179 { 6180 struct drm_i915_gem_object *obj; 6181 6182 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, 6183 mode_cmd->handles[0])); 6184 if (&obj->base == NULL) 6185 return ERR_PTR(-ENOENT); 6186 6187 return intel_framebuffer_create(dev, mode_cmd, obj); 6188 } 6189 6190 static const struct drm_mode_config_funcs intel_mode_funcs = { 6191 .fb_create = intel_user_framebuffer_create, 6192 .output_poll_changed = intel_fb_output_poll_changed, 6193 }; 6194 6195 /* Set up chip specific display functions */ 6196 static void intel_init_display(struct drm_device *dev) 6197 { 6198 struct drm_i915_private *dev_priv = dev->dev_private; 6199 6200 /* We always want a DPMS function */ 6201 if (HAS_PCH_SPLIT(dev)) { 6202 dev_priv->display.dpms = ironlake_crtc_dpms; 6203 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 6204 dev_priv->display.update_plane = ironlake_update_plane; 6205 } else { 6206 dev_priv->display.dpms = i9xx_crtc_dpms; 6207 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 6208 dev_priv->display.update_plane = i9xx_update_plane; 6209 } 6210 6211 /* Returns the core display clock speed */ 6212 if (IS_VALLEYVIEW(dev)) 6213 dev_priv->display.get_display_clock_speed = 6214 valleyview_get_display_clock_speed; 6215 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) 6216 dev_priv->display.get_display_clock_speed = 6217 i945_get_display_clock_speed; 6218 else if (IS_I915G(dev)) 6219 dev_priv->display.get_display_clock_speed = 6220 i915_get_display_clock_speed; 6221 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) 6222 dev_priv->display.get_display_clock_speed = 6223 i9xx_misc_get_display_clock_speed; 6224 else if (IS_I915GM(dev)) 6225 dev_priv->display.get_display_clock_speed = 6226 i915gm_get_display_clock_speed; 6227 else if (IS_I865G(dev)) 6228 dev_priv->display.get_display_clock_speed = 6229 i865_get_display_clock_speed; 6230 else if (IS_I85X(dev)) 6231 dev_priv->display.get_display_clock_speed = 6232 i855_get_display_clock_speed; 6233 else /* 852, 830 */ 6234 dev_priv->display.get_display_clock_speed = 6235 i830_get_display_clock_speed; 6236 6237 if (HAS_PCH_SPLIT(dev)) { 6238 if (IS_GEN5(dev)) { 6239 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 6240 dev_priv->display.write_eld = ironlake_write_eld; 6241 } else if (IS_GEN6(dev)) { 6242 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 6243 dev_priv->display.write_eld = ironlake_write_eld; 6244 } else if (IS_IVYBRIDGE(dev)) { 6245 /* FIXME: detect B0+ stepping and use auto training */ 6246 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 6247 dev_priv->display.write_eld = ironlake_write_eld; 6248 } else 6249 dev_priv->display.update_wm = NULL; 6250 } else if (IS_G4X(dev)) { 6251 dev_priv->display.write_eld = g4x_write_eld; 6252 } 6253 6254 /* Default just returns -ENODEV to indicate unsupported */ 6255 dev_priv->display.queue_flip = intel_default_queue_flip; 6256 6257 switch (INTEL_INFO(dev)->gen) { 6258 case 2: 6259 dev_priv->display.queue_flip = intel_gen2_queue_flip; 6260 break; 6261 6262 case 3: 6263 dev_priv->display.queue_flip = intel_gen3_queue_flip; 6264 break; 6265 6266 case 4: 6267 case 5: 6268 dev_priv->display.queue_flip = intel_gen4_queue_flip; 6269 break; 6270 6271 case 6: 6272 dev_priv->display.queue_flip = intel_gen6_queue_flip; 6273 break; 6274 case 7: 6275 dev_priv->display.queue_flip = intel_gen7_queue_flip; 6276 break; 6277 } 6278 } 6279 6280 /* 6281 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 6282 * resume, or other times. This quirk makes sure that's the case for 6283 * affected systems. 6284 */ 6285 static void quirk_pipea_force(struct drm_device *dev) 6286 { 6287 struct drm_i915_private *dev_priv = dev->dev_private; 6288 6289 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 6290 DRM_DEBUG("applying pipe a force quirk\n"); 6291 } 6292 6293 /* 6294 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 6295 */ 6296 static void quirk_ssc_force_disable(struct drm_device *dev) 6297 { 6298 struct drm_i915_private *dev_priv = dev->dev_private; 6299 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 6300 } 6301 6302 struct intel_quirk { 6303 int device; 6304 int subsystem_vendor; 6305 int subsystem_device; 6306 void (*hook)(struct drm_device *dev); 6307 }; 6308 6309 #define PCI_ANY_ID (~0u) 6310 6311 struct intel_quirk intel_quirks[] = { 6312 /* HP Mini needs pipe A force quirk (LP: #322104) */ 6313 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, 6314 6315 /* Thinkpad R31 needs pipe A force quirk */ 6316 { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, 6317 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 6318 { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, 6319 6320 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ 6321 { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, 6322 /* ThinkPad X40 needs pipe A force quirk */ 6323 6324 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 6325 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 6326 6327 /* 855 & before need to leave pipe A & dpll A up */ 6328 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 6329 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 6330 6331 /* Lenovo U160 cannot use SSC on LVDS */ 6332 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 6333 6334 /* Sony Vaio Y cannot use SSC on LVDS */ 6335 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 6336 }; 6337 6338 static void intel_init_quirks(struct drm_device *dev) 6339 { 6340 struct intel_quirk *q; 6341 device_t d; 6342 int i; 6343 6344 d = dev->dev; 6345 for (i = 0; i < DRM_ARRAY_SIZE(intel_quirks); i++) { 6346 q = &intel_quirks[i]; 6347 if (pci_get_device(d) == q->device && 6348 (pci_get_subvendor(d) == q->subsystem_vendor || 6349 q->subsystem_vendor == PCI_ANY_ID) && 6350 (pci_get_subdevice(d) == q->subsystem_device || 6351 q->subsystem_device == PCI_ANY_ID)) 6352 q->hook(dev); 6353 } 6354 } 6355 6356 /* Disable the VGA plane that we never use */ 6357 static void i915_disable_vga(struct drm_device *dev) 6358 { 6359 struct drm_i915_private *dev_priv = dev->dev_private; 6360 u8 sr1; 6361 u32 vga_reg; 6362 6363 if (HAS_PCH_SPLIT(dev)) 6364 vga_reg = CPU_VGACNTRL; 6365 else 6366 vga_reg = VGACNTRL; 6367 6368 #if 0 6369 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 6370 #endif 6371 outb(VGA_SR_INDEX, 1); 6372 sr1 = inb(VGA_SR_DATA); 6373 outb(VGA_SR_DATA, sr1 | 1 << 5); 6374 #if 0 6375 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 6376 #endif 6377 DELAY(300); 6378 6379 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 6380 POSTING_READ(vga_reg); 6381 } 6382 6383 void intel_modeset_init_hw(struct drm_device *dev) 6384 { 6385 /* We attempt to init the necessary power wells early in the initialization 6386 * time, so the subsystems that expect power to be enabled can work. 6387 */ 6388 intel_init_power_wells(dev); 6389 6390 #if 0 6391 intel_prepare_ddi(dev); 6392 #endif 6393 6394 intel_init_clock_gating(dev); 6395 6396 DRM_LOCK(dev); 6397 intel_enable_gt_powersave(dev); 6398 DRM_UNLOCK(dev); 6399 } 6400 6401 void intel_modeset_init(struct drm_device *dev) 6402 { 6403 struct drm_i915_private *dev_priv = dev->dev_private; 6404 int i, ret; 6405 6406 drm_mode_config_init(dev); 6407 6408 dev->mode_config.min_width = 0; 6409 dev->mode_config.min_height = 0; 6410 6411 dev->mode_config.preferred_depth = 24; 6412 dev->mode_config.prefer_shadow = 1; 6413 6414 dev->mode_config.funcs = &intel_mode_funcs; 6415 6416 intel_init_quirks(dev); 6417 6418 intel_init_pm(dev); 6419 6420 intel_init_display(dev); 6421 6422 if (IS_GEN2(dev)) { 6423 dev->mode_config.max_width = 2048; 6424 dev->mode_config.max_height = 2048; 6425 } else if (IS_GEN3(dev)) { 6426 dev->mode_config.max_width = 4096; 6427 dev->mode_config.max_height = 4096; 6428 } else { 6429 dev->mode_config.max_width = 8192; 6430 dev->mode_config.max_height = 8192; 6431 } 6432 dev->mode_config.fb_base = dev->agp->base; 6433 6434 DRM_DEBUG_KMS("%d display pipe%s available.\n", 6435 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); 6436 6437 for (i = 0; i < dev_priv->num_pipe; i++) { 6438 intel_crtc_init(dev, i); 6439 ret = intel_plane_init(dev, i); 6440 if (ret) 6441 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); 6442 } 6443 6444 intel_cpu_pll_init(dev); 6445 intel_pch_pll_init(dev); 6446 6447 /* Just disable it once at startup */ 6448 i915_disable_vga(dev); 6449 intel_setup_outputs(dev); 6450 } 6451 6452 void intel_modeset_gem_init(struct drm_device *dev) 6453 { 6454 intel_modeset_init_hw(dev); 6455 6456 intel_setup_overlay(dev); 6457 } 6458 6459 void intel_modeset_cleanup(struct drm_device *dev) 6460 { 6461 struct drm_i915_private *dev_priv = dev->dev_private; 6462 struct drm_crtc *crtc; 6463 struct intel_crtc *intel_crtc; 6464 6465 drm_kms_helper_poll_fini(dev); 6466 DRM_LOCK(dev); 6467 6468 #if 0 6469 intel_unregister_dsm_handler(); 6470 #endif 6471 6472 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6473 /* Skip inactive CRTCs */ 6474 if (!crtc->fb) 6475 continue; 6476 6477 intel_crtc = to_intel_crtc(crtc); 6478 intel_increase_pllclock(crtc); 6479 } 6480 6481 intel_disable_fbc(dev); 6482 6483 intel_disable_gt_powersave(dev); 6484 6485 ironlake_teardown_rc6(dev); 6486 6487 if (IS_VALLEYVIEW(dev)) 6488 vlv_init_dpio(dev); 6489 6490 DRM_UNLOCK(dev); 6491 6492 /* Disable the irq before mode object teardown, for the irq might 6493 * enqueue unpin/hotplug work. */ 6494 drm_irq_uninstall(dev); 6495 cancel_work_sync(&dev_priv->hotplug_work); 6496 cancel_work_sync(&dev_priv->rps.work); 6497 6498 /* flush any delayed tasks or pending work */ 6499 flush_scheduled_work(); 6500 6501 /* destroy backlight, if any, before the connectors */ 6502 intel_panel_destroy_backlight(dev); 6503 6504 drm_mode_config_cleanup(dev); 6505 } 6506 6507 /* 6508 * Return which encoder is currently attached for connector. 6509 */ 6510 struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 6511 { 6512 return &intel_attached_encoder(connector)->base; 6513 } 6514 6515 void intel_connector_attach_encoder(struct intel_connector *connector, 6516 struct intel_encoder *encoder) 6517 { 6518 connector->encoder = encoder; 6519 drm_mode_connector_attach_encoder(&connector->base, 6520 &encoder->base); 6521 } 6522 6523 /* 6524 * set vga decode state - true == enable VGA decode 6525 */ 6526 int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 6527 { 6528 struct drm_i915_private *dev_priv; 6529 device_t bridge_dev; 6530 u16 gmch_ctrl; 6531 6532 dev_priv = dev->dev_private; 6533 bridge_dev = intel_gtt_get_bridge_device(); 6534 gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2); 6535 if (state) 6536 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 6537 else 6538 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 6539 pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2); 6540 return (0); 6541 } 6542 6543 struct intel_display_error_state { 6544 struct intel_cursor_error_state { 6545 u32 control; 6546 u32 position; 6547 u32 base; 6548 u32 size; 6549 } cursor[2]; 6550 6551 struct intel_pipe_error_state { 6552 u32 conf; 6553 u32 source; 6554 6555 u32 htotal; 6556 u32 hblank; 6557 u32 hsync; 6558 u32 vtotal; 6559 u32 vblank; 6560 u32 vsync; 6561 } pipe[2]; 6562 6563 struct intel_plane_error_state { 6564 u32 control; 6565 u32 stride; 6566 u32 size; 6567 u32 pos; 6568 u32 addr; 6569 u32 surface; 6570 u32 tile_offset; 6571 } plane[2]; 6572 }; 6573 6574 struct intel_display_error_state * 6575 intel_display_capture_error_state(struct drm_device *dev) 6576 { 6577 drm_i915_private_t *dev_priv = dev->dev_private; 6578 struct intel_display_error_state *error; 6579 int i; 6580 6581 error = kmalloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT); 6582 if (error == NULL) 6583 return NULL; 6584 6585 for (i = 0; i < 2; i++) { 6586 error->cursor[i].control = I915_READ(CURCNTR(i)); 6587 error->cursor[i].position = I915_READ(CURPOS(i)); 6588 error->cursor[i].base = I915_READ(CURBASE(i)); 6589 6590 error->plane[i].control = I915_READ(DSPCNTR(i)); 6591 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 6592 error->plane[i].size = I915_READ(DSPSIZE(i)); 6593 error->plane[i].pos = I915_READ(DSPPOS(i)); 6594 error->plane[i].addr = I915_READ(DSPADDR(i)); 6595 if (INTEL_INFO(dev)->gen >= 4) { 6596 error->plane[i].surface = I915_READ(DSPSURF(i)); 6597 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); 6598 } 6599 6600 error->pipe[i].conf = I915_READ(PIPECONF(i)); 6601 error->pipe[i].source = I915_READ(PIPESRC(i)); 6602 error->pipe[i].htotal = I915_READ(HTOTAL(i)); 6603 error->pipe[i].hblank = I915_READ(HBLANK(i)); 6604 error->pipe[i].hsync = I915_READ(HSYNC(i)); 6605 error->pipe[i].vtotal = I915_READ(VTOTAL(i)); 6606 error->pipe[i].vblank = I915_READ(VBLANK(i)); 6607 error->pipe[i].vsync = I915_READ(VSYNC(i)); 6608 } 6609 6610 return error; 6611 } 6612 6613 void 6614 intel_display_print_error_state(struct sbuf *m, 6615 struct drm_device *dev, 6616 struct intel_display_error_state *error) 6617 { 6618 int i; 6619 6620 for (i = 0; i < 2; i++) { 6621 sbuf_printf(m, "Pipe [%d]:\n", i); 6622 sbuf_printf(m, " CONF: %08x\n", error->pipe[i].conf); 6623 sbuf_printf(m, " SRC: %08x\n", error->pipe[i].source); 6624 sbuf_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); 6625 sbuf_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); 6626 sbuf_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); 6627 sbuf_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); 6628 sbuf_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); 6629 sbuf_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); 6630 6631 sbuf_printf(m, "Plane [%d]:\n", i); 6632 sbuf_printf(m, " CNTR: %08x\n", error->plane[i].control); 6633 sbuf_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 6634 sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size); 6635 sbuf_printf(m, " POS: %08x\n", error->plane[i].pos); 6636 sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr); 6637 if (INTEL_INFO(dev)->gen >= 4) { 6638 sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface); 6639 sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 6640 } 6641 6642 sbuf_printf(m, "Cursor [%d]:\n", i); 6643 sbuf_printf(m, " CNTR: %08x\n", error->cursor[i].control); 6644 sbuf_printf(m, " POS: %08x\n", error->cursor[i].position); 6645 sbuf_printf(m, " BASE: %08x\n", error->cursor[i].base); 6646 } 6647 } 6648